JP2011160225A - Semiconductor device - Google Patents

Abstract

Variations in output of a semiconductor device caused by a change in the number of operating main buffers connected to the same power supply system are suppressed.
A semiconductor device according to an aspect of the present invention includes a main buffer circuit 2 including a plurality of main buffers that drives a plurality of signal lines in accordance with input data, and dummy buffers as many as the main buffers. The dummy buffer circuit 5 provided, the power supply connected to the main buffer circuit 2 and the dummy buffer circuit 5, the main buffer wiring to which the main buffer circuit 2 is connected, and the dummy buffer circuit 5 are connected to the main buffer wiring and are substantially the same as the main buffer wiring. A dummy buffer wiring having a plurality of loads, a switching detection circuit 3 for detecting a switching state of a plurality of main buffers of the main buffer circuit, and a dummy buffer switching circuit 4 for controlling the number of switching of the dummy buffers based on the switching detection result, Is provided.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to control of a buffer disposed in a circuit constituting the semiconductor device.

  In recent years, with the rapid spread of the Internet and the like, communication devices include semiconductor memory devices (SRAM, DRAM) having a large capacity and high speed operation such as DDR (Double Data Rate) and QDR (Quad Data Rate). As a result, the market demand for a semiconductor memory device that achieves both large capacity and high transmission speed is increasing.

  In a semiconductor device having a large capacity and capable of high-speed operation, a time change in current consumption increases when data is read from the memory core as the number of signal lines and transistors increases. For this reason, the signal transmitted through the signal line has a problem that output delay varies due to non-uniform potential fluctuations in the power supply of the output buffer circuit and GND.

  Patent Document 1 describes a power supply and a semiconductor device that suppresses a GND potential fluctuation amount. FIG. 9 is a diagram showing a configuration of a semiconductor integrated circuit 10 having a power supply decoupling capacitor described in Patent Document 1. In FIG. The semiconductor integrated circuit 10 has an I / O region 12 and a core region 14. Each of the I / O region 12 and the core region 14 includes a plurality of semiconductor devices or cells. For example, the I / O area 12 has an inverter 20, and the core area 14 has an inverter 22.

  Inverter 22 is a pre-driver that provides a digital signal on output 23 to inverter 20. The inverter 20 receives the digital signal and drives the signal off-chip via the output Dout. The inverter 20 forms a part of the I / O cell in the I / O region 12.

  The power supply buses VDD and VSS are coupled to the external power supply 24 and supply charges to the semiconductor devices inside the I / O region 12. Similarly, the power buses VDD2 and VSS2 are coupled to the external power supply 26 and supply charges to the semiconductor devices inside the core region 14. Inductors L and L2 represent inductances in power buses VDD and VDD2, respectively.

  Capacitor C 1 represents the interconnection capacitance at the output of inverter 20. When the output of inverter 20 changes state, inverter 20 either applies current to capacitor C1 or sinks current from capacitor C1. The charge required during switching is provided by the external power supply 24 on the power buses VDD and VSS.

  Therefore, the external power supply 24 shares the charge with the capacitor C1. The capacitance provided by the external power supply 24 is relatively inefficient because the distance from the inverter 20 is large because the external power supply 24 is external to the semiconductor integrated circuit. This tends to cause noise in the rate of change of current with respect to time at the output of the inverter 20.

  In Patent Document 1, the power supply decoupling capacitor C2 is formed in a die structure between the power supply buses VDD and VSS in the vicinity of the inverter 20. The decoupling capacitor C2 extends an unused metal structure (dummy metal) in the I / O region 12 and physically overlaps either the power bus VDD or VSS, and electrically connects the dummy metal to the other power bus. Formed by bonding to

  Decoupling capacitor C2 includes plates 34 and 36. The plate 34 is formed by the power supply bus VDD, and the plate 36 is formed by a dummy metal overlapping the power supply bus VDD. One end of the dummy metal forming the plate 36 is coupled to the power supply bus VSS so that the plate 34 and the plate 36 have opposite polarities.

  Similarly, capacitor C3 represents the interconnection capacitance between the output 23 of inverter 22 and the input of inverter 20. In the semiconductor integrated circuit 10, on-die type power supply decoupling capacitors (C2, C4) are electrically coupled between the first and second power supply conductors in the vicinity of a plurality of transistors that perform switching at the same time. And provide additional charge to those transistors to reduce noise.

  Although it is indispensable to perform an appropriate timing design in a product design for a semiconductor device that operates at a large capacity and satisfies a market requirement, the timing design is difficult in the semiconductor device described in Patent Document 1. .

  In the semiconductor device shown in FIG. 9, if there are two circuits composed of the inverter 22 and the inverter 20 in the same power supply system, the signal input to the first inverter 22 is at a high level. (Hereinafter referred to as 'H') to Low level (hereinafter referred to as 'L'), or from 'L' to 'H', the state changes from one state to the other state to the second inverter 22. The signal input to the two inverters 22 is still in the state of “L” or “H”. Compared to the case, the timing of the signal appearing at the output Dout is delayed.

  This is because, for example, the P-channel transistor and the N-channel transistor that constitute the inverter 20 and the inverter 22 in FIG. The charge is lost and the power supply potential drops. Further, since electric charges flow into the VSS and VSS2 lines that supply the GND potential, the GND potential rises. As a result, the potential difference required for the circuit operation is reduced, and the operation timing is delayed.

  As described above, the generation timing of the output Dout varies due to the change in the number of changes in the signal input to the inverter 22. Hereinafter, this variation in generation timing is referred to as jitter.

  In the semiconductor device of FIG. 9, decoupling capacitors (C2, C4) are incorporated in order to prevent a delay in operation timing. However, although the decoupling capacitor can suppress the rapid fluctuation of the power supply voltage and prevent a local drop in the power supply voltage, and can reduce the variation of the power supply voltage value, it does not eliminate the jitter generated in the output Dout. I can't.

Japanese Patent Laid-Open No. 10-270643

  As described above, in the semiconductor device described in Patent Document 1, when a plurality of buffers are connected to the same power supply system, it is not possible to suppress variations in output of the semiconductor device caused by a change in the number of operating buffers. Is

  A semiconductor device according to one embodiment of the present invention includes a main buffer circuit including a plurality of main buffers that drives a plurality of signal lines according to input data, and a dummy buffer circuit including the same number of dummy buffers as the main buffers. A power source connected to the main buffer circuit and the dummy buffer circuit, a main buffer wiring connected to the main buffer circuit, and a load connected to the dummy buffer circuit and substantially the same as the main buffer wiring. A dummy buffer wiring; a switching detection circuit for detecting a switching state of a plurality of main buffers of the main buffer circuit; and a dummy buffer switching circuit for controlling the number of switching of the dummy buffers based on a switching detection result. is there.

  With such a configuration, it is possible to perform control such that the dummy buffer circuit is not switched when the main buffer is switched, and the dummy buffer is switched when the main buffer is not switched. As a result, the number of buffers operating in the entire signal line can always be the same. For this reason, even if any combination pattern of input data for switching the main buffer is input, the amount of fluctuation of the power supply voltage caused by the switching can be made the same. Therefore, the output timing of the semiconductor device can always be made simultaneously, and jitter can be suppressed.

  According to the present invention, in a semiconductor device in which a plurality of buffers are connected to the same power supply system, variation in output of the semiconductor device can be suppressed even if the number of operating buffers is changed.

1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. 3 is a diagram showing a configuration of a jitter reduction buffer circuit in the semiconductor device according to the first embodiment. FIG. 3 is a timing chart for explaining the operation of the semiconductor device according to the first embodiment; It is a figure which shows the fluctuation | variation of the generated jitter and (DELTA) V for demonstrating the effect of this invention. It is a figure which shows the fluctuation | variation of the generated jitter and (DELTA) V for demonstrating the effect of this invention. It is a graph which shows the relationship of (DELTA) V with the buffer operation | movement number. 5 is a graph showing the relationship between the number of buffer operations and jitter. FIG. 4 is a diagram showing a configuration of a semiconductor device according to a second embodiment. 6 is a diagram illustrating a configuration of a jitter reduction buffer circuit in a semiconductor device according to a second embodiment; FIG. 1 is a diagram illustrating a configuration of a semiconductor device described in Patent Document 1. FIG.

Embodiment 1 FIG.
A semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram showing a configuration of a semiconductor device according to the present embodiment. The present invention relates to control of a buffer arranged in a circuit constituting a semiconductor device. In particular, the present invention controls a buffer circuit disposed on a signal line that outputs data from a memory core in a semiconductor memory device, and suppresses jitter (variation in output generation timing).

  In the semiconductor device illustrated in FIG. 1, an example in which the first input signal IN1 to the fourth input signal IN4 are input from four signal lines connected to the memory core will be described. Note that the memory core indicates a DRAM cell or an SRAM cell and has a known configuration, and thus detailed description thereof is omitted.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes a first jitter reduction buffer circuit 1001, a second jitter reduction buffer circuit 1002, a third jitter reduction buffer circuit 1003, and a fourth jitter reduction buffer. A circuit 1004 is provided. The first input signal IN1 to the fourth input signal IN4 are input to the first jitter reduction buffer circuit 1001 to the fourth jitter reduction buffer circuit 1004, respectively.

  The first jitter reduction buffer circuit 1001 includes a timing adjustment delay circuit 1, a main buffer circuit 2, a switching detection circuit 3, a dummy buffer switching circuit 4, a dummy buffer circuit 5, and a timing adjustment delay circuit 6. In FIG. 1, the second jitter reduction buffer circuit 1002 to the fourth jitter reduction buffer circuit 1004 have the same configuration as the first jitter reduction buffer circuit 1001, and are not shown.

  The timing input delay circuit 1 receives the first input signal IN1. The timing adjustment delay circuit 1 outputs a first main switching signal A1. The first main switching signal A1 is input to the main buffer circuit 2. The main buffer circuit 2 outputs a first main output signal M1. That is, the main buffer circuit 2 drives the corresponding signal line according to the first input signal IN1.

  The first input signal IN1 is input to the switching detection circuit 3 together with the internal clock signal CLK and the internal reset signal RST. The switching detection circuit 3 detects the switching state of the main buffer circuit 2 and outputs a first dummy switching detection signal SW1.

  An internal clock signal CLK is input to the timing adjustment delay circuit 6. The timing adjusting delay circuit 6 outputs a first delayed internal clock signal DCLK1. The first dummy switching detection signal SW1 is input to the dummy buffer switching circuit 4 together with the first delayed internal clock signal DCLK1 and the internal reset signal RST.

  The dummy buffer switching circuit 4 outputs a first dummy switching signal Q1. The dummy buffer switching circuit 4 controls the number of switching of dummy buffers of the dummy buffer circuit 5 described later based on the result detected by the switching detection circuit 3.

  The first dummy switching signal Q1 is input to the dummy buffer circuit 5. The dummy buffer circuit 5 outputs a first dummy output signal D1. Note that the switching capabilities of the main buffer circuit 2 and the dummy buffer circuit 5 and the signal lines on which the first main output signal M1 and the first dummy output signal D1 as the outputs are transmitted are substantially the same. For example, the wiring loads of the signal lines through which the first main output signal M1 and the first dummy output signal D1 are transmitted are substantially equal. In the present embodiment, a total of four main buffer circuits 2 are provided, one for each of the first jitter reduction buffer circuit 1001 to the fourth jitter reduction buffer circuit 1004.

  The second input signal IN2 is input to the second jitter reduction buffer circuit 1002. Further, in the second jitter reduction buffer circuit 1002, a second main switching signal A2, a second dummy switching detection signal SW2, and a second dummy switching signal Q2 are generated, and the second main output signal M2 and the second dummy switching signal Q2 are generated. The dummy output signal D2 is output.

  The third input signal IN3 is input to the third jitter reduction buffer circuit 1003. In the third jitter reduction buffer circuit 1003, a third main switching signal A3, a third dummy switching detection signal SW3, and a third dummy switching signal Q3 are generated, and the third main output signal M3 and the third dummy switching signal Q3 are generated. 3 dummy output signal D3 is output.

  The fourth input signal IN4 is input to the fourth jitter reduction buffer circuit 1004. In the fourth jitter reduction buffer circuit 1004, the fourth main switching signal A4, the fourth dummy switching detection signal SW4, and the fourth dummy switching signal Q4 are generated, and the fourth main output signal M4 and the fourth main switching signal M4 are generated. 4 dummy output signals D4 are output.

  Next, the detailed configuration of the first jitter reduction buffer circuit 1001 will be described with reference to FIG. FIG. 2 is a diagram showing a configuration of the first jitter reduction buffer circuit 1001 in the semiconductor device shown in FIG.

  As shown in FIG. 2, the timing adjustment delay circuit 1 includes a delay element 100. The first input signal IN1 is input to the delay element 100. The delay element 100 outputs a first main switching signal A1.

  The main buffer circuit 2 includes inverter elements 200 and 201. The inverter elements 200 and 201 are connected in series. The two inverter elements 200 and 201 constitute a buffer. The inverter element 200 receives the first main switching signal A1. The inverter element 200 outputs the first main switching inversion signal A1B and inputs it to the inverter element 201. The inverter element 201 outputs a first main output signal M1. The first main output signal M1 that is the output of the inverter element 201 is always in reverse phase with respect to the main switching inversion signal A1B that is the output of the inverter element 200.

  The switching detection circuit 3 includes a D-FF element 300 and an ExNOR element 301. The first input signal IN1 is input to the D terminal of the D-FF element 300. The internal clock signal CLK is input to the CLK terminal of the D-FF element 300, and the internal reset signal RST is input to the RST terminal. The first data holding signal D1p is output from the output terminal Q of the D-FF element 300.

  The first input signal IN1 is input to one input terminal of the ExNOR element 301, and the first data holding signal D1p is input to the other input terminal. The ExNOR element 301 performs a 2-input ExNOR operation. The ExNOR element 301 outputs a first dummy switching detection signal SW1 to the dummy buffer switching circuit 4.

  The timing adjustment delay circuit 6 includes a delay element 600. Internal clock signal CLK is input to delay element 600. The delay element 600 outputs the first delayed internal clock signal DCLK1 to the dummy buffer switching circuit 4.

  The dummy buffer switching circuit 4 includes a T-FF element 400 and an AND element 401. The AND element 401 receives the first dummy switching detection signal SW1 and the internal reset signal RST. The AND element 401 outputs the first switching enable signal Tin1 to the T-FF element 400.

  The first switching enable signal Tin1 is input to the T terminal of the T-FF element 400, the first delayed internal clock signal DCLK1 is input to the CLK terminal, and the internal reset signal RST is input to the RST terminal. . The T-FF element 400 outputs a first dummy switching signal Q1.

  The dummy buffer circuit 5 includes inverter elements 500 and 501 and a capacitor CP. The inverter elements 500 and 501 and the capacitor CP are connected in series. The two inverter elements 500 and 501 constitute a dummy buffer. The first dummy switching signal Q <b> 1 that is the output of the T-FF element 400 is input to the inverter element 500. The inverter element 500 outputs the first dummy switching inversion signal Q1B to the inverter element 501. The inverter element 501 outputs a first dummy output signal D1. Further, the first dummy output signal D1 that is the output of the inverter 501 is always in reverse phase with respect to the dummy switching inversion signal Q1B that is the output of the inverter element 500.

  The first dummy output signal D1 and the first main output signal M1 are output via a signal line that combines parasitic capacitances by using the same wiring layer at the same distance. Also, a capacitor CP is connected to the output side of the inverter element 501 in accordance with the parasitic capacitance of the next stage transistor to which the first main output signal M1 is input.

  Note that the second jitter reduction buffer circuit 1002 to the fourth jitter reduction buffer circuit 1004 have the same configuration as the first jitter reduction buffer circuit 1001. The main buffer circuit 2 and the dummy buffer circuit 5 of each of the first jitter reduction buffer circuit 1001 to the fourth jitter reduction buffer circuit 1004 are connected to the same power supply system (power supply potential and GND).

  In the semiconductor device shown in FIG. 1, four main buffers including two inverter elements 200 and 201 are provided. These main buffers serve as main buffer circuits for driving a plurality of signal lines in accordance with input data. In addition, four dummy buffers including two inverter elements 500 and 501 are provided. That is, the number of main buffers in the main buffer circuit is equal to the number of dummy buffers in the dummy buffer circuit.

  In the second jitter reduction buffer circuit 1002, the second data holding signal D2p, the second dummy switching detection signal SW2, the second delayed internal clock signal DCLK2, the second switching enable signal Tin2, and the second dummy switching signal. Q2, a second main switching signal A2, a second main switching inversion signal A2B, and a second dummy switching inversion signal Q2B are generated.

  In the third jitter reduction buffer circuit 1003, the third data holding signal D3p, the third dummy switching detection signal SW3, the third delayed internal clock signal DCLK3, the third switching enable signal Tin3, and the third dummy switching signal Q3, a third main switching signal A3, a third main switching inversion signal A3B, and a third dummy switching inversion signal Q3B are generated.

  In the fourth jitter reduction buffer circuit 1004, the fourth data holding signal D4p, the fourth dummy switching detection signal SW4, the fourth delayed internal clock signal DCLK4, the fourth switching enable signal Tin4, and the fourth dummy switching signal. Q4, the fourth main switching signal A4, the fourth main switching inversion signal A4B, and the fourth dummy switching inversion signal Q4B are generated.

  Here, the operation of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a flowchart for explaining the operation of the semiconductor device according to the present embodiment. Since the first delayed internal clock signal DCLK1 to the fourth delayed internal clock signal DCLK4 change in the same phase and in the same manner, they are referred to as the delayed internal clock signal DCLK in FIG. 3 and the following description.

  In FIG. 3, the time when any one of the signals changes is defined as Tinit, T0, T1,... T16, T17. In FIG. 3, other signal states do not change at the timing of the falling edge of the internal clock signal CLK and the falling edge of the delayed internal clock signal DCLK. Therefore, this timing is not defined as the time when the signal changes. Description is omitted.

  However, the D-FF element 300 operates in synchronization with the rising edge of the internal clock signal CLK, and the T-FF element 400 operates in synchronization with the rising edge of the delayed internal clock signal DCLK. Note that the first input signal IN1 to the fourth input signal IN4 are signals latched in synchronization with the internal clock signal CLK.

  The first input signal IN1 to the fourth input signal IN4 before the time Tinit are all set to “L”. Since the internal reset signal RST is 'L' at the same time, the first data holding signal D1p to the fourth data holding signal D4p, which are the outputs of the D-FF element 300, indicate the reset state. L '. Similarly, the first dummy switching detection signal Tin1 to the fourth dummy switching detection signal Tin4, which are the outputs of the T-FF element 400, also become “L” indicating the reset state.

  Since the delayed internal clock signal DCLK obtained by delaying the internal clock signal CLK is delayed by the delay element 600, it becomes indefinite before the time Tinit. Here, the indefinite state is a state where the value is determined to be either “L” or “H”.

  Since the first main output signal M1 to the fourth main output signal M4 are delayed through the delay element 100, they are in an indefinite state before the time Tinit. Since the internal reset signal RST is “L” and the T-FF element 400 is in the reset state, the first dummy switching signal Q1 to the fourth dummy switching signal Q4 become “L”, and the inverter elements 500 and 501 are turned on. The first dummy output signal D1 to the fourth dummy output signal D4 that are output via the first and second dummy output signals D1 are all set to “L”.

  At time Tinit, the internal reset signal RST changes from 'L' to 'H'. Here, the reset state of the D-FF element 300 and the T-FF element 400 is released. However, since the internal clock signal CLK does not change from “L” to “H” and does not have a rising edge, the first data holding signal D1p to the fourth data holding signal D4p, which are the outputs of the D-FF element 300, are provided. Remains 'L'. In addition, the first dummy switching signal Q1 to the fourth dummy switching signal Q4, which are the outputs of the T-FF element 400, also remain 'L'.

  At time T0, the delayed internal clock signal DCLK changes from an indeterminate state to 'L' as the delay time set by the delay element 600 elapses. At this time, there is no other signal state change. Note that the delay time amount in the delay element 600 is a delay time amount set in consideration of delays in the D-FF element 300 and the ExNOR element 301.

  At time T1, the internal clock signal CLK changes from “L” to “H”. At this time, the first input signal IN1 to the fourth input signal IN4 are latched in synchronization with the internal clock signal CLK. Here, it is assumed that the first input signal IN1 to the fourth input signal IN4 remain 'L'. There is no other signal state change.

  At time T2, the first input signal IN1 to the fourth input signal IN4 and the first data enable signal Tin1 to the fourth data hold signal D4p are subjected to ExNOR operation and the first switching enable signal Tin1 to 4 switching enable signal Tin4 changes from 'L' to 'H'.

  The ExNOR element 301 outputs “H” as the dummy switching detection signals SW1 to SW4 when the two input signals are the same, and “L” as the dummy switching detection signals SW1 to SW4 when the two input signals are different. Output. There is no other signal state change.

  At time T3, the delayed internal clock signal DCLK changes from 'L' to 'H'. There is no other signal state change.

  At time T4, the change of the delayed internal clock signal DCLK at time T3 is received, and since the first switching enable signal Tin1 to the fourth switching enable signal Tin4 are 'H', the output of the T-FF element 400 is The first dummy switching signal Q1 to the fourth dummy switching signal Q4 change from 'L' to 'H'. There is no other signal state change.

  At time T5, since the delay time set by the delay element 100 has elapsed from the first main output signal M1 to the fourth main output signal M4, the first input signal IN1 to the fourth input signal IN4 at time T1. The state changes from the indeterminate state to 'L'. The delay time amount in the delay element 100 is such that the output timings of the first main output signal M1 to the fourth main output signal and the output timings of the first dummy output signal D1 to the fourth dummy output signal D4 are simultaneously set. This is the amount of delay time set for the purpose.

  Further, in response to a change in the first dummy switching signal Q1 to the fourth dummy switching signal Q4 at time T4, the first dummy output signal D1 to the fourth dummy output signal D4 change from 'L' to 'H'. And change. There is no other signal state change.

  At time T6, the internal clock signal CLK changes from “L” to “H”. At this time, similarly to the time T1, the first input signal IN1 to the fourth input signal IN4 are latched in synchronization with the internal clock signal CLK. Here, the first input signal IN1 and the fourth input signal IN4 remain 'L', and the second input signal IN2 and the third input signal IN3 are changed from 'L' to 'H'. And There is no other signal state change.

  At time T7, similarly to time T2, first switching is the result of ExNOR operation of the first input signal IN1 to the fourth input signal IN4 and the first data holding signal D1p to the fourth data holding signal D4p. A fourth switching enable signal Tin4 is output from the enable signal Tin1.

  The first switching enable signal Tin1 remains “H”, the second switching enable signal Tin2 changes from “H” to “L”, and the third switching enable signal Tin3 also changes from “H” to “L”. It changes to L, and the fourth switching enable signal Tin4 remains “H”. There are no other signal state changes.

  At time T8, the delayed internal clock signal DCLK changes from 'L' to 'H'. There is no other signal state change.

  At time T9, in response to the change in the delayed internal clock signal DCLK at time T8, the first dummy switching signal Q1 to the fourth dummy switching signal Q4 that are the outputs of the T-FF element 400 change as follows. Since the first switching enable signal Tin1 is “H”, the first dummy switching signal Q1 changes from “H” to “L”. Further, since the fourth switching enable signal Tin4 is “H”, the fourth dummy switching signal Q4 changes from “H” to “L”.

  Since the second switching enable signal Tin2 is “L”, the second dummy switching signal Q2 remains “H” and does not change. Since the third switching enable signal Tin3 is “L”, the third dummy switching signal Q3 remains “H”. Furthermore, there is no other change in signal state.

  At time T10, the delay time set by the delay element 100 elapses, and the state of the first input signal IN1 to the fourth input signal IN4 at time T6 is received, and the first main output signal M1 is 'L'. The second main output signal M2 changes from 'L' to 'H', the third main output signal M3 changes from 'L' to 'H', and the fourth main output signal M2 remains unchanged. The output signal M4 remains “L”.

  In response to the change of the first dummy switching signal Q1 to the fourth dummy switching signal Q4 at time T9, the first dummy output signal D1 changes from 'H' to 'L', and the second dummy switching signal Q1 changes. The output signal D2 remains “H”, the third dummy output signal D3 remains “H”, and the fourth dummy output signal D4 changes from “H” to “L”. There is no other signal state change.

  At time T11, the internal clock signal CLK changes from 'L' to 'H'. At this time, like the time T1 and the time T6, the first input signal IN1 to the fourth input signal IN4 are latched in synchronization with the internal clock signal CLK. Here, the first input signal IN1 changes from “L” to “H”, the second input signal IN2 remains “H”, and the third input signal IN3 remains “H”. It is assumed that there is no change and the fourth input signal IN4 remains “L” and there is no change. There is no other signal state change.

  At time T12, the second data holding signal D2p changes from 'L' to 'H', and the third data holding signal D3p changes from 'L' to 'H'. The values of the first input signal IN1 to the fourth input signal IN4 at time T6 are reflected, and the fourth data hold signal D4p is determined from the first data hold signal D1p. There is no other signal state change.

  At time T13, the first switching enable signal Tin1 changes from 'H' to 'L'. This is because the first input signal IN1 changes from 'L' to 'H' at time T11 and the change due to the first data holding signal D1p being 'L' at time T12. It is. There is no other signal state change.

  At time T14, the second switching enable signal Tin2 changes from 'L' to 'H', and the third switching enable signal Tin3 changes from 'L' to 'H'. This is because the second input signal IN2 and the third input signal IN3 are “H” at time T11, and the second data holding signal D2p and the third data holding signal D3p are “at time T12”. This change is caused by the change from L 'to' H '. There is no other signal state change.

  At time T15, the delayed internal clock signal DCLK changes from 'L' to 'H'. There is no other signal state change.

  At time T16, in response to the change of the delayed internal clock signal DCLK at time T15, the first dummy switching signal Q1 to the fourth dummy switching signal Q4, which are the outputs of the T-FF element 400, change as follows. .

  Since the second switching enable signal Tin2 is “H”, the second dummy switching signal Q2 changes from “H” to “L”. Since the third switching enable signal Tin3 is “H”, the third dummy switching signal Q3 changes from “H” to “L”. Since the fourth switching enable signal Tin4 is “H”, the fourth dummy switching signal Q4 changes from “L” to “H”.

  Since the first switching enable signal Tin1 is 'L', the first dummy switching signal Q1 remains 'L' and does not change. There is no other signal state change.

  At time T17, the delay time set by the delay element 100 elapses from the first main output signal M1 to the fourth main output signal M4, and from the first input signal IN1 to the fourth input signal IN4 at time T11. Accordingly, the first main output signal M1 changes from 'L' to 'H', the second main output signal M2 remains 'H', and the third main output signal M3 is not changed. “H” remains unchanged, and the fourth main output signal M4 remains “L”.

  In response to the change of the first dummy switching signal Q1 to the fourth dummy switching signal Q4 at time T16, the first dummy output signal D1 remains “L”, and the second dummy output signal D2 remains unchanged. Changes from 'H' to 'L', the third dummy output signal D3 changes from 'H' to 'L', and the fourth dummy output signal D4 changes from 'L' to 'H'. Change. There is no other signal state change.

  Thus, in the semiconductor device according to the present embodiment, the switching detection circuit 3 determines whether or not the main buffer circuit 2 is switching. When the main buffer circuit 2 is switched, the dummy buffer circuit 5 is not switched. When the main buffer circuit 2 is not switched, the dummy buffer circuit 5 is switched.

  Thereby, the number of buffer circuits to be switched can be made the same regardless of any change in input data. That is, the sum of the number of buffers switched in the main buffer circuit 2 and the dummy buffer circuit 5 is always the same. Therefore, the potential fluctuation between GND is made uniform from the power supply voltage generated at the time of data input to data output, and the signal line for transmitting the output signal of the main buffer circuit 2 can always change at the same timing. As a result, jitter can be eliminated.

  Next, a mechanism for solving the problem will be described with reference to FIGS. 4A and 4B. 4A and 4B are diagrams showing the generated jitter and the variation of ΔV for explaining the effect of the present invention. Note that ΔV is a voltage difference between the power supply voltage and GND. 4A shows a comparative example, and FIG. 4B shows the result of the semiconductor device according to the present embodiment. In the comparative example, the number of buffers to be switched is not constant as in the present invention.

As shown in FIG. 4A, when the first input signal IN1 changes, ΔV varies at a timing according to the output of the first main output signal M1. The difference in potential between the power supply voltage and GND when one main buffer circuit 2 operates is ΔVa_0, the difference in potential between the power supply voltage and GND when two main buffer circuits 2 operate is ΔVb_0, and four main buffer circuits 2 operate Assuming that the potential difference between the power supply voltage and GND in this case is ΔVc_0, the amount of fluctuation in the potential between the power supply voltage and GND is represented by the formula (1) according to the number of main buffer circuits 2 that operate.
ΔVa — 0> ΔVb — 0> ΔVc — 0 (1)

  Here, the time when the first input signal IN1 changes and the signal level reaches half is Ts. Let Ti be the time at which the first main output signal M1 switches in response to the change in the first input signal IN1, since there is no fluctuation in the power supply voltage and GND from the time Ts.

The delay from Ti when one main buffer circuit 2 is operated is ΔTa_0, the delay from Ti when two main buffer circuits 2 are operated is ΔTb_0, and the delay from Ti when four main buffer circuits 2 are operated Assuming that the delay is ΔTc_0, the delay of the first main output signal M1 is expressed by the equation (2) according to the number of main buffer circuits 2 that operate.
ΔTa — 0 <ΔTb — 0 <ΔTc — 0 (2)

However, the semiconductor device of the present invention operates so that the sum of the main buffer circuit 2 and the dummy buffer circuit 5 is always the same. Therefore, as shown in FIG. 4B, the potential difference between the power supply voltage and GND when one main buffer circuit 2 operates is ΔVa, and the potential difference between the power supply voltage and GND when two main buffer circuits 2 operate is ΔVb. If the potential difference between the power supply voltage and GND when four main buffer circuits 2 operate is ΔVc, the potential difference between the power supply voltage and GND during operation is equal to the expression (3) regardless of the number of main buffer circuits 2 operating. Therefore, the potential difference is always constant.
ΔVa = ΔVb = ΔVc (3)

Since there is no potential difference variation from equation (3), the delay from Ti when one main buffer circuit 2 operates is ΔTa, the delay from Ti when two main buffer circuits 2 operate is ΔTb, the main buffer If the delay from Ti when four circuits 2 are operated is ΔTc, the relationship from Equation (4) is satisfied, and the delay from Ti is always constant.
ΔTa = ΔTb = ΔTc (4)

  Even if the phases of the first main output signal M1 to the fourth main output signal M4 and the first dummy output signal D1 to the fourth dummy output signal D4 are not controlled, time T5 in the timing chart of FIG. As long as the number of signal lines to be switched is controlled as in the operation at T10 and time T17, the potential difference and the delay from Ti are constant regardless of the number of operating main buffer circuits 2 as shown in FIG. 4b.

  This is because the path (main buffer wiring) from the first main switching signal A1 to the first main output signal M1 in which the main buffer circuit 2 is arranged and the first dummy switching in which the dummy buffer circuit 5 is arranged. In the path (dummy buffer wiring) from the output of the signal Q1 to the output of the first dummy output signal D1, loads such as wiring capacitance are set to be equal. For this reason, it is possible to make the drop of the power supply voltage and the floating amount of the GND during operation constant.

  FIG. 5 is a graph showing the relationship between the number of buffer operations and ΔV, and FIG. 6 is a graph showing the relationship between the number of buffer operations and jitter. 5 and 6, the solid line indicates the result of the comparative example, and the broken line indicates the result of the present embodiment. As shown in FIG. 5, in the comparative example, the value of ΔV also varies as the number of operating buffers changes. However, when the present invention is applied, a constant ΔV can always be supplied as the power supply voltage.

  Further, as shown in FIG. 6, in the comparative example, the data arrival timing is shifted due to the change in the number of operating buffers, and jitter occurs. However, when the present invention is applied, it is always possible regardless of the number of operating buffers. Since the output changes at the same timing, jitter can be eliminated. As described above, by applying the present invention, in a semiconductor device equipped with a plurality of main buffer circuits, jitter due to fluctuations in the power supply voltage and the GND potential is eliminated, and appropriate timing design is facilitated.

Embodiment 2. FIG.
A semiconductor device according to the second embodiment will be described with reference to FIG. FIG. 7 is a diagram showing a configuration of the semiconductor device according to the present embodiment. In FIG. 7, the same components as those of FIG.

  The present embodiment is different from the semiconductor device shown in FIG. 1 in that a dummy buffer A circuit 5 A is provided instead of the dummy buffer circuit 5 in the first jitter reduction buffer circuit 1001. In FIG. 7, the jitter reduction buffer circuit provided with the dummy buffer A circuit 5A is referred to as a first jitter reduction buffer circuit 1001A to a fourth jitter reduction buffer circuit 1004A.

  In the present embodiment, the parasitic capacitance of the wiring in which the main buffer circuit 2 is arranged is replaced with a capacitive element in the dummy buffer A circuit 5A. Since the operation of the semiconductor device according to the present embodiment is the same as that of the first embodiment, description thereof is omitted. FIG. 8 shows the configuration of the first jitter reduction buffer circuit 1001A.

  As shown in FIG. 8, the dummy buffer A circuit 5A includes inverter elements 500 and 501, and capacitors CP, C500, and C501. The inverter elements 500 and 501 and the capacitor CP are connected in series. One end of the capacitor C500 is connected to a point between the inverter element 500 and the inverter element 501, and the other end is connected to GND. One end of the capacitor C501 is connected to a point between the inverter element 501 and the capacitor CP, and the other end is connected to GND. Capacitors C500 and C501 have a capacitance value substantially equal to the parasitic capacitance of the wiring between the first main switching inversion signal A1B and GND. The capacitor C500 has a capacitance value equal to the wiring capacitance of the signal line of the first main switching inversion signal A1B, and the capacitor C501 has a capacitance value equal to the wiring capacitance of the signal line of the first main output signal M1. have.

  The first dummy switching signal Q <b> 1 that is the output of the T-FF element 400 is input to the inverter element 500. The inverter element 500 outputs the first dummy switching inversion signal Q1B to the inverter element 501. The inverter element 501 outputs the first dummy output signal D1 via the capacitor CP. The capacitor CP has a capacitance value that matches the parasitic capacitance of the next-stage transistor to which the first main output signal M1 is input.

  As described above, the capacitor C500 is connected to the wiring that transmits the first dummy switching inversion signal Q1B, and the capacitor C501 is connected to the wiring that transmits the first dummy output signal D1. The sum of the wiring capacity of the dummy buffer wiring and the capacitive elements C500 and C501 is equal to the wiring capacity of the main buffer wiring. As described above, by replacing a part of the wiring capacity of the dummy buffer wiring with the capacitive element, it is possible to reduce the formation area of the dummy buffer wiring and suppress an increase in the area of the semiconductor device.

  As described above, according to the present invention, the total number of main buffer circuits 2 and dummy buffer circuits 5 to be switched can be made constant regardless of the combination pattern of input data. Thereby, the potential fluctuation of the signal line from the data input to the output can be made uniform, and the output jitter due to the change of the input data can be suppressed.

  Conventionally, in order to realize a highly reliable product, it is necessary to perform timing simulation under a plurality of conditions in accordance with signal line input conditions in consideration of jitter. However, by applying the present invention, jitter can be eliminated, and the timing margin can be set by performing only one simulation, so that the timing design is easier than in the prior art. Further, since the jitter is eliminated, the timing margin for guaranteeing the circuit operation can be minimized, and the operation cycle can be easily speeded up.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1001 1st jitter reduction buffer circuit 1002 2nd jitter reduction buffer circuit 1003 3rd jitter reduction buffer circuit 1004 4th jitter reduction buffer circuit 1 Timing adjustment delay circuit 2 Main buffer circuit 3 Switching detection circuit 4 Dummy buffer switching Circuit 5 Dummy buffer circuit 5A Dummy buffer A circuit 6 Timing adjustment delay circuit 100 Delay element 600 Delay element 200 Inverter element 201 Inverter element 500 Inverter element 501 Inverter element 300 D-FF element 301 ExNOR element 400 T-FF element 401 AND element C500 capacity C501 capacity CP capacity IN1 first input signal IN2 second input signal IN3 third input signal IN4 fourth input signal A1 first main switching signal A2 2nd main switching signal A3 3rd main switching signal A4 4th main switching signal SW1 1st dummy switching detection signal SW2 2nd dummy switching detection signal SW3 3rd dummy switching detection signal SW4 4th dummy Switching detection signal Q1 first dummy switching signal Q2 second dummy switching signal Q3 third dummy switching signal Q4 fourth dummy switching signal M1 first main output signal M2 second main output signal M3 third main Output signal M4 Fourth main output signal D1 First dummy output signal D2 Second dummy output signal D3 Third dummy output signal D4 Fourth dummy output signal D1p First data holding signal D2p Second data holding Signal D3p Third data holding signal D4p Fourth data Holding signal CLK Internal clock signal DCLK1 First delayed internal clock signal DCLK2 Second delayed internal clock signal DCLK3 Third delayed internal clock signal DCLK4 Fourth delayed internal clock signal Tin1 First switching enable signal Tin2 Second switching Enable signal Tin3 Third switching enable signal Tin4 Fourth switching enable signal RST Internal reset signal A1B First main switching inversion signal Q1B First dummy switching inversion signal A2B Second main switching inversion signal Q2B Second dummy switching Inverted signal A3B Third main switching inverted signal Q3B Third dummy switching inverted signal A4B Fourth main switching inverted signal Q4B Fourth dummy switching inverted Issue

Claims (5)

A main buffer circuit having a plurality of main buffers for driving a plurality of signal lines according to input data;
A dummy buffer circuit comprising the same number of dummy buffers as the main buffer;
A power source connected to the main buffer circuit and the dummy buffer circuit;
A main buffer wiring to which the main buffer circuit is connected;
A dummy buffer wiring connected to the dummy buffer circuit and having substantially the same load as the main buffer wiring;
A switching detection circuit for detecting a switching state of a plurality of main buffers of the main buffer circuit;
A dummy buffer switching circuit for controlling the number of switching of the dummy buffer based on a switching detection result;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the dummy buffer switching circuit makes the total number of the main buffer and the dummy buffer to operate constant regardless of a change in input data.   3. The first timing adjustment circuit according to claim 1, further comprising a first timing adjustment circuit that adjusts a propagation time of a clock for operating the dummy buffer switching circuit and substantially simultaneously outputs an output from the main buffer circuit and an output from the dummy buffer circuit. The semiconductor device described.   4. The semiconductor device according to claim 1, further comprising a second timing adjustment circuit that adjusts a propagation time of input data according to a delay amount of the switching detection circuit. The dummy buffer wiring has a wiring capacitance of the dummy buffer wiring as the load, and a capacitive element,
5. The semiconductor device according to claim 1, wherein a sum of a wiring capacitance of the dummy buffer wiring and the capacitive element is equal to a wiring capacitance of the main buffer wiring.

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