JP2011244086A - Oscillator circuit - Google Patents

Abstract

An oscillation circuit that is small and excellent in noise suppression is provided.
An oscillation circuit according to the present invention includes inverters 1 and 2 and a tank circuit 3. The tank circuit 3 is connected in parallel between the output node OUTT and the output node OUTB. The inverter 1 has an n-type MIS transistor M1 and a p-type MIS transistor M3 whose drains are connected to the output node OUTB. The inverter 2 includes an n-type MIS transistor M2 and a p-type MIS transistor M4 whose drains are connected to the output node OUTT. The gate terminals of the p-type MIS transistors M3 and M4 are directly connected to the output nodes OUTT and OUTB, respectively. The gate terminals of the n-type MIS transistors M1 and M2 are connected to the output nodes OUTT and OUTB via the coupling capacitors CG1 and CG2, respectively, and the bias voltage VBIAS is applied via the resistors CG1 and CG2.
[Selection] Figure 1

Description

  The present invention relates to an oscillation circuit, and more particularly to a low noise oscillation circuit.

  In recent years, various high-speed digital wireless systems such as mobile phones, wireless LANs, Bluetooth, and terrestrial digital TV have been put into practical use. In particular, in a digital semiconductor integrated circuit that operates at a high speed of GHz or higher, analog technology similar to that of a wireless circuit is used.

  FIG. 9 is a configuration diagram showing a model of a normal LC oscillator 400 formed on a silicon substrate. The LC oscillator 400 includes an LC tank unit 41 and an inverter unit 42. The LC tank unit 41 is a circuit that determines the oscillation frequency of the LC oscillator 400. The LC tank unit 41 includes an inductor Lp and a capacitor Cp. The inductor Lp and the capacitor Cp are connected in parallel between the output node OUTT and the output node OUTB. The capacitor Cp is a fixed capacitor or a variable capacitor (varactor). When the capacitance Cp is a variable capacitance, the oscillation frequency of the LC oscillator 400 can be changed by changing the capacitance. The resistor Rp indicates an equivalent parasitic resistance of the inductor Lp and the capacitor Cp. Therefore, the resistance element is not actually connected.

The inverter unit 42 is a circuit for compensating for a decrease in amplitude due to loss in the LC tank unit 41 and maintaining oscillation. The inverter unit 42 includes inverters INV1 and INV2. The input of inverter INV1 is connected to output node OUTB. The output of inverter INV1 is connected to output node OUTT. The input of inverter INV2 is connected to output node OUTT. The output of inverter INV2 is connected to output node OUTB. The inverter unit 42 is realized by a MIS (Metal-Insulator-Semiconductor) transistor on a silicon substrate. Since the MIS transistor generates noise, in FIG. 9, the noise of the MIS transistor is indicated by a current noise source | In | ² .

The oscillation frequency of the LC oscillator 400 is determined by the inductance value of the inductor Lp and the capacitance value of the capacitor Cp. Therefore, stable oscillation can be obtained as compared with an oscillator composed of only active elements. However, the oscillation frequency in the LC oscillator varies depending on the noise generated by the constituent elements. As this noise source, there are thermal noise generated by the resistor Rp and current noise source | In | ² of the MIS transistor. The fluctuation of the oscillation frequency of the LC oscillator is observed as phase noise.

FIG. 10 is a graph showing the dependence of phase noise on the offset frequency fo of a general LC oscillator. As shown in FIG. 10, the phase noise on the low frequency side decreases in proportion to 1 / fo ³ (broken line NL). On the other hand, the phase noise on the high frequency side decreases in proportion to 1 / fo ² (broken line NH). The noise on the low frequency side is mainly due to 1 / f noise generated by the MIS transistor. The noise on the high frequency side is caused by the thermal noise of the series resistance of the inductor.

  As a technique for reducing noise generated by the MIS transistor, a Class-C LC oscillator has been proposed (Non-Patent Document 1). The configuration of the Class-C type LC oscillator will be described in comparison with a conventional LC oscillator. FIG. 11A is a circuit diagram showing a basic configuration of a conventional LC oscillator 500. As shown in FIG. 11A, in the conventional LC oscillator 500, one ends of the inductors LB and LT are connected to a fixed potential. The other end of the inductor LB is connected to the drain of the MIS transistor M11. The other end of the inductor LT is connected to the drain of the MIS transistor M12. The source of the MIS transistor M11 and the source of the MIS transistor M12 are connected to the drain of the MIS transistor MCN that is a current source. The gate terminal of the MIS transistor M11 is directly connected to the output node OUTT (the drain of the MIS transistor M12). The gate terminal of the MIS transistor M12 is directly connected to the output node OUTB (the drain of the MIS transistor M11). The drain of the MIS transistor MCN is connected to the ground. The control voltage VREF is input to the gate of the MIS transistor MCN. Variable capacitors Cv11 and Cv12 are connected in series between the output node OUTT and the output node OUTB. A control voltage VCNT is input to a connection point between the variable capacitor Cv1 and the variable capacitor Cv2.

  FIG. 11B is a circuit diagram showing a basic configuration of a Class-C type LC oscillator 600. The Class-C type LC oscillator 600 is obtained by adding resistors RG11 and RG12 and coupling capacitors CG11 and CG12 to the conventional LC oscillator 500. The coupling capacitor CG11 is connected between the gate of the MIS transistor M11 and the output node OUTT. The coupling capacitor CG12 is connected between the gate of the MIS transistor M12 and the output node OUTB. The resistor RG11 is connected between the gate of the MIS transistor M11 and a node to which the bias voltage VBIAS is supplied. The resistor RG12 is connected between the gate of the MIS transistor M12 and a node to which the bias voltage VBIAS is supplied. Since the other configuration of the Class-C type LC oscillator 600 is the same as that of the conventional LC oscillator 500, description thereof is omitted.

  Both the conventional LC oscillator 500 and the Class-C LC oscillator 600 use only n-type MIS transistors, and do not use p-type MIS transistors. Hereinafter, an LC oscillator composed only of an n-type MIS transistor is referred to as an n-type LC oscillator.

  FIG. 12 is a graph showing voltage waveforms and current waveforms of the conventional LC oscillator 500 and the Class-C LC oscillator 600. FIG. 12 shows temporal changes in the current flowing through the MIS transistor M1 and the voltages at the output nodes OUTT and OUTB. Both the conventional LC oscillator 500 and the Class-C LC oscillator 600 are differential circuits. Therefore, the voltage waveform at the output node OUTT and the voltage waveform at the output node OUTB are inverted. Here, when the voltage waveform of the output node OUTT and the voltage waveform of the output node OUTB intersect, the voltage VT of the output node OUTT and the voltage VB of the output node OUTB become equal. At this time, in terms of logic, the output transitions from H to L or from L to H. This timing shift is observed as phase noise.

  Each noise source in the circuit of the LC oscillator always emits noise. In particular, noise generated when VT = VB has a greater contribution to phase noise than noise generated at other timings.

  In the conventional LC oscillator 500, the gate voltage and the drain voltage of the MIS transistor M11 are equal when VT = VB. Similarly, the gate voltage and the drain voltage of the MIS transistor M12 when VT = VB are equal. Under this bias condition, the MIS transistors M11 and M12 operate in the saturation region, so noise in the saturation operation is added to the output.

  On the other hand, in the Class-C type LC oscillator 600, the gate voltage and the drain voltage of the MIS transistor M11 are different when VT = VB. Similarly, the gate voltage and the drain voltage of the MIS transistor M12 when VT = VB are different. In this case, the gate bias of the MIS transistors M11 and M12 is set so that both the MIS transistors M11 and M12 are turned off. As a result, the MIS transistors M11 and M12 do not emit channel noise, which is the main noise of the MIS transistor. Therefore, noise observed at the output of the Class-C type LC oscillator 600 can be reduced.

  In the conventional LC oscillator 500, a current flows when VT = VB. On the other hand, in the Class-C type LC oscillator 600, no current flows when VT = VB. In other words, in the Class-C type LC oscillator 600, noise can be reduced by deepening the bias of the MIS transistor and performing a class C (Class-C) operation.

  Next, a CMOS type LC oscillator (hereinafter, referred to as a “COMS-LC oscillator”) will be described. In the CMOS-LC oscillator type, since the signal amplitude does not exceed the power supply voltage, the problem of withstand voltage in the fine MIS transistor can be avoided. In addition, there is an advantage that phase noise when the same current flows can be reduced as compared with the n-type LC oscillator.

  FIG. 13 is a circuit diagram showing a basic configuration of a conventional CMOS-LC oscillator 700. In the conventional CMOS-LC oscillator 700, the source of the p-type MOS transistor MC2 is connected to a fixed potential. The drain of the p-type MOS transistor MC2 is connected to the source of the p-type MOS transistor M23 and the source of the p-type MOS transistor M24. The control voltage VREF is input to the gate terminal of the p-type MOS transistor MC2. The gate terminal of p-type MOS transistor M23 is connected to output node OUTT (that is, the drain of p-type MOS transistor M24). The gate terminal of p-type MOS transistor M24 is connected to output node OUTB (that is, the drain of p-type MOS transistor M23).

  Variable capacitors (varactors) Cv11 and Cv12 are connected in series between the output node OUTT and the output node OUTB. An inductor L11 is further connected between the output node OUTT and the output node OUTB. The inductor L11 and the variable capacitors Cv11 and Cv12 connected in parallel constitute a resonance circuit. The resonance frequency of the resonance circuit is adjusted by changing the control voltage VCNT at the connection point between the variable capacitor Cv11 and the variable capacitor Cv12.

  The drain of n-type MOS transistor M21 is connected to output node OUTT. The drain of n-type MOS transistor M22 is connected to output node OUTB. The source of the n-type MOS transistor M21 and the source of the n-type MOS transistor M22 are connected to the ground.

  FIG. 14 is a circuit diagram showing a basic configuration of a Class-C type CMOS-LC oscillator 800. The Class-C type LC oscillator 800 is obtained by adding resistors RG11-14 and coupling capacitors CG11-14 to the conventional CMOS-LC oscillator 700. The coupling capacitor CG11 is connected between the gate of the n-type MOS transistor M21 and the output node OUTT. The coupling capacitor CG12 is connected between the gate of the n-type MOS transistor M22 and the output node OUTB. The coupling capacitor CG13 is connected between the gate of the p-type MOS transistor M23 and the output node OUTB. The coupling capacitor CG14 is connected between the gate of the p-type MOS transistor M24 and the output node OUTB. Resistor RG11 is connected between the gate of n-type MOS transistor M21 and a node supplied with bias voltage VBIASn. The resistor RG12 is connected between the gate of the n-type MOS transistor M22 and a node to which the bias voltage VBIASn is supplied. Resistor RG13 is connected between the gate of p-type MOS transistor M23 and a node to which bias voltage VBIASp is supplied. Resistor RG14 is connected between the gate of p-type MOS transistor M24 and a node to which bias voltage VBIASp is supplied. Since the other configuration of the Class-C type LC oscillator 800 is the same as that of the conventional CMOS-LC oscillator 700, description thereof is omitted.

  Patent Document 1 discloses an example of a semiconductor integrated circuit device that supplies a bias voltage to both a p-type MOS transistor pair and a type MOS transistor pair, similar to the Class-C type LC oscillator 800 shown in FIG. ing.

JP 2009-284329 A

"A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc / Hz", ISSCC Tech. Dig., 2008, pp474-475

  Although the Class-C type LC oscillator 600 can reduce noise, there is a problem that oscillation cannot be started. Hereinafter, a problem that oscillation cannot be started in the Class-C type LC oscillator 600 will be described. At the moment when the power of the Class-C type LC oscillator 600 is turned on, the Class-C type LC oscillator 600 does not oscillate. Therefore, VT = VB. In order to start oscillation from this state, a slight potential difference needs to be generated between the output node OUTT and the output node OUTB due to some factor (noise, variation, etc.). The Class-C type LC oscillator 600 oscillates by amplifying this minute potential difference by the gain of the MIS transistor.

  However, in the Class-C type LC oscillator 600, the MIS transistors M11 and M12 are turned off under the bias condition of VT = VB. Therefore, the gain of the MIS transistor cannot be obtained and oscillation cannot be started. For this reason, in a normal Class-C type LC oscillator, it is necessary to add a starter circuit for starting oscillation or to change the bias voltage only at the start of oscillation. Once oscillation is started, oscillation can be continued due to inertia due to the magnetic energy stored in inductors LT and LB, even if there is no gain when VT = VB.

  Further, it is necessary to supply separate bias voltages VBIASn and VBIASp to the normal Class-C type CMOS-LC oscillator 800, n-type MOS transistor and p-type MOS transistor. That is, since two bias power supply circuits are required, the increase in chip area and power consumption due to the bias power supply circuit is large.

  An oscillation circuit according to one embodiment of the present invention includes a tank circuit including at least a capacitor and an inductor connected in parallel between a first output node and a second output node, the first output node, and the first output node. A first inverter connected between the two output nodes, a second inverter whose input terminal is connected to the output terminal of the first inverter, and whose output terminal is connected to the input terminal of the first inverter. An inverter, wherein the first inverter has a first conductivity type first MIS transistor connected between the first voltage source and the first output node, and the first voltage source. And a second MIS transistor having a second conductivity type different from the first conductivity type connected between a second voltage source having a different voltage and the first output node, and The inverter includes the first voltage source and the second voltage source. A third MIS transistor of the first conductivity type connected between the second voltage source and the second output node, and a third MIS transistor of the first conductivity type connected between the second voltage source and the second output node. A control terminal of the first MIS transistor is directly connected to the second output node, and a control terminal of the third MIS transistor is connected to the first output node. The control terminal of the second MIS transistor is directly connected to the second output node via a first capacitor element, and a third voltage source via the first resistor element. And the control terminal of the fourth MIS transistor is connected to the first output node via a second capacitor element and to the third voltage source via a second resistor element. To be connected. In the oscillation circuit which is one embodiment of the present invention, the second and fourth transistors are connected to an output node through a capacitor. Furthermore, a bias voltage (third voltage source) may be supplied only to the second and fourth transformers. Thereby, noise can be effectively suppressed while reducing the circuit area.

  According to the present invention, an oscillation circuit that is small and excellent in noise suppression can be provided.

1 is a circuit diagram showing a basic configuration of an oscillation circuit 100 according to a first embodiment. It is a block diagram which shows the model of the inductor used by simulation. It is a circuit diagram which shows the equivalent circuit of the inductor used by simulation. The graph which shows the frequency characteristic of series inductance Ls and series resistance Rs. 7 is a graph showing temporal changes in gate voltage and drain voltage of a conventional CMOS-LC oscillator 700. 7 is a graph showing temporal changes in gate voltage and drain voltage of a Class-C type CMOS-LC oscillator 800. 3 is a graph showing temporal changes in gate voltage and drain voltage of an oscillation circuit 100. It is a graph which shows the offset frequency fo dependence of the simulation value of the phase noise of the oscillation circuit 100 and the conventional type COM-LC oscillator 700. FIG. 3 is a block diagram showing a configuration of an oscillation circuit 200 according to a second exemplary embodiment. FIG. 6 is a block diagram showing a configuration of an oscillation circuit 300 according to a third exemplary embodiment. It is a block diagram which shows the model of the normal LC oscillator 400 formed on a silicon substrate. It is a graph which shows the dependence of the phase noise with respect to the offset frequency fo of a general LC oscillator. 3 is a circuit diagram showing a basic configuration of a conventional LC oscillator 500. FIG. 2 is a circuit diagram showing a basic configuration of a Class-C type LC oscillator 600. FIG. 6 is a graph showing voltage waveforms and current waveforms of a conventional LC oscillator 500 and a Class-C LC oscillator 600. 6 is a circuit diagram showing a basic configuration of a conventional CMOS-LC oscillator 700. FIG. 3 is a circuit diagram showing a basic configuration of a Class-C type CMOS-LC oscillator 800. FIG.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a basic configuration of an oscillation circuit 100 according to the first embodiment of the present invention. The oscillation circuit 100 includes an inverter 1, an inverter 2, a tank circuit (LC tank unit) 3, a p-type MIS transistor MC, coupling capacitors CG1 and CG2, and resistors RG1 and RG2. The inverter 1 and the inverter 2 have their inputs and outputs connected to each other. The tank circuit 3 is connected between the output of the inverter 1 and the output of the inverter 2.

  The inverter 1 includes an n-type MIS transistor M1 and a p-type MIS transistor M3. The source of the p-type MIS transistor M3 is connected to the power supply potential via the p-type MIS transistor MC. The drain of the p-type MIS transistor M3 is connected to the output node OUTB of the inverter 1. The source of the n-type MIS transistor M1 is connected to the ground. The drain of n-type MIS transistor M1 is connected to output node OUTB of inverter 1.

  The gate terminal of the p-type MIS transistor M3 is connected to the output node OUTT of the inverter 2. The gate terminal of the n-type MIS transistor M1 is connected to the output node OUTT of the inverter 2 through the coupling capacitor CG1. Further, the bias voltage VBIAS is applied to the gate terminal of the n-type MIS transistor M1 via the resistor RG1.

  The inverter 2 includes an n-type MIS transistor M2 and a p-type MIS transistor M4. The source of the p-type MIS transistor M4 is connected to the power supply potential via the p-type MIS transistor MC. The drain of the p-type MIS transistor M4 is connected to the output node OUTT of the inverter 2. The source of the n-type MIS transistor M2 is connected to the ground. The drain of n-type MIS transistor M2 is connected to output node OUTT of inverter 2.

  The gate terminal of the p-type MIS transistor M4 is connected to the output node OUTB of the inverter 1. The gate terminal of the n-type MIS transistor M2 is connected to the output node OUTB of the inverter 1 through the coupling capacitor CG2. Further, a bias voltage VBIAS is applied to the gate terminal of the n-type MIS transistor M2 via the resistor RG2.

  The tank circuit 3 includes an inductor L1 and variable capacitors (varactors) Cv1 and Cv2. The inductor L1 is connected between the output node OUTT and the output node OUTB. The variable capacitors Cv1 and Cv2 are connected in parallel with the inductor L1 between the output node OUTT and the output node OUTB. The variable capacitance can be realized on the silicon substrate by the gate capacitance of the MIS transistor and the junction capacitance of the source / drain portion. The inductor L1 and the variable capacitors Cv1 and Cv2 connected in parallel constitute a resonance circuit (LC tank). The resonance frequency in the tank circuit 3 is adjusted by changing the control voltage VCNT at the connection point between the variable capacitor Cv1 and the variable capacitor Cv2.

  A control voltage VREF is applied to the gate terminal of the p-type MIS transistor MC. The p-type MIS transistor MC operates as a current source controlled by the control voltage VREF.

  As described above, the gate terminal of the p-type MIS transistor M3 is directly connected to the output node OUTT. The gate terminal of the p-type MIS transistor M4 is directly connected to the output node OUTB. On the other hand, the gate terminal of the n-type MIS transistor M1 is connected to the output node OUTT via the coupling capacitor CG1. The gate terminal of the n-type MIS transistor M2 is connected to the output node OUTB via the coupling capacitor CG2. Therefore, the bias voltage VBIAS at the gate terminal of the n-type MIS transistor M1 can be set to a value different from the voltage at the output node OUTT. Similarly, the bias voltage VBIAS at the gate terminal of the n-type MIS transistor M2 can be set to a value different from the voltage at the output node OUTB.

  In the oscillation circuit 100, the n-type MIS transistor portion has a Class-C configuration, and the p-type MIS transistor portion has a normal inverter configuration. Thereby, one bias control voltage can be omitted as compared with the Class-C type CMOS-LC oscillator 800 shown in FIG. Therefore, according to the oscillation circuit 100, the chip area and power consumption of the bias power supply circuit can be reduced.

  In the oscillation circuit 100, only the n-type MIS transistor performs the Class-C operation. The adoption of the Class-C configuration is effective in reducing the influence of noise generated by the MIS transistor, particularly 1 / f noise. In general, the 1 / f noise of the n-type MIS transistor is larger than the 1 / f noise of the p-type MIS transistor. Therefore, when only the n-type MIS transistor portion has the Class-C type configuration, the noise is not significantly different from the noise when both the n-type and p-type MIS transistors have the Class-C type configuration. Therefore, noise from the MIS transistor can be effectively suppressed by making only the n-type MIS transistor portion a Class-C type configuration.

  Furthermore, by using a p-type MIS transistor as a normal inverter circuit, it is possible to solve the problem that it is difficult to start oscillation, which is a drawback of the Class-C type LC oscillator. That is, since the gain is obtained on the p-type MIS transistor side even when the voltage of the output node OUTT and the voltage of the output node OUTB are the same, a minute signal at the initial stage of oscillation can be effectively amplified.

  Therefore, according to the oscillation circuit 100, it is possible to provide an oscillation circuit that can easily oscillate while suppressing noise.

  Next, the operation of the oscillation circuit 100 is shown by circuit simulation. In this simulation, the circuit characteristics of the conventional CMOS-LC oscillator 700 shown in FIG. 13, the Class-C CMOS-LC oscillator 800 shown in FIG. 14, and the oscillation circuit 100 were calculated by the circuit simulator SPICE. In this simulation, a MIS transistor by a 90 nm node CMOS process was assumed. It is assumed that the inductor can be realized by a 90 nm node CMOS process in this process. FIG. 2 is a configuration diagram showing an inductor model used in the simulation. As shown in FIG. 2, this inductor has a structure in which inductors composed of three wiring layers are connected in series by three turns. The wiring layers are appropriately connected by vias or the like. The lead line under the inductor is connected to the output node OUTT and the output node OUTB.

  FIG. 3 is a circuit diagram showing an equivalent circuit of an inductor used in the simulation. FIG. 3 shows an apparent series inductance Ls and series resistance Rs. A capacitor Csub1 and a resistor Rsub1 are connected in series between one end of the series inductance Ls and the ground. A capacitor Csub2 and a resistor Rsub2 are connected in series between one end of the series resistor Rs and the ground.

  FIG. 4 is a graph showing frequency characteristics of the series inductance Ls and the series resistance Rs. The power supply voltage in this simulation was 1V.

  FIG. 5A is a graph showing temporal changes in the gate voltage and drain voltage of the conventional CMOS-LC oscillator 700. FIG. 5B is a graph showing temporal changes in the gate voltage and the drain voltage of the laser-C type CMOS-LC oscillator 800. FIG. 5C is a graph showing temporal changes in the gate voltage and drain voltage of the oscillation circuit 100. The conventional CMOS-LC oscillator 700, the Class-C type CMOS-LC oscillator 800, and the oscillation circuit 100 oscillate at about 20 GHz. In the conventional CMOS-LC oscillator 700, the gate voltage and the drain voltage are equal. In the oscillation circuit 100, the gate voltage can be adjusted by adjusting the bias voltage VBIAS. Here, the maximum value of the gate voltage of the MIS transistors M1 and M2 is set to be about 0.1 V lower than the drain voltage. Therefore, the time during which the MIS transistors M1 and M2 are turned off is longer than that in the conventional CMOS-LC oscillator 700.

  That is, the bias voltage VBIAS supplied to the gate terminals of the MIS transistors M1 and M2 is set lower than the DC offset voltage of the output nodes OUTT and OUTB. Thereby, the influence of the noise generated from the MISFET can be reduced.

  FIG. 6 is a graph showing the offset frequency fo dependence of the simulation value of the phase noise of the oscillation circuit 100 and the conventional COMS-LC oscillator 700. The phase noise of the conventional COMS-LC oscillator 700 has an inflection point in the vicinity where the offset frequency fo is about 100 kHz.

The phase noise of the conventional COMS-LC oscillator 700 decreases at a slope of 1 / fo ² with respect to the offset frequency on the higher frequency side than the inflection point. The phase noise in this region is mainly due to thermal noise. Thermal noise is generated by parasitic resistance of passive elements such as inductors or MIS transistors. Since the inductor has a large series resistance in a small-area LC oscillator, the cause of noise here is mainly the parasitic resistance of the inductor.

On the lower frequency side than the inflection point, the frequency decreases with a slope of 1 / fo ³ with respect to the offset frequency. The phase noise in this region is mainly due to 1 / f noise. Passive elements do not emit 1 / f noise. Therefore, 1 / f noise is generated by the MIS transistor.

  When comparing the oscillation circuit 100 and the conventional COMS-LC oscillator 700, the noise of the oscillation circuit 100 is small in the region on the lower frequency side than the inflection point. It can be seen that there is no difference between the two in the low frequency region from the inflection point.

  As described above, the Class-C operation can reduce the influence of noise generated by the MIS transistor, but cannot reduce the noise of the passive element. FIG. 6 shows this tendency. As can be seen from FIG. 6, according to the oscillation circuit 100, it is possible to effectively reduce noise in a region where noise generated by the MIS transistor is dominant.

Embodiment 2
Next, an oscillation circuit according to the second embodiment of the present invention will be described. FIG. 7 is a block diagram of a configuration of the oscillation circuit 200 according to the second embodiment. The oscillation circuit 200 includes the oscillation circuit 100, the amplitude detection circuit 21, and the voltage source 22 shown in FIG. Output nodes OUTT and OUTB of the oscillation circuit 100 are connected to the input of the amplitude detection circuit 21. The amplitude detection circuit 21 outputs a detection signal VAMP corresponding to the voltages of the output nodes OUTT and OUTB to the voltage source 22. The output VAMP changes monotonously with respect to the voltage amplitude of the output nodes OUTT and OUTB. For example, the output VAMP increases when the voltage amplitude of the output nodes OUTT and OUTB is large, and decreases when the voltage amplitude is small. Alternatively, the detection signal VAMP has a low voltage when the voltage amplitude of the output nodes OUTT and OUTB is large, and a high voltage when the voltage amplitude is small.

  In this configuration, the amplitude fluctuation of the output nodes OUTT and OUTB is feedback-controlled. Therefore, according to this configuration, the amplitude fluctuation of the output nodes OUTT and OUTB can be effectively suppressed.

Embodiment 3
Next, an oscillation circuit according to Embodiment 3 of the present invention will be described. FIG. 8 is a block diagram of a configuration of the oscillation circuit 300 according to the third embodiment. The oscillation circuit 300 has a configuration in which a comparator 31 is added to the oscillation circuit 200. The detection signal VAMP of the amplitude detection circuit 21 is input to the non-inverting input terminal of the comparator 31. The reference voltage REFBIAS is input to the inverting input terminal of the comparator 31. The comparator 31 outputs a comparison signal VCMP, which is a comparison result between the detection signal VAMP and the reference voltage REFBIAS, to the voltage source 22. Since the other configuration of the oscillation circuit 300 is the same as that of the oscillation circuit 200, the description thereof is omitted.

  The oscillation circuit 300 reduces the bias voltage VBIAS if the voltage amplitude of the output nodes OUTT and OUTB is greater than a certain value determined by the reference voltage REFBIAS. On the other hand, if the voltage amplitude of the output nodes OUTT and OUTB is smaller than a constant value determined by the reference voltage REFBIAS, the bias voltage VBIAS is increased. As a result, the voltage amplitude of the output nodes OUTT and OUTB can be set to a constant value determined by the reference voltage REFBIAS. Therefore, according to the oscillation circuit 300, it is possible to effectively suppress amplitude fluctuation due to variations in MIS transistors.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the variable capacitors Cv1 and Cv2 in the oscillation circuit 100 shown in FIG. 1 can be fixed capacitors.

  Further, the tank circuit 3 in FIG. 1 is merely an example. Therefore, it is needless to say that the tank circuit 3 can be replaced with a tank circuit having another configuration.

DESCRIPTION OF SYMBOLS 1, 2 Inverter 3 Tank circuit 21 Amplitude detection circuit 22 Voltage source 31 Comparator 41 LC tank part 42 Inverter part 100, 200, 300 Oscillation circuit 400 LC oscillator 500 Conventional LC oscillator 500
600 Class-C type LC oscillator 700 Conventional CMOS-LC oscillator 800 Class-C type CMOS-LC oscillator CG1, CG2, CG11-14 Coupling capacitance Cp, Csub1, Csub2 Capacitance Cv1, Cv2, Cv11, Cv12 Variable capacitance INV1, INV2 Inverters L1, L11, LB, Lt, Lp Inductors Ls Series inductance M1, M2 n-type MIS transistors M11, M12, MCN MIS transistors M3, M4, MC p-type MIS transistors M21, M22 n-type MOS transistors M23, M24, MC2 p Type MOS transistor OUTT, OUTB Output node REFIAS Reference voltage RG1, RG2, RG11-14, Rp, Rsub1, Rsub2 Resistor Rs Series resistance VAMP Detection signal VBI AS, VBIASn, VBIASp Bias voltage VCMP Comparison signal VCNT, VREF Control voltage

Claims (6)

A tank circuit having at least a capacitor and an inductor connected in parallel between the first output node and the second output node;
A first inverter connected between the first output node and the second output node;
A second inverter having an input terminal connected to an output terminal of the first inverter and an output terminal connected to an input terminal of the first inverter;
The first inverter is
A first MIS transistor of a first conductivity type connected between a first voltage source and the first output node;
A second MIS transistor of a second conductivity type different from the first conductivity type connected between a second voltage source having a voltage different from that of the first voltage source and the first output node; Prepared,
The second inverter is
A third MIS transistor of the first conductivity type connected between the first voltage source and the second output node;
A second MIS transistor of the second conductivity type connected between the second voltage source and the second output node;
The control terminal of the first MIS transistor is directly connected to the second output node,
The control terminal of the third MIS transistor is directly connected to the first output node,
The control terminal of the second MIS transistor is connected to the second output node via a first capacitive element, and is connected to a third voltage source via a first resistive element,
The control terminal of the fourth MIS transistor is connected to the first output node via a second capacitive element, and is connected to the third voltage source via a second resistance element.
Oscillator circuit. The voltage of the third voltage source is lower than the DC offset voltage of the first output node and the DC offset voltage of the second output node,
The oscillation circuit according to claim 1. An amplitude detection circuit for outputting a detection signal corresponding to the output amplitude of the first output node and the output amplitude of the second output node;
The third voltage source changes a voltage of the third voltage source according to the detection signal,
The oscillation circuit according to claim 1 or 2. The detection circuit outputs a voltage signal corresponding to a difference between a voltage of the first output node and a voltage of the second output node as the detection signal.
The oscillation circuit according to claim 3. A comparator that compares the voltage signal output as the detection signal with a reference voltage supplied from the outside and outputs a comparison result to the third voltage source;
The third voltage source increases the voltage of the third voltage source in response to an increase in the voltage signal.
The oscillation circuit according to claim 4. The first MIS transistor and the third MIS transistor are p-type MOS transistors,
The second MIS transistor and the fourth MIS transistor are n-type MOS transistors,
The oscillation circuit as described in any one of Claims 1 thru | or 5.

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