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JP2011249744A - Printed circuit board and method of manufacturing the same - Google Patents

Printed circuit board and method of manufacturing the same Download PDF

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Publication number
JP2011249744A
JP2011249744A JP2010175295A JP2010175295A JP2011249744A JP 2011249744 A JP2011249744 A JP 2011249744A JP 2010175295 A JP2010175295 A JP 2010175295A JP 2010175295 A JP2010175295 A JP 2010175295A JP 2011249744 A JP2011249744 A JP 2011249744A
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Japan
Prior art keywords
layer
circuit board
printed circuit
metal substrate
circuit
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Pending
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JP2010175295A
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Japanese (ja)
Inventor
Jon-Kyun Park
キュン パク，ション
Sung Hyun Shin
ヒュン シン，サン
Kyan-Soo Kim
ス キム，キャン
Syong Mun Choi
ムン チョイ，ション
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Publication of JP2011249744A publication Critical patent/JP2011249744A/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0256—Electrical insulation details, e.g. around high voltage areas
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C26/00—Coating not provided for in groups C23C2/00 - C23C24/00
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/18—After-treatment, e.g. pore-sealing
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/18—After-treatment, e.g. pore-sealing
    • C25D11/20—Electrolytic after-treatment
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/18—After-treatment, e.g. pore-sealing
    • C25D11/24—Chemical after-treatment
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13034—Silicon Controlled Rectifier [SCR]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor

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  • Chemical & Material Sciences (AREA)
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  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electrochemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a printed circuit board, which can improve heat radiation performance and can prevent an electric short circuit from occurring between a circuit wiring of a circuit layer formed on the printed circuit board because a sol-gel layer is formed between the circuit wiring of the circuit layer and which can increase the heat radiation effect because an anodic oxide layer is removed from that one side of a metal substrate on which the a circuit layer is not provided, and to provide a method of manufacturing the same.SOLUTION: A printed circuit board according to the present invention includes: a metal substrate 10; an anodic oxide layer 20 formed by anodizing the metal substrate 10; circuit layers 30, 31 formed on the anodic oxide layer 20; and a first sol-gel layer 50 formed by applying a photocatalytic material between circuit wiring of the circuit layers 30, 31, in which photocatalytic material is exposed, and then curing the applied photocatalytic material.

Description

本発明は、プリント基板およびその製造方法に関する。   The present invention relates to a printed circuit board and a method for manufacturing the same.

最近、信号処理に必要な半導体技術の急速な発展に伴い、半導体素子が目覚ましい成長を遂げている。これと共に、半導体素子などの電子素子をプリント基板に予め実装してパッケージとして構成するＳＩＰ（Ｓｙｓｔｅｍ ｉｎ ｐａｃｋａｇｅ）、ＣＳＰ（Ｃｈｉｐ ｓｉｚｅｄ ｐａｃｋａｇｅ）、ＦＣＰ（Ｆｌｉｐ ｃｈｉｐ ｐａｃｋａｇｅ）などの半導体パッケージに対する開発が盛んに行われている。最近では、半導体技術の発展によってダイ（ｄｉｅ）の大きさが縮小しており、これにより半導体素子などを実装するためのパッケージ用基板の大きさも縮小して、電子素子との電気的接続のために基板に形成されるボンドパッド（Ｂｏｎｄ ｐａｄ）を実現することが可能な面積も減っている実情である。   Recently, with the rapid development of semiconductor technology required for signal processing, semiconductor devices have achieved remarkable growth. At the same time, development of semiconductor packages such as SIP (System in Package), CSP (Flip Chip Package), and FCP (Flip Chip Package), in which electronic elements such as semiconductor elements are pre-mounted on a printed circuit board and configured as a package, is actively conducted. Has been done. Recently, due to the development of semiconductor technology, the size of a die has been reduced, and thus the size of a package substrate for mounting a semiconductor device or the like has also been reduced, for electrical connection with an electronic device. In fact, the area where bond pads formed on the substrate can be realized is also reduced.

電力素子、例えば、シリコン制御整流器、電力トランジスタ、絶縁されたゲートバイポーラトランジスタ、ＭＯＳトランジスタ、電力整流器、電力レギュレータ、インバータ、コンバータ、またはこれらが組み合わせられた高電力半導体チップは、３０Ｖ〜１０００Ｖ或いはそれ以上の電圧で動作するように設計される。高電力半導体チップは、論理素子またはメモリ素子などの低電力半導体チップとは異なり高電圧で動作するので、高電力半導体チップから発生する熱の優れた放出能力と高圧における絶縁能力が要求される。   Power devices such as silicon controlled rectifiers, power transistors, insulated gate bipolar transistors, MOS transistors, power rectifiers, power regulators, inverters, converters, or high power semiconductor chips that combine these are 30V to 1000V or more Designed to operate at a voltage of Since a high power semiconductor chip operates at a high voltage unlike a low power semiconductor chip such as a logic element or a memory element, it is required to have an excellent ability to release heat generated from the high power semiconductor chip and an insulation ability at high pressure.

図１は、従来の高電力半導体パッケージ１００の構造を図式的に示す断面図である。   FIG. 1 is a cross-sectional view schematically showing the structure of a conventional high power semiconductor package 100.

従来の高電力半導体パッケージ１００の構造は、基板１４０上に高電力半導体チップ１５０ａまたは低電力半導体チップ１５０ｂが搭載され、高電力半導体チップ１５０ａおよび低電力半導体チップ１５０ｂの一面には対応する回路層１３０に電気的に接続されるボンディングパッド１５１が形成される。   The conventional high power semiconductor package 100 has a structure in which a high power semiconductor chip 150a or a low power semiconductor chip 150b is mounted on a substrate 140, and a corresponding circuit layer 130 is provided on one surface of the high power semiconductor chip 150a and the low power semiconductor chip 150b. Bonding pads 151 are formed which are electrically connected to each other.

高電力半導体チップ１５０ａまたは低電力半導体チップ１５０ｂのボンディングパッド１５１は、一般にワイヤー１７０によって回路層１３０に電気的に接続される。ワイヤーボンディング工程の後、回路層１３０は半導体パッケージの外部端子の役割を果たすリードに接続される。しかる後に、ＥＭＣ（Ｅｐｏｘｙ ｍｏｌｄｉｎｇ ｐｒｏｃｅｓｓ）などのモールディング部材の注入工程が行われ、これにより高電力半導体パッケージ１００が完成される。   The bonding pad 151 of the high power semiconductor chip 150 a or the low power semiconductor chip 150 b is generally electrically connected to the circuit layer 130 by a wire 170. After the wire bonding process, the circuit layer 130 is connected to leads that serve as external terminals of the semiconductor package. Thereafter, a molding member injection process such as EMC (Epoxy molding process) is performed, whereby the high power semiconductor package 100 is completed.

一般に、高電力半導体パッケージは、動作の際に多くの熱を発生させるので、基底金属層１１０上に放熱板１８０が取り付けられて使用される。放熱板１８０は、通常、熱伝導率に優れた金属からなる。放熱板１８０は、耐熱グリースなどの接着部材１８５によって基底金属層１１０上に付着できる。   Generally, a high power semiconductor package generates a lot of heat during operation, and thus a heat sink 180 is attached to the base metal layer 110 for use. The heat sink 180 is usually made of a metal having excellent thermal conductivity. The heat sink 180 can be attached on the base metal layer 110 by an adhesive member 185 such as heat-resistant grease.

このような放熱板１８０を備えた従来の高電力半導体パッケージは、熱放出のための放熱板１８０を備えるために別途の基底金属層１１０が必要であり、放熱板１８０が備わることにより、構造上の厚さ制御が容易ではなく、小型化の実現が難しいという問題点があった。また、製造工程上でリードフレームを用いてチップを実装し、ワイヤーボンディングする工程の他にも、基底金属層１１０を接着し注入する工程などの複雑な工程が追加されるので、工程の迅速性および信頼性に問題が発生するおそれがあった。また、別途の基底金属層１１０の具備および接着部材１８５の必要性により、全体的な製造コストが増加する問題点があった。そして、基底金属層１１０による放熱効果のみでは限界があって、必要な放熱効果が十分実現できないという問題点があった。   The conventional high power semiconductor package including the heat sink 180 requires a separate base metal layer 110 in order to include the heat sink 180 for releasing heat. However, there is a problem that it is difficult to control the thickness, and it is difficult to realize downsizing. In addition to the process of mounting a chip using a lead frame and wire bonding in the manufacturing process, a complicated process such as a process of bonding and injecting the base metal layer 110 is added. In addition, there was a risk of problems in reliability. In addition, there is a problem in that the entire manufacturing cost increases due to the provision of the separate base metal layer 110 and the necessity of the adhesive member 185. Further, the heat dissipation effect by the base metal layer 110 is limited, and there is a problem that a necessary heat dissipation effect cannot be sufficiently realized.

また、パッケージ用プリント基板の場合、従来、放熱効果のためにアルミニウム基板に陽極酸化層を絶縁層として形成して使用したが、この場合、回路層の回路配線間の電気的短絡が発生する問題点があった。しかも、回路層の形成のための金属層の残留物、または陽極酸化工程でアルミニウム基板の添加物（Ｍｇ、Ｓｉ、Ｃｕなど）が析出される過程から発生する絶縁層の不安定状態による電気的短絡などが発生する問題点もあった。   In the case of printed circuit boards for packaging, conventionally, an anodized layer is formed as an insulating layer on an aluminum substrate for heat dissipation, but in this case, an electrical short circuit between circuit wirings in the circuit layer occurs. There was a point. In addition, the metal layer residue for forming the circuit layer, or the electrical state due to the unstable state of the insulating layer generated from the process of depositing the aluminum substrate additive (Mg, Si, Cu, etc.) in the anodizing process There was also a problem that a short circuit occurred.

したがって、本発明は、上述した従来の技術の問題点を解決するためのもので、その目的は、プリント基板に形成される回路層の回路配線の間にゾルゲル層を形成して放熱特性を向上させることができ、回路層の回路配線の間に発生する電気的短絡を防止することができるうえ、回路層の形成されていない金属基板の他面の陽極酸化層を除去することにより放熱効果を増加させることができるプリント基板およびその製造方法を提供することにある。   Therefore, the present invention is to solve the above-mentioned problems of the prior art, and its purpose is to improve the heat dissipation characteristics by forming a sol-gel layer between the circuit wirings of the circuit layer formed on the printed circuit board. In addition to preventing an electrical short circuit that occurs between the circuit wiring of the circuit layer, the heat dissipation effect can be achieved by removing the anodized layer on the other side of the metal substrate on which the circuit layer is not formed. It is an object of the present invention to provide a printed circuit board that can be increased and a method for manufacturing the same.

上記目的を達成するために、本発明の好適な実施例に係るプリント基板は、金属基板と、前記金属基板を陽極酸化処理（ａｎｏｄｉｚｉｎｇ）して形成される陽極酸化層と、前記陽極酸化層に形成される回路層と、前記陽極酸化層を露出させる、前記回路層の回路配線の間に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて形成される第１ゾルゲル層とを含んでなるものである。   In order to achieve the above object, a printed circuit board according to a preferred embodiment of the present invention includes a metal substrate, an anodized layer formed by anodizing the metal substrate, and an anodized layer. A first sol-gel layer formed by coating the circuit layer to be formed, exposing the anodized layer, coating the photocatalyst agent between the circuit wirings of the circuit layer, and then curing the coated photocatalyst agent; Is included.

ここで、光触媒剤は、アルミナまたは二酸化チタニウムであることが好ましい。   Here, the photocatalytic agent is preferably alumina or titanium dioxide.

また、前記陽極酸化層は、前記金属基板の一面および両側面にのみ形成されることが好ましい。   The anodized layer is preferably formed only on one side and both sides of the metal substrate.

本発明の好適な実施例に係るプリント基板の製造方法は、（Ａ）金属基板を準備する段階と、（Ｂ）前記金属基板の全面に陽極酸化処理を施して陽極酸化層を形成する段階と、（Ｃ）前記金属基板の一面に形成された前記陽極酸化層に回路層を形成する段階と、（Ｄ）前記陽極酸化層を露出させる、前記回路層の回路配線の間に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて第１ゾルゲル層を形成する段階とを含むものである。   A printed circuit board manufacturing method according to a preferred embodiment of the present invention includes: (A) preparing a metal substrate; and (B) forming an anodized layer by subjecting the entire surface of the metal substrate to anodization. (C) forming a circuit layer on the anodized layer formed on one surface of the metal substrate; and (D) coating the circuit wiring of the circuit layer with a photocatalyst agent to expose the anodized layer. And curing the coated photocatalytic agent to form a first sol-gel layer.

ここで、前記（Ｂ）段階では、前記金属基板の一面および両側面にのみ陽極酸化処理を施して陽極酸化層を形成することが好ましい。   Here, in the step (B), it is preferable that an anodic oxidation process is performed on only one surface and both side surfaces of the metal substrate to form an anodized layer.

また、前記（Ｃ）段階は、（Ｃ−１）前記陽極酸化層にシード層を形成する段階と、（Ｃ−２）前記シード層に電解メッキで回路メッキ層を形成する段階と、（Ｃ−３）前記回路メッキ層に回路パターンの形成のためにエッチングレジストを塗布した後、エッチングを行う段階と、（Ｃ−４）前記エッチングレジストを除去する段階とを含むことが好ましい。   The step (C) includes (C-1) a step of forming a seed layer on the anodized layer, (C-2) a step of forming a circuit plating layer on the seed layer by electrolytic plating, and (C -3) It is preferable to include a step of performing etching after applying an etching resist to the circuit plating layer for forming a circuit pattern, and (C-4) a step of removing the etching resist.

更に、前記（Ｃ）段階は、（Ｃ−１）前記陽極酸化層にシード層を形成する段階と、（Ｃ−２）前記シード層に回路パターンのためのメッキレジストを塗布する段階と、（Ｃ−３）前記シード層に回路メッキ層を形成する段階と、（Ｃ−４）前記メッキレジストを除去し、露出された前記シード層をエッチングする段階とを含むことが好ましい。   Further, the step (C) includes (C-1) a step of forming a seed layer on the anodized layer, (C-2) a step of applying a plating resist for a circuit pattern to the seed layer, Preferably, the method includes: C-3) forming a circuit plating layer on the seed layer; and (C-4) removing the plating resist and etching the exposed seed layer.

次に、前記（Ｄ）段階は、（Ｄ−１）前記金属基板の他面に形成された陽極酸化層に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて第２ゾルゲル層を形成する段階と、（Ｄ−２）前記第２ゾルゲル層を除去する段階と、（Ｄ−３）前記金属基板の他面に形成された前記陽極酸化層を除去する段階とを含むことが好ましい。   Next, in the step (D), (D-1) the anodized layer formed on the other surface of the metal substrate is coated with a photocatalyst agent, and then the coated photocatalyst agent is cured to form a second sol gel. Forming a layer; (D-2) removing the second sol-gel layer; and (D-3) removing the anodized layer formed on the other surface of the metal substrate. Is preferred.

前記光触媒剤は、アルミナまたは二酸化チタニウムあることが好ましい。   The photocatalytic agent is preferably alumina or titanium dioxide.

前記光触媒剤のコーティング処理は、スプレー噴射法、ディッピング（ｄｉｐｐｉｎｇ）法またはエアロゾル沈着法で行われることが好ましい。   The coating treatment of the photocatalytic agent is preferably performed by a spraying method, a dipping method, or an aerosol deposition method.

前記コーティング処理された光触媒剤を硬化させる段階は、１００℃〜２００℃の温度で行われることが好ましい。   The step of curing the coated photocatalytic agent is preferably performed at a temperature of 100C to 200C.

本発明によれば、金属基板に陽極酸化処理を施して形成した陽極酸化層を絶縁層として使用することにより、放熱特性を向上させる効果がある。   According to the present invention, the use of an anodized layer formed by anodizing a metal substrate as an insulating layer has an effect of improving heat dissipation characteristics.

また、本発明によれば、回路層の回路配線の間にゾルゲル層を形成することにより、従来の基板では適用が不可能であった高電圧のパッケージプリント基板の実現が可能な効果がある。   Further, according to the present invention, by forming the sol-gel layer between the circuit wirings of the circuit layer, there is an effect that it is possible to realize a high-voltage package printed board that cannot be applied to the conventional board.

そして、本発明によれば、回路層の回路配線の間にゾルゲル層を形成することにより、回路層の形成のための金属層の残留物、または陽極酸化工程でアルミニウム基板の添加物（Ｍｇ、Ｓｉ、Ｃｕなど）が析出される過程で発生する絶縁層の不安定を防止することができるという効果がある。   And according to the present invention, by forming a sol-gel layer between the circuit wirings of the circuit layer, the metal layer residue for forming the circuit layer, or the additive (Mg, There is an effect that instability of the insulating layer generated in the process of depositing Si, Cu, etc.) can be prevented.

更に、本発明によれば、陽極酸化層を形成するための陽極酸化処理の工程条件を変更することなく、ゾルコーティングの材料、厚さに応じて絶縁電圧を向上させることができるという効果がある。   Furthermore, according to the present invention, the insulation voltage can be improved according to the material and thickness of the sol coating without changing the process conditions of the anodizing treatment for forming the anodized layer. .

従来の高電力半導体パッケージの構造を図式的に示す断面図である。It is sectional drawing which shows the structure of the conventional high power semiconductor package typically. 本発明の第１実施例に係るプリント基板を示す断面図である。It is sectional drawing which shows the printed circuit board which concerns on 1st Example of this invention. 本発明の第２実施例に係るプリント基板を示す断面図である。It is sectional drawing which shows the printed circuit board which concerns on 2nd Example of this invention. 本発明の第３実施例に係るプリント基板の製造方法を工程順に示す工程断面図（１）である。It is process sectional drawing (1) which shows the manufacturing method of the printed circuit board which concerns on 3rd Example of this invention in process order. 本発明の第３実施例に係るプリント基板の製造方法を工程順に示す工程断面図（２）である。It is process sectional drawing (2) which shows the manufacturing method of the printed circuit board concerning 3rd Example of this invention in process order. 本発明の第３実施例に係るプリント基板の製造方法を工程順に示す工程断面図（３）である。It is process sectional drawing (3) which shows the manufacturing method of the printed circuit board concerning 3rd Example of this invention in process order. 本発明の第３実施例に係るプリント基板の製造方法を工程順に示す工程断面図（４）である。It is process sectional drawing (4) which shows the manufacturing method of the printed circuit board concerning 3rd Example of this invention in process order. 本発明の第３実施例に係るプリント基板の製造方法を工程順に示す工程断面図（５）である。It is process sectional drawing (5) which shows the manufacturing method of the printed circuit board concerning 3rd Example of this invention in process order. 本発明の第３実施例に係るプリント基板の製造方法を工程順に示す工程断面図（６）である。It is process sectional drawing (6) which shows the manufacturing method of the printed circuit board concerning 3rd Example of this invention in order of a process. 本発明の第３実施例に係るプリント基板の製造方法を工程順に示す工程断面図（７）である。It is process sectional drawing (7) which shows the manufacturing method of the printed circuit board which concerns on 3rd Example of this invention in process order. 本発明の第３実施例に係るプリント基板の製造方法を工程順に示す工程断面図（８）である。It is process sectional drawing (8) which shows the manufacturing method of the printed circuit board which concerns on 3rd Example of this invention in process order. 本発明の第４実施例に係るプリント基板の製造方法を工程順に示す工程断面図（１）である。It is process sectional drawing (1) which shows the manufacturing method of the printed circuit board which concerns on 4th Example of this invention in process order. 本発明の第４実施例に係るプリント基板の製造方法を工程順に示す工程断面図（２）である。It is process sectional drawing (2) which shows the manufacturing method of the printed circuit board which concerns on 4th Example of this invention in process order. 本発明の第４実施例に係るプリント基板の製造方法を工程順に示す工程断面図（３）である。It is process sectional drawing (3) which shows the manufacturing method of the printed circuit board which concerns on 4th Example of this invention in process order. 本発明の第４実施例に係るプリント基板の製造方法を工程順に示す工程断面図（４）である。It is process sectional drawing (4) which shows the manufacturing method of the printed circuit board which concerns on 4th Example of this invention to process order. 本発明の第４実施例に係るプリント基板の製造方法を工程順に示す工程断面図（５）である。It is process sectional drawing (5) which shows the manufacturing method of the printed circuit board which concerns on 4th Example of this invention in process order. 本発明の第４実施例に係るプリント基板の製造方法を工程順に示す工程断面図（６）である。It is process sectional drawing (6) which shows the manufacturing method of the printed circuit board which concerns on 4th Example of this invention in process order. 本発明の第４実施例に係るプリント基板の製造方法を工程順に示す工程断面図（７）である。It is process sectional drawing (7) which shows the manufacturing method of the printed circuit board which concerns on 4th Example of this invention in process order. 本発明の第４実施例に係るプリント基板の製造方法を工程順に示す工程断面図（８）である。It is process sectional drawing (8) which shows the manufacturing method of the printed circuit board concerning 4th Example of this invention in process order.

本発明の目的、特定の利点および新規の特徴は、添付図面に連関する以下の詳細な説明と好適な実施例からさらに明白になるであろう。   Objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and preferred embodiments when taken in conjunction with the accompanying drawings.

これに先立ち、本明細書および請求の範囲に使用された用語または単語は、通常的で辞典的な意味で解釈されてはならず、発明者が自分の発明を最善の方法で説明するために用語の概念を適切に定義することができるという原則に基づき、本発明の技術的思想に符合する意味と概念で解釈されなければならない。   Prior to this, terms or words used in the specification and claims should not be construed in a normal and lexical sense, so that the inventor best describes the invention. Based on the principle that the concept of terms can be appropriately defined, it should be interpreted with a meaning and concept consistent with the technical idea of the present invention.

本発明において、各図面の構成要素に参照番号を付加するにおいて、同一の構成要素については、他の図面上に表示されても、出来る限り同一の番号を付することに留意すべきであろう。また、「第１」、「第２」などの用語は一つの構成要素を他の構成要素から区別するために使用されるもので、構成要素が前記用語によって限定されない。なお、本発明を説明するにおいて、関連した公知の技術に対する具体的な説明が、本発明の要旨を無駄に乱すおそれがあると判断される場合、その詳細な説明は省略する。   In the present invention, it is to be noted that when reference numerals are added to components in each drawing, the same components are given the same numbers as much as possible even if they are displayed on other drawings. . Further, terms such as “first” and “second” are used to distinguish one component from other components, and the component is not limited by the terms. In the description of the present invention, when it is determined that a specific description of a related known technique may unnecessarily disturb the gist of the present invention, a detailed description thereof will be omitted.

以下、添付図面を参照して本発明の好適な実施例を詳細に説明する。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図２は、本発明の第１実施例に係るプリント基板を示す断面図である。   FIG. 2 is a cross-sectional view showing a printed circuit board according to the first embodiment of the present invention.

図２に示すように、本発明の第１実施例に係るプリント基板は、金属基板１０と、前記金属基板１０に陽極酸化処理を施して形成される陽極酸化層２０と、前記陽極酸化層２０に形成される回路層３０、３１と、前記陽極酸化層２０を露出させる、前記回路層３０、３１の回路配線の間に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて形成される第１ゾルゲル層５０とを含んでなるものである。   As shown in FIG. 2, the printed circuit board according to the first embodiment of the present invention includes a metal substrate 10, an anodized layer 20 formed by anodizing the metal substrate 10, and the anodized layer 20. The circuit layers 30 and 31 formed on the circuit layer 30 and the circuit wiring of the circuit layers 30 and 31 exposing the anodized layer 20 are coated with a photocatalyst agent, and then the coated photocatalyst agent is cured. The first sol-gel layer 50 to be formed is included.

金属基板１０は、陽極酸化処理によって陽極酸化層２０を形成することが可能な材質で形成され、放熱効果を同時に有する。金属基板１０は、アルミニウム、マグネシウムおよびチタニウムなどの金属材質で形成できるが、陽極酸化処理による陽極酸化層２０を形成することができ且つ放熱特性のある材質であれば特に限定されない。   The metal substrate 10 is formed of a material capable of forming the anodized layer 20 by anodization, and has a heat dissipation effect at the same time. The metal substrate 10 can be formed of a metal material such as aluminum, magnesium, and titanium, but is not particularly limited as long as the material can form the anodized layer 20 by anodizing treatment and has a heat dissipation characteristic.

陽極酸化層２０は、陽極酸化処理によって形成され、陽極酸化層２０は、金属基板１０を硫酸などの特定溶液内で陽極として作用させて金属基板１０の表面に酸化作用を促進させることにより、均一な厚さで人為的な酸化膜が生成されるようにして形成される。ここで、陽極酸化層２０の形成厚さは、陽極酸化処理の処理時間および程度によって決定され、陽極酸化処は、絶縁特性のための陽極酸化層２０を形成するために必要な範囲で行われる。   The anodic oxidation layer 20 is formed by an anodic oxidation treatment. The anodic oxidation layer 20 is made uniform by causing the metal substrate 10 to act as an anode in a specific solution such as sulfuric acid to promote the oxidation action on the surface of the metal substrate 10. It is formed in such a manner that an artificial oxide film is generated with a sufficient thickness. Here, the formation thickness of the anodic oxidation layer 20 is determined by the treatment time and degree of the anodic oxidation treatment, and the anodic oxidation treatment is performed within a range necessary for forming the anodic oxidation layer 20 for insulating characteristics. .

回路層３０、３１は、陽極酸化層２０に形成される。回路層３０、３１は、サブトラクティブ（ｓｕｂｔｒａｃｔｉｖｅ）またはアディティブ（ａｄｄｉｔｉｖｅ）方式によって形成でき、この他にも多様な方式で形成できる。   The circuit layers 30 and 31 are formed on the anodized layer 20. The circuit layers 30 and 31 may be formed by a subtractive or additive method, and may be formed by various other methods.

ゾルゲル層５０、５１は、陽極酸化層２０に形成される回路層３０、３１、および陽極酸化層２０を露出させる、回路層３０、３１の回路配線の間に、光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させることにより形成される。   The sol-gel layers 50 and 51 are coated with a photocatalytic agent between the circuit layers 30 and 31 formed on the anodized layer 20 and the circuit wiring of the circuit layers 30 and 31 that expose the anodized layer 20. It is formed by curing the coated photocatalytic agent.

ここで、ゾルゲル層５０、５１は、ゾルゲル（ｓｏｌ−ｇｅｌ）法によって積層される層である。ゾルゲル法とは、「ゾルゲルセラミックス（ｓｏｌ−ｇｅｌ ｄｅｒｉｖｅｄ ｃｅｒａｍｉｃｓ）」を製造する方法を意味する。特に、ゾルゲル法では、水とアルコキシドの割合、溶液のｐＨ、溶媒の種類および量などの様々な要素などにより反応速度の変化および最終構造物の構造変化が起こる。このようなゾルゲル法は、実験者によってそれぞれ異なる結果を得ることができるほど敏感な反応である。   Here, the sol-gel layers 50 and 51 are layers stacked by a sol-gel method. The sol-gel method means a method for producing “sol-gel derived ceramics”. In particular, in the sol-gel method, a change in the reaction rate and a change in the structure of the final structure occur depending on various factors such as the ratio of water and alkoxide, the pH of the solution, and the type and amount of the solvent. Such a sol-gel method is a reaction that is sensitive enough to obtain different results depending on the experimenter.

ゾルゲル層５０、５１の形成では、適切な温度、熱処理時の適切な昇温温度および冷却速度の調節が重要である。ここで、ゾル（ｓｏｌ）は、アルコール系の溶媒にナノセラミック粉末を分散させ、コートした後、熱処理する工程を経るが、この際、有機成分を除いたセラミック粉末のみをコートする。熱処理の後、コーティング処理されたゾルゲル層５０、５１は、一定の密着力を有し、最終動作の際に金属基板１０の破損問題を防止することができる。ゾルゲル層５０、５１のコーティング方法は、スプレー噴射法、ディッピング法またはエアロゾル沈着法である。ゾルゲル層５０、５１の形成の際に、溶媒として光処理剤を用いることができる。光触媒剤のコーティング処理後、コートされた光触媒剤を硬化させることにより、ゾルゲル層５０、５１を形成することができる。光触媒剤は、二酸化チタニウム（ＴｉＯ２）またはアルミナ（Ａｌ２Ｏ３）の材質で形成できる。ゾル硬化は、ゾルの有機成分を除去するためのもので、約１００℃〜２００℃の範囲内で行われることが好ましい。 In the formation of the sol-gel layers 50 and 51, it is important to adjust an appropriate temperature, an appropriate temperature rise during heat treatment, and a cooling rate. Here, the sol is obtained by dispersing the nanoceramic powder in an alcohol-based solvent and coating it, followed by a heat treatment step. At this time, only the ceramic powder excluding the organic component is coated. After the heat treatment, the coated sol-gel layers 50 and 51 have a constant adhesion, and can prevent the metal substrate 10 from being damaged during the final operation. The coating method of the sol-gel layers 50 and 51 is a spray injection method, a dipping method, or an aerosol deposition method. In forming the sol-gel layers 50 and 51, a phototreatment agent can be used as a solvent. After the photocatalytic agent coating treatment, the sol-gel layers 50 and 51 can be formed by curing the coated photocatalytic agent. The photocatalytic agent can be formed of titanium dioxide (TiO 2 ) or alumina (Al 2 O 3 ). The sol curing is for removing the organic component of the sol, and is preferably performed within a range of about 100 ° C to 200 ° C.

図３は、本発明の第２実施例に係るプリント基板を示す断面図である。   FIG. 3 is a sectional view showing a printed circuit board according to the second embodiment of the present invention.

図３に示すように、本発明の第２実施例に係るプリント基板は、金属基板１０と、前記金属基板１０に陽極酸化処理を施して形成される陽極酸化層２０と、前記陽極酸化層２０に形成される回路層３０、３１と、前記陽極酸化層２０を露出させる、前記回路層３０、３１の回路配線の間に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて形成された第１ゾルゲル層５０とを含み、前記陽極酸化層２０は、前記金属基板１０の回路層３０、３１が形成された一面および両側面にのみ形成されることを特徴とする。したがって、回路層３０、３１の形成されていない金属基板１０の他面に陽極酸化層２０を形成せず、金属基板１０を露出させることにより、放熱効果を向上させることができる。   As shown in FIG. 3, the printed circuit board according to the second embodiment of the present invention includes a metal substrate 10, an anodized layer 20 formed by anodizing the metal substrate 10, and the anodized layer 20. The circuit layers 30 and 31 formed on the circuit layer 30 and the circuit wiring of the circuit layers 30 and 31 exposing the anodized layer 20 are coated with a photocatalyst agent, and then the coated photocatalyst agent is cured. And the first sol-gel layer 50 is formed, and the anodized layer 20 is formed only on one side and both side surfaces of the metal substrate 10 on which the circuit layers 30 and 31 are formed. Therefore, the heat dissipation effect can be improved by exposing the metal substrate 10 without forming the anodic oxide layer 20 on the other surface of the metal substrate 10 where the circuit layers 30 and 31 are not formed.

本発明の第２実施例は、プリント基板の放熱特性をさらに向上させるために、回路層３０、３１の形成されていない金属基板１０の他面から陽極酸化層２０を除去することができる。これは、陽極酸化層２０の場合も一般な絶縁層よりは放熱特性があるが、陽極酸化層を除去して金属基板１０の他面をそのまま露出させることにより、放熱特性をさらに向上させることができるためである。陽極酸化層２０以外の構成による説明は、第１実施例のそれと重複するので省略する。   In the second embodiment of the present invention, the anodized layer 20 can be removed from the other surface of the metal substrate 10 on which the circuit layers 30 and 31 are not formed in order to further improve the heat dissipation characteristics of the printed circuit board. This is because the anodic oxide layer 20 also has a heat dissipation characteristic than a general insulating layer, but the heat dissipation characteristic can be further improved by removing the anodized layer and exposing the other surface of the metal substrate 10 as it is. This is because it can. The description of the configuration other than the anodized layer 20 is omitted because it overlaps with that of the first embodiment.

図４〜１１は、本発明の第３実施例に係るプリント基板の製造方法を工程順に示す工程断面図（１）〜（８）である。特に、プリント基板の回路層３０、３１をサブトラクティブ方式によって形成してプリント基板を製造する工程である。   4-11 is process sectional drawing (1)-(8) which shows the manufacturing method of the printed circuit board based on 3rd Example of this invention in order of a process. In particular, this is a process of manufacturing a printed circuit board by forming circuit layers 30 and 31 of the printed circuit board by a subtractive method.

以下、図４〜１１を参照して本発明の第３実施例に係るプリント基板の製造工程を説明する。また、本発明の第１実施例および第２実施例に係るプリント基板の構成および作用と重複する内容は、以下で省略する。   Hereinafter, the manufacturing process of the printed circuit board according to the third embodiment of the present invention will be described with reference to FIGS. Further, the description overlapping with the configuration and operation of the printed circuit boards according to the first and second embodiments of the present invention will be omitted below.

本発明に係る第３実施例のプリント基板の製造工程は、（Ａ）金属基板１０を準備する段階と、（Ｂ）前記金属基板１０の全面に陽極酸化処理を施して陽極酸化層２０を形成する段階と、（Ｃ）前記金属基板１０の一面に形成された前記陽極酸化層２０に回路層３０、３１を形成する段階と、（Ｄ）前記回路層３０、３１の形成された前記陽極酸化層２０を露出させる、前記回路層３０、３１の回路配線の間に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて第１ゾルゲル層５０を形成する段階とを含むものである。   The printed circuit board manufacturing process according to the third embodiment of the present invention includes (A) a step of preparing the metal substrate 10 and (B) anodizing the entire surface of the metal substrate 10 to form the anodized layer 20. (C) forming circuit layers 30 and 31 on the anodized layer 20 formed on one surface of the metal substrate 10, and (D) anodizing the circuit layers 30 and 31 formed. And a step of coating the circuit wiring of the circuit layers 30 and 31 with the photocatalyst agent to expose the layer 20, and then curing the coated photocatalyst agent to form the first sol-gel layer 50.

以下、図４〜１１を参照してプリント基板の製造工程を説明する。   Hereinafter, the manufacturing process of the printed circuit board will be described with reference to FIGS.

図４は、（Ａ）金属基板１０を準備する段階、および（Ｂ）前記金属基板１０の全面に陽極酸化処理を施して陽極酸化層２０を形成する段階を示す断面図である。   FIG. 4 is a cross-sectional view showing (A) a step of preparing the metal substrate 10 and (B) a step of forming the anodized layer 20 by subjecting the entire surface of the metal substrate 10 to anodization.

本段階における金属基板１０は、陽極酸化処理による陽極酸化層２０を形成し、放熱特性のある材質で形成することが好ましい。例えば、金属基板１０は、アルミニウム、マグネシウムおよびチタニウムなどの金属材質で構成できる。（Ｂ）段階では、金属基板１０を硫酸などの特定の溶液内で陽極として作用させて金属基板１０の表面に酸化作用を促進させることにより、均一な厚さで人為的な酸化膜が形成されるようにする。ここで、陽極酸化層２０の形成厚さは、陽極酸化処理の処理時間および程度によって決定され、 陽極酸化処理は、絶縁特性のための陽極酸化層２０を形成するために必要な範囲で行われる。   The metal substrate 10 at this stage is preferably formed of a material having a heat dissipation characteristic by forming the anodized layer 20 by anodizing treatment. For example, the metal substrate 10 can be made of a metal material such as aluminum, magnesium, and titanium. In step (B), an artificial oxide film having a uniform thickness is formed by causing the metal substrate 10 to act as an anode in a specific solution such as sulfuric acid to promote the oxidation action on the surface of the metal substrate 10. So that Here, the formation thickness of the anodic oxidation layer 20 is determined by the treatment time and degree of the anodic oxidation treatment, and the anodic oxidation treatment is performed within a range necessary for forming the anodic oxidation layer 20 for insulating characteristics. .

図５〜８は、（Ｃ）陽極酸化層２０に回路層３０、３１を形成する工程を示す断面図である。特に、本実施例では、回路層３０、３１をサブトラクティブ方式によって形成するので、これによるプリント基板の製造工程を説明する。   5 to 8 are cross-sectional views showing a process of forming the circuit layers 30 and 31 on the anodic oxide layer 20 (C). In particular, in the present embodiment, the circuit layers 30 and 31 are formed by a subtractive method, and thus a printed circuit board manufacturing process will be described.

このような回路層３０、３１の形成工程は、（Ｃ−１）前記陽極酸化層２０にシード層３１を形成する段階と、（Ｃ−２）前記シード層３１に電解メッキで回路メッキ層３０を形成する段階と、（Ｃ−３）前記回路メッキ層３０に回路パターンのためのエッチングレジスト４０を塗布した後、エッチングを行う段階と、（Ｃ−４）前記エッチングレジスト４０を除去する段階とを含む。   The circuit layers 30 and 31 are formed by (C-1) forming the seed layer 31 on the anodized layer 20 and (C-2) electrolytic plating the circuit layer 30 on the seed layer 31. (C-3) applying an etching resist 40 for a circuit pattern to the circuit plating layer 30 and then performing etching; and (C-4) removing the etching resist 40. including.

図５は、（Ｃ−１）前記陽極酸化層２０にシード層３１を形成する段階、および（Ｃ−２）前記シード層３１に電解メッキで回路メッキ層３０を形成する段階を示す断面図である。   FIG. 5 is a sectional view showing (C-1) a step of forming a seed layer 31 on the anodized layer 20 and (C-2) a step of forming a circuit plating layer 30 on the seed layer 31 by electrolytic plating. is there.

シード層３１は、電解メッキのための引き込み線の役割を果たすもので、爾後回路メッキ層３０の積層のために湿式メッキ法（無電解）または乾式メッキ法（スパッタリング）で形成できる。シード層３１の形成後、シード層３１に回路メッキ層３０を電解メッキ方式で形成することにより、所望の厚さの回路層３０、３１を形成することができる。   The seed layer 31 serves as a lead-in wire for electrolytic plating, and can be formed by wet plating (electroless) or dry plating (sputtering) for laminating the post-circuit plating layer 30. After the seed layer 31 is formed, the circuit layers 30 and 31 having a desired thickness can be formed by forming the circuit plating layer 30 on the seed layer 31 by electrolytic plating.

図６および図７は、（Ｃ−３）前記回路メッキ層３０に回路パターン形成のためのエッチングレジスト４０を塗布した後、エッチングを行う段階を示す断面図である。   FIGS. 6 and 7 are cross-sectional views showing a stage of (C-3) applying an etching resist 40 for forming a circuit pattern to the circuit plating layer 30 and then performing etching.

図６に示すように、回路メッキ層３０に回路層３０、３１を形成するために、回路パターンに応じるエッチングレジスト４０を塗布する。図７に示すように、エッチングを行って回路パターンを形成する。この場合、エッチングは、湿式エッチングまたは乾式エッチングによって行われ得る。ところが、このようなエッチング方式に限定されず、これ以外の方法でも回路パターンを形成することができる。   As shown in FIG. 6, in order to form the circuit layers 30 and 31 on the circuit plating layer 30, an etching resist 40 corresponding to the circuit pattern is applied. As shown in FIG. 7, a circuit pattern is formed by etching. In this case, the etching can be performed by wet etching or dry etching. However, the present invention is not limited to such an etching method, and the circuit pattern can be formed by other methods.

図８は、（Ｃ−４）前記エッチングレジスト４０を除去する段階を示す断面図である。 エッチングレジスト４０を除去することにより、最終的に所望の回路層３０、３１が陽極酸化層２０に形成される。   FIG. 8 is a sectional view showing the step (C-4) of removing the etching resist 40. By removing the etching resist 40, desired circuit layers 30 and 31 are finally formed on the anodized layer 20.

図９〜１１は、（Ｄ）前記陽極酸化層２０を露出させる、前記回路層３０、３１の回路配線の間に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて第１ゾルゲル層５０を形成する段階を示す。   FIGS. 9 to 11 show (D) a coating treatment with a photocatalyst agent between the circuit wirings of the circuit layers 30 and 31, which exposes the anodic oxidation layer 20, and then the coating photocatalyst agent is cured to be first. The step of forming the sol-gel layer 50 is shown.

ここで、（Ｄ）段階は、（Ｄ−１）前記金属基板１０の他面に形成された陽極酸化層２０に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて第２ゾルゲル層５１を形成する段階と、（Ｄ−２）前記第２ゾルゲル層５１を除去する段階と、（Ｄ−３）前記金属基板１０の他面に形成された前記陽極酸化層２０を除去する段階とを含んでなるものである。   Here, in step (D), (D-1) the anodic oxidation layer 20 formed on the other surface of the metal substrate 10 is coated with a photocatalyst agent, and then the coated photocatalyst agent is cured to be second. Forming a sol-gel layer 51; (D-2) removing the second sol-gel layer 51; and (D-3) removing the anodized layer 20 formed on the other surface of the metal substrate 10. A stage.

図９は、（Ｄ）陽極酸化層２０を露出させる、回路層３０、３１の回路配線の間に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて第１ゾルゲル層５０を形成する段階と、（Ｄ−１）金属基板１０の他面に形成された陽極酸化層２０に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて第２ゾルゲル層５１を形成する段階とを示す。   FIG. 9 shows (D) a coating treatment with a photocatalyst agent between circuit wirings of the circuit layers 30 and 31 that exposes the anodized layer 20, and then the coated photocatalyst agent is cured to form the first sol-gel layer 50. And (D-1) coating the anodic oxide layer 20 formed on the other surface of the metal substrate 10 with a photocatalyst agent, and then curing the coated photocatalyst agent to form the second sol-gel layer 51. The stage to perform.

（Ｄ）段階で工程が完了してプリント基板を形成することができ、工程において金属基板１０の両面に同時または順次第１ゾルゲル層５０および第２ゾルゲル層５１を付着させて形成することができる。ここでの第１ゾルゲル層５０および第２ゾルゲル層５１の形成と光触媒剤のコーティングおよび硬化に関する説明は、本発明の第１実施例および第２実施例に係る内容と同一なので省略する。   In step (D), the process can be completed and a printed circuit board can be formed. In the process, the first sol-gel layer 50 and the second sol-gel layer 51 can be formed on both surfaces of the metal substrate 10 simultaneously or sequentially. . The description regarding the formation of the first sol-gel layer 50 and the second sol-gel layer 51 and the coating and curing of the photocatalyst agent is the same as the contents according to the first and second embodiments of the present invention, and will be omitted.

図１０は、（Ｄ−２）前記第２ゾルゲル層５１を除去する段階を示す断面図である。これは、金属基板１０の他面から第２ゾルゲル層５１を除去して放熱特性を向上させるためである。   FIG. 10 is a sectional view showing the step (D-2) of removing the second sol-gel layer 51. This is because the second sol-gel layer 51 is removed from the other surface of the metal substrate 10 to improve the heat dissipation characteristics.

また、図１１に示すように、（Ｄ−３）前記金属基板１０の他面に形成された前記陽極酸化層２０を除去する段階をさらに含むことにより、金属基板１０が直接露出されて放熱特性効果がさらに増進できる。   In addition, as shown in FIG. 11, (D-3) by further removing the anodized layer 20 formed on the other surface of the metal substrate 10, the metal substrate 10 is directly exposed to dissipate heat. The effect can be further improved.

図１２〜１９は、本発明の第４実施例に係るプリント基板の製造方法を工程順に示す工程断面図（１）〜（８）である。特に、プリント基板の回路層３０、３１をアディティブ方式によって形成してプリント基板を製造する工程である。   12 to 19 are process cross-sectional views (1) to (8) illustrating a method of manufacturing a printed circuit board according to the fourth embodiment of the present invention in the order of processes. In particular, this is a process for manufacturing a printed circuit board by forming circuit layers 30 and 31 of the printed circuit board by an additive method.

以下、図１２〜１９を参照して本発明の第４実施例に係るプリント基板の製造工程を説明する。また、第３実施例に係るプリント基板の製造工程と重複する内容は以下で省略する。   Hereinafter, a printed circuit board manufacturing process according to the fourth embodiment of the present invention will be described with reference to FIGS. Further, the description overlapping with the manufacturing process of the printed circuit board according to the third embodiment is omitted below.

本発明のプリント基板の製造工程は、（Ａ）金属基板１０を準備する段階と、（Ｂ）前記金属基板１０の全面に陽極酸化処理して陽極酸化層２０を形成する段階と、（Ｃ）前記金属基板１０の一面に形成された前記陽極酸化層２０に回路層３０、３１を形成する段階と、（Ｄ）前記陽極酸化層３０、３１の形成された前記陽極酸化層２０を露出させる、前記回路層３０、３１の回路配線の間に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて第１ゾルゲル層５０を形成する段階とを含むものである。   The printed circuit board manufacturing process of the present invention includes (A) a step of preparing a metal substrate 10, (B) a step of forming an anodic oxide layer 20 by anodizing the entire surface of the metal substrate 10, and (C). Forming circuit layers 30 and 31 on the anodized layer 20 formed on one surface of the metal substrate 10; and (D) exposing the anodized layer 20 on which the anodized layers 30 and 31 are formed. A step of coating the circuit wiring of the circuit layers 30 and 31 with a photocatalyst agent, and then curing the coated photocatalyst agent to form a first sol-gel layer 50.

以下、図１２〜１９を参照してプリント基板の製造工程を説明する。   Hereinafter, the manufacturing process of the printed circuit board will be described with reference to FIGS.

図１２は、（Ａ）金属基板１０を準備する段階、および（Ｂ）前記金属基板１０の全面に陽極酸化処理を施して陽極酸化層２０を形成する段階を示す断面図である。これについての詳細な説明は、本発明の第３実施例に係るプリント基板の製造工程と同様なので省略する。   FIG. 12 is a cross-sectional view showing (A) a step of preparing the metal substrate 10 and (B) a step of forming the anodized layer 20 by subjecting the entire surface of the metal substrate 10 to anodization. Detailed description thereof is omitted because it is the same as the printed circuit board manufacturing process according to the third embodiment of the present invention.

図１３〜１６は、（Ｃ）陽極酸化層２０に回路層３０、３１を形成する工程を示す断面図である。特に、本実施例では、回路層３０、３１をアディティブ方式によって形成するので、これによるプリント基板の製造工程を説明する。   13 to 16 are cross-sectional views showing a process of forming the circuit layers 30 and 31 on the anodic oxide layer 20 (C). In particular, in the present embodiment, the circuit layers 30 and 31 are formed by the additive method, and therefore, a printed circuit board manufacturing process will be described.

このような回路層３０、３１の形成工程は、（Ｃ−１）前記陽極酸化層２０にシード層３１を形成する段階と、（Ｃ−２）前記シード層３１に回路パターンのためのメッキレジスト４１を塗布する段階と、（Ｃ−３）前記シード層３１に回路メッキ層３０を形成する段階と、（Ｃ−４）前記メッキレジスト４１を除去し、露出された前記シード層３１をエッチングする段階とを含むことを特徴とする。   The circuit layers 30 and 31 are formed by (C-1) forming a seed layer 31 on the anodized layer 20 and (C-2) plating resist for a circuit pattern on the seed layer 31. (C-3) forming a circuit plating layer 30 on the seed layer 31, and (C-4) removing the plating resist 41 and etching the exposed seed layer 31. A stage.

図１３は、（Ｃ−１）前記陽極酸化層２０にシード層３１を形成する段階、および（Ｃ−２）前記シード層３１に回路パターンのためのメッキレジスト４１を塗布する段階を示す断面図である。   13 is a cross-sectional view showing (C-1) a step of forming a seed layer 31 on the anodized layer 20 and (C-2) a step of applying a plating resist 41 for a circuit pattern to the seed layer 31. It is.

シード層３１は、電解メッキのための引き込み線の役割を果たすもので、爾後回路メッキ層３０の形成のために湿式メッキ法（無電解）または乾式メッキ法（スパッタリング）で形成できる。シード層３１の形成後、シード層３１に回路メッキ層３０を電解メッキ方式で形成する。その後、所望の回路パターン形成のためにメッキレジスト４１を塗布する。   The seed layer 31 serves as a lead-in wire for electrolytic plating, and can be formed by a wet plating method (electroless) or a dry plating method (sputtering) for forming the post-circuit plating layer 30. After the seed layer 31 is formed, the circuit plating layer 30 is formed on the seed layer 31 by electrolytic plating. Thereafter, a plating resist 41 is applied to form a desired circuit pattern.

図１４は、（Ｃ−３）前記シード層３１に回路メッキ層３０を形成する段階を示す断面図である。メッキレジストの塗布された部分以外に回路メッキ層３０が形成される。   FIG. 14 is a sectional view showing the step (C-3) of forming the circuit plating layer 30 on the seed layer 31. The circuit plating layer 30 is formed in a portion other than the portion where the plating resist is applied.

図１５は、（Ｃ−４）前記メッキレジスト４１を除去する段階を示し、図１６は、（Ｃ−４）露出された前記シード層３１をエッチングする段階を示す断面図である。メッキレジスト４１を除去した後、回路パターンの間に露出されたシード層３１を選択的にエッチングすることにより、最終回路層３０、３１を形成する。   FIG. 15 shows a step (C-4) of removing the plating resist 41, and FIG. 16 is a cross-sectional view showing a step (C-4) of etching the exposed seed layer 31. After removing the plating resist 41, the final circuit layers 30 and 31 are formed by selectively etching the seed layer 31 exposed between the circuit patterns.

図１７は、（Ｄ）前記陽極酸化層２０を露出させる、前記回路層３０、３１の回路配線の間に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて第１ゾルゲル層５０を形成し、（Ｄ−１）回路層３０、３１の形成されていない金属基板１０の他面に第２ゾルゲル層５１を形成する段階を示す。   FIG. 17 shows (D) the first sol-gel layer obtained by coating the photocatalyst with a photocatalyst between the circuit wirings of the circuit layers 30 and 31 that expose the anodized layer 20 and then curing the coated photocatalyst. 50, and (D-1) forming the second sol-gel layer 51 on the other surface of the metal substrate 10 on which the circuit layers 30 and 31 are not formed is shown.

その後、図１８に示すように、（Ｄ−２）金属基板１０の他面に形成された第２ゾルゲル層５１を除去する段階によって、プリント基板が完成できる。その上、図１９に示すように、（Ｄ−３）前記金属基板１０の他面に形成された前記陽極酸化層２０を除去する段階を行って金属基板１０の他面を露出させることにより、放熱特性をさらに向上させることができる。その他の詳細な説明は、上述した第３実施例に係るプリント基板製造工程の図９〜１１の工程と同様なので、ここでは省略する。   Thereafter, as shown in FIG. 18, (D-2) a printed circuit board can be completed by removing the second sol-gel layer 51 formed on the other surface of the metal substrate 10. In addition, as shown in FIG. 19, (D-3) performing the step of removing the anodized layer 20 formed on the other surface of the metal substrate 10 to expose the other surface of the metal substrate 10; The heat dissipation characteristics can be further improved. Since other detailed description is the same as that of FIGS. 9-11 of the printed circuit board manufacturing process based on 3rd Example mentioned above, it abbreviate | omits here.

以上、本発明を具体的な実施例によって詳細に説明したが、これは本発明を具体的に説明するためのもので、本発明に係るタッチパネル製造装置は、これに限定されず、本発明の技術的思想内で当該分野における通常の知識を有する者によって多様な変形または改良を加え得るのは明白であろう。本発明の単純な変形または変更は、いずれも本発明の領域に属するもので、本発明の具体的な保護範囲は、特許請求の範囲によって明白になるであろう。   As described above, the present invention has been described in detail by way of specific examples. However, this is for specifically explaining the present invention, and the touch panel manufacturing apparatus according to the present invention is not limited thereto, and the present invention is not limited thereto. It will be apparent that various modifications or improvements can be made by those having ordinary knowledge in the art within the technical idea. All simple variations or modifications of the invention belong to the scope of the invention, and the specific scope of protection of the invention will be apparent from the claims.

本発明は、放熱特性を向上させることができ、回路層の回路配線の間に発生する電気的短絡を防止することができるうえ、放熱効果を増加させることができるプリント基板およびその製造方法に適用可能である。   INDUSTRIAL APPLICABILITY The present invention can be applied to a printed circuit board capable of improving heat dissipation characteristics, preventing an electrical short circuit occurring between circuit wirings in a circuit layer, and increasing a heat dissipation effect, and a method for manufacturing the same. Is possible.

１０ 金属基板
２０ 陽極酸化層
３０ 回路メッキ層
３１ シード層
３０、３１ 回路層
４０ エッチングレジスト
４１ メッキレジスト
５０ 第１ゾルゲル層
５１ 第２ゾルゲル層 DESCRIPTION OF SYMBOLS 10 Metal substrate 20 Anodized layer 30 Circuit plating layer 31 Seed layer 30, 31 Circuit layer 40 Etching resist 41 Plating resist 50 1st sol-gel layer 51 2nd sol-gel layer

Claims (11)

金属基板と、
前記金属基板に陽極酸化処理を施して形成される陽極酸化層と、
前記陽極酸化層に形成される回路層と、
前記陽極酸化層を露出させる、前記回路層の回路配線の間に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて形成される第１ゾルゲル層とを含んでなることを特徴とするプリント基板。 A metal substrate;
An anodized layer formed by anodizing the metal substrate;
A circuit layer formed on the anodized layer;
A first sol-gel layer formed by coating the photocatalyst agent with a photocatalyst agent between the circuit wirings of the circuit layer, exposing the anodized layer, and then curing the coated photocatalyst agent. Printed circuit board. 前記光触媒剤が、アルミナまたは二酸化チタニウムであることを特徴とする請求項１に記載のプリント基板。   The printed circuit board according to claim 1, wherein the photocatalytic agent is alumina or titanium dioxide. 前記陽極酸化層が、前記金属基板の一面および両側面にのみ形成されることを特徴とする請求項１に記載のプリント基板。   The printed board according to claim 1, wherein the anodized layer is formed only on one surface and both side surfaces of the metal substrate. （Ａ）金属基板を準備する段階と、
（Ｂ）前記金属基板の全面に陽極酸化処理を施して陽極酸化層を形成する段階と、
（Ｃ）前記金属基板の一面に形成された前記陽極酸化層に回路層を形成する段階と、
（Ｄ）前記陽極酸化層を露出させる、前記回路層の回路配線の間に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて第１ゾルゲル層を形成する段階とを含んでなることを特徴とするプリント基板の製造方法。 (A) preparing a metal substrate;
(B) anodizing the entire surface of the metal substrate to form an anodized layer;
(C) forming a circuit layer on the anodized layer formed on one surface of the metal substrate;
(D) exposing the anodized layer, coating with a photocatalyst agent between circuit wirings of the circuit layer, and curing the coated photocatalyst agent to form a first sol-gel layer. A printed circuit board manufacturing method comprising: 前記（Ｂ）段階では、前記金属基板の一面および両側面にのみ陽極酸化処理を施して陽極酸化層を形成することを特徴とする請求項４に記載のプリント基板の製造方法。   5. The method of manufacturing a printed circuit board according to claim 4, wherein in step (B), an anodic oxidation layer is formed by anodizing only one side and both side surfaces of the metal substrate. 前記（Ｃ）段階が、
（Ｃ−１）前記陽極酸化層にシード層を形成する段階と、
（Ｃ−２）前記シード層に電解メッキで回路メッキ層を形成する段階と、
（Ｃ−３）前記回路メッキ層に回路パターンの形成のためにエッチングレジストを塗布した後、エッチングを行う段階と、
（Ｃ−４）前記エッチングレジストを除去する段階とを含むことを特徴とする請求項４に記載のプリント基板の製造方法。 In step (C),
(C-1) forming a seed layer on the anodized layer;
(C-2) forming a circuit plating layer on the seed layer by electrolytic plating;
(C-3) applying an etching resist to the circuit plating layer to form a circuit pattern, and then performing etching;
(C-4) The method of manufacturing the printed circuit board of Claim 4 including the step which removes the said etching resist. 前記（Ｃ）段階が、
（Ｃ−１）前記陽極酸化層にシード層を形成する段階と、
（Ｃ−２）前記シード層に回路パターンのためのメッキレジストを塗布する段階と、
（Ｃ−３）前記シード層に回路メッキ層を形成する段階と、
（Ｃ−４）前記メッキレジストを除去し、露出された前記シード層をエッチングする段階とを含むことを特徴とする請求項４に記載のプリント基板の製造方法。 In step (C),
(C-1) forming a seed layer on the anodized layer;
(C-2) applying a plating resist for a circuit pattern to the seed layer;
(C-3) forming a circuit plating layer on the seed layer;
(C-4) removing the plating resist and etching the exposed seed layer. 5. The method of manufacturing a printed circuit board according to claim 4, further comprising: etching the exposed seed layer. 前記（Ｄ）段階が、
（Ｄ−１）前記金属基板の他面に形成された陽極酸化層に光触媒剤でコーティング処理した後、コーティング処理された光触媒剤を硬化させて第２ゾルゲル層を形成する段階と、
（Ｄ−２）前記第２ゾルゲル層を除去する段階と、
（Ｄ−３）前記金属基板の他面に形成された前記陽極酸化層を除去する段階とを含むことを特徴とする請求項４に記載のプリント基板の製造方法。 In step (D),
(D-1) coating the anodized layer formed on the other surface of the metal substrate with a photocatalyst agent, then curing the coated photocatalyst agent to form a second sol-gel layer;
(D-2) removing the second sol-gel layer;
(D-3) The method of manufacturing the printed circuit board of Claim 4 including the step of removing the said anodic oxidation layer formed in the other surface of the said metal substrate. 前記光触媒剤が、アルミナまたは二酸化チタニウムであることを特徴とする請求項４に記載のプリント基板の製造方法。   The method for producing a printed circuit board according to claim 4, wherein the photocatalytic agent is alumina or titanium dioxide. 前記光触媒剤のコーティング処理が、スプレー噴射法、ディッピング（ｄｉｐｐｉｎｇ）法またはエアロゾル沈着法で行われることを特徴とする請求項４に記載のプリント基板の製造方法。   The method for manufacturing a printed circuit board according to claim 4, wherein the coating treatment of the photocatalytic agent is performed by a spraying method, a dipping method, or an aerosol deposition method. 前記コーティング処理された光触媒剤を硬化させる段階が、１００℃〜２００℃の温度で行われることを特徴とする請求項４に記載のプリント基板の製造方法。   The method for producing a printed circuit board according to claim 4, wherein the step of curing the coated photocatalytic agent is performed at a temperature of 100C to 200C.
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