JP2011249970A - Delay circuit and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay circuit capable of applying delay with high accuracy to an input signal and a control method thereof.SOLUTION: A delay circuit is provided with an edge detection circuit 1004 to detect transition time of rising or falling of an input signal 1001 based on multiple clock signals having different phases; and an output signal generation part 1015 to reproduce and output a signal waveform of the input signal, after lapse of predetermined delay time from the transition time of the detected input signal, based on a clock signal corresponding to the transition time of the input signal.

Description

  The present invention relates to a delay circuit and a control method thereof, and more particularly to a delay circuit used in a polar modulation amplifier that amplifies a high-frequency signal and a control method thereof.

  The configuration of the class AB amplifier of the technology related to FIG. 17 is shown, and the configuration of the polar modulation type amplifier (hereinafter referred to as polar modulation PA) of the technology related to FIG. 18 is shown. These amplifiers are amplifiers for amplifying a transmission signal in the wireless device. The power consumption of these amplifiers occupies a large proportion of the power consumption in the radio. Therefore, in order to reduce the power of the radio, it is essential to reduce the power of these amplifiers.

  The class AB amplifier shown in FIG. 17 includes a power amplifier (amplifier) 2001 and a DC power source 2002. The DC power supply 2002 generates a voltage 2202 and outputs it to the power supply terminal 2003 of the power amplifier 2001. The power amplifier 2001 is driven based on the voltage 2202 and amplifies an input signal (amplified signal). Here, as shown in FIG. 19, in the related class AB amplifier, the voltage 2202 supplied to the power amplifier 2001 is constant with respect to the change in the amplitude 2201 of the input signal. Therefore, these differences become losses and are consumed as wasted power.

  On the other hand, the polar modulation PA shown in FIG. 18 includes a power supply modulator 2004 in addition to the power amplifier 2001 and the DC power supply 2002. The power supply modulator 2004 is provided between the DC power supply 2002 and the power amplifier 2001. The power supply modulator 2004 changes the voltage 2202 generated from the DC power supply 2002 in accordance with the signal amplitude 2201 and outputs the voltage 2203 to the power supply terminal 2003 of the power amplifier 2001. Therefore, as shown in FIG. 20, in the polar modulation PA of the related technique, the voltage 2203 supplied to the power amplifier 2001 is synchronized with the amplitude 2201 of the input signal. With such a circuit configuration, power that is wasted from the power amplifier 2001 is reduced, and as a result, it is possible to improve the operating efficiency of the wireless device and reduce the power.

  FIG. 21 shows an example of the power supply modulator 2004. Usually, the efficiency of the entire amplifier is obtained by the product of the efficiency of the power supply modulator and the efficiency of the power amplifier, and therefore, the power supply modulator is required to have high efficiency. For this reason, the power supply modulator is often provided with a digital amplifier circuit using a technique such as pulse width modulation (PAM) or delta modulation. The power supply modulator 2004 shown in FIG. 21 is also provided with a digital amplifier circuit configured using a comparator 2011, a driver amplifier 2012, and a switching amplifier 2013.

  An operational amplifier (linear amplifier) 2010 provided in the power supply modulator 2004 outputs an AM (Amplitude Modulation) signal detected using a detection circuit (envelope detector) 2015. The detection circuit 2015 is a circuit that detects an amplitude component (amplitude signal; hereinafter referred to as an AM signal) of an input signal (amplified signal). In the digital amplifier circuit, the comparator 2011 compares the AM signal output from the operational amplifier 2010 with a feedback signal (described later) and outputs a comparison result. The comparison result is input to the switching amplifier 2013 via the driver amplifier 2012. Then, the switching amplifier 2013 generates an output signal corresponding to the comparison result. This output signal is smoothed using an inductor 2014 having a role of a low-pass filter, used as a feedback signal, and supplied as a voltage 2203 to the power supply terminal 2003 of the power amplifier 2001.

  Here, as shown in FIG. 21, the power supply modulator includes various filters such as a low-pass filter in order to remove quantization noise generated from the digital amplifier circuit. Use of this filter is essential for noise removal. However, the delay generated according to this filter and the delay generated according to the feedback of the digital amplifier are in units of several ns to several tens of ns. The influence of this delay is observed as a phase shift between the signal amplitude 2201 and the voltage 2203 shown in FIG.

  In order to solve this phase shift, mainly three circuit configurations or combinations thereof have been proposed.

  As shown in FIG. 22, the first circuit configuration is a circuit configuration in which an output signal (amplified signal) of the power amplifier 2001 is detected by using a detection circuit 2005 or the like, and the result is fed back to the power supply modulator 2004. is there. In Patent Document 1, a circuit configuration corresponding to this is used.

  The second circuit configuration is a circuit configuration in which a delay circuit for delaying an input signal (amplified signal) is inserted on the input side of the power amplifier. In Patent Document 2 and Patent Document 3, a circuit configuration in which the second and first are combined is used. In addition, Patent Document 4 and Patent Document 5 disclose related techniques.

  The third circuit configuration is a circuit configuration in which a delay is added when a modulated waveform is generated from an IQ signal. In Patent Document 6, a circuit configuration combined with the third and first is used.

JP 2005-184866 A JP 2005-287011 A JP 2006-203456 A JP 2005-203960 A JP 02-284510 A JP 2006-174418 A

  However, the above method has the following problems. Hereinafter, it demonstrates in order.

  The use of feedback in the first circuit configuration is an ideal configuration. However, problems occur when this circuit configuration is used for a signal with a carrier wave of about 2 GHz and a modulated wave band of about 5 MHz, such as a WCDMA (Wideband Code Division Multiple Access) signal or an LTE (Long Term Evolution) signal. To do. That is, in this situation, when the delay amount based on the filter or the like becomes several tens of ns, the delay becomes relatively large. Therefore, when feedback is performed, there is a problem that the operation of the power amplifier becomes unstable and oscillation occurs.

  The insertion of the delay circuit in the second circuit configuration is a simple idea of delaying an early input signal (amplified signal) in order to correct the mutual phase shift. This circuit configuration is mainly divided into a digital delay circuit and an analog delay circuit, but no effective circuit configuration has been proposed. This will be specifically described below.

  As the digital delay circuit, for example, there is a delay circuit using a D flip-flop circuit as shown in FIG. The delay circuit shown in FIG. 23 includes two cascade-connected D flip-flops 2016 and 2017, and outputs an output signal OUT obtained by delaying the input signal IN according to the cycle of the clock signal CLK. However, in the digital delay circuit shown in FIG. 23, the output signal OUT changes from high to low (hereinafter referred to as “falling”) and low to high (hereinafter referred to as “rising”). The timing is in accordance with the CLK cycle. Therefore, the digital delay circuit cannot be used for a phase adjustment signal such as a PM (Phase modulation) signal that requires high accuracy. Solutions to such a problem are proposed in Patent Document 2 and Patent Document 4. Patent Documents 2 and 4 propose a circuit configuration in which an input signal (amplified signal) is converted into a digital signal and then generated as an amplified signal with a delay added using a VCO. This circuit configuration has the same concept as the third circuit configuration (details will be described later). However, when this circuit configuration is used for a WCDMA signal or an LTE signal, there is a functional block that cannot satisfy the required operating frequency, which is difficult to realize with the current technology.

  On the other hand, as proposed in Patent Document 5, analog delay circuits include delay circuits that change the constant of a low-pass filter by changing the capacitance. That is, the delay circuit changes the delay amount by changing the filter. However, when a low-pass filter is used for delay adjustment, the cutoff frequency may be lower than the carrier wave included in the PM signal. That is, a necessary carrier wave is cut off. A solution to such a problem is proposed in Patent Document 3. Patent Document 3 proposes a circuit configuration in which a signal attenuated using an analog delay device is amplified using an additional amplifier and used as an amplified signal of a power amplifier. However, the purpose of using the polar modulation PA is to reduce power consumption. Nevertheless, if an additional amplifier is provided in the delay circuit, there is a problem that the polar modulation PA cannot achieve a reduction in power as a whole circuit.

  A third circuit configuration that adds a delay when a waveform is generated from an IQ signal is also an ideal circuit configuration. Actually, this circuit configuration is adopted in a radio base station or the like, but it is difficult to adopt this circuit configuration in a portable terminal. This is because in the current mobile terminal market, the producers of digital signal processing blocks and power amplifier blocks are different, so adding or changing blocks beyond the boundary of both limits the use of the corresponding product It is because it will do.

  As described above, in the related technology, in the polar modulation amplifier, the phase between the output potential of the power supply modulator (power supply voltage supplied to the power amplifier) and the input signal (amplified signal) of the power amplifier. There is a problem that the shift cannot be suppressed and the power consumption increases. In particular, the delay circuit of the related technique has a problem that a highly accurate delay cannot be added to the input signal.

  An object of the present invention is to solve such problems and to provide a delay circuit capable of adding a highly accurate delay to an input signal and a control method thereof.

  The delay circuit according to the present invention includes an input signal detection unit that detects a time at which the voltage level of the input signal transits from the first voltage level to the second voltage level based on a plurality of clock signals having different phases, and a detection An output signal generation unit that reproduces and outputs a signal waveform of the input signal after a predetermined delay time has elapsed from the transition time based on the clock signal corresponding to the transition time of the input signal.

  According to the delay circuit control method of the present invention, the time at which the voltage level of the input signal transitions from the first voltage level to the second voltage level is detected based on a plurality of clock signals having different phases. Based on the clock signal corresponding to the transition time of the input signal, the signal waveform of the input signal is reproduced and output after a predetermined delay time has elapsed from the transition time.

  ADVANTAGE OF THE INVENTION According to this invention, the delay circuit which can add a highly accurate delay to an input signal, and its control method can be provided.

1 is a block diagram showing a delay circuit according to a first exemplary embodiment of the present invention. 1 is a block diagram showing a delay circuit according to a first exemplary embodiment of the present invention. 3 is a timing chart showing an operation of the delay circuit according to the first exemplary embodiment of the present invention; 6 is a diagram showing transition information of input signals stored in a memory 1006. FIG. 3 is a circuit diagram showing an example of a clock signal source 1003. FIG. 6 is a circuit diagram showing another example of the clock signal source 1003. FIG. 3 is a circuit diagram showing an example of a clock oscillator 1020. FIG. 4 is a timing chart showing a part of a clock signal output from a clock signal source 1003. It is a timing chart which shows a basic clock signal and an input signal. It is a timing chart which shows two basic clock signals and an input signal. It is a block diagram which shows the delay circuit concerning Embodiment 2 of this invention. It is a block diagram which shows the delay circuit concerning Embodiment 3 of this invention. It is a block diagram which shows the delay circuit concerning Embodiment 4 of this invention. 14 is a timing chart showing an input waveform and an output waveform after delay of the delay circuit shown in FIG. It is a block diagram which shows polar modulation PA concerning Embodiment 5 of this invention. It is a block diagram which shows polar modulation PA concerning Embodiment 6 of this invention. It is a block diagram which shows the class AB amplifier of related technology. It is a block diagram of polar modulation PA of related technology. It is a figure which shows the relationship between the power supply voltage supplied to the class AB amplifier shown in FIG. 17, and the amplitude of an input signal. It is a figure which shows the relationship between the power supply voltage supplied to polar modulation PA of FIG. 18, and the amplitude of an input signal. It is a block diagram which shows the VCCP type | mold power supply modulator of related technology. It is a block diagram which shows the amplifier using a feedback method. It is a block diagram which shows the delay circuit for digital using D flip-flop.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Since the drawings are simplified, the technical scope of the present invention should not be interpreted narrowly based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description shall be abbreviate | omitted.

Embodiment 1
FIG. 1 is a block diagram showing a delay circuit according to the first exemplary embodiment of the present invention. The delay circuit shown in FIG. 1 is provided mainly in the polar modulation PA, and is used as a circuit that delays an input signal (amplified signal) of the power amplifier. The delay circuit shown in FIG. 1 includes an edge detection circuit (input signal detection unit) 1004 and an output signal generation unit 1015.

  The edge detection circuit 1004 is a circuit that detects rising and falling of the input signal 1001 based on a plurality of clock signals having different phases. The output signal generation unit 1015 is a circuit that reproduces the signal waveform of the input signal 1001 after a predetermined delay time has elapsed based on a clock signal whose timing substantially coincides with the detected transition of the input signal 1001.

  FIG. 2 shows a specific example of the delay circuit shown in FIG. FIG. 2 is a block diagram showing the delay circuit according to the first exemplary embodiment of the present invention. The delay circuit illustrated in FIG. 2 includes a clock signal source 1003, an edge detection circuit 1004, a counter 1005, a memory (storage circuit) 1006, a comparison circuit 1007, and a pulse output circuit (output circuit) 1008.

  The clock signal source 1003 is a circuit that generates a plurality of clock signals having different phases. The edge detection circuit 1004 is a circuit that detects rising and falling of the input signal 1001 based on a plurality of clock signals. The counter 1005 is a circuit that counts the number of rises or falls (number of changes to high or low) of a selected clock signal among a plurality of clock signals. The memory 1006 is a circuit that stores transition information of the input signal 1001.

  The comparison circuit 1007 is a circuit that confirms whether a predetermined delay time has elapsed based on the transition information stored in the memory 1006 and the count value of the counter 1005. The pulse output circuit 1008 is a circuit that reproduces a signal waveform of the input signal 1001 based on a clock signal corresponding to the transition information stored in the memory 1006 and outputs it as an output signal 1002 after a predetermined delay time has elapsed. . Details will be described below.

  Configuration examples of the clock signal source 1003 are shown in FIGS. A clock signal source 1003 illustrated in FIG. 5 includes a clock oscillator 1020 and inverters 1021-1 to 1021-N (N is a natural number) connected in series. The clock oscillator 1020 generates a reference clock signal using, for example, a crystal oscillator. Note that the clock oscillator 1020 may have a circuit configuration that generates the reference clock signal based on a signal supplied from the outside. Alternatively, as shown in FIG. 7, the clock oscillator 1020 is a circuit that generates the reference clock signal using an oscillator in which an odd number of inverters 1021-1 to 1020-M (M is an odd number) is connected in a loop. It may be a configuration. There are many other oscillation circuits for generating a reference clock, but the present invention does not depend on a method for generating a reference clock signal, and therefore a circuit configuration other than that described here may be used. Note that the clock signal source 1003 may be provided outside the circuit illustrated in FIG.

  In FIG. 5, a clock signal source 1003 generates a reference clock signal and a signal with a delay added thereto as a plurality of clock signals having different phases. Specifically, the clock signal source 1003 generates the signals output from the output terminals of the clock oscillator 1020 and the inverters 1021-1 to 1021-N as a plurality of clock signals having different phases.

  In the example of FIG. 5, the clock signal source 1003 delays the reference clock signal via an even number of inverters. Specifically, the clock signal source 1003 includes a reference clock signal (clock signal CLK0), a clock signal CLK1 with a delay for two inverters, and a clock signal CLK2 with a delay for two inverters, and so on. A plurality of clock signals to which delays of two inverters are added are output.

  In the example of FIG. 5, the clock signal source 1003 outputs a reverse-phase clock signal obtained by delaying the reference clock signal through an odd number of inverters. For example, the clock signal CLK0B is a reverse phase clock signal obtained by adding a delay corresponding to one inverter to the clock signal CLK0. The clock signal CLK1B is a reverse phase clock signal obtained by adding a delay corresponding to one inverter to the clock signal CLK1.

  FIG. 6 shows a clock signal source 1003 including a clock oscillator 1020 and delay lines 1022-1 to 1022-N connected in series. In the clock signal source 1003 shown in FIG. 6, a delay is added to the reference clock signal using the delay lines 1022-1 to 1022-N to generate a plurality of clock signals. For example, when the frequency of the reference clock signal is 1 GHz, the wavelength is about 30 cm. Therefore, in a 0.8 mm line, it is possible to generate a phase shift of 0.1 deg and a delay equivalent to 0.3 ps in terms of delay time. It is.

  FIG. 8 shows a timing chart of a plurality of clock signals generated from the clock signal source 1003. FIG. 8 shows a timing chart of some clock signals CLK0 to CLK4. As described above, the clock signal source 1003 generates a plurality of clock signals having different phases.

  In the present invention, it is not necessary to make the delay time between a plurality of clock signals constant. Therefore, the delay time can be finely changed or changed by the circuit configuration shown in FIGS. 5 and 6 or a combination thereof. The number of clock signals to be generated depends on the degree of phase reproduction accuracy. For example, when the accuracy of 1 deg is required, 360 or more clock signals need to be generated when the accuracy of 2 deg is required, 180 or more.

  In FIG. 2, the edge detection circuit 1004 detects a clock signal whose timing substantially coincides with the rising edge or falling edge of the input signal 1001 among a plurality of clock signals. Then, the edge detection circuit 1004 sets the detected information of the clock signal (for example, the clock signal number) and the corresponding count value (count value when the transition of the input signal 1001 is detected) as a set. Are sequentially output to the memory 1006.

  The counter 1005 performs a counting operation based on one or more clock signals (basic clock signals) selected from the plurality of clock signals. For example, the counter 1005 counts the number of rises, falls, or both of the selected clock signal as “the count value when the transition of the input signal 1001 is detected”.

  Note that the bit length of the counter 1005 needs to be a bit length capable of counting a time longer than the target delay time. Here, the delay time is determined according to the count value of the counter 1005 based on the clock signal (details will be described later). Therefore, for example, when the frequency of the clock signal is 1 GHz, the bit length of the counter 1005 needs to be 5 bits (0 to 31) or more in order to be able to set a delay time of 30 ns.

  In the above, it is described that the counter 1005 performs the counting operation based on one or more basic clock signals. Here, when the counter 1005 performs the counting operation with only one basic clock signal, the following phenomenon may occur. That is, as shown in FIG. 9, when the transition times t0 and t3 of the basic clock signal (BASECLK-1 in FIG. 9) and the transition times t1 and t2 of the input signal 1001 (IN in FIG. 9) are close to each other, There is a possibility that an error occurs in the count value stored in the memory 1006 as “the count value when the transition of the input signal 1001 is detected”. In particular, when the difference between these transition times is a time corresponding to the delay time of the logic circuit, the possibility of an error is further increased.

  In order to avoid such a phenomenon, the counter 1005 can also perform a counting operation based on two basic clock signals (BASECLK-1 and BASECLK-2 in FIG. 10). In this case, the original basic clock signal (first basic clock signal) is different from the first basic clock signal in phase by 90 degrees (1/4 cycle delayed or 1/4 cycle advanced). 2 basic clock signals). Thereby, the delay circuit shown in FIG. 2 performs the counting operation using the second basic clock signal even when the transition time of the first basic clock signal and the transition time of the input signal 1001 are close to each other, Malfunctions can be prevented.

  The memory 1006 includes clock signal identification information (for example, a clock signal number) whose timing substantially coincides with the rising or falling edge of the input signal 1001 and a corresponding count value (a count at the time when a transition of the input signal 1001 is detected). Value) and a set are sequentially stored. Note that the memory 1006 needs to have a storage area corresponding to the number of rises and falls of the input signal 1001 that can occur during the set delay time.

  The comparison circuit 1007 confirms the transition information stored in the memory 1006. Specifically, the comparison circuit 1007 compares the count value included in the transition information (the count value at the time when the transition of the input signal 1001 is detected) with the current count value of the counter 1005 to determine a predetermined delay. Check if time has passed. When the comparison circuit 1007 confirms that the predetermined delay time has elapsed, the comparison circuit 1007 outputs the information to the pulse output circuit 1008. Note that the memory 1006 stores corresponding transition information side by side in the order of the rise and fall times of the input signal 1001. Therefore, in accordance with the principle of FIFO (First In First Out), the transition information stored first is read in order, and the comparison circuit 1007 executes the processing.

  After a predetermined delay time has elapsed, the pulse output circuit 1008 selects a clock signal that matches the identification information based on the transition information stored in the memory 1006. The pulse output circuit 1008 controls the rise or fall of the output signal 1002 based on the selected clock signal. In other words, the pulse output circuit 1008 reproduces the signal waveform of the input signal 1001 and outputs it as the output signal 1002 based on the clock signal whose timing substantially coincides with the transition of the input signal 1001 after a predetermined delay time elapses. . This output signal 1002 is input to a power amplifier in the polar modulation PA as an amplified signal to which a desired delay is added, for example.

  Next, the operation of the present invention will be described with reference to FIGS. FIG. 3 shows a timing chart of the input signal 1001 (IN in FIG. 3), the clock signals CLK1 to CLK4, and the basic clock signal BASECLK. FIG. 4 shows an example of transition information of the input signal 1001 stored in the memory 1006. The clock signals CLK1 to CLK4 and the basic clock signal BASECLK are all part of a plurality of clock signals output from the clock signal source 1003.

  In the example of FIG. 3, the counter 1005 increments the internal counter by “1” every time the basic clock signal BASECLK goes high. In other words, the counter 1005 performs a count operation in synchronization with the rising edge of the basic clock signal BASECLK. Therefore, the count value is 0 until time ta, the count value is 1 from time ta to time tb, and the count value is 2 from time tb to the next rising edge (not shown) of the basic clock signal BASECLK.

  On the other hand, the input signal 1001 (IN in FIG. 3) rises at time t1. At this time, the memory 1006 uses the identification information (clock signal CLK2) of the clock signal whose timing substantially coincides with the rising edge of the input signal 1001, and the count value (0) of the counter 1005 at that time as a set of transition information. Remember. Similarly, at time t2 to t4, the memory 1006 stores the identification information of the clock signal whose timing substantially coincides with the transition of the input signal 1001, and the corresponding count value as a set of transition information.

  As a result, the memory 1006 stores transition information of the input signal 1001 as shown in FIG. In the example of FIG. 4, the memory 1006 includes information indicating whether the input signal 1001 is rising or falling, identification information of a clock signal whose timing substantially coincides with the transition of the input signal 1001, and a corresponding count. Value is stored. The binary input signal 1001 is represented only by high or low. Therefore, the rising and falling edges of the input signal 1001 always occur alternately. Therefore, the memory 1006 is not necessarily required to store information indicating whether the input signal 1001 is rising or falling. In this way, transition information of the input signal 1001 is sequentially stored in the memory 1006.

  Thereafter, the signal waveform of the output signal 1002 of the delay circuit, that is, the input signal 1001 to which a predetermined delay is added is reproduced in the following procedure. The counter 1005 adds the count value in synchronization with the basic clock signal. When the count value of the counter 1005 is the sum of the count value included in the transition information initially stored in the memory 1006 and a preset delay time, the comparison circuit 1007 displays the clock signal included in the transition information. Is transferred to the pulse output circuit 1008. The pulse output circuit 1008 selects a clock signal having the same identification information from a plurality of clock signals, and controls rising or falling of the output signal 1002 in synchronization with the clock signal. That is, the pulse output circuit 1008 reproduces the signal waveform of the input signal 1001 and outputs it as the output signal 1002 based on the clock signal whose timing substantially coincides with the transition of the input signal 1001 after a predetermined delay time elapses. With such a circuit configuration, the delay circuit according to this embodiment can add a delay with a time accuracy shorter than the cycle of the clock signal to the input signal 1001.

  As described above, the delay circuit according to the present embodiment detects rising and falling edges of the input signal 1001 based on a plurality of clock signals having different phases. The delay circuit according to the present embodiment reproduces the signal waveform of the input signal 1001 after a predetermined delay time, based on the clock signal whose timing substantially matches the detected transition of the input signal 1001. With such a circuit configuration, the delay circuit according to this embodiment can detect the transition time of the input signal 1001 with a time accuracy shorter than the clock cycle. Thereby, the delay circuit according to this embodiment can add a highly accurate delay to the input signal 1001.

Embodiment 2
FIG. 11 is a block diagram showing a delay circuit according to the second embodiment of the present invention. The delay circuit shown in FIG. 11 differs from the delay circuit shown in FIG. 2 in that a plurality of counters 1005-1 to 1005-4, a plurality of pulse output circuits 1008-1 to 1008-4, and an output synthesis circuit 1009 are provided. Prepare. In the example of the delay circuit illustrated in FIG. 11, the comparison circuit 1007 is not provided. Specifically, the delay circuit illustrated in FIG. 11 includes a clock signal source 1003, an edge detection circuit 1004, counters 1005-1 to 1005-4, a memory 1006, and pulse output circuits 1008-1 to 1008-4. .

  The clock signal source 1003 is a circuit that generates a plurality of clock signals having different phases. The edge detection circuit 1004 is a circuit that detects rising and falling of the input signal 1001 based on a plurality of clock signals. The memory 1006 is a circuit that stores transition information of the input signal 1001 detected using the edge detection circuit 1004. The counters 1005-1 to 1005-4 are circuits that count the number of times the clock signal selected based on the transition information stored in the memory 1006 rises or falls (the number of times it changes to high or low). The pulse output circuits 1008-1 to 1008-4 use the count values of the corresponding counters 1005-1 to 1005-4, and after confirming that a predetermined delay time has elapsed, each pulse output circuit 1008-1 to 1008-4 This is a circuit that outputs one waveform information (rising or falling signal waveform). The output combining circuit 1009 is a circuit that combines the waveform information output from the plurality of pulse output circuits 1008-1 to 1008-4 and outputs it as an output signal 1002. Details will be described below.

  Since the clock signal source 1003 has the same circuit configuration as that of the first embodiment, description thereof is omitted.

  The edge detection circuit 1004 detects a clock signal whose timing substantially coincides with the rising edge or falling edge of the input signal 1001 among the plurality of clock signals. Then, the edge detection circuit 1004 sequentially outputs the identification information (for example, the clock signal number) of the detected clock signal to the memory 1006. That is, since the edge detection circuit 1004 shown in FIG. 11 does not have a common counter unlike the first embodiment, only the identification information of the clock signal is output to the memory 1006 as transition information of the input signal 1001.

  The memory 1006 sequentially stores clock signal identification information (for example, a clock signal number) whose timing substantially coincides with the rising edge or falling edge of the input signal 1001. Note that the memory 1006 needs to have a storage area corresponding to the number of rises and falls of the input signal 1001 that can occur during the set delay time.

  The counters 1005-1 to 1005-4 are provided in the same number as the transition information (clock signal identification information) stored in the memory 1006. In the example of FIG. 11, the case where four counters 1005-1 to 1005-4 are provided is described as an example, but the present invention is not limited to this. An arbitrary number of counters are provided according to the number of pieces of transition information stored in the memory 1006. Here, in the first embodiment, the counter 1005 performs the counting operation using the basic clock signal. On the other hand, in this embodiment, the counters 1005-1 to 1005-4 each perform a count operation using the clock signal selected based on the corresponding transition information. In other words, each of the counters 1005-1 to 1005-4 performs a counting operation in synchronization with a clock signal whose timing substantially matches the transition of the corresponding input signal 1001. The counters 1005-1 to 1005-4 are initialized first, and then give a signal (waveform information) output instruction to the pulse output circuit 1008 when the count value becomes a value corresponding to the set delay time.

  The same number of pulse output circuits 1008-1 to 1008-4 as the counters 1005-1 to 1005-4 are provided. Each of the pulse output circuits 1008-1 to 1008-4 receives an output instruction from the corresponding counter 1005-1 to 1005-4, and each waveform information (rising or falling signal) corresponding to the transition of the input signal 1001. Waveform).

  The waveform information output from each of the pulse output circuits 1008-1 to 1008-4 forms one or two signal waveforms of the input signal 1001 to be reproduced. Therefore, the output synthesis circuit 1009 reproduces the signal waveform of the input signal 1001 by synthesizing the waveform information output from the pulse output circuits 1008-1 to 1008-4.

  Thus, unlike the case of the first embodiment, the delay circuit according to the present embodiment includes a plurality of counters and a pulse output circuit. However, as in the case of the first embodiment, the delay circuit according to the present embodiment detects the rising or falling edge of the input signal 1001 based on a plurality of clock signals. Then, as in the case of the first embodiment, the delay circuit according to the present embodiment receives the input signal after a predetermined time has elapsed based on the clock signal whose timing substantially coincides with the detected transition of the input signal 1001. The signal waveform of 1001 is reproduced. That is, the delay circuit according to this embodiment can add a delay with a time accuracy shorter than the cycle of the clock signal to the input signal 1001, as in the first embodiment. In other words, the delay circuit according to this embodiment can add a highly accurate delay to the input signal 1001.

  Note that the same effect as described above can be obtained even when the edge detection circuit 1004 directly outputs transition information of the input signal 1001 to the counters 1005-1 to 1005-4. In this case, the memory 1006 need not be provided.

Embodiment 3
FIG. 12 is a block diagram showing a delay circuit according to the third embodiment of the present invention. The delay circuit illustrated in FIG. 12 includes a clock signal source 1003, a plurality of pulse delay blocks 1010-1 to 1010-4, an input switch 1011 and an output switch 1012. Each of the pulse delay blocks 1010-1 to 1010-4 includes an edge detection circuit 1004, a counter 1005, and a pulse output circuit 1008. In the example of FIG. 12, a case where four pulse delay blocks 1010-1 to 1010-4 are provided is described as an example, but the present invention is not limited to this. Any number of pulse delay blocks are provided as required.

  The clock signal source 1003 is a circuit that generates a plurality of clock signals having different phases. In each of the pulse delay blocks 1010-1 to 1010-4, the edge detection circuit 1004 is a circuit that detects rising or falling of the digital input signal 1001 based on a plurality of clock signals. The counter 1005 is a circuit that performs a counting operation based on a clock signal whose timing substantially matches the detected transition of the input signal 1001. After confirming that a predetermined delay time has elapsed using the count value of the counter 1005, the pulse output circuit 1008 outputs one waveform information (rising or falling signal waveform) corresponding to the transition of the input signal 1001. Circuit. Each of the pulse delay blocks 1010-1 to 1010-4 includes the edge detection circuit 1004, the counter 1005, and the pulse output circuit 1008 as described above. The input switch 1011 is a circuit that switches the supply destination of the input signal 1001 to one of the pulse delay blocks 1010-1 to 1010-4 every time the input signal 1001 rises or falls. The output switch 1012 is a circuit that reproduces the signal waveform of the input signal 1001 and outputs it as the output signal 1002 by selectively outputting the waveform information output from the pulse delay blocks 1010-1 to 1010-4. Details will be described below.

  The clock signal source 1003 has a circuit configuration similar to that of the above embodiment, and thus description thereof is omitted. The edge detection circuit 1004 has a circuit configuration similar to that of the second embodiment. However, in the present embodiment, since the memory 1006 does not exist, the edge detection circuit 1004 outputs the identification information of the clock signal to the counter 1005. In addition, since the counter 1005 and the pulse output circuit 1008 have the same circuit configuration as that of the second embodiment, description thereof is omitted.

  As described above, one pulse delay block is configured by using the edge detection circuit 1004, the counter 1005, and the pulse output circuit 1008. One pulse delay block outputs one waveform information corresponding to the transition of the input signal 1001 for one transition of the input signal 1001. Therefore, the delay circuit shown in FIG. 12 includes a number of pulse delay blocks corresponding to the transition of the input signal 1001. The delay circuit shown in FIG. 12 switches the connection of these pulse delay blocks using the switches 1011 and 1012 every time waveform information is output from the pulse delay block. As described above, the delay circuit shown in FIG. 12 reproduces the signal waveform of the input signal 1001 by selectively outputting the waveform information output from each pulse delay block.

  Specifically, the input switch 1011 first selects the pulse delay block 1010-1 as the supply destination of the input signal 1001. When the rising edge or falling edge of the input signal 1001 is detected in the pulse delay block 1010-1, the input switch 1011 selects the pulse delay block 1010-2 as the next supply destination of the input signal 1001. The input switch 1011 performs such an operation on each of the pulse delay blocks 1010-1 to 1010-4. The input switch 1011 has a selection circuit (not shown) for controlling such an operation.

  The input switch 1011 may have a circuit configuration that supplies the input signal 1001 to any one of the plurality of pulse delay blocks 1010-1 to 1010-4. Therefore, a general switch that switches the supply destination of the input signal 1001 may be used as long as the circuit configuration has the same function as described above. Alternatively, a circuit configuration in which the input signal 1001 is not supplied to a place other than the supply destination of the input signal 1001 may be controlled using an AND circuit.

  On the other hand, the output switch 1012 first selects the pulse delay block 1010-1. The output switch 1012 switches the selection to the pulse delay block 1010-2 when one waveform information corresponding to the transition of the input signal 1001 is output from the pulse delay block 1010-1. The output switch 1012 performs such an operation on each of the pulse delay blocks 1010-1 to 1010-4. The output switch 1012 has a selection circuit (not shown) for controlling such an operation. The output switch 1012 may have a circuit configuration that selectively outputs waveform information output from any one of the plurality of pulse delay blocks 1010-1 to 1010-4. Therefore, a general switch that switches the output source of the output signal 1002 may be used as long as the circuit configuration has the same function as described above. Alternatively, a circuit configuration using a circuit that generates a logical sum of waveform information output from all the pulse delay blocks 1010-1 to 1010-4 may be used. That is, a circuit configuration having a function equivalent to that of the output synthesis circuit 1009 described in Embodiment 2 may be employed.

  Unlike the case of the second embodiment, the delay circuit according to the present embodiment includes a plurality of edge detection circuits 1004. However, the delay circuit according to this embodiment detects the rising or falling of the input signal 1001 based on a plurality of clock signals, as in the case of the above embodiment. Then, the delay circuit according to this embodiment is configured so that the input after a predetermined delay time elapses based on the clock signal whose timing substantially coincides with the detected transition of the input signal 1001, as in the above embodiment. The signal waveform of the signal 1001 is reproduced. That is, the delay circuit according to this embodiment can add a delay with a time accuracy shorter than the cycle of the clock signal to the input signal 1001 as in the case of the above embodiment. In other words, the delay circuit according to this embodiment can add a highly accurate delay to the input signal 1001.

Embodiment 4
FIG. 13 is a block diagram showing a delay circuit according to the fourth embodiment of the present invention. In the delay circuit shown in FIG. 13, an analog input signal 1001 is used instead of the digital input signal 1001 as compared with the delay circuit shown in FIG. 13 includes a level detection circuit 1013 instead of the edge detection circuit 1004, and a waveform output circuit 1014 instead of the pulse output circuit 1008. Other circuit configurations and operations are the same as those in the first embodiment.

  The delay circuit shown in FIG. 13 includes a clock signal source 1003, a level detection circuit (input signal detection unit) 1013, a counter 1005, a memory 1006, a comparison circuit 1007, and a waveform output circuit 1014.

  The clock signal source 1003 is a circuit that generates a plurality of clock signals having different phases. The level detection circuit 1013 is a circuit that detects a voltage level transition in the analog input signal 1001 based on a plurality of clock signals. The counter 1005 is a circuit that counts the number of rises or falls (number of changes to high or low) of a selected clock signal among a plurality of clock signals. The memory 1006 is a circuit that stores transition information of the input signal 1001.

  The comparison circuit 1007 is a circuit that confirms whether a predetermined delay time has elapsed based on the transition information stored in the memory 1006 and the count value of the counter 1005. The waveform output circuit 1014 is a circuit that reproduces the signal waveform of the input signal 1001 based on the clock signal corresponding to the transition information stored in the memory 1006 after a predetermined delay time has elapsed, and outputs the signal waveform as the output signal 1002. is there.

  In the level detection circuit 1013, a plurality of voltage levels are set in advance. The level detection circuit 1013 detects that the input signal 1001 has transitioned from a certain voltage level (first voltage level) to a different voltage level (second voltage level) based on a plurality of clock signals. Note that the voltage level may be set in the level detection circuit 1013 at regular intervals, similarly to a normal A / D converter (analog / digital converter). Alternatively, in the case of an analog signal, since there is a high possibility that a certain fixed amplitude appears, the voltage level may be set at uneven intervals according to the amplitude.

  The memory 1006 also needs to store information indicating which voltage level the transition is as transition information of the input signal 1001. The waveform output circuit 1014 reproduces the signal waveform of the input signal 1001 after a predetermined delay time based on the transition information stored in the memory 1006 (see FIG. 14). Since other circuit configurations and operations are the same as those in the first embodiment, description thereof is omitted.

  As described above, the delay circuit according to this embodiment adds a delay having a time accuracy shorter than the cycle of the clock signal to the input signal 1001 even in the case where an analog signal is input. It is possible. In other words, the delay circuit according to this embodiment can add a highly accurate delay to the input signal 1001.

  Note that the delay circuit according to the second and third embodiments is also changed to an analog delay circuit by including a level detection circuit 1013 instead of the edge detection circuit 1004 and a waveform output circuit 1014 instead of the pulse output circuit 1008. can do.

Embodiment 5
FIG. 15 is a block diagram showing a polar modulation PA according to the fifth exemplary embodiment of the present invention. In the present embodiment, an example will be described in which the delay circuit shown in FIG. 2 is applied to a polar modulation PA, particularly a circuit called an EER (envelope elimination and restoration) amplifier. As shown in FIG. 15, the amplitude component (AM signal) of the input signal 1001 is detected using the detection circuit 2015 and input to the power supply modulator 2004. On the other hand, the phase component (PM signal) of the input signal 1001 is generated by removing the amplitude component of the input signal 1001 by the limiter circuit 1016 and input to the digital delay circuit 1019. The PM signal output from the delay circuit 1019 and the AM signal output from the power supply modulator 2004 are combined and output using the power amplifier 2001.

  As described above, the low-pass filter provided in the power supply modulator 2004 causes a delay in the AM signal. Therefore, the delay circuit 1019 adds a delay equivalent to the AM signal to the PM signal, thereby substantially matching the phases of the delayed AM signal and the delayed PM signal. Thereby, the polar modulation PA according to the present embodiment can suppress an increase in power consumption.

  In the present embodiment, the case where the delay circuit according to the first embodiment is used as the delay circuit 1019 is described, but the present invention is not limited to this. The delay circuit according to the second and third embodiments may be used as the delay circuit 1019.

Embodiment 5
FIG. 16 is a block diagram showing a polar modulation PA according to the sixth embodiment of the present invention. In the present embodiment, a case will be described in which the delay circuit shown in FIG. 13 is applied to a polar modulation PA, particularly an EER amplifier. As shown in FIG. 16, the amplitude component (AM signal) of the input signal 1001 is detected using the detection circuit 2015 and input to the power supply modulator 2004. On the other hand, the phase component (PM signal) of the input signal 1001 is input to the analog delay circuit 1019 as an analog signal in which the amplitude component remains. The PM signal output from the delay circuit 1019 and the AM signal output from the power supply modulator 2004 are combined and output using the power amplifier 2001.

  As described above, the low-pass filter provided in the power supply modulator 2004 causes a delay in the AM signal. Therefore, the delay circuit 1019 adds a delay equivalent to the AM signal to the PM signal, thereby substantially matching the phases of the delayed AM signal and the delayed PM signal. Thereby, the polar modulation PA according to the present embodiment can suppress an increase in power consumption.

  The present embodiment is the same as the fifth embodiment in that the phase of the PM signal is delayed to match the phase of the AM signal. The difference between the present embodiment and the fifth embodiment is whether the signal delayed using the delay circuit is an analog signal having an amplitude component or a digital signal having no amplitude component. In the present embodiment, the case where the delay circuit according to the fourth embodiment is used as the delay circuit 1019 has been described, but the present invention is not limited to this. As the delay circuit 1019, a circuit in which the delay circuit according to the second and third embodiments is changed to an analog circuit may be used.

  As described above, the delay circuit according to the above embodiment detects the rising and falling edges of the input signal 1001 based on a plurality of clock signals having different phases. The delay circuit according to the above embodiment reproduces the signal waveform of the input signal 1001 after a predetermined delay time, based on the clock signal whose timing substantially coincides with the detected transition of the input signal 1001. With such a circuit configuration, the delay circuit according to the above embodiment can detect the transition time of the input signal 1001 with a time accuracy shorter than the clock cycle. Accordingly, the delay circuit according to the above embodiment can add a highly accurate delay to the input signal 1001.

  In addition, by using the delay circuit according to the above-described embodiment for the polar modulation PA, the polar modulation PA includes the output potential of the power supply modulator (power supply voltage supplied to the power amplifier), the amplified signal of the power amplifier, Can be eliminated. Thereby, the polar modulation PA can suppress an increase in power consumption.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. In the above-described embodiment, the case where a power supply modulator of the VCCP (Voltage Controlled Current Parallel) system is used is described as an example, but the present invention is not limited to this. Similar effects can be obtained even when other types of power supply modulators are used.

1001 Input signal 1002 Output signal 1003 Clock signal source 1004 Edge detection circuit 1005 Counter 1006 Memory 1007 Comparison circuit 1008 Pulse output circuit 1009 Output synthesis circuit 1010 Pulse delay block 1011 Input switch 1012 Output switch 1013 Level detection circuit 1014 Waveform output circuit 1016 Limiter circuit DESCRIPTION OF SYMBOLS 1019 Delay circuit 1020 Clock oscillator 1021 Inverter 1022 Delay line 2001 Power amplifier 2002 DC power supply 2003 Power supply terminal of power amplifier 2001 2004 Power supply modulator 2005 Detection circuit 2010 Operational amplifier (linear amplifier)
2011 Comparator 2012 Driver Amplifier 2013 Switching Amplifier 2014 Inductor 2015 Detector Circuit (Envelope Detector)
2016, 2017 D-flip flop 2017 inverter 2201 amplitude of amplified signal 2202 voltage of power source 2002 2203 output voltage of power source modulator 2004

Claims (10)

An input signal detection unit that detects a time at which the voltage level of the input signal transits from the first voltage level to the second voltage level based on a plurality of clock signals having different phases;
An output signal generation unit that reproduces and outputs the signal waveform of the input signal after a predetermined delay time has elapsed from the transition time based on the detected clock signal corresponding to the transition time of the input signal. Delay circuit. The input signal is a digital signal whose logical value transition time changes from high to low or low to high,
The input signal detector is
The delay circuit according to claim 1, wherein a transition time of a logical value of the input signal is detected based on the plurality of clock signals.   The delay circuit according to claim 1, wherein the input signal is a modulation signal whose phase and amplitude change. The output signal generator is
A counter that performs a counting operation based on any one of the plurality of clock signals;
A storage circuit that stores information of a clock signal corresponding to the transition time of the input signal, and a count value of the counter at the time of detection of the transition time;
Based on the clock signal selected according to the information of the corresponding clock signal after the delay time determined based on the count value stored in the storage circuit and the count value counted using the counter The delay circuit according to any one of claims 1 to 3, further comprising: an output circuit that reproduces and outputs a signal waveform of the input signal. The output signal generator is
A plurality of counters each performing a counting operation based on a clock signal corresponding to each transition time of the input signal;
A plurality of output circuits for generating waveform information for reproducing the signal waveform of the input signal after a delay time determined based on the count value of the corresponding counter;
The delay circuit according to claim 1, further comprising: an output synthesis circuit that synthesizes waveform information output from the plurality of output circuits and reproduces a signal waveform of the input signal. A plurality of the input signal detectors;
A plurality of the output signal generation units corresponding to the plurality of input signal detection units,
The plurality of input signal detectors are
Detecting different transition times among the transition times of the input signal,
The output signal generator is
A counter that performs a counting operation based on a clock signal corresponding to a transition time of the corresponding input signal;
An output circuit for generating waveform information for reproducing the signal waveform of the input signal after a delay time determined based on the count value of the counter,
4. The delay circuit according to claim 1, wherein a signal waveform of the input signal is reproduced based on waveform information generated from the plurality of output signal generation units. 5.   The delay circuit according to claim 1, further comprising a clock signal source that generates a plurality of clock signals having different phases. The counter is
The delay circuit according to claim 1, wherein a count operation is performed based on a clock signal having a transition time different from that of the input signal. An amplifier for amplifying the input signal;
A power supply modulator for controlling a power supply voltage supplied to the amplifier according to the signal amplitude of the input signal;
A polar modulation amplifier comprising: the delay circuit according to claim 1 provided to compensate for a delay between the input signal and the power supply voltage. Detecting a time at which the voltage level of the input signal transits from the first voltage level to the second voltage level based on a plurality of clock signals having different phases;
A control method of a delay circuit that reproduces and outputs a signal waveform of an input signal after a predetermined delay time has elapsed from the transition time based on a detected clock signal corresponding to the transition time of the input signal.

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