JP2012089779A - Semiconductor module and method for manufacturing the same - Google Patents

Abstract

The characteristics of a semiconductor device are improved.
A semiconductor device of the present invention includes a silicon substrate having a (110) plane orientation and a p-channel field effect transistor formed in a pMIS region 1B. This p-channel field effect transistor is arranged inside a gate electrode GE2 arranged through a gate insulating film 3 and a groove g2 provided in the silicon substrate 1 on both sides of the gate electrode GE2, and is made of a lattice constant from Si. And a source / drain region made of SiGe. The groove g2 has a first slope and a second slope that intersects the first slope at the side wall portion located on the gate electrode GE2 side. Thus, the compressive strain applied to the channel region of the p-channel field effect transistor can be increased by setting the shape of the groove g2 to the Σ shape.
[Selection] Figure 11

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, to a semiconductor device having a MISFET and a technique effective when applied to the manufacture thereof.

  At present, miniaturization of transistors and improvement of performance are widely performed. However, the improvement in the performance of a transistor only by miniaturization has a problem of an increase in cost when viewed in terms of performance ratio.

  Therefore, not only the performance improvement of the transistor only by miniaturization but also a technique for improving the performance of the transistor by controlling the stress has appeared.

  As a technique for improving the performance of a transistor using a stress film, for example, a technique for improving the performance by applying SiGe to the source / drain region of a p-channel MISFET formed on a Si substrate has been studied. Yes. Such techniques are disclosed in, for example, Patent Documents 1 and 2 below.

  Also, a compressive stress film is formed on the p-channel MISFET, a tensile stress film is formed on the n-channel MISFET, and stress is applied to the channels of both MISFETs to improve performance, so-called DSL (Dual Stress Liner) ) Is being studied.

JP 2009-26795 A JP 2008-78347 A

  The present inventor considers improving the transistor performance by applying SiGe to the source / drain region of a p-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed on a Si substrate. is doing.

  In order to improve the transistor performance, it is desired to improve the device structure that can apply stress to the channel more effectively. In addition, it is desired to study a manufacturing method for realizing the device configuration.

  Therefore, an object of the present invention is to provide a technique capable of improving the characteristics of a semiconductor device.

  Another object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device having good characteristics.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  Among the inventions disclosed in the present application, a semiconductor device shown in a typical embodiment includes (a) a plane orientation of (110), a substrate made of a first semiconductor, and (b) a first region of the substrate. A p-channel field effect transistor. The p-channel field effect transistor is disposed in (b1) a gate electrode disposed on the first region via a gate insulating film, and (b2) in a groove provided in the substrate on both sides of the gate electrode. And a source / drain region made of a second semiconductor having a lattice constant larger than that of the first semiconductor. The trench has a first slope and a second slope that intersects the first slope at the side wall located on the gate electrode side.

  Among the inventions disclosed in the present application, a method for manufacturing a semiconductor device shown in a representative embodiment includes: (a) a step of preparing a substrate having a (110) plane orientation and made of a first semiconductor; b) forming a first gate electrode on the first region of the substrate via the first gate insulating film. Further, (c) a step of forming sidewall films on both sides of the first gate electrode, and (d) dry etching of the substrates on both sides of the first gate electrode using the sidewall film as a mask, thereby forming both sides of the first gate electrode. Forming a first groove in the substrate. Further, (e) by performing anisotropic wet etching on the first groove, the side wall located on the gate electrode side has a first slope and a second slope that intersects the first slope. Forming a second groove. And (f) forming a semiconductor region made of the second semiconductor in the second groove by epitaxially growing a second semiconductor having a lattice constant larger than that of the first semiconductor from the first and second slopes. Have.

  Among the inventions disclosed in the present application, according to the semiconductor device described in the following representative embodiment, the characteristics of the semiconductor device can be improved.

  In addition, among the inventions disclosed in the present application, according to the method for manufacturing a semiconductor device shown in the following representative embodiment, a semiconductor device with good characteristics can be manufactured.

It is principal part sectional drawing which shows the manufacturing process of the semiconductor device of embodiment. FIG. 3 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 1 in the manufacturing process of the semiconductor device; FIG. 3 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 2 in the manufacturing process of the semiconductor device; FIG. 4 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 3 in the manufacturing process of the semiconductor device; FIG. 5 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 4 in the manufacturing process of the semiconductor device; FIG. 6 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 5 during the manufacturing process of the semiconductor device; It is sectional drawing for demonstrating the etching process in the manufacturing process of the semiconductor device of embodiment. It is a top view for demonstrating the etching process in the manufacturing process of the semiconductor device of embodiment. It is a top view which shows typically the surface orientation of a silicon substrate, and the arrangement direction of a gate electrode. FIG. 8 is a cross-sectional view for explaining an etching step in the manufacturing process of the semiconductor device of the embodiment, and is a cross-sectional view after the first etching following FIG. 7. FIG. 11 is a cross-sectional view for explaining an etching step in the manufacturing process of the semiconductor device of the embodiment, and is a cross-sectional view after the second etching following FIG. 10. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device of embodiment. FIG. 13 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 12 in the manufacturing process of the semiconductor device; FIG. 14 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 13 in the manufacturing process of the semiconductor device; FIG. 15 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, following the process shown in FIG. 14 in the manufacturing process of the semiconductor device; FIG. 16 is a main-portion cross-sectional view illustrating the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 15; FIG. 17 is a main-portion cross-sectional view illustrating the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 16 during the manufacturing process of the semiconductor device; FIG. 18 is a main-portion cross-sectional view illustrating the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 17 in the manufacturing process of the semiconductor device; FIG. 19 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 18 in the manufacturing process of the semiconductor device; FIG. 20 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 19 in the manufacturing process of the semiconductor device; FIG. 21 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, which is subsequent to FIG. 20 in the manufacturing process of the semiconductor device; It is a top view which shows the structural example of the semiconductor chip using the semiconductor device of embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments illustrating the present invention will be described in detail with reference to the drawings.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment)
Hereinafter, the configuration and manufacturing method of the semiconductor device of the present embodiment will be described in detail with reference to the drawings. 1 to 6 and FIGS. 12 to 21 are cross-sectional views of relevant parts showing the manufacturing process of the semiconductor device of the present embodiment. 7, 10 and 11 are cross-sectional views for explaining the etching process in the manufacturing process of the semiconductor device of the present embodiment. FIG. 8 is a plan view (top view) for explaining an etching process in the manufacturing process of the semiconductor device of the present embodiment. FIG. 7 corresponds to, for example, the AA cross section of FIG. FIG. 9 is a plan view schematically showing the surface orientation of the silicon substrate 1 and the arrangement direction of the gate electrode GE2. FIG. 22 is a plan view showing a configuration example of a semiconductor chip using the semiconductor device of the present embodiment.

[Description of structure]
First, a characteristic configuration of the semiconductor device of the present embodiment will be described with reference to FIG. 21 which is a final process cross-sectional view of the semiconductor device manufacturing process of the present embodiment.

  As shown in FIG. 21, the semiconductor device according to the present embodiment includes an n-channel MISFET Qn1 disposed in an nMIS region 1A of a silicon substrate (semiconductor substrate) 1 and a p-region disposed in a pMIS region 1B of the silicon substrate 1. A channel-type MISFET Qp1. The nMIS region 1A and the pMIS region 1B are active regions (active) partitioned by the element isolation region 2, respectively.

The n-channel type MISFET Qn1 has a gate electrode GE1 disposed on the silicon substrate 1 via a gate insulating film 3, and source / drain regions disposed in the silicon substrate 1 on both sides of the gate electrode GE1. This source / drain region is constituted by an n ⁺ type semiconductor region SD1 and an n ⁻ type semiconductor region EX1.

The p-channel type MISFET Qp1 has a gate electrode GE2 disposed on the silicon substrate 1 via a gate insulating film 3, and source / drain regions disposed in the silicon substrate 1 on both sides of the gate electrode GE2. This source / drain region is constituted by a p ⁺ type semiconductor region SD2 (10) and a p ⁻ type semiconductor region EX2.

The plane orientation of the silicon substrate 1 is (110). The p ⁺ type semiconductor region SD2 constituting the source / drain region of the p channel MISFET Qp1 is arranged in the silicon germanium region 10.

  The silicon germanium region 10 is disposed in the groove g2. The groove g2 has two inclined surfaces on the side surface on the gate electrode GE2 side. One of the two slopes is a slope extending obliquely in the direction below the surface of the silicon substrate 1 and toward the gate electrode GE2. In addition, the other second slope is further below the end of the first slope and extends obliquely in a direction opposite to the direction on the gate electrode GE2 side (direction on the element isolation region 2 side). It is a slope. These two slopes are located below the sidewall SW2. Such a shape of the groove g2 having the first slope and the second slope is referred to as a Σ (sigma) shape.

  Note that the bottom surface of the groove g2 is substantially horizontal. Further, the side surface of the element isolation region 2 is exposed on the side surface of the groove g2 opposite to the gate electrode GE2 side.

  The silicon germanium region 10 is a region in which crystals are grown inside the groove g2.

  A metal silicide layer 23 is disposed on the silicon germanium region 10.

  Thus, according to the present embodiment, since the silicon substrate 1 having the plane orientation (110) is used, in the p-channel type MISFET Qp1, <110> having a high hole mobility can be used as a channel. The characteristics of the p-channel type MISFET Qp1 can be improved.

  Further, since the silicon germanium region 10 having a lattice constant larger than that of the silicon substrate 1 is used as the source / drain region, compressive strain can be applied to the channel region of the p-channel type MISFET Qp1, as will be described in detail later. The characteristics of the p-channel type MISFET Qp1 can be improved. Here, the lattice constant means the length of the side forming the unit cell of the crystal.

  Further, by forming the groove g2 in the Σ shape, it is possible to increase the compressive strain applied to the channel region of the p-channel type MISFET Qp1.

[Production method explanation]
Next, the method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 1 to 21 and the configuration of the semiconductor device will be clarified.

  First, as shown in FIG. 1, a silicon substrate 1 is prepared as a semiconductor substrate (semiconductor wafer). Specifically, for example, a silicon substrate 1 made of p-type single crystal silicon is prepared. The plane orientation of the silicon substrate 1 is (110). The plane orientation (110) means that the surface of the substrate 1 is the (110) plane. Note that (hkl) represents a Miller index. (Hkl) represents a surface, and <hkl> represents a normal vector with respect to the (hkl) surface.

  The silicon substrate 1 includes an nMIS region (second region) 1A in which an n-channel type MISFET is formed, a pMIS region (first region) 1B in which a p-channel type MISFET is formed, have.

  Next, an element isolation region 2 is formed on the main surface of the silicon substrate 1. For example, element isolation trenches are formed in the silicon substrate 1 so as to surround the nMIS region 1A and the pMIS region 1B, and an element isolation region 2 is formed by embedding an insulating film in the element isolation trench (see FIG. 8). . Such an element isolation method is called an STI (Shallow Trench Isolation) method. In addition, the element isolation region 2 may be formed using a LOCOS (Local Oxidization of Silicon) method or the like.

  Next, after the surface of the silicon substrate 1 is cleaned (washed) by wet etching using a hydrofluoric acid (HF) aqueous solution, for example, as shown in FIG. A thin silicon oxide film is formed by a thermal oxidation method. Next, a silicon film 4 is formed as a conductive film on the gate insulating film 3 with a film thickness of about 50 to 150 nm by using, for example, a CVD (Chemical Vapor Deposition) method. As this silicon film 4, for example, a polycrystalline silicon film containing impurities (a doped polysilicon film) can be used. Further, an amorphous silicon film may be formed at the time of film formation and polycrystallized by heat treatment. As this heat treatment, for example, activation annealing of impurities introduced for forming the source / drain regions can be used. Further, after forming a silicon film not containing impurities, impurities may be implanted by an ion implantation method.

  Next, a silicon oxide film 5 is formed as an insulating film on the silicon film 4, and a silicon nitride film 6 is formed as an insulating film on the silicon oxide film 5. The silicon oxide film 5 and the silicon nitride film 6 can be formed using, for example, a CVD method. The film thickness (deposition film thickness) of the silicon oxide film 5 is, for example, about 2 to 8 nm. The thickness (deposited film thickness) can be about 10 to 60 nm, for example.

  Next, as shown in FIG. 3, a photoresist film (not shown) is formed on the laminated film of the silicon film 4, the silicon oxide film 5 and the silicon nitride film 6, and is exposed and developed (photolithography). The photoresist film is left in the region (here, the formation region of the gate electrodes GE1 and GE2). Next, the laminated film is etched using the remaining photoresist film as a mask, and the photoresist film is removed. Hereinafter, a process of forming a film having a desired planar shape by forming a film having a predetermined planar shape and performing etching (selective removal) using the film as a mask will be referred to as patterning. By this patterning step, the gate electrode GE1 made of the silicon film 4 is formed in the nMIS region 1A, and the gate electrode GE2 made of the silicon film 4 is formed in the pMIS region 1B. On the gate electrodes GE1 and GE2, a cap insulating film CP made of a laminated film of a silicon oxide film 5 and a silicon nitride film 6 is disposed, respectively.

  Next, as shown in FIG. 4, for example, a silicon oxide film 7 is formed as an insulating film on the main surface of the silicon substrate 1 including the sidewalls of the gate electrodes GE <b> 1 and GE <b> 2. The silicon oxide film 7 is formed with a film thickness of about 4 to 20 nm using, for example, a thermal oxidation method. The silicon oxide film 7 may be formed by a CVD method. In this case, the silicon oxide film 7 is also formed on the silicon nitride film 6.

  Next, a silicon nitride film 8 is formed as an insulating film on the silicon oxide film 7 and the silicon nitride film 6. The silicon nitride film 8 is laminated with a film thickness necessary for forming a side wall to be described later, for example, a film thickness of about 50 nm by using, for example, a CVD method.

  Next, as shown in FIG. 5, a photoresist film is applied onto the silicon nitride film 8, and this photoresist film is exposed and developed to leave the photoresist film PR1 so as to cover the nMIS region 1A.

  Next, the silicon nitride film 8 and the silicon oxide film 7 in the pMIS region 1B are anisotropically etched (etched back). As a result, a sidewall (sidewall insulating film, sidewall spacer) SW1 made of the silicon oxide film 7 and the silicon nitride film 8 is formed on the sidewall portion of the gate electrode GE2 in the pMIS region 1B. Thereafter, the photoresist film PR1 is removed.

  Next, as shown in FIG. 6, in the pMIS region 1B, etching is performed using the silicon nitride film 6 on the gate electrode GE2 and the sidewall SW1 as a mask, and silicon substrates on both sides of the combined pattern of the gate electrode GE2 and the sidewall SW1. A groove g2 is formed in 1. This etching is performed by two-step etching. After the groove g1 is formed by the first etching, the second etching is further performed to form the groove g2.

<Description of the first and second etching steps>
Hereinafter, the first etching step and the second etching step will be described with reference to FIGS. In FIG. 6 and the like, the surface of the element isolation region 2 and the surface of the silicon substrate 1 are described at the same position. However, the heights of these elements vary depending on various processes. In FIG. 7 and the like, this difference in height is clearly shown.

<1> Description of Shape of Each Component before First Etching First, referring to FIGS. 7 and 8, sidewalls (silicon oxide film 7, silicon nitride film 8) SW1 and gate electrode GE2 serving as a mask for this etching are used. The shape of the upper cap insulating film (laminated film composed of the silicon oxide film 5 and the silicon nitride film 6) CP will be described.

  As shown in FIG. 7 (sectional view), the sidewall SW1 is located on the sidewall of the gate electrode GE2, and the cap insulating film CP is located on the gate electrode GE2. Therefore, the gate electrode GE2 is covered with the sidewall SW1 and the cap insulating film CP. Etching is performed using the sidewall SW1 and the cap insulating film CP as a mask, thereby etching the silicon substrate 1 exposed from the end portion of the sidewall SW1, thereby forming grooves (g1, g2).

  Further, as shown in FIG. 8 (plan view), the pMIS region (1B) where the p-channel MISFET (Qp1) is formed is an exposed region (active region) of the silicon substrate 1 surrounded by the element isolation region 2. is there. Here, the planar shape (the shape and pattern seen from the upper surface) is shown as a substantially first rectangular region a. The long side of the first rectangle extends in the x direction, and the short side extends in the y direction. As is apparent from FIG. 9, the x direction is the <110> direction and the y direction is the <100> direction.

  The planar shape of the gate electrode GE2 is a substantially second rectangular shape, and is arranged at the substantially central portion of the region a. The short side of the second rectangle extends in the x direction (<110> direction), and the long side extends in the y direction (<100> direction). The long side of the second rectangle extends across the region a, but the short side extends on the element isolation region 2. The planar shape of the cap insulating film CP above the gate electrode GE2 is also approximately the second rectangle.

  The combined planar shape of the cap insulating film CP and the sidewall SW1 is a substantially third rectangular shape that is slightly larger than the second rectangular shape. The short side of the third rectangle extends in the x direction (<110> direction), and the long side extends in the y direction (<100> direction). The long side of the third rectangle extends across the region a, but the short side extends on the element isolation region 2.

  On both sides of the third rectangular shape, substantially fourth rectangular regions e1 and e2 are arranged as exposed regions of the silicon substrate 1, respectively. Grooves (g1, g2) are formed in this region e1. Grooves (g1, g2) are formed in this region e2. The long sides (end portions) of the regions e1 and e2 on the gate electrode GE2 side extend in the y direction (<100> direction). As will be described in detail later, the first inclined surface of the groove g2 extends obliquely downward from the long side (end portion) on the gate electrode GE2 side of the regions e1 and e2 in the direction toward the gate electrode GE2. It will be.

  FIG. 9 schematically shows the plane orientation of the silicon substrate 1 and the arrangement direction of the gate electrode GE2. The gate electrode GE2 and the like are arranged in a very fine shape with respect to the size of the silicon substrate 1. Needless to say. The plan view shown in FIG. 8 is an example, and various changes can be made to the shape of the active region and the layout of the gate electrode GE2. For example, the shape of the active region may be L-shaped. Further, when the gate electrode GE2 is routed to connect to the gate electrode of another MISFET, there may be a portion extending in a direction other than the <100> direction in the planar shape of the gate electrode GE2.

  Next, a process of etching the silicon substrate 1 (regions e1 and e2) on both sides of the combined pattern of the gate electrode GE2 and the sidewall SW1 using the sidewall SW1 and the cap insulating film CP having the above shape as a mask will be described.

<2> Description of First Etching Step First, the first etching is performed. Specifically, as shown in FIG. 10, in the pMIS region 1B, the silicon substrate 1 on both sides of the combined pattern of the gate electrode GE2 and the sidewall SW1 is etched from the surface to a predetermined depth to form a groove (substrate recess portion). , Substrate receding portion) g1 is formed. This first etching is performed by anisotropic dry etching, and the groove shape is substantially box-shaped. For example, the depth of the groove is about 30 nm to 50 nm. By the first etching, the first side surface is exposed on the gate electrode GE2 side of the groove g1, and the second side surface is exposed on the element isolation region 2 side. Here, the side wall of the element isolation region 2 is exposed as the second side surface.

<3> Explanation of Second Etching Step Next, the second etching is performed. Specifically, as shown in FIG. 11, the silicon substrate 1 exposed from the bottom surface of the groove g1 is further retreated by about 30 nm to 50 nm.

This second etching is performed by anisotropic wet etching. As the anisotropic wet etching solution, for example, a TMAH (Tetramethyl ammonium hydroxide; N (CH ₃ ) ₄ OH) etching solution can be used. For example, anisotropic wet etching is performed at 23 ° C. using an ultrapure water diluted solution containing 2.38% by weight of TMAH.

  If such anisotropic wet etching is used as the second etching, etching proceeds in an oblique direction from the first side surface of the groove g1, and as shown in FIG. 11, the side wall portion located on the gate electrode GE2 side. , A Σ (sigma) -shaped groove g2 having a first slope and a second slope that intersects the first slope can be formed.

  The plane orientations of these two slopes will be described in more detail. One of the two slopes is a slope extending downward from the surface of the silicon substrate 1 and obliquely extending in the direction of the gate electrode GE2, and the other second slope is the first slope. It is a slope that extends further downward from the end of one slope and extends obliquely in a direction opposite to the direction on the gate electrode GE2 side (direction on the element isolation region 2 side). In other words, as shown in FIG. 11, one of the two slopes intersects the (110) plane at an angle (α1) on the upper side, and the other is on the lower side with respect to the (110) plane. Cross at an angle (α2). The formed angles α1 and α2 are each less than 90 °, and are preferably substantially equal. The two slopes are located below the sidewall SW1.

  As described above in detail, since the first slope and the second slope constituting the Σ (sigma) -shaped groove g2 enter below the sidewall SW1, the compressive strain applied to the channel region of the p-channel type MISFET Qp1 Can be increased.

  On the other hand, the bottom surface of the groove g2 recedes from the bottom surface of the groove g1, but the bottom surface is substantially horizontal.

  Thus, according to the present embodiment, the Σ-shaped groove g2 can be formed. Therefore, compressive strain can be applied to the channel region of the p-channel type MISFET by epitaxial growth of silicon germanium inside the groove g2, which will be described in detail later, and its operating characteristics can be improved.

<4> Explanation of Effect of SiGe Strain Technology That is, compressive stress is applied (applied) to the channel region of the p-channel type MISFET Qp1 (substrate region immediately below the gate electrode GE2) by the silicon germanium region 10, thereby (The mobility of holes in the channel region) can be increased (this technique is called the SiGe strain technique). As a result, the on-current flowing through the channel of the p-channel type MISFET Qp1 can be increased, and high-speed operation can be achieved.

  The reason why the silicon germanium region 10 exerts compressive stress on the channel region is mainly due to the fact that the lattice constant of silicon germanium (silicon germanium region 10) is larger than the lattice constant of silicon (silicon substrate 1).

  Further, when the SiGe strain technique as described above is used, it is preferable to use a <110> channel having a high sensitivity to mobility (hole mobility) against strain. That is, the amount of change in hole mobility when the channel region is distorted by compressive stress is higher in the <110> direction than in other directions. Therefore, it is preferable to use the <110> channel in order to improve the mobility and the on-current due to the SiGe strain technique.

  Here, the <110> channel corresponds to the gate length direction of the channel region being the <110> direction of the silicon substrate 1 (see FIG. 9). Thus, by making the channel region of the p-channel type MISFET a <110> channel, the effect of improving the hole mobility can be enhanced, and the effect of improving the on-current can be enhanced.

On the other hand, it is preferable not to apply the SiGe strain technique as described above to the n-channel MISFET Qn1. This is because, in the n-channel MISFET Qn1, when compressive stress acts on the channel region, the mobility of electrons as carriers decreases. For this reason, the nMIS region 1A is covered with the silicon nitride film 8 (see FIG. 6), the groove g2 is not formed, and a source / drain region (n ⁺ type semiconductor region SD1) made of silicon is formed as will be described later. (See FIG. 15).

  Thus, by applying the SiGe strain technique as described above to the p-channel type MISFET Qp1 and not applying the SiGe strain technique as described above to the n-channel type MISFET Qn1, the channel region of the n-channel type MISFET Qn1 The mobility of holes in the channel region of the p-channel type MISFET Qp1 can be improved without reducing the mobility of electrons in. Accordingly, the on-current of the p-channel MISFET Qp1 can be improved without reducing the on-current of the n-channel MISFET.

<Explanation of SiGe growth process>
Next, as shown in FIG. 12, silicon germanium (SiGe) is epitaxially grown (crystal growth) in the groove g2 of the pMIS region 1B. Si (silicon substrate 1) and SiGe have approximate lattice constants, and can be formed as continuous crystals only by adjusting the source gas in the vapor phase epitaxy method. This silicon germanium is grown until the groove g2 is filled. In this way, a silicon germanium region (SiGe region, silicon germanium layer, epitaxial silicon germanium layer) 10 is formed. Further, silicon (Si) is epitaxially grown continuously on the silicon germanium region 10 to form a silicon region (silicon layer, epitaxial silicon layer) 11. The silicon germanium region 10 can be formed to a thickness of about 40 to 100 nm, for example, and the silicon region 11 can be formed to a thickness of about 5 to 20 nm, for example.

The silicon germanium region 10 can be formed, for example, by epitaxial growth using silane-based gas and germane-based gas as source gases. For example, monosilane gas (SiH ₄ ) or dichlorosilane (SiH ₂ Cl ₂ ) can be used as the silane-based gas. Moreover, monogermane gas (GeH ₄ ) or the like can be used as the germane gas. Here, by forming a film in a state where the source gas contains a p-type doping gas (p-type impurity addition gas) such as borohydride (B ₂ H ₆ ), for example, p A silicon germanium region 10 of the mold is formed. Note that after forming the non-doped silicon germanium region 10, p-type impurity ions may be implanted by an ion implantation method. This ion implantation step will be described later.

  In this silicon germanium and silicon epitaxial growth step, the region other than the groove g2 is covered with the silicon nitride film 6, the sidewall SW1, or the silicon nitride film 8, so that the silicon germanium region 10 (and the silicon on it) Region 11) is not formed. Accordingly, the silicon germanium region 10 (and the silicon region 11 thereon) is formed in the pMIS region 1B, but not in the nMIS region 1A.

  Next, a silicon oxide film (not shown) is formed on the surface of the silicon region 11 by oxidizing the surface layer portion of the silicon region 11 by a thermal oxidation method or the like. This silicon oxide film serves as an etching protective film for preventing the silicon region 11 and the silicon germanium region 10 from being etched when the silicon nitride film 8 described later is removed.

  Next, the silicon nitride film 8 in the nMIS region 1A and the silicon nitride film 8 in the sidewall SW1 in the pMIS region 1B are removed by etching using hot phosphoric acid (hot phosphoric acid) or the like. At this time, the silicon nitride film 6 on the gate electrodes GE1 and GE2 can also be removed.

  Next, the silicon oxide film 7 is removed by etching. Here, anisotropic etching is performed to leave the silicon oxide film 7 on the side walls of the gate electrodes GE1 and GE2. During this etching, the silicon oxide film 5 on the gate electrodes GE1 and GE2 is also removed. Further, the above-described silicon oxide film on the surface of the silicon region 11 is also removed. Although all of the silicon oxide film 7 may be removed by wet etching, the gate oxide GE1 and the gate electrode GE1 and GE2 are left on the side walls of the gate electrodes GE1 and GE2, so that the gate electrodes GE1 and GE1 and GE2 can be protected. Alternatively, the step of removing the silicon oxide film 7 may be omitted, and ion implantation described later may be performed through the silicon oxide film 7.

Next, as shown in FIG. 13, an n ⁻ type semiconductor region (n ⁻ type extension region) EX1 is formed in the silicon substrate 1 on both sides of the gate electrode GE1 in the nMIS region 1A. Further, a p ⁻ type semiconductor region (p ⁻ type extension region) EX2 is formed in the silicon substrate 1 on both sides of the gate electrode GE2 in the pMIS region 1B.

The n ⁻ type semiconductor region EX1 is formed, for example, by ion-implanting n-type impurities (for example, phosphorus or arsenic) into the nMIS region 1A using the gate electrode GE1 as a mask. By this step, the n ⁻ type semiconductor region EX1 is formed in alignment with the gate electrode GE1. Further, the p ⁻ type semiconductor region EX2 is formed, for example, by ion-implanting a p-type impurity (for example, boron) into the pMIS region 1B using the gate electrode GE2 as a mask. By this step, the p ⁻ type semiconductor region EX2 is formed in alignment with the gate electrode GE2.

  Next, as shown in FIG. 14, for example, a silicon nitride film 13 is deposited as an insulating film on the main surface of the silicon substrate 1 with a thickness of about 10 to 40 nm by a CVD method. Through this step, the gate electrodes GE 1 and GE 2 are covered with the silicon nitride film 13.

  Next, the silicon nitride film 13 is anisotropically etched (etched back) to form sidewalls (sidewall insulating films, sidewall spacers) SW2 made of the silicon nitride film 13 on the sidewalls of the gate electrodes GE1 and GE2 (see FIG. FIG. 15). By this anisotropic etching (etchback), the silicon nitride film 13 other than the portion remaining as the sidewall SW2 on the sidewalls of the gate electrodes GE1 and GE2 is removed. Further, even when the silicon nitride film 6 described above remains on the gate electrodes GE1 and GE2, the silicon nitride film 6 is removed by an anisotropic etching process for forming the sidewall SW2. .

Next, as shown in FIG. 16, an n ⁺ type semiconductor region SD1 is formed in the silicon substrate 1 on both sides of the gate electrode GE1 and the sidewall SW2. The n ⁺ type semiconductor region SD1 is formed by ion-implanting an n-type impurity (for example, phosphorus or arsenic) into the nMIS region 1A.

At this time, since the gate electrode GE1 and the sidewall SW2 on the sidewall function as an ion implantation blocking mask, the n ⁺ type semiconductor region SD1 is formed in alignment with the gate electrode GE1 and the sidewall SW2.

As described above, when the non-doped silicon germanium region 10 is formed as the silicon germanium region 10, ap ⁺ type semiconductor region is formed in the silicon germanium region 10 and the silicon region 11 on the silicon germanium region 10. This p ⁺ type semiconductor region is formed by ion-implanting a p-type impurity (for example, boron) into the pMIS region 1B.

At this time, since the gate electrode GE2 and the sidewall SW2 on the sidewall function as an ion implantation blocking mask, the p ⁺ type semiconductor region is formed in alignment with the gate electrode GE2 and the sidewall SW2. As described above, when the silicon germanium region 10 is formed as the silicon germanium region 10 while introducing p-type impurities, this region (10) becomes the p ⁺ type semiconductor region SD2. In addition, when a p-type impurity (for example, boron) is ion-implanted into the silicon germanium region 10 and the silicon region 11 thereabove, the p ⁺ -type semiconductor region SD2 and the non-doped region below the silicon germanium region 10 are used. And a boundary occurs.

After the ion implantation, annealing treatment (activation annealing, heat treatment) for activating the introduced impurities is performed. For example, spike annealing at about 900 to 1100 ° C. is performed. Thereby, impurities in the n ⁻ type semiconductor region EX1, the p ⁻ type semiconductor region EX2, the n ⁺ type semiconductor region SD1, and the silicon germanium region 10 (p ⁺ type semiconductor region SD2) can be activated.

Through the above steps, a source / drain region having an LDD (Lightly doped Drain) structure is formed. That is, the n ⁺ -type semiconductor region SD1 and the n ⁻ -type semiconductor region EX1 are n-type semiconductor regions (impurity diffusion layers) that function as the source or drain of the n-channel type MISFET Qn1, and the n ⁺ -type semiconductor region SD1 is n ^The impurity concentration is higher and the junction depth is deeper than that of the ⁻ type semiconductor region EX1. The silicon germanium region 10 (p ⁺ type semiconductor region SD2) and the p ⁻ type semiconductor region EX2 are p-type semiconductor regions (impurity diffusion layers) that function as the source or drain of the p-channel MISFET Qp1, and the silicon germanium region 10 (p ⁺ -type semiconductor region SD2) has a higher impurity concentration and a deeper junction depth than the p ⁻ -type semiconductor region EX2.

  Through the above steps, the n-channel MISFET Qn1 is formed in the nMIS region 1A. In addition, a p-channel type MISFET Qp1 is formed in the pMIS region 1B.

Next, the surface of the silicon substrate 1 is cleaned using RCA cleaning or the like. This RCA cleaning is a series of cleaning steps in which cleaning with hydropure acid, cleaning with a mixed solution of ammonia and hydrogen peroxide, and cleaning with a mixed solution of hydrochloric acid and hydrogen peroxide are sequentially performed, followed by cleaning with ultrapure water. Further, after the RCA cleaning, the natural oxide film on the surface of the silicon substrate 1 is removed using hydrofluoric acid or the like. The surface of the gate electrodes GE1, GE2, the n ⁺ type semiconductor region SD1 and the silicon region 11 is exposed by this natural oxide film removal step.

Next, metal silicide layers (23a, 23) are formed on the surfaces of the gate electrodes GE1, GE2 and the source / drain regions (n ⁺ type semiconductor region SD1 and silicon region 11) by salicide (Salicide: Self Aligned Silicide) technology. . Hereinafter, the formation process of the metal silicide layers (23a, 23) will be described.

First, as shown in FIG. 16, for example, a nickel alloy film 21 is sputtered as a metal film on the main surface of the silicon substrate 1 including the gate electrodes GE ^< b> 1, GE ^< b> ² , the n ⁺ type semiconductor region SD ^< b> 1 and the silicon region 11. Use to deposit. Next, a first heat treatment (annealing process) is performed on the silicon substrate 1. By this first heat treatment, the silicon film (4) constituting the gate electrodes GE1 and GE2 and the nickel alloy film 21 are reacted. In addition, the single crystal silicon constituting the n ⁺ type semiconductor region SD1 and the silicon region 11 and the nickel alloy film 21 are reacted. As a result, as shown in FIG. 17, a metal silicide layer 23a, which is a reaction layer of metal and semiconductor, is formed. The metal silicide layer 23a is a metal-rich silicide layer.

Next, the unreacted nickel alloy film 21 is removed by wet etching using, for example, sulfuric acid / hydrogen peroxide. The etching processing time is, for example, about 30 to 60 minutes. As a result, as shown in FIG. 17, the metal silicide layer 23a remains only on the surfaces of the gate electrodes GE1, GE2, the n ⁺ type semiconductor region SD1 and the silicon region 11.

  Next, a second heat treatment (annealing process) is performed on the silicon substrate 1. By performing this second heat treatment, the silicidation reaction further proceeds, and as shown in FIG. 18, the metal silicide layer 23a is close to the stoichiometric ratio in which the composition ratio of the metal element to Si is 1: 1. A stable metal silicide layer 23 is obtained.

In the metal silicide layer 23 formed on the source / drain region (that is, the p ⁺ -type semiconductor region SD2) of the p-channel type MISFET Qp1, the lower silicon germanium region 10 also contributes to the silicidation reaction, and the metal silicide layer 23 In some cases, Ge may be contained. In addition, only the surface layer portion of the silicon region 11 may contribute to the silicidation reaction, and the thin silicon region 11 may remain between the silicon germanium region 10 and the metal silicide layer 23. The metal silicide layer 23 can reduce the connection resistance with the plug PG described later. In the above description, silicidation is performed by two heat treatments. However, for example, the first heat treatment may be performed at a temperature of about 450 ° C. and the second heat treatment may be omitted.

  Next, as shown in FIG. 19, for example, silicon oxide is deposited as an interlayer insulating film 32 on the entire main surface of the silicon substrate 1 using a CVD method or the like. Next, the surface of the interlayer insulating film 32 is planarized using a CMP (Chemical Mechanical Polishing) method or the like.

Next, as shown in FIG. 20, on the source / drain region (n ⁺ type semiconductor region SD1) of the n-channel type MISFET Qn1 and the source / drain region of the p-channel type MISFET Qp1 (silicon germanium region 10 (p ⁺ type semiconductor region SD2)) The contact hole (through hole, hole) CNT is formed by selectively removing the upper interlayer insulating film 32.

  Next, a plug (connection conductor portion) PG is formed by forming a conductive film in the contact hole CNT. In order to form the plug PG, for example, a barrier conductor film (not shown) is deposited on the interlayer insulating film 32 including the inside (on the bottom and side walls) of the contact hole CNT, and then led on the barrier conductor film. The body film is deposited with a film thickness that fills the contact holes CNT. Thereafter, unnecessary main conductor films and barrier conductor films on the interlayer insulating film 32 are removed by a CMP method or an etch back method.

  Next, as shown in FIG. 21, a stopper insulating film 33 and an interlayer insulating film 34 are sequentially formed on the interlayer insulating film 32 including the plug PG. The stopper insulating film 33 has etching selectivity with respect to the interlayer insulating film 34. For example, a silicon nitride film can be used as the stopper insulating film 33 and a silicon oxide film can be used as the interlayer insulating film 34.

  Next, the first layer wiring M1 is formed by a single damascene method. After patterning the interlayer insulating film 34, the stopper insulating film 33 is etched to form a wiring groove. Next, a barrier conductor film (not shown) and a seed layer (not shown) are formed on the interlayer insulating film 34 including the inside of the wiring trench. Next, after a metal plating film is formed on the seed layer using an electrolytic plating method or the like, the metal plating film, the seed layer, and the barrier metal film in regions other than the wiring trench are removed by the CMP method, whereby the first layer The wiring M1 is formed.

  The wiring M1 is electrically connected to the source / drain regions (SD1, SD2) of the n-channel MISFET Qn1 and the p-channel MISFET Qp1, the gate electrodes GE1, GE2, and the like through the plug PG. Thereafter, the second and subsequent wirings are formed by a dual damascene method or the like, but the description thereof is omitted here. Further, the wiring M1 and the second and subsequent layers are not limited to damascene wiring, and can be formed by patterning a wiring conductor film. As the conductor film for wiring, for example, tungsten or aluminum (Al) can be used.

  Thereafter, after forming a protective film or the like on the uppermost wiring, the silicon substrate 1 is cut (divided) by dicing or the like, thereby forming a plurality of semiconductor devices (semiconductor chips).

  FIG. 22 is a plan view showing a configuration example of a semiconductor chip using the semiconductor device of the present embodiment. The semiconductor chip SM1 shown in FIG. 22 has a memory region 41 and a peripheral circuit region 42 in which a circuit (peripheral circuit) other than the memory is formed. The peripheral circuit region 42 includes a logic circuit region 42a in which a logic circuit is formed. As described above, the semiconductor device (MISFET) formed by the above process may be used as a MISFET constituting the memory or the logic circuit.

  As described above in detail, according to the present embodiment, the characteristics of the semiconductor device can be improved.

  Although the present embodiment has been described in detail above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

  The present invention is effective when applied to a semiconductor device and its manufacturing technology.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 1A nMIS region 1B pMIS region 2 Element isolation region 3 Gate insulating film 4 Silicon film 5 Silicon oxide film 6 Silicon nitride film 7 Silicon oxide film 8 Silicon nitride film 10 Silicon germanium region 11 Silicon region 13 Silicon nitride film 21 Nickel alloy Films 23 and 23a Metal silicide layer 32 Interlayer insulating film 33 Stopper insulating film 34 Interlayer insulating film 41 Memory region 42 Peripheral circuit region 42a Logic circuit region a Region α1, α2 Angle CNT Contact hole CP Cap insulating film e1, e2 Region EX1 n ⁻ Type semiconductor region EX2 p ⁻ type semiconductor region g1 groove g2 groove GE1, GE2 gate electrode M1 wiring PD pad electrode PG plug PR1 photoresist film Qn1 n channel type MISFET
Qp1 p-channel MISFET
SD1 n ⁺ type semiconductor region SD2 p ⁺ type semiconductor region SM1 Semiconductor chip SW1, SW2 Side wall

Claims (18)

(A) the plane orientation is (110), and a substrate made of a first semiconductor;
(B) a p-channel field effect transistor formed in the first region of the substrate,
(B1) a gate electrode disposed on the first region via a gate insulating film;
(B2) a source / drain region made of a second semiconductor disposed in a groove provided in the substrate on both sides of the gate electrode and having a lattice constant larger than that of the first semiconductor;
A p-channel field effect transistor having
The groove has a first inclined surface and a second inclined surface intersecting the first inclined surface in a side wall portion located on the gate electrode side.   2. The semiconductor device according to claim 1, wherein the second semiconductor in the source / drain region is epitaxially grown inside the trench.   The semiconductor device according to claim 1, wherein the first semiconductor is silicon (Si), and the second semiconductor is silicon germanium (SiGe).   2. The semiconductor device according to claim 1, wherein a compound layer of the first semiconductor and a metal is formed on the source / drain region made of the second semiconductor.   The semiconductor device according to claim 4, wherein the first semiconductor is silicon, and the compound layer is a metal silicide.   2. The semiconductor device according to claim 1, wherein the groove is formed by dry etching the substrate and then anisotropically wet etching the substrate. Side wall films are disposed on both sides of the gate electrode,
2. The semiconductor device according to claim 1, wherein the first slope and the second slope are located below the sidewall film.   8. The p-type semiconductor region having a concentration lower than that of the source / drain region is disposed in the substrate on both sides of the gate electrode and below the side wall film. Semiconductor device.   2. The semiconductor device according to claim 1, further comprising an n-channel field effect transistor formed in the second region of the substrate.   The semiconductor device according to claim 9, wherein a source / drain region of the n-channel field effect transistor is made of the first semiconductor. (A) preparing a substrate having a plane orientation of (110) and made of a first semiconductor;
(B) forming a first gate electrode on the first region of the substrate via a first gate insulating film;
(C) forming a sidewall film on both sides of the first gate electrode;
(D) forming a first groove in the substrate on both sides of the first gate electrode by dry etching the substrate on both sides of the first gate electrode using the sidewall film as a mask;
(E) By performing anisotropic wet etching on the first groove, a first inclined surface and a second inclined surface intersecting the first inclined surface are formed on the side wall portion located on the gate electrode side. Forming a second groove having:
(F) A semiconductor region made of the second semiconductor is formed in the second groove by epitaxially growing a second semiconductor having a lattice constant larger than that of the first semiconductor from the first slope and the second slope. Process,
A method for manufacturing a semiconductor device, comprising:   12. The method of manufacturing a semiconductor device according to claim 11, wherein the first groove has a box shape.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the second groove has a sigma shape having the first slope and the second slope.   The semiconductor device according to claim 11, wherein the first semiconductor is silicon (Si), and the anisotropic wet etching is performed using a liquid containing tetramethylammonium hydroxide. Method.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the epitaxial growth in the step (f) is performed in a state in which a doping gas is included. The substrate has a second region;
12. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of forming an n-channel field effect transistor in the second region. The step of forming the n-channel field effect transistor includes:
Forming a second gate electrode on the second region of the substrate via a second gate insulating film;
Forming source / drain regions made of the first semiconductor on both sides of the second gate electrode;
17. The method of manufacturing a semiconductor device according to claim 16, further comprising: The first semiconductor is silicon (Si), the second semiconductor is silicon germanium (SiGe),
12. The method of manufacturing a semiconductor device according to claim 11, wherein the epitaxial growth in the step (f) is performed using a silane-based gas and a germane-based gas as source gases.

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