JP2012159370A - Semiconductor device and test method thereof - Google Patents

Abstract

A conventional semiconductor device has a problem that the circuit scale becomes large in order to suppress fluctuations in power supply voltage.
In a semiconductor device according to the present invention, test target circuits 11 to 13, a scan mode control signal SMC, a noise control signal CNT, a clock signal CLK, and a test pattern SIN are input to the test target circuit 12. A test circuit 20 that performs a test. The test circuit 20 maintains a test value based on the test pattern SIN held in the test circuit 20 during a dummy noise generation period in which the noise control signal CNT is enabled. Dummy power supply noise that fluctuates according to the cycle of the clock signal CLK is generated during the noise generation period, and the test target circuit 12 is tested with a test pattern after the dummy noise generation period ends.
[Selection] Figure 6

Description

  The present invention relates to a semiconductor device and a test method thereof, and more particularly to a semiconductor device that performs a function test using a scan chain circuit and a test method thereof.

  In recent years, the circuit scale of semiconductor devices has increased. For this reason, various test methods such as a test method using a scan chain circuit have been proposed in order to efficiently test a large-scale circuit. However, in such a test method, the number of elements operated at a time is larger than that in the normal operation in order to perform the test efficiently. For this reason, power supply noise due to current consumption during testing tends to be larger than power supply noise during normal operation. When performing a wafer level test, the semiconductor device and the test device are connected via a probe needle. The contact resistance between the probe needle and the semiconductor device is larger than the contact resistance of wire bonding. That is, when the wafer level test is performed, the size becomes larger than the semiconductor device after packaging due to the contact resistance between the probe needle and the semiconductor device.

  In order to ensure appropriate performance, semiconductor devices take measures at the time of design against power supply noise in normal operation after packaging. However, measures against power supply noise during testing are usually not taken because the circuit scale increases or design restrictions become too large. For this reason, if the power supply noise increases during the test, there is a problem that a false determination in which a failure determination is made in a test that is supposed to be a pass determination due to a larger power supply noise than in a normal operation occurs, resulting in a decrease in yield. Therefore, Patent Literature 1 and Non-Patent Literature 1 disclose methods for reducing power supply noise during testing.

  In the semiconductor device, when the supply of the clock signal is stopped after the function test, all the gates of the internal transistors are turned off, so that the power consumption voltage is increased as the current consumption rapidly decreases. In the test method disclosed in Patent Document 1, dummy test data is further supplied in post-processing after a function test of the semiconductor device. Furthermore, in the test method of Patent Document 1, post-processing is performed based on a system clock that is slower than the function test. FIG. 11 shows a timing chart of a clock supply procedure according to the test method of Patent Document 1. Thereby, in patent document 1, the overshoot of the power supply voltage after a functional test is suppressed.

  However, the test method described in Patent Document 1 is to reduce the fluctuation of the power supply voltage generated after the function test with a dummy clock, and cannot reduce the fluctuation of the power supply voltage during the scan test. The test method of Patent Document 1 takes measures against the phenomenon that the gate of the entire semiconductor device changes from on to off after the function test, and the voltage change time is several tens of microseconds. On the other hand, the fluctuation of the power supply voltage during the scan test is generated in synchronization with the operation of the launch clock and the capture clock, and it is known that the voltage fluctuation time is several tens of nsec in the high-speed scan test. Yes.

  The test method of Patent Document 1 mitigates sudden fluctuations in power supply voltage that occur when operating over a period of several tens of microseconds by slowing down the operating speed. That is, the test method disclosed in Patent Document 1 cannot reduce instantaneous power supply voltage fluctuations during a scan test. The clock speed at the time of the scan test is determined at the time of the test, and the clock speed cannot be reduced for the purpose of reducing fluctuations in the power supply voltage. In addition, since the test method of Patent Document 1 aims to reduce the fluctuation of the power supply voltage after the function test, the fluctuation of the power supply voltage that occurs during the test cannot be reduced.

  Therefore, Non-Patent Document 1 proposes a test method for suppressing power supply voltage fluctuation during a scan test. In Non-Patent Document 1, a power supply noise generation circuit is provided in a semiconductor device. In the test method described in Non-Patent Document 1, the power supply noise generation circuit is operated after the scan clock shift clock is input, and then the power supply noise generation circuit operation is stopped in accordance with the input of the capture clock. As a result, Non-Patent Document 1 alleviates fluctuations in the power supply voltage that occur during capture. Here, FIG. 12 shows a timing chart at the time of a test by the test method described in Non-Patent Document 1.

JP2007-108016A

"Voltage Transient Detection and Induction for Debug and Test", Rex Petersen, Pankaj Pant, Pablo Lopez, Aaron Barton, Jim Ignowski, Doug Josephson, ITC, 2009

  However, the technique described in Patent Document 2 requires a power supply noise generation circuit in the semiconductor device. This power supply noise generating circuit is composed of many analog transistors. The amount of power supply voltage fluctuation that can be reduced is determined by the scale or number of power supply noise generation circuits.

  In recent years, in semiconductor devices, the number of integrated elements has increased due to multifunctionalization, and an increase in circuit scale due to a test circuit must be suppressed as much as possible. On the other hand, in Non-Patent Document 1, a power supply noise generation circuit must be newly added in order to reduce power supply noise during a scan test. That is, when Non-Patent Document 1 is used, there is a problem that the circuit scale increases.

  One aspect of a semiconductor device according to the present invention is a test circuit that receives a test target circuit, a scan mode control signal, a noise control signal, a clock signal, and a test pattern, and performs a test on the test target circuit; The test circuit maintains a test value based on the test pattern held in the test circuit during a dummy noise generation period in which the noise control signal is enabled, and the clock signal during the dummy noise generation period. The dummy power supply noise which fluctuates according to the period is generated, and the test target circuit is tested with the test pattern after the dummy noise generation period ends.

  One aspect of a test method for a semiconductor device according to the present invention is a test in which a test target circuit, a scan mode control signal, a noise control signal, a clock signal, and a test pattern are input and a test is performed on the test target circuit. A test method based on the test pattern held in the test circuit during a dummy noise generation period in which the noise control signal is enabled to generate the dummy noise. A dummy power supply noise that fluctuates according to the period of the clock signal is generated in a period, and the test target circuit is tested with the test pattern after the dummy noise generation period ends.

  In the semiconductor device and the test method thereof according to the present invention, the dummy power supply noise indicating the voltage fluctuation corresponding to the cycle of the clock signal is generated while holding the value corresponding to the test pattern before performing the functional test based on the test pattern. . That is, in the semiconductor device and the test method according to the present invention, the dummy power supply noise is generated by the clock signal. And the amplitude of the power supply noise which arises by the function test based on a test pattern is suppressed by dummy power supply noise.

  According to the semiconductor device and the test method of the present invention, it is possible to suppress power supply noise while suppressing an increase in circuit scale.

1 is a block diagram of a semiconductor device according to a first embodiment; 1 is a block diagram of a scan flip-flop according to a first embodiment. 3 is a timing chart showing a procedure of a test method for the semiconductor device according to the first embodiment; 3 is an equivalent circuit for power supply wiring of a semiconductor device for simulating power supply voltage fluctuations during a test of the semiconductor device according to the first embodiment; It is a graph which shows the power supply voltage fluctuation | variation reproduced by the equivalent circuit shown in FIG. 4 is a graph comparing power supply voltage fluctuations of the semiconductor device according to the first embodiment and a conventional semiconductor device. 6 is a timing chart illustrating a procedure of a test method for a semiconductor device according to a second embodiment; It is a graph which shows the power supply voltage fluctuation | variation at the time of setting a dummy clock to one. It is a graph which shows the power supply voltage fluctuation | variation at the time of setting four dummy clocks. FIG. 6 is a block diagram of a scan flip-flop of a semiconductor device according to a third embodiment. 10 is a timing chart of a clock supply procedure according to the test method of Patent Document 1. 6 is a timing chart at the time of a test by a test method described in Non-Patent Document 1.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of the semiconductor device 1 according to the first embodiment. As illustrated in FIG. 1, the semiconductor device 1 includes combinational circuits 11 to 13 and a test circuit 20. The combinational circuits 11 to 13 are an example of a test target circuit.

  The test circuit 20 receives the scan mode control signal SMC, the noise control signal CNT, the clock signal CLK, and the test pattern SIN, and performs a test on the test target circuit. More specifically, the test circuit 20 maintains a test value based on the test pattern SIN held in the test circuit 20 during the dummy noise generation period in which the noise control signal CNT is enabled, and the clock signal during the dummy noise generation period. Dummy power supply noise that fluctuates according to the period of CLK is generated, and the test target circuit 12 is tested with the test pattern SIN after the dummy noise generation period ends.

  Here, a detailed configuration of the test circuit 20 will be described. As shown in FIG. 1, the test circuit 20 includes scan flip-flops 21 to 2n (n is an integer, the same applies hereinafter) and clock buffer groups 31 to 3n. The clock buffer groups 31 to 3n are provided for controlling the timing at which the clock signal CLK reaches the scan flip-flops 21 to 2n. The number of clock buffers included in the clock buffer groups 31 to 3n and The arrangement is appropriately set at the time of design.

  The scan flip-flops 21 to 2n receive the scan mode control signal SMC, the noise control signal CNT, the clock signal CLK, the test pattern SIN, and the data input signal DIN, respectively, and output an output signal Q. In the following description, the input terminal to which the scan mode control signal SMS is input is the scan mode control signal input terminal SMC, the input terminal to which the noise control signal CNT is input is the noise control signal input terminal CNT, and the clock signal CLK is input. The input terminal is the clock input terminal CLK, the input terminal to which the test pattern SIN is input is the test pattern input terminal SIN, the input terminal to which the data input signal DIN is input is the data input terminal DIN, and the output terminal to which the output signal Q is output It is called output terminal Q.

  When the scan mode control signal SMC is in a state indicating the first mode (for example, low level), the scan flip-flops 21 to 2n hold the test value based on the test pattern SIN in synchronization with the clock signal CLK and output it Output from terminal Q. The scan flip-flops 21 to 2n hold the test value based on the data input signal DIN in synchronization with the clock signal CLK when the scan mode control signal SMC is in the state indicating the second mode (for example, high level). And output as an output signal Q. Furthermore, when the noise control signal CNT is in an enable state (for example, high level), the scan flip-flops 21 to 2n hold the value stored at that time.

  The scan flip-flops 21 to 2n are cascade-connected to form a scan chain circuit. More specifically, the scan flip-flop is input such that the test pattern input terminal SIN is connected to the output terminal Q of the scan flip-flop disposed in the preceding stage. The data input terminals DIN of the scan flip-flops 21 to 2n are connected to one of the combinational circuits 11 and 12. The output terminals Q of the scan flip-flops 21 to 2n are connected to the test pattern input terminals SIN and the combinational circuits 12 and 13 of the scan flip-flops 21 to 2n arranged in the subsequent stage. Note that the test pattern input terminal SIN of the scan flip-flop 21 arranged in the first stage of the scan chain circuit is supplied with the test pattern SIN from the outside. The output terminal Q of the scan flip-flop 2n arranged at the last stage of the scan chain circuit outputs a test result signal SOUT to the outside.

  The scan flip-flops 21 to 2n according to the first embodiment have a configuration different from that of a general scan flip-flop. Specifically, the scan flip-flops 21 to 2n have a configuration capable of switching whether to update or maintain a value held in accordance with the noise control signal CNT as one of the features. Therefore, the configuration of the scan flip-flops 21 to 2n will be described in detail. Since the scan flip-flops 21 to 2n have the same configuration, in the following description, the scan flip-flop according to the first embodiment will be described using the scan flip-flop 21 as an example.

  A detailed block diagram of the scan flip-flop 21 is shown in FIG. As shown in FIG. 2, the scan flip-flop 21 has a test vector holding circuit 50 in a general scan flip-flop 40. The test vector holding circuit 50 prevents the value of the scan flip-flop from being updated during the dummy noise generation period according to the noise control signal.

  A general scan flip-flop 40 includes a flip-flop circuit 41 and a first selector 42. The flip-flop circuit 41 has a clock input terminal, a hold value input terminal D, and an output terminal Q. The flip-flop circuit 41 holds a test value based on a signal applied to the hold value input terminal D in accordance with the clock signal CLK. In the first selector 42, the test pattern SIN is given to the first input terminal (the terminal selected when the scan mode control signal SMC is 0), and the output value of the test target circuit (for example, the data input signal DIN) Is applied to the second input terminal (selected when the scan mode signal is 1), and the value applied to the hold value input terminal D of the flip-flop circuit is switched according to the scan mode control signal SMC.

  The test vector holding circuit 50 has a second selector 51. The second selector 51 receives the test pattern and the output value of the flip-flop circuit 41, and switches a signal to be given as a test pattern to the first selector 42 according to the noise control signal CNT.

  Next, a test method for the semiconductor device 1 according to the first embodiment will be described. First, FIG. 3 shows a timing chart showing the procedure of the test method for the semiconductor device 1 according to the first embodiment. As shown in FIG. 3, the test method of the semiconductor device 1 is called a scan test. A scan flip-flop in which a test pattern is built in synchronization with a clock signal by a first shift operation (SHIFT 1 in FIG. 3). To enter. Next, a dummy noise generation period (period in which the noise control signal CMT is at a high level) is provided, and a dummy noise generation operation (DUMMY in FIG. 3) for generating a dummy power supply noise by inputting a clock during the dummy noise generation period is performed. Next, a test pattern is given to the circuit under test by a launch operation (LAUNCH in FIG. 3). Next, a test result is acquired from the test target circuit by a capture operation (CAPTURE in FIG. 3). In this capture operation, the scan mode control signal SMC becomes high level. Next, the test result is taken out to the external device in the second shift operation (SHIFT2 in FIG. 3).

  As shown in FIG. 3, in the test method of the semiconductor device 1, the noise control signal CNT is set to the high level during the dummy noise generation period. Thus, in the dummy noise generation period, the scan flip-flops 21 to 2n do not update the held test value even when the dummy clock is input. More specifically, when the noise control signal CNT is at a high level and the scan mode signal is at a low level, the output value of the flip-flop circuit 41 is flip-flop circuit via the first selector 42 and the second selector 51. Return to 41.

  In the semiconductor device 1 according to the first embodiment, the clock signal CLK shown in FIG. 3 is input, and the power supply noise during the scan test is reduced by controlling the test circuit 20 with the noise control signal CNT. Therefore, the operation principle for reducing power supply noise will be described in detail below. FIG. 4 shows an equivalent circuit of the power supply wiring of the semiconductor device for simulating the power supply voltage fluctuation during the test of the semiconductor device 1.

  In the equivalent circuit shown in FIG. 4, the power supply that the semiconductor tester gives to the semiconductor device to be tested is shown as the power supply PWR. Then, an equivalent circuit of the power supply wiring from the semiconductor tester to the test target circuit in the semiconductor device is formed by the resistors R1 to R3 and the coil L1. In addition, an equivalent circuit of the ground wiring from the semiconductor tester to the test target circuit in the semiconductor device is formed by the resistors R4 to R6 and the coil L2. More specifically, resistors R1 and R2 are wiring resistances of wiring from the tester to the probe needle, resistors R2 and R5 are contact resistances between the probe needle and the semiconductor device, and resistors R3 and R6 are wirings of power supply wiring in the semiconductor device. The resistors and coils L1 and L2 are inductance components accompanying the wiring. Further, in the equivalent circuit shown in FIG. 4, a bypass capacitor between the power supply grounds provided on the test board on which the probe needle is provided is indicated by a capacitance C. Furthermore, in the equivalent circuit shown in FIG. 4, the current consumption during the test of the semiconductor device is shown as a current IDD.

  FIG. 5 is a graph showing the power supply voltage fluctuation obtained by simulating the fluctuation of the current IDD during the test in the equivalent circuit shown in FIG. In FIG. 5, the upper graph shows the power supply fluctuation, the middle graph shows the current IDD fluctuation by the test method according to the first embodiment, and the lower graph shows the current IDD fluctuation by the general test method. . Further, in FIG. 5, voltage and current fluctuations by the test method according to the first embodiment are shown by solid lines, and voltage and current fluctuations by the conventional test method are shown by broken lines.

  As shown in FIG. 5, in the conventional test method, the current IDD increases according to a clock signal CLK (hereinafter referred to as a launch clock) that performs a launch operation. As the current IDD increases, the power supply voltage VDD decreases. Thereafter, the power supply voltage VDD converges to a preset voltage while repeatedly rising and falling according to the period determined by the electrical characteristics of the power supply wiring and the ground wiring. In FIG. 5, the fluctuation range of the power supply voltage VDD according to the conventional test method is indicated by Vdm0.

  On the other hand, in the test method according to the first embodiment, a clock signal CLK (hereinafter referred to as a dummy clock) input in the dummy noise generation period is input, and the current IDD increases according to the dummy clock. Therefore, the power supply voltage VDD decreases as the current IDD increases. The power supply voltage fluctuation based on the dummy clock is referred to as dummy power supply noise. Note that the fluctuation of the current IDD based on the dummy clock is caused by the operation of the clock buffer groups 31 to 3n transmitting the clock signal CLK. That is, in the semiconductor device according to the first embodiment, the clock buffer groups 31 to 3n that distribute the clock signal CLK to the scan flip-flops 21 to 2n are used as noise sources.

  Thereafter, the power supply voltage VDD rises at a period determined by the electrical characteristics of the power supply wiring and the ground wiring. However, in the test method according to the first embodiment, the launch clock is input at the timing when the power supply voltage VDD rises. Then, the current IDD increases according to the launch clock. This increase in the current IDD suppresses the increase in the power supply voltage VDD, and further reduces the power supply voltage VDD. Thereafter, the power supply voltage VDD repeatedly rises and falls in a cycle determined by the electrical characteristics of the power supply wiring and the ground wiring. In the test method according to the first embodiment, the power supply voltage VDD fluctuates with a waveform obtained by synthesizing the fluctuation waveform of the dummy power supply noise based on the dummy clock and the fluctuation waveform of the power supply voltage VDD based on the launch clock.

  In the test method according to the first embodiment, the dummy clock is input so that the fluctuation of the dummy power supply noise based on the dummy clock and the fluctuation of the power supply voltage VDD based on the launch clock are caused by a phase difference that suppresses the amplitude. To do. As a result, the fluctuation of the power supply voltage VDD caused by the test method according to the first embodiment is smaller than the fluctuation of the power supply voltage VDD caused by the conventional test method. In the example shown in FIG. 5, the fluctuation range Vdm1 of the power supply voltage VDD in the test method according to the first embodiment is smaller than the fluctuation width Vdm0 of the power supply voltage VDD obtained by the conventional test method.

  Next, power supply voltage fluctuations when a launch clock and a capture clock (clock signal CLK input at the time of a capture operation) are input (during an actual test) will be described. FIG. 6 is a graph comparing power supply voltage fluctuations during a test of a semiconductor device and a conventional semiconductor device.

  As shown in FIG. 6, the power supply voltage fluctuation in the conventional test method (without a dummy clock) has a larger fluctuation width when the phase of the power supply voltage fluctuation based on the launch clock is close to the phase of the power supply voltage fluctuation based on the capture clock. Become.

  However, as shown in FIG. 6, even when the launch clock and the capture clock are input at the same period, the test method according to the first embodiment can suppress the amplitude of the power supply voltage fluctuation. . This is a composite waveform of power supply voltage fluctuation waveforms based on the power supply voltage fluctuation based on the dummy clock, launch clock, and capture clock, and the dummy power supply noise caused by the dummy clock is caused by the launch clock and the capture clock. This is because it is generated with a phase that suppresses fluctuations.

  A circuit operation in a scan test of a semiconductor device can be roughly divided into a shift operation and a launch / capture operation. The shift operation is an operation of setting a test pattern in a scan flip-flop in the test circuit, and few circuit elements operate at a time. Therefore, current consumption is small and power supply voltage fluctuation is small. In the shift operation, it is possible to suppress fluctuations in the power supply voltage by reducing the operation speed of the circuit. On the other hand, the launch / capture operation is an operation that gives a test value to the circuit under test based on the test pattern (actual test operation). By operating many circuit elements at once, the test time is shortened (the number of test patterns is reduced). Less). Therefore, in the launch / capture operation, the current consumption is large and the power supply voltage fluctuation is large. In addition, the number of circuit elements that operate at one time during launch / capture operation is larger than that during normal operation of the circuit under test. Bigger than. In general design, circuit operation is assured in consideration of power supply voltage fluctuations during normal operation, so if a larger power supply voltage fluctuation than expected occurs in the launch / capture operation, it is judged that the semiconductor device is normally defective. Made. Furthermore, in the launch / capture operation, since the interval between the launch clock and the capture clock is determined by the specifications of the test target circuit, it is difficult to reduce the power supply noise by adjusting the interval between the two clocks.

  However, in the semiconductor device 1 according to the first embodiment, the dummy power supply noise is generated by inputting the dummy clock, and the amplitude of the power supply noise during the launch / capture operation that is the test operation is reduced by the dummy power supply noise. Further, in the semiconductor device 1, clock buffer groups 31 to 3n that distribute the clock signal CLK to the scan flip-flops 21 to 2n are used as the noise source of the dummy power supply noise. Therefore, in the semiconductor device 1, it is not necessary to add a circuit for reducing power supply noise, and an increase in circuit scale can be prevented.

  Further, the period of fluctuation of the power supply voltage caused by the clock during the scan test depends on the electrical characteristics of the power supply wiring and the ground wiring. However, the conventional method is not a method for controlling the circuit operation in consideration of the period and phase. As a result, there has been a problem that sufficient power supply voltage cannot be relaxed. However, the semiconductor device 1 according to the first embodiment has a function of holding the test value held in the scan flip-flop during the dummy noise generation period in which the dummy clock is input. Thereby, a dummy clock can be input at an arbitrary timing. That is, in the semiconductor device 1 according to the first embodiment, an appropriate dummy clock can be input according to the power supply voltage generated due to the clock signal at the time of the scan test. In the semiconductor device 1 according to the first embodiment, power supply noise during the scan test can be effectively reduced. Furthermore, in the semiconductor device 1 according to the first embodiment, the interval between the dummy clock and the launch clock can be freely set by a tester provided outside, so that fluctuations in the power supply voltage can be more effectively suppressed.

Embodiment 2
In the second embodiment, another embodiment of a dummy clock input method will be described. The semiconductor device to which the test method according to the second embodiment is applied is the same as that of the first embodiment. For this reason, the second embodiment will be described by paying attention only to the difference in the test method.

  In the first embodiment, one dummy clock is input before the launch clock. On the other hand, FIG. 7 shows a timing chart at the time of a test showing a dummy clock input method in the test method according to the second embodiment. As shown in FIG. 7, in the second embodiment, a plurality of dummy clocks (3 clocks in the example of FIG. 7) are input before the launch clock. In this way, by inputting a plurality of dummy clocks, it is possible to effectively suppress fluctuations in the power supply during launch / capture even when the dummy power supply noise generated by the dummy clock is small.

  Therefore, power supply voltage fluctuations when a plurality of dummy clocks are input will be described. First, as a comparative example, FIG. 8 shows a graph showing fluctuations in power supply voltage when one dummy clock is input. In the example shown in FIG. 8, the graph of the power supply voltage VDD and the current IDD when the dummy clock is input is indicated by a solid line, and the graph of the power supply voltage VDD and the current IDD when the dummy clock is not input is indicated by a broken line.

  In the example shown in FIG. 8, as shown in the middle graph, the current IDD flowing by the dummy clock is smaller than the current IDD flowing by the launch clock. Therefore, even if a dummy clock is input, the fluctuation width Vdm1 of the power supply voltage VDD caused by the launch clock is only slightly smaller than the fluctuation width Vdm0 of the power supply voltage VDD when no dummy clock is input. .

  Next, FIG. 9 shows a graph showing fluctuations in the power supply voltage when four dummy clocks are input. In the example shown in FIG. 9, the graph of the power supply voltage VDD and the current IDD when the dummy clock is input is indicated by a solid line, and the graph of the power supply voltage VDD and the current IDD when the dummy clock is not input is indicated by a broken line.

  As shown in FIG. 9, the dummy clock is input in accordance with the fluctuation period of the dummy power supply noise. Therefore, the amplitude of the dummy power supply noise increases every time a dummy clock is input. Then, after four dummy clocks are input, the launch clock is input. At this time, the interval between the last dummy clock and the launch clock is adjusted so that fluctuations in the power supply voltage caused by the launch clock are reduced. Here, referring to FIG. 9, the fluctuation width Vdmn of the power supply voltage VDD suppressed by the four dummy clocks is clearly smaller than the fluctuation width Vdm0 of the power supply voltage VDD generated when there is no dummy clock. Further, comparing FIG. 8 and FIG. 9, it can be seen that the variation width of the power supply voltage VDD is smaller when a plurality of dummy clocks are input than when there is only one dummy clock.

  In the semiconductor device according to the second embodiment, the dummy power source is operated by operating the clock buffer groups 31 to 3n with the dummy clock without updating the test value stored in the scan flip-flop with respect to the input of the dummy clock. Generate noise. Therefore, it is possible that the fluctuation of the current IDD caused by the dummy clock is sufficiently smaller than the fluctuation width of the current IDD caused by the launch clock.

  However, in the method for testing a semiconductor device according to the second embodiment, even when the current IDD flowing by the dummy clock is smaller than the current IDD flowing by the launch clock, the power supply voltage fluctuation can be effectively suppressed. In the test method according to the second embodiment, only the number of dummy clocks to be input is adjusted, and there is no need to add a circuit to adjust the magnitude of dummy power supply noise. That is, according to the test method according to the second embodiment, it is possible to control the magnitude of the dummy power supply noise that can effectively suppress the power supply voltage fluctuation caused by the launch clock and the capture clock without adding a circuit. Have.

Embodiment 3
In the third embodiment, a scan flip-flop 21a that is a modification of the scan flip-flops 21 to 2n will be described. A block diagram of the scan flip-flop 21a is shown in FIG. As shown in FIG. 10, the scan flip-flop 21a also has a configuration capable of switching whether to update or maintain the value held in accordance with the noise control signal CNT. More specifically, the scan flip-flop 21 a includes a general scan flip-flop 60 and a test vector holding circuit 70. The test vector holding circuit 70 prevents the value of the scan flip-flop from being updated during the dummy noise generation period according to the noise control signal CNT.

  A general scan flip-flop 60 includes a flip-flop circuit 61 and a first selector 62. The flip-flop circuit 61 has a clock input terminal, a hold value input terminal D, and an output terminal Q. The flip-flop circuit 61 holds a test value based on a signal applied to the hold value input terminal D in accordance with the clock signal CLK. In the first selector 62, the test pattern SIN is given to the first input terminal (the terminal selected when the scan mode control signal SMC is 0), and the output value of the test target circuit (for example, the data input signal DIN) Is applied to the second input terminal (selected when the scan mode signal is 1), and the value applied to the hold value input terminal D of the flip-flop circuit is switched according to the scan mode control signal SMC.

  The test vector holding circuit 70 has a second selector 71. The second selector 71 receives the clock signal CLK and a fixed value (for example, 0), and switches whether to supply the clock signal CLK to the flip-flop circuit 61 according to the noise control signal CNT.

  That is, also in the scan flip-flop 21a according to the third embodiment, the second selector 71 gives a fixed value to the flip-flop circuit 61 in accordance with the noise control signal CNT, so that the test held in the scan flip-flop 21a. The value update is stopped. Thus, even when the scan flip-flop 21a according to the third embodiment is used as the scan flip-flops 21 to 2n of the semiconductor device 1, the same operation and effect can be obtained between the first embodiment and the third embodiment. .

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11-13 Combination circuit 20 Test circuit 21-2n Scan flip-flop 21a Scan flip-flop 31-3n Clock buffer group 40, 60 Scan flip-flop 41, 61 Flip-flop circuit 42, 62 Selector 50, 70 Test vector holding circuit 51, 71 selector

Claims (18)

The circuit under test,
A test circuit for inputting a scan mode control signal, a noise control signal, a clock signal, and a test pattern, and performing a test on the test target circuit;
The test circuit includes:
Maintaining a test value based on the test pattern held in the test circuit during a dummy noise generation period in which the noise control signal is enabled;
Generating dummy power supply noise that varies according to the period of the clock signal during the dummy noise generation period;
A semiconductor device that tests the test target circuit with the test pattern after the dummy noise generation period ends.   The semiconductor device according to claim 1, wherein the test circuit includes a clock buffer group in a path through which the clock signal is transmitted. The test circuit has a plurality of scan flip-flops connected in cascade,
Each of the scan flip-flops is
A flip-flop circuit that holds a test value based on a signal applied to a hold value input terminal according to the clock signal;
A first selector that switches between the test pattern and the output value of the test target circuit to be applied to the hold value input terminal of the flip-flop circuit according to the scan mode control signal;
A test vector holding circuit that prevents updating of the value of the flip-flop circuit in the dummy noise generation period in response to the noise control signal;
The semiconductor device according to claim 1, comprising: The test vector holding circuit is
4. The test apparatus according to claim 3, further comprising: a second selector that switches between the test pattern and the output value of the flip-flop circuit according to the noise control signal as the test pattern to be given to the first selector. Semiconductor device. The test vector holding circuit is
4. The device according to claim 3, further comprising: a second selector that receives the clock signal and a predetermined fixed value and switches between supply and cutoff of the clock signal to the flip-flop circuit according to the noise control signal. Semiconductor device. The scan flip-flop
A shift operation for shifting the value given by the test pattern in accordance with the clock signal to the next-stage scan flip-flop, and a value held in the scan flip-flop in accordance with the noise control signal regardless of the clock signal Hold operation to maintain, and launch and capture operation to apply the test pattern to the test target circuit in accordance with the clock signal and obtain a test result based on the test pattern,
6. The semiconductor device according to claim 3, wherein a period of the clock signal given in the launch / capture operation is set in accordance with a specification of the test target circuit.   The semiconductor device according to claim 1, wherein the clock signal input during the dummy noise generation period has a period in which the amplitude of the dummy power supply noise is gradually increased.   The semiconductor device according to claim 1, wherein the dummy power supply noise has a phase different from a test power supply noise generated by the clock signal after the dummy noise generation period ends.   The semiconductor device according to claim 1, wherein the scan mode control signal, the noise control signal, the clock signal, and the test pattern are output by a test device provided outside. The circuit under test,
A test method for a semiconductor device having a scan mode control signal, a noise control signal, a clock signal, and a test circuit that receives a test pattern and performs a test on the test target circuit,
Maintaining a test value based on the test pattern held in the test circuit during a dummy noise generation period in which the noise control signal is enabled;
Generating dummy power supply noise that varies according to the period of the clock signal during the dummy noise generation period;
A test method for a semiconductor device, wherein the test target circuit is tested with the test pattern after the dummy noise generation period ends.   11. The method of testing a semiconductor device according to claim 10, wherein the dummy power supply noise is generated due to current consumption by a clock buffer group provided in a path through which the clock signal is transmitted in the test circuit. The test circuit has a plurality of scan flip-flops connected in cascade,
Each of the scan flip-flops is
A test value is held according to the clock signal,
Switching between holding the test pattern and the output value of the test target circuit as the test value according to the scan mode control signal,
12. The method for testing a semiconductor device according to claim 10, wherein updating of the test value in the dummy noise generation period is prevented according to the noise control signal. The scan flip-flop
13. The method of testing a semiconductor device according to claim 12, wherein an output value is fed back as an input signal during the dummy noise generation period. The scan flip-flop
13. The method of testing a semiconductor device according to claim 12, wherein the supply of the clock signal to the flip-flop that holds the test value is stopped in the dummy noise generation period. The scan flip-flop
A shift operation for shifting the value given by the test pattern in accordance with the clock signal to the next-stage scan flip-flop, and a value held in the scan flip-flop in accordance with the noise control signal regardless of the clock signal Hold operation to maintain, and launch and capture operation to apply the test pattern to the test target circuit in accordance with the clock signal and obtain a test result based on the test pattern,
15. The method of testing a semiconductor device according to claim 12, wherein a period of the clock signal given in the launch / capture operation is set according to a specification of the test target circuit.   16. The method of testing a semiconductor device according to claim 10, wherein the clock signal input during the dummy noise generation period has a period in which the amplitude of the dummy power supply noise is gradually increased.   17. The method of testing a semiconductor device according to claim 10, wherein the dummy power supply noise has a phase different from that of the test power supply noise generated by the clock signal after the dummy noise generation period ends.   The semiconductor device according to claim 10, wherein the scan mode control signal, the noise control signal, the clock signal, and the test pattern are output by a test device provided outside. Test method.

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