JP2012159435A - Detection circuit and detection method for battery residual amount, and electronic apparatus using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a battery residual amount detection circuit which can detect a battery residual amount with small power consumption.SOLUTION: A detection circuit 100 is installed in an electronic apparatus 1 with a communication function that comprises at least a battery 2, a CPU 4 and a communication unit 6, to detect a residual amount of the battery 2. An A/D converter 10 performs sampling of magnitude of a current Ireleased from the battery 2 and converts the magnitude into a digital current value D1. When the electronic apparatus 1 is in a waiting mode and the communication unit 6 is in a non-communication state, and if the current value D1 is included in a predetermined range that is assumed, a control unit 18 operates the A/D converter 10 with a first sampling frequency Fs1, and if the current value D1 becomes out of the predetermined range, the control unit 18 operates the A/D converter 10 with a second sampling frequency Fs2>Fs1.

Description

  The present invention relates to a battery remaining amount detection circuit.

  CPUs (Central Processing Units) and DSPs (Digital Signal Processors) that perform digital signal processing in various battery-powered electronic devices such as mobile phone terminals, digital cameras, PDAs (Personal Digital Assistants), and notebook personal computers Each electronic circuit such as a liquid crystal panel and other analog and digital circuits operates with power supplied from a battery.

  Such an electronic device has a function of measuring a current supplied from a battery to a load (hereinafter referred to as a battery current) and integrating the value to detect a remaining battery level, such as a coulomb counter. It is provided by a battery remaining amount detection circuit, also called.

Now, the remaining amount detection in an electronic device having a communication function such as a mobile phone terminal is examined. FIG. 1 is a diagram illustrating an example of a waveform of the battery current I _BAT when the mobile phone terminal is in a standby state (sleep state). Note that the vertical and horizontal axes of the waveform diagrams and time charts in this specification are enlarged or reduced as appropriate for easy understanding, and each waveform shown is also simplified for easy understanding. ing.

Even in the standby state (sleep state), the cellular phone terminal periodically transmits (TX) and receives (RX) packets with the base station for the purpose of location registration and the like. In the transmission period T _TX , a large current flows through a transmission circuit having a power amplifier, a modulator, and a baseband IC (Integrated Circuit), so that the battery current I _BAT increases. At this time, the battery current I _BAT changes dynamically according to the distance from the base station. In the receiving period T _RX, low noise amplifier, a demodulator, for receiving circuit including a baseband IC, etc. to operate, the battery current I _BAT is increased. On the other hand, in a period in which communication is not performed in the standby state (non-communication period), most of the blocks inside the mobile phone terminal are in a standby state, so that the battery current I _BAT becomes extremely small and hardly fluctuates.

In order to accurately integrate the burst current that flows intermittently in the transmission period T _TX and the reception period T _RX , it is necessary to increase the frequency for sampling the battery current I _BAT to increase the resolution in the time axis direction. This is not preferable because it means an increase in power consumption of the remaining amount detection circuit.

  The present invention has been made in view of these problems, and one of exemplary purposes of an embodiment thereof is to provide a remaining battery level detection circuit capable of detecting the remaining battery level with low power consumption.

  One embodiment of the present invention relates to a detection circuit that is mounted on an electronic device having a communication function including at least a battery, a processor, and a communication unit, and detects a remaining battery level. The detection circuit samples the magnitude of the current discharged from the battery and converts it into a digital current value, and the current value indicates that the electronic device is in a standby state and the communication unit is in a non-communication state The A / D converter is operated at the first sampling frequency when included in the predetermined range that is sometimes assumed, and when the current value is out of the predetermined range, the A / D converter is set to the second higher than the first sampling frequency. A control unit that operates at a sampling frequency.

  In this aspect, the sampling frequency is switched according to the level of the current value. When the level of the current value falls within a predetermined range, it is considered as a standby state and a non-communication state where there is almost no fluctuation in the battery current, and by reducing the sampling frequency, it is possible to consume without reducing the detection accuracy. Electric power can be reduced. In a communication state or other load operating condition, by increasing the sampling frequency, it is possible to detect a burst-like battery current that changes sharply in a burst shape, and to accurately integrate the values.

The control unit may stop sampling of the A / D converter for a predetermined period in a state where the electronic device is in a standby state and the communication unit is not communicating based on an instruction from the processor.
In a state where the electronic device is in a standby state and the communication unit does not perform communication, the battery current does not fluctuate and tends to maintain a substantially constant level. The processor can calculate the battery current in the predetermined period or the discharge charge amount of the battery by using the current value detected by the A / D converter or the integrated value thereof. In this aspect, since sampling of the A / D converter is stopped, power consumption can be reduced.

  The control unit may output flag data indicating whether or not the current value is included in a predetermined range to the processor.

  Another aspect of the present invention also relates to a detection circuit that detects a remaining battery level in an electronic device having a communication function including at least a battery, a processor, and a communication unit. The detection circuit samples the magnitude of the current discharged from the battery and converts it into a digital current value, an integration circuit that integrates the current value acquired by the A / D converter, and the A / D And a counter circuit that counts the number of times of sampling by the converter.

  By providing the detection circuit with a function of accumulating and holding the current value, the processor does not need to read out the current value for each sampling of the A / D converter, and the calculation processing amount of the processor, the processor and the detection circuit In the meantime, the number of times of data transmission / reception can be reduced, and power consumption can be reduced.

The detection circuit of an aspect may further include an interface circuit that passes the integration value of the integration circuit and the count value of the counter circuit to the processor when the processor is in an operating state.
In many cases, the processor is in an operating state when the electronic device is in a communication state, and the processor is in an inactive state when the electronic device is in a non-communication state. According to this aspect, data is transferred to the processor in the operating state, and it is unnecessary to start up the processor in the non-operating state, so that power consumption can be further reduced.

  When the current value is included in a predetermined range that is assumed when the electronic device is in a standby state and the communication unit is in a non-communication state, the detection circuit according to an aspect causes the A / D converter to operate at the first sampling frequency. A controller may be further provided that operates and operates the A / D converter at a second sampling frequency higher than the first sampling frequency when the current value is out of a predetermined range.

  The integrating circuit includes a first integrator that is used when the A / D converter operates at the first sampling frequency, a second integrator that is used when the A / D converter operates at the second sampling frequency, May be included. The counter circuit includes a first counter that is used when the A / D converter operates at the first sampling frequency, and a second counter that is used when the A / D converter operates at the second sampling frequency. But you can.

  Yet another embodiment of the present invention is an electronic device having a communication function. The electronic device having the communication function includes a battery, a processor, a communication unit, and the detection circuit according to any one of the above-described aspects that detects the remaining amount of the battery.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, there is provided a detection circuit capable of detecting the remaining battery level with low power consumption.

It is a figure which shows an example of the waveform of the battery current in the standby state (sleep state) of a mobile phone terminal. It is a block diagram which shows the structure of an electronic device provided with the battery remaining charge detection circuit which concerns on embodiment. FIG. 3A is a diagram showing an operation when the standby battery current is sampled at the first sampling frequency, and FIG. 3B is a diagram when the standby battery current is sampled at the second sampling frequency. FIG. FIG. 3 is a waveform diagram showing an operation of the detection circuit of FIG. 2. It is a wave form diagram which shows operation | movement of the detection circuit which concerns on a modification.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected to each other. Including the case of being indirectly connected through other members that do not substantially affect the state of connection, or do not impair the functions and effects achieved by the combination thereof.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

  Further, in this specification, a reference numeral attached to a voltage signal, a current signal, or a resistor represents a voltage value, a current value, or a resistance value as necessary.

FIG. 2 is a block diagram illustrating a configuration of the electronic apparatus 1 including the remaining battery level detection circuit 100 according to the embodiment.
The electronic device 1 includes a battery 2, a CPU 4, a communication unit 6, another load 8, and a battery remaining amount detection circuit (hereinafter also simply referred to as a detection circuit) 100. The electronic device 1 is a mobile phone terminal, for example, and has a communication function with a base station.

The battery 2 is a power source of the electronic device 1, and is a secondary battery such as a lithium ion battery or a nickel metal hydride battery, outputs a battery voltage V _BAT , and is a load such as a CPU 4, a communication unit 6, a load 8 and a detection circuit 100.

  The CPU 4 is a unit that controls the entire electronic device 1 in an integrated manner, and each functional block mounted on the electronic device 1 operates based on a command from the CPU 4. The CPU 4 may be a baseband circuit. The communication unit 6 is a block that communicates with the base station, and modulates a baseband signal from the baseband circuit, a power amplifier that amplifies the transmission signal, and transmits a signal from the power amplifier to the base station. Antenna, an LNA (low noise amplifier) that amplifies the signal received by the antenna from the base station, a demodulation circuit that demodulates the output of the LNA, and the like. The configuration and communication method of the communication unit 6 are not particularly limited.

  The load 8 includes a switching regulator, a linear regulator (LDO: Low Drop Output), a power supply circuit including a charge pump circuit, a battery 2 charging circuit, a DSP (Digital Signal Processor), a liquid crystal panel, and other analog circuits. Including digital circuits.

The battery remaining amount detection circuit 100 is also referred to as a coulomb counter, detects the battery current I _BAT discharged from the battery 2, and detects the remaining amount of the battery 2 through cooperative processing with the CPU 4. The detection circuit 100 includes an A / D converter 10, an integration circuit 12, a counter circuit 14, a register 16, a control unit 18, and an interface circuit 20. The detection circuit 100 may be integrated in one IC together with a charging circuit (not shown), a DC / DC converter control circuit, a linear regulator (LDO: Low Drop Output), and GPIO (General Purpose Input / Output). Such an IC is also called a power management IC.

A detection resistor R _SENSE is provided on the path of the battery current I _BAT discharged from the battery 2. The detection resistor R _SENSE may be provided on the ground terminal side of the battery 2. A voltage drop V _SENSE proportional to the battery current I _BAT occurs in the detection resistor R _SENSE . The detection circuit 100 samples a voltage drop (also referred to as a detection voltage) V _SENSE of the detection resistor R _SENSE and converts it to a digital current value D1 corresponding to the detection voltage V _SENSE .

The A / D converter 10 operates in accordance with the sampling clock _SCLK from the control unit 18. The A / D converter 10 has a variable sampling frequency Fs, and generates a digital current value D1 corresponding to the detection voltage V _SENSE for each sampling period Ts (= 1 / Fs). The discharge amount of the battery 2 is given by the time integration of the battery current I _BAT . That is, the discharge amount of the battery 2 is calculated by integrating the current value D1.

The control unit 18 sets the sampling frequency of the A / D converter 10. When the electronic device 1 is in a standby state (also referred to as a sleep state), the battery current I _BAT is very high except for a period during which the communication unit 6 communicates with a base station (referred to as a communication period) as shown in FIG. Get smaller. The lengths of the communication periods T _TX and T _RX are, for example, about several ms to several tens of ms, and a non-communication period of, for example, several hundred ms to several seconds exists between the communication periods _TX and T _RX .

As described above, in the non-communication period, each block of the electronic device 1 is in a sleep state except for necessary ones, so that the battery current I _BAT becomes very small and the fluctuation thereof becomes small. Therefore, the control unit 18 operates the A / D converter 10 at a relatively low first sampling frequency Fs1 during the non-communication period. The first sampling frequency Fs1 is, for example, 32 ksps (kilo-sample per second).

  Conversely, in the communication period, the control unit 18 causes the A / D converter 10 to operate at the second sampling frequency Fs2 that is higher than the first sampling frequency Fs1. The second sampling frequency Fs2 is, for example, 400 ksps. When the detection circuit 100 operates at the first sampling frequency Fs1 (32 ksps), the current consumption is several hundred μA, for example. When the detection circuit 100 operates at the second sampling frequency Fs2 (400 ksps), the current consumption is several mA. In other words, the consumption current of the detection circuit 100 is large depending on the sampling frequency, and specifically varies nearly 10 times.

FIG. 3A shows the operation when the standby battery current I _BAT is sampled at the first sampling frequency, and FIG. 3B shows the standby battery current I _BAT sampled at the second sampling frequency. It is a figure which shows operation | movement at the time.
As shown in FIG. 3A, when the operation is performed at the first sampling frequency Fs1, the sampling period (1 / Fs1) is not sufficiently shorter than the communication periods T _TX and T _RX. It becomes a detection error.

In FIG. 3B, the battery current I _BAT in FIG. 3A is referred to, and the waveform thereof is omitted. As shown in FIG. 3B, when the second sampling frequency Fs2 is operated, the hatched area is reduced and the detection error is reduced. However, the current consumption of the detection circuit 100 at this time far exceeds the current allowed in the standby state.

Therefore, the control unit 18 determines whether the electronic device 1 is in a non-communication state or a communication state based on the current value D1 corresponding to the battery current I _BAT . Specifically, when the current value D1 is included in a predetermined range assumed when the electronic device 1 is in a standby state and in a non-communication state, the A / D converter 10 is operated at the first sampling frequency Fs1. Let On the other hand, when the current value D1 corresponding to the battery current I _BAT increases during the communication period and deviates from the predetermined range, the detection circuit 100 causes the A / D converter 10 to operate at the second sampling frequency Fs2.

The detection circuit 100 and the CPU 4 are connected via an I ² C (Inter IC) Bus or the like. The interface circuit 20 transmits and receives various data to and from the CPU 4.

  The control unit 18 outputs to the CPU 4 flag data D2 indicating whether or not the current value D1 is included in a predetermined range. For example, the control unit 18 may write the flag data D2 into the register 16, and the interface circuit 20 may transmit the flag data D2 to the CPU 4. Thereby, the CPU 4 can know whether the control unit 18 is operating at the first sampling frequency Fs1 or the second sampling frequency Fs2.

  The current value D1 acquired by the A / D converter 10 may be sent to the CPU 4 every sampling. However, in this case, data transmission occurs between the interface circuit 20 and the CPU 4 every sampling, and the CPU 4 needs to integrate the current value D1 every sampling. Therefore, even if the CPU 4 is in the standby state in the standby state and in the non-communication state, the CPU 4 is activated and performs calculations for the accumulation of the current value D1, and the power consumption of the entire system increases. In order to solve this problem, the detection circuit 100 according to the embodiment has the following characteristics.

The integrating circuit 12 integrates the current value D1 acquired by the A / D converter 10. The integrated value D3 corresponds to the integrated value of the battery current I _BAT , that is, indicates the amount of charge released from the battery 2. The integrated value D3 is written in the register 16.

  The counter circuit 14 counts the number of times that the A / D converter 10 has sampled. A count value D4 indicating the number of samplings is also written into the register 16.

  The interface circuit 20 transmits the integrated value D3 and the count value D4 to the CPU 4 not at every sampling but at a frequency lower than that. As a result, the number of data transmissions is reduced, so that power consumption can be reduced. This transmission may be performed in response to a request from the CPU 4.

More preferably, the interface circuit 20 supplies the integrated value D3 and the count value D4 to the CPU 4 during the period in which the CPU 4 is operating, more specifically during the communication periods T _TX and T _RX , instead of the standby period of the CPU 4. hand over. This eliminates the need to bother to start up the CPU 4 in the standby state, thereby further reducing power consumption.

The CPU 4 calculates the discharge charge amount of the battery 2 based on the flag data D2 indicating the sampling frequency Fs, the integrated value D3, and the count value D4. That is, when the number of samplings indicated by D3 is n, the integrated value D3 is m, and the sampling frequency indicated by the flag data dD2 is Fs, the discharge charge amount Q _DIS is
Q _DIS = m × n × 1 / Fs
It becomes. CPU4 from the detection circuit 100, each time it receives a set of data D2-D4, the discharge charge quantity _{Q DIS} is calculated and added together with it until the cumulated discharge charge quantity _{Q DIS.}

  The integrating circuit 12 includes two integrators 12a and 12b. Similarly, the counter circuit 14 includes two counters 14a and 14b. The set of the first integrator 12a and the first counter 14a is used when the A / D converter 10 operates at the first sampling frequency Fs1, and the set of the second integrator 12b and the second counter 14b is A / D. This is used when the converter 10 operates at the second sampling frequency Fs2.

  That is, the integrated value D3a of the first integrator 12a and the count value D4a of the first counter 14a indicate values when the A / D converter 10 operates at the first sampling frequency Fs1. The integrated value D3b of the second integrator 12b and the count value D4b of the second counter 14b indicate values when operating at the second sampling frequency Fs2.

The above is the configuration of the detection circuit 100. Next, the operation will be described. FIG. 4 is a waveform diagram showing the operation of the detection circuit 100 of FIG. In the standby state of the period t ₀ -t ₁ , the battery current I _BAT hardly flows, so the A / D converter 10 operates at the first sampling frequency Fs 1, and the integrated value D 3 a is operated by the first integrator 12 a and the first counter 14 a. The count value D4a is updated.

The battery current I _BAT increases at the transmission period T _TX when the communication unit 6 transmits data to the base station at time t ₁ . Current value D1 to be sampled in the subsequent time _{t 2,} since the outside of the predetermined range RNG, switched to a second sampling frequency Fs2. During the communication period _{T TX,} second integrator 12b, the integrated value by the second counter 14b D3b and the count value D4b is updated.
The final values m ₁ and n ₁ of the integrated value D3a and the count value D4a are passed to the CPU 4 by the interface circuit 20 during the communication period T _TX in which the CPU 4 is operating.

Communication period _{T TX} is completed in time _{t 3.} Current value D1 acquired by the sampling at time t ₄ when the subsequent is included in a predetermined range RNG. Therefore, the time _{t 4} and later, back to the first sampling frequency Fs1. When the communication period T _TX ends, the CPU 4 enters a standby state. Therefore, the final values m ₂ and n ₂ of the integrated value D3b and the count value D4b are not immediately transmitted to the CPU 4, but are transmitted during the next period in which the CPU 4 returns from the standby state, for example, the next reception period _TRX .

The CPU 4 can calculate the discharge charge amount Q _DIS in the period t _{0 to} t ₆ by the following calculation.
Q _DIS = m ₁ × n ₁ / Fs1 + m ₂ × n ₂ / Fs2

The above is the operation of the detection circuit 100.
According to the detection circuit 100, the sampling frequency Fs can be automatically changed according to the battery current I _BAT , and both high detection accuracy and low current consumption can be achieved.
Further, by providing the detection circuit 100 with a function of integrating the current value D1, data transmission does not occur between the detection circuit 100 and the CPU 4 every sampling, so that the power consumption of the entire system can be reduced.

  Furthermore, the integrated value D3 and the count value D4 acquired in the detection circuit 100 are transmitted to the CPU 4 that is assumed to be operating instead of the standby CPU 4, so that the CPU 4 can be activated unnecessarily. Thus, the power consumption of the system can be reduced.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications may exist in each of those constituent elements, each processing process, and a combination thereof. Hereinafter, such modifications will be described.

(Modification)
When the battery current I _BAT is constant during the non-communication period in the standby state, the following modification is effective. In this modification, the control unit 18 stops sampling of the A / D converter 10 for a predetermined period T _STOP included in the non-communication period in the standby state. This predetermined period T _STOP is controlled by an instruction from the CPU 4. This is because the CPU 4 knows the timing at which the communication unit 6 or other load operates in order to control the entire electronic device 1. Based on the notification from the CPU 4, the detection circuit 100 knows the predetermined period T _STOP that is in the standby state and included in the non-communication period. Then, a stop signal D5 that is asserted (for example, low level) is generated for a predetermined period _TSTOP . The A / D converter 10 stops sampling by the A / D converter 10 while the stop signal D5 is asserted.

FIG. 5 is a waveform diagram showing the operation of the detection circuit 100 according to the modification. Since the sampling is stopped during the period T _{STOP in which} the stop signal D5 is asserted (low level), the integrated value D3a and the count value D4a do not change.

A method in which the CPU 4 having received the final values m ₁ and n ₁ of the integrated value D3a and the count value D4a calculates the discharge charge amount Q _DIS will be described. CPU4 a period that the stop signal D5 is asserted, i.e. knows the length of the sampling of the stop period _{T STOP,} the sampling frequency Fs1 and the sampling period (1 / Fs1) knows. Number _{n STOP} sampling that would originally have occurred in the stop period _{T STOP} is
n _STOP = T _STOP × Fs1
It is. The discharge charge Q _{DIS of the} entire discharge period including the stop period T _STOP is
Q _DIS = m ₁ × n ₁ / Fs1 × (1 + n _STOP ) / n ₁
Can be calculated from

  Thus, according to the detection circuit 100 according to the modification, the power consumption can be further reduced by stopping the sampling of the A / D converter 10 based on the instruction from the CPU 4.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Electronic device, 2 ... Battery, 4 ... CPU, 6 ... Communication unit, 8 ... Load, 100 ... Detection circuit, 10 ... A / D converter, 12 ... Integration circuit, 12a ... 1st integrator, 12b ... 2nd Integrator, 14 ... counter circuit, 14a ... first counter, 14b ... second counter, 16 ... register, 18 ... control unit, 20 ... interface circuit, D1 ... current value, D2 ... flag data, D3 ... integrated value, D4 ... count value, D5 ... stop signal.

Claims (12)

In an electronic device having a communication function having at least a battery, a processor, and a communication unit, a detection circuit that detects the remaining amount of the battery,
An A / D converter that samples the magnitude of the current discharged from the battery and converts it into a digital current value;
When the current value falls within a predetermined range assumed when the electronic device is in a standby state and the communication unit is in a non-communication state, the A / D converter is operated at a first sampling frequency, A controller that operates the A / D converter at a second sampling frequency higher than the first sampling frequency when the current value is out of the predetermined range;
A detection circuit comprising:   The control unit stops sampling of the A / D converter for a predetermined period when the electronic device is in a standby state and the communication unit is in a non-communication state based on an instruction from the processor. The detection circuit according to claim 1.   The detection circuit according to claim 1, wherein the control unit outputs flag data indicating whether or not the current value is included in the predetermined range to the processor. In an electronic device having a communication function having at least a battery, a processor, and a communication unit, a detection circuit that detects the remaining amount of the battery,
An A / D converter that samples the magnitude of the current discharged from the battery and converts it into a current value;
An integrating circuit for integrating the current values acquired by the A / D converter;
A counter circuit for counting the number of times of sampling by the A / D converter;
A detection circuit comprising:   5. The detection circuit according to claim 4, further comprising an interface circuit that transfers an integration value of the integration circuit and a count value of the counter circuit to the processor when the processor is in an operating state.   When the current value falls within a predetermined range assumed when the electronic device is in a standby state and the communication unit is in a non-communication state, the A / D converter is operated at a first sampling frequency, The control unit according to claim 4, further comprising a control unit that causes the A / D converter to operate at a second sampling frequency higher than the first sampling frequency when the current value is out of the predetermined range. Detection circuit. The integration circuit includes:
A first integrator utilized when the A / D converter operates at the first sampling frequency;
A second integrator utilized when the A / D converter operates at the second sampling frequency;
Including
The counter circuit is
A first counter used when the A / D converter operates at the first sampling frequency;
A second counter used when the A / D converter operates at the second sampling frequency;
The detection circuit according to claim 4, comprising: Battery,
A processor;
A communication unit;
The detection circuit according to any one of claims 1 to 7, which detects a remaining amount of the battery;
An electronic device having a communication function. In an electronic device having a communication function having at least a battery, a processor, and a communication unit, a method for detecting the remaining amount of the battery,
Sampling the magnitude of the current discharged from the battery by an A / D converter and converting it to a digital current value;
When the current value falls within a predetermined range assumed when the electronic device is in a standby state and the communication unit is in a non-communication state, the A / D converter is operated at a first sampling frequency, Operating the A / D converter at a second sampling frequency higher than the first sampling frequency when the current value is out of the predetermined range;
A method comprising the steps of:   A step of stopping sampling of the A / D converter for a predetermined period based on an instruction from the processor when the electronic device is in a standby state and the communication unit is in a non-communication state. Item 10. The method according to Item 9. In an electronic device having a communication function having at least a battery, a processor, and a communication unit, a method for detecting the remaining amount of the battery,
Sampling the magnitude of current discharged from the battery by an A / D converter and converting it to a current value;
Integrating the current values;
Counting the number of samplings by the A / D converter;
A method comprising the steps of:   The method of claim 11, further comprising: passing the accumulated current value and the counted value to the processor when the processor is in operation.

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