JP2012160679A - Thin-film transistor, display device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor capable of easily improving the operating speed, and a display device and an electronic apparatus using such a thin-film transistor.SOLUTION: A thin-film transistor 1 comprises: a gate electrode 141; an oxide semiconductor layer 12 composed of a multilayer film including a carrier transit layer 121 constituting a channel and a carrier supply layer 122 for supplying carriers to the carrier transit layer 121; a gate insulating film 131 provided between the gate electrode 141 and the oxide semiconductor layer 12; and source and drain electrodes 16A and 16B. A source and drain region 12SD and a formation region of the gate electrode 141 in the oxide semiconductor layer 12 are spaced apart from each other. The mobility of the carriers can be improved by suppressing transit scattering of the carrier and access resistance to the channel, and the formation of parasitic capacitance can be avoided, without forming a conventional complicated structure.

Description

  The present invention relates to a thin film transistor (TFT) using an oxide semiconductor layer, and a display device and an electronic device using such a thin film transistor.

  In flat panel displays such as liquid crystal displays and organic EL (Electro Luminescence) displays, thin film transistors (TFTs) have been widely put into practical use as drive elements. The thin film transistor is generally manufactured using a semiconductor material such as amorphous (amorphous) silicon (Si) or polycrystalline silicon on a glass substrate.

  A thin film transistor using amorphous silicon is easy to deal with a large area (large) substrate, but has a low field effect mobility (carrier mobility). On the other hand, a thin film transistor using polycrystalline silicon, on the other hand, has a high field effect mobility, but is difficult to adapt to a large substrate.

  On the other hand, it is known that an oxide semiconductor such as zinc oxide (ZnO) or indium / gallium / zinc (InGaZnO) can be formed at a low temperature and has excellent semiconductor characteristics. Therefore, in recent years, application to active thin film transistors in active matrix flat panel displays has been actively studied (for example, see Patent Documents 1 to 7 and Non-Patent Document 1).

  A thin film transistor using such an oxide semiconductor exhibits an electron mobility of 10 times or more as compared with a conventional thin film transistor using amorphous silicon, and also exhibits good off characteristics. Therefore, thin film transistors using an oxide semiconductor are desired to be applied to large-screen, high-definition and high-frame-rate liquid crystal displays and organic EL displays.

JP 2009-272427 A JP 2010-56546 A JP 2006-165227 A JP 2010-74061 A JP 2007-220816 A JP 2007-259883 A JP 2009-278115 A

JOURNAL OF DISPLAY TECHNOLOGY vol5, No.12, 2009

  However, in order to achieve higher performance in a flat panel display, further improvement in carrier mobility is required even in a thin film transistor using such an oxide semiconductor as a channel layer.

  In order to increase the operation speed of the thin film transistor for the purpose of high performance, in addition to the increase in carrier mobility as described above, it occurs in the overlapping portion of the source / drain region and the gate electrode in the oxide semiconductor layer. It is also necessary to reduce the parasitic capacitance.

  Here, in Patent Documents 1 to 4 described above, by performing self-aligned pattern formation using backside exposure, it is attempted to reduce parasitic capacitance as much as it is not necessary to allow for misalignment of mask exposure. In the above Patent Documents 5 to 7, a technique is proposed in which the resistance of the source / drain regions is reduced in a self-aligned manner using a gate electrode as a mask in a so-called top gate type thin film transistor. Among these, in particular, Patent Document 7 discloses a technique (LDD structure) for forming an intermediate resistance region (a so-called LDD (Lightly Doped Drain) region) between a source / drain region and a channel portion. Yes.

  However, when self-aligned pattern formation using backside exposure is performed as in Patent Documents 1 to 4, the source / drain regions and the gate are actually caused by the light diffraction phenomenon during backside exposure. An overlapping portion is generated between the electrodes and it is difficult to reduce the parasitic capacitance.

  In the methods of Patent Documents 5 to 7, in order to use the source / drain regions whose resistance is reduced by plasma irradiation as the source / drain electrodes, the resistivity of the source / drain regions is reduced to about 1/1000 of the channel portion. It is required to be resistant. In order to achieve this, when plasma irradiation using hydrogen gas, argon gas, or the like is performed, there is a problem in that the low-resistance region partially wraps around the region serving as a low-resistance mask or the lower portion of the gate electrode. That is, a parasitic capacitance is generated by overlapping (overlap) of the source / drain regions and the gate electrode. Non-Patent Document 1 reports that the low-resistance region diffuses from the pattern end serving as a mask to the inside of about 2 μm at the maximum.

  In this way, when the source / drain regions and the gate electrode are made close to each other by self-aligned pattern formation, the access resistance to the channel is reduced and the carrier resistance is reduced as compared with the case where they are formed so as to be separated from each other. Although the mobility can be improved, parasitic capacitance is formed. That is, it is difficult to achieve both improvement in carrier mobility and avoidance of formation of parasitic capacitance, and the operation speed of the transistor cannot be sufficiently increased.

  On the other hand, when the LDD structure described above is employed, the access resistance to the channel can be reduced by the presence of the LDD region while avoiding the overlap of the source / drain regions and the gate electrode. In other words, it is possible to improve both the carrier mobility and avoid the formation of parasitic capacitance, and to increase the operation speed of the transistor. However, since it is necessary to form a complicated structure such as an LDD structure, the manufacturing cost is increased.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a thin film transistor capable of easily improving the operation speed of the transistor, and a display device and an electronic apparatus using such a thin film transistor. It is in.

  The thin film transistor of the present invention includes an oxide semiconductor layer including a gate electrode, a carrier traveling layer constituting a channel, and a carrier supply layer for supplying carriers to the carrier traveling layer, a gate electrode and an oxide A gate insulating film provided between the oxide semiconductor layer and a pair of electrodes serving as a source / drain, and the source / drain region and the gate electrode formation region of the oxide semiconductor layer are separated from each other Is. Here, the conduction band bottom level or the valence band top level of the semiconductor layer in the carrier supply layer is more energetically than the conduction band bottom level or the valence band top level of the semiconductor layer in the carrier traveling layer. It is preferable to make it high.

  A display device of the present invention includes a display element and the thin film transistor of the present invention for driving the display element.

  An electronic apparatus according to the present invention includes the display device according to the present invention.

  In the thin film transistor, the display device, and the electronic device of the present invention, in the oxide semiconductor layer, carriers are supplied from the carrier supply layer to the carrier travel layer, and the carrier travels in a region near the interface with the carrier supply layer in the carrier travel layer. Is accumulated. Therefore, when the carrier traveling layer functions as a channel, the carrier travels almost two-dimensionally in this region. Therefore, the carrier travels three-dimensionally in the channel (oxide semiconductor layer). In comparison, traveling scattering with respect to the carrier is suppressed. In addition, since the carrier is supplied from the carrier supply layer, the carrier concentration in the carrier traveling layer itself can be kept low. From this viewpoint, the oxide semiconductor layer is a single layer as compared with the conventional layer. In addition, traveling scattering with respect to carriers by ionized donors and ionized acceptors can be suppressed. Furthermore, the access resistance to the channel is reduced without forming a complicated structure (for example, an LDD structure) as in the prior art. In addition, the source / drain region and the gate electrode formation region in the oxide semiconductor layer are separated from each other (not overlapped or not overlapped), so that the source / drain region and the gate in the oxide semiconductor layer are separated. The formation of parasitic capacitance composed of an insulating film and a gate electrode is avoided.

  According to the thin film transistor, the display device, and the electronic device of the present invention, the oxide semiconductor layer is configured by the multilayer film including the carrier traveling layer and the carrier supply layer that configure the channel. Without forming a structure, it is possible to suppress carrier scattering and carrier access resistance to a channel and improve carrier mobility. In addition, since the source / drain region and the gate electrode formation region in the oxide semiconductor layer are separated from each other, the formation of parasitic capacitance is avoided while reducing the access resistance to the channel as described above. be able to. Therefore, in spite of a simple structure, both improvement of carrier mobility and avoidance of formation of parasitic capacitance can be achieved, and the operation speed of the transistor can be easily improved.

It is sectional drawing showing the structure of the thin-film transistor which concerns on the 1st Embodiment of this invention. It is a figure showing the example of the energy band structure in the thin-film transistor shown in FIG. FIG. 2 is a cross-sectional view illustrating a method of manufacturing the thin film transistor illustrated in FIG. 1 in order of steps. It is a figure showing the cross-sectional structure of the thin-film transistor concerning the comparative example 1, and the example of an energy band structure. 6 is a cross-sectional view illustrating a configuration of a thin film transistor according to Comparative Example 2 and Comparative Example 3. FIG. It is a characteristic view showing the relationship between the gate-source voltage and drain current in the Example which concerns on 1st Embodiment, and the comparative example 1. FIG. 10 is a cross-sectional view illustrating a configuration of a thin film transistor according to Modification 1. FIG. It is a figure showing the cross-sectional structure of the thin film transistor which concerns on the modification 2, and the example of an energy band structure. It is sectional drawing showing the structure of the thin-film transistor which concerns on 2nd Embodiment. FIG. 10 is a cross-sectional view illustrating a method of manufacturing the thin film transistor illustrated in FIG. 9 in order of steps. It is sectional drawing showing the structure of the thin-film transistor which concerns on 3rd Embodiment. FIG. 12 is a cross-sectional view illustrating a method of manufacturing the thin film transistor illustrated in FIG. 11 in order of steps. FIG. 13 is a cross-sectional diagram illustrating a process following the process in FIG. 12. It is sectional drawing showing the structure of the thin-film transistor which concerns on 4th Embodiment. 10 is a cross-sectional view illustrating a configuration of a thin film transistor according to Modification 3. FIG. It is sectional drawing showing the structure of the thin-film transistor which concerns on 5th Embodiment. It is a figure showing the energy band structural example in the thin-film transistor which concerns on the modification 4 and the modification 5. It is a block diagram showing the structural example of the display apparatus provided with the thin-film transistor which concerns on each embodiment and each modification. FIG. 19 is a circuit diagram illustrating a detailed configuration example of a pixel illustrated in FIG. 18. FIG. 20 is a cross-sectional view illustrating a configuration example of the display device illustrated in FIGS. 18 and 19. FIG. 20 is a cross-sectional view illustrating another configuration example of the display device illustrated in FIGS. 18 and 19. FIG. 20 is a cross-sectional view illustrating another configuration example of the display device illustrated in FIGS. 18 and 19. FIG. 20 is a plan view illustrating a schematic configuration of a module including the display device illustrated in FIGS. 18 and 19. FIG. 20 is a perspective view illustrating an appearance of application example 1 of the display device illustrated in FIGS. 18 and 19. (A) is a perspective view showing the external appearance seen from the front side of the application example 2, (B) is a perspective view showing the external appearance seen from the back side. 12 is a perspective view illustrating an appearance of application example 3. FIG. 14 is a perspective view illustrating an appearance of application example 4. FIG. (A) is a front view of the application example 5 in an open state, (B) is a side view thereof, (C) is a front view in a closed state, (D) is a left side view, and (E) is a right side view, (F) is a top view and (G) is a bottom view.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The description will be given in the following order.

1. First Embodiment (Top Gate Type Example 1 Including Carrier Supply Layer and Carrier Traveling Layer)
2. Modified example of the first embodiment Modified example 1 (example in which the source / drain region is a low resistance layer)
Modification 2 (example in which the stacking order of the carrier supply layer and carrier running layer is reversed)
3. Second embodiment (top gate type example 2: example in which a carrier traveling layer is selectively provided in a gate electrode formation region)
4). Third embodiment (example in which a low resistance layer is further provided)
5. Fourth Embodiment (Bottom Gate Type Example 1 Including Carrier Supply Layer and Carrier Travel Layer)
6). Modification Example of Fourth Embodiment Modification Example 3 (Bottom Gate Type Example 2: Example Using Channel Protection Film as Interlayer Insulation Film)
7). Fifth embodiment (example of dual gate type including carrier supply layer and carrier traveling layer)
8). Modifications common to each embodiment and modification Modifications 4 and 5 (examples using holes as carriers)
9. Application examples (application examples for display devices and electronic devices)
10. Other variations

<First Embodiment>
[Cross-sectional structure of thin film transistor 1]
FIG. 1 shows a cross-sectional configuration of a thin film transistor (thin film transistor 1) according to a first embodiment of the present invention. The thin film transistor 1 includes an oxide semiconductor layer 12, a gate insulating film 131, and a gate electrode 141 in this order on a substrate 11. That is, the thin film transistor 1 is a so-called top gate type (staggered structure) thin film transistor. The thin film transistor 1 also includes an interlayer insulating film 15 and a pair of source / drain electrodes 16A and 16B (a pair of electrodes). The thin film transistor 1 uses electrons as carriers, as will be described later.

  The substrate 11 is, for example, a silicon substrate, but may be made of a material such as synthetic quartz, glass, metal, resin, or resin film. An insulating layer (not shown) made of an insulating film material containing, for example, silicon (Si) is provided as a base layer between the substrate 11 and the oxide semiconductor 12 and the interlayer insulating film 15. May be. This prevents impurities such as metal elements from diffusing from the substrate 11 toward the oxide semiconductor layer 12.

(Oxide semiconductor layer 12)
The oxide semiconductor layer 12 includes, for example, MO (M is at least one of Al, Ga, In, Zn, Sn, and Ti) as a main component.

The oxide semiconductor layer 12 is composed of a multilayer film (two-layer structure) in which a carrier traveling layer 121 and a carrier supply layer 122 are stacked in order from the substrate 11 side (modulation dope structure). In other words, the oxide semiconductor layer 12 is configured using a single hetero (SH) structure including one carrier supply layer 122 and one carrier travel layer 121. Note that at least one of these multilayer films is preferably composed of an amorphous semiconductor or a polycrystalline semiconductor. For example, when amorphous InGaZnO ₄ is used, the carrier mobility is as high as about 10 cm ² / V · s regardless of the amorphous phase.

The carrier supply layer 122 is an oxide semiconductor layer that plays a role of supplying carriers (electrons here) to the carrier traveling layer 121 described below, and has a thickness of about 10 to 100 nm. Examples of the oxide semiconductor that constitutes the carrier supply layer 122 include Al _x Ga _y In _z O _{1.5x +1.5} y _{+ 1.5z} (x, y, z: integer), Ga _x In _y Zn _z O _{1.5. x + 1.5y + z} (x, y, z: integer). Note that the oxygen partial pressure during film formation is adjusted so that the carrier concentration of the oxide semiconductor in the carrier supply layer 122 is, for example, about 10 ¹⁸ to 10 ²⁰ cm ⁻³ .

The carrier traveling layer 121 is an oxide semiconductor layer for carriers (electrons) supplied from the carrier supply layer 122 to travel between the source / drain electrodes 16A and 16B. That is, in this carrier travel layer 121, although the details will be described later, a channel in the thin film transistor 1 is formed (configures a channel) in a region near the interface with the carrier supply layer 122. It is about 10 to 100 nm. Examples of the oxide semiconductor constituting the carrier travel layer 121 include Al _x Ga _y In _z O _{1.5x +1.5} y _{+ 1.5z} (x, y, z: integer), In ₂ O ₃ , Ga _x In _{y. Zn z O 1.5x + 1.5y + z} (x, y, z: an integer), and the like. Note that the oxygen partial pressure at the time of film formation is such that the carrier concentration of the oxide semiconductor in the carrier transit layer 121 is sufficiently low, for example, about 10 ¹⁴ to 10 ¹⁵ cm ⁻³ (concentration region in which an intrinsic semiconductor is formed). It has come to be adjusted.

  Here, in the oxide semiconductor layer 12 of this embodiment, both the carrier travel layer 121 and the carrier supply layer 122 have a pair of source / drain regions 12SD corresponding to the formation regions of the source / drain electrodes 16A and 16B. ing. In other words, in the oxide semiconductor layer 12, both the carrier travel layer 121 and the carrier supply layer 122 are formed from the formation region of the gate electrode 141 to each source / drain region 12SD. Although the details will be described later in these source / drain regions 12SD, the sheet resistance is lower than that of a conventional single-layer oxide semiconductor layer (oxide semiconductor layers 102, 202, 302, etc. of Comparative Examples 1 to 3 described later). Has been reduced. Further, it is desirable that the sheet resistance in the source / drain region 12SD is smaller than the sheet resistance in the channel region. For example, if the sheet resistance in the source / drain region 12SD is about 10 (kΩ / □) or less, the source / drain region 12SD can be used as (a part of) the source / drain electrode.

  In the oxide semiconductor layer 12 of this embodiment, as shown in FIG. 1, the source / drain region 12SD and the formation region of the gate electrode 141 are separated from each other (not overlapped or overlapped). No, not superimposed). Thereby, although the details will be described later, formation of a predetermined parasitic capacitance is avoided.

Next, the energy band structure of the oxide semiconductor layer 12 will be described with reference to FIG. FIG. 2 illustrates an energy band structure example in a layer structure near the oxide semiconductor layer 12 (the oxide semiconductor layer 12, the gate insulating film 131, and the gate electrode 141). In this figure, “E _F ” indicates Fermi energy. “Ev0”, “Ev1”, and “Ev2” indicate the valence band upper end levels in the gate insulating film 131, the carrier traveling layer 121, and the carrier supply layer 122, respectively. “Ec0”, “Ec1”, and “Ec2” indicate the conduction band bottom levels in the gate insulating film 131, the carrier traveling layer 121, and the carrier supply layer 122, respectively. “E” schematically represents electrons as carriers. These symbols are the same in other energy band structures appearing thereafter.

  In the oxide semiconductor layer 12, the conduction band lower level Ec2 of the semiconductor layer in the carrier supply layer 122 is set to be higher in energy than the conduction band lower level Ec1 of the semiconductor layer in the carrier traveling layer 121. (Ec2> Ec1). As a result, although details will be described later, electrons e are supplied from the carrier supply layer 122 to the carrier travel layer 121, and as shown in FIG. 2, the vicinity of the interface with the carrier supply layer 122 in the carrier travel layer 121 is provided. Electrons e are accumulated in the area. Here, the valence band upper level Ev2 in the carrier supply layer 122 is energetically lower than the valence band upper level Ev1 in the carrier traveling layer 121 (Ev2 <Ev1). The energy band structure on the side may be any structure.

  The gate insulating film 131 is made of an insulating film material containing silicon, for example. The gate insulating film 131 is provided in a region (formation region) facing the gate electrode 13 on the carrier supply layer 122.

  The gate electrode 141 is an electrode for controlling the carrier density (here, electron density) of the channel portion in the oxide semiconductor layer 12 by the gate voltage applied to the thin film transistor 1. The gate electrode 141 has, for example, a two-layer structure of a molybdenum (Mo) layer having a thickness of about 50 nm and an aluminum (Al) layer or an aluminum alloy layer having a thickness of about 400 nm. In addition, as an aluminum alloy layer, an aluminum-neodymium alloy layer is mentioned, for example.

  The interlayer insulating film 15 is made of an insulating film material containing silicon, for example. The interlayer insulating film 15 is an insulating film for separating (insulating) the gate electrode 141 and the source / drain electrodes 16A and 16B from each other.

  The source / drain electrodes 16A and 16B are each made of a metal such as molybdenum, aluminum, or titanium, or a multilayer film thereof.

[Method of Manufacturing Thin Film Transistor 1]
The thin film transistor 1 can be manufactured, for example, as follows. FIG. 3 is a cross-sectional view showing an example of a process for manufacturing the thin film transistor 1.

First, as shown in FIG. 3A, for example, a sputtering method (for example, using an oxide semiconductor target made of the above-described material, for example, over the entire surface of the substrate 11 having an insulating surface in a vacuum) The oxide semiconductor layer 12 is formed by a DC / RF sputtering method) or a pulsed laser deposition method. At this time, the carrier traveling layer 121 and the carrier supply layer 122 are formed by, for example, switching the target in a single sputtering apparatus and adjusting the oxygen partial pressure during film formation. Note that in the case where the above-described insulating layer as the base layer is provided between the substrate 11 and the oxide semiconductor 12, for example, a CVD (Chemical Vapor Deposition) method is used to have a thickness of about 300 nm. An SiO _x (silicon oxide) layer may be formed.

After that, as shown in FIG. 3A, a gate insulating film 131 and a gate electrode 141 are formed in this order on the oxide semiconductor layer 12 to form a pattern. Specifically, the gate insulating film 131 is formed by, for example, plasma CVD, and the gate electrode 141 is formed by, for example, sputtering. Then, it is patterned into a desired shape by photolithography and dry etching. As the gate insulating film 131, for example, a silicon oxide with a thickness of about 200 nm can be used, and as the gate electrode 141, an aluminum film with a thickness of about 300 nm and a titanium film with a thickness of about 30 nm are sequentially stacked. Things can be used. At this time, the gate insulating film 131 can be formed, for example, by collective dry etching that is continuous with the etching of the gate electrode 141. At this time, it is desirable to control the overetching time so that the carrier concentration (sheet carrier density) of the carrier running layer 121 and the carrier supply layer 122 is about 10 ¹³ cm ⁻² or more.

  Next, as shown in FIG. 3B, after patterning the resist (photosensitive resin film) by photolithography, the oxide semiconductor layer 12 is selected by performing dry etching using, for example, chlorine gas. (The isolation of the oxide semiconductor layer 12 for each transistor is performed).

Next, as shown in FIG. 3C, an interlayer insulating film 15 is formed and patterned. Specifically, a silicon oxide film having a thickness of about 400 nm is formed by using, for example, a plasma CVD method, and then patterned into a desired shape by photolithography and etching. At this time, it is desirable to control the carrier concentration (sheet carrier density) of the carrier running layer 121 and the carrier supply layer 122 to be about 10 ¹³ cm ⁻² or more. Further, when dry etching is used for etching the interlayer insulating film 15, the resistance of the oxide semiconductor layer 12 exposed at the time of overetching can be reduced to a carrier concentration (sheet carrier density) of about 10 ¹⁴ cm ^−2. it can.

  Subsequently, after forming a film using, for example, a sputtering method, the source / drain electrodes 16A and 16B are formed by performing wet etching using a mixed acid composed of phosphoric acid, nitric acid and acetic acid, for example. At this time, as the source / drain electrodes 16A and 16B, one in which molybdenum (Mo) having a thickness of about 30 nm, aluminum (Al) having a thickness of about 300 nm, and molybdenum having a thickness of about 30 nm are sequentially stacked. Can do. Thus, the top gate type thin film transistor 1 shown in FIG. 1 is completed.

[Operation / Effect of Thin Film Transistor 1]
In the thin film transistor 1, when a voltage (gate-source voltage V _GS ) equal to or higher than a predetermined threshold voltage Vth is applied to the gate electrode 141 through a wiring (not shown), a channel is formed in the oxide semiconductor layer 12. . As a result, a current (drain current _ID ) flows between the source / drain electrodes 16A and 16B, and functions as a transistor.

  Here, with reference to FIGS. 4-6, the effect | action and effect of the characteristic part of the thin-film transistor 1 of this Embodiment are demonstrated in detail, comparing with a comparative example (comparative examples 1-3).

(Comparative Example 1)
4A illustrates a cross-sectional configuration of a conventional thin film transistor (thin film transistor 101) according to Comparative Example 1. FIG. 4B illustrates an energy band structure example in the layer structure (the oxide semiconductor layer 102, the gate insulating film 131, and the gate electrode 141) in the vicinity of the oxide semiconductor layer 102 in the thin film transistor 101 according to the comparative example 1. It is a representation. Note that in FIG. 4B, “Ev102” and “Ec102” indicate the valence band upper level and the conduction band lower level in the oxide semiconductor layer 102, respectively.

  In the thin film transistor 101 of Comparative Example 1, as illustrated in FIG. 4A, unlike the oxide semiconductor layer 12 in the thin film transistor 1 of this embodiment, the oxide semiconductor layer 102 includes a single layer. That is, the entire oxide semiconductor layer 102 of Comparative Example 1 is a channel layer, and carriers are supplied from donors in the channel layer.

  Therefore, in the thin film transistor 101, as illustrated in FIG. 4B, carriers (electrons here) travel three-dimensionally in the channel layer (oxide semiconductor layer 102). That is, carriers travel along the thickness direction of the oxide semiconductor layer 102 in addition to the two-dimensional direction between the source / drain electrodes 16A and 16B. For this reason, traveling scattering with respect to carriers increases, and as a result, the mobility of carriers in the thin film transistor 101 of Comparative Example 1 decreases.

  In the thin film transistor 101, as illustrated in FIG. 4A, the pair of source / drain regions 102SD and the formation region of the gate electrode 141 in the oxide semiconductor layer 102 are separated from each other. Therefore, the access resistance to the channel when traveling between the source / drain electrodes 16A and 16B is increased, and also from this point of view, the mobility of carriers in the thin film transistor 101 of Comparative Example 1 is decreased.

(Comparative Example 2)
On the other hand, in the conventional thin film transistor (thin film transistor 201) according to the comparative example 2 shown in FIG. 5A, the source / drain regions 202SD and the gate electrode 141 in the oxide semiconductor layer 202 are formed by, for example, self-aligned pattern formation. The area is close to each other. As a result, the access resistance to the channel can be reduced as compared with the first comparative example in which these regions are formed so as to be separated from each other.

  However, in the thin film transistor 201 of Comparative Example 2, as shown in FIG. 5A, the source / drain region 202SD and the formation region of the gate electrode 141 are actually overlapped (overlapped). Therefore, in this overlapping region (overlap region), parasitic capacitance including the oxide semiconductor layer 202, the gate insulating film 131, and the gate electrode 141 is generated (formed). Specifically, when the resistance of the source / drain region 202SD is reduced by performing plasma irradiation using, for example, hydrogen gas or argon gas, the low resistance region is a region or gate electrode that serves as a low resistance mask. A part of this also wraps around the lower part of the substrate, and such an overlapping region (parasitic capacitance) is formed. Therefore, in Comparative Example 2, it is difficult to achieve both improvement in carrier mobility and avoidance of formation of parasitic capacitance, and the operation speed of the transistor cannot be sufficiently increased as in Comparative Example 1. Although not shown in the figure, when the back surface exposure using the gate electrode in the bottom gate type thin film transistor as a mask, the source / drain electrode or the channel protective film is formed in a self-aligned manner. Due to the diffraction phenomenon, an overlapping region (parasitic capacitance) between the gate electrode and the source / drain electrode is formed.

(Comparative Example 3)
On the other hand, in the conventional thin film transistor (thin film transistor 301) according to Comparative Example 3 shown in FIG. 5B, the pair of source / drain regions 302SD and the gate electrode 141 in the oxide semiconductor layer 302 are formed as in Comparative Example 1. The formation regions are separated from each other. However, in Comparative Example 3, the LDD regions 302 are provided between the pair of source / drain regions 302SD and the formation region of the gate electrode 141, respectively. As described above, since the thin film transistor 301 of the comparative example 3 has a so-called LDD structure, the channel is accessed due to the presence of the LDD region 302SD while avoiding the overlap between the source / drain region 302SD and the formation region of the gate electrode 141. Resistance can be reduced. That is, it seems that it is possible to improve the carrier mobility and avoid the formation of parasitic capacitance, and to increase the operation speed of the transistor.

  However, in the thin film transistor 301 of the comparative example 3, since it is necessary to form a complicated structure such as an LDD structure, the manufacturing cost is increased.

  As described above, in Comparative Examples 1 to 3, it is difficult to achieve both improvement in carrier mobility by reducing the access resistance to the channel and avoidance of formation of parasitic capacitance with a simple structure. That is, it is difficult to easily improve the operation speed of the transistor.

(This embodiment)
On the other hand, in the thin film transistor 1 of this embodiment, as illustrated in FIG. 1, the oxide semiconductor layer 12 includes a multilayer film (two-layer structure) including a carrier supply layer 122 and a carrier travel layer 121. ing. For example, as illustrated in FIG. 2, in the oxide semiconductor layer 12, the conduction band lower level Ec <b> 2 of the semiconductor layer in the carrier supply layer 122 is lower than the conduction band lower level Ec <b> 1 of the semiconductor layer in the carrier traveling layer 121. Is also high in terms of energy (Ec2> Ec1). Thereby, in the oxide semiconductor layer 12, electrons e are supplied from the carrier supply layer 122 to the carrier travel layer 121, and as shown in FIG. 2, the vicinity of the interface with the carrier supply layer 122 in the carrier travel layer 121 is provided. Electrons e are accumulated in the region. In other words, in the oxide semiconductor layer 12, a region for supplying the electrons e (carrier supply layer 122) and a region where the electrons e actually travel (region in the vicinity of the interface with the carrier supply layer 122 in the carrier traveling layer 121). Are spatially separated along the thickness direction.

  Therefore, in the thin film transistor 1 of the present embodiment, when the carrier traveling layer 121 functions as a channel, the electrons e travel almost two-dimensionally in the region near the interface. That is, unlike the comparative example 1, the electron e travels substantially along the two-dimensional direction along the source / drain electrodes 16A and 16B (along the thickness direction of the oxide semiconductor layer 12). E hardly travels e). Therefore, in the thin film transistor 1, traveling scattering with respect to the electrons e is suppressed as compared with Comparative Examples 1 to 3 in which carriers travel three-dimensionally in the channel layer (oxide semiconductor layers 102, 202, and 302).

  Further, in the thin film transistor 1 of the present embodiment, since the electrons e are supplied from the carrier supply layer 122 as described above, the carrier concentration of the carrier traveling layer 121 itself can be suppressed to a low level (for example, substantially an intrinsic semiconductor layer). Concentration region). Therefore, since the donor concentration in the region where the carriers actually travel can be set to be extremely low, the oxide semiconductor layers 102, 202, and 302 are a single layer in the thin film transistor 1 also from this viewpoint. Compared with Comparative Examples 1 to 3, traveling scattering on the electrons e by the ionized donor is suppressed.

Here, FIG. 6 shows the gate-source voltage V _GS and the drain current I _{D in the} example according to the present embodiment (here, an example using a bottom-gate thin film transistor) and the comparative example 1 described above. This represents the relationship. In the oxide semiconductor layer 12 in the example, GaInZnO ₄ was used as the carrier traveling layer 121, and n-ITO (Indium Tin Oxide) was used as the carrier supply layer 122. As the oxide semiconductor layer 102 in Comparative Example 1, a single layer structure of GaInZnO ₄ was used. Note that in both Example and Comparative Example 1, an n-type Si substrate having a base layer (silicon oxide film) formed by a thermal oxidation method was used, and the mobility μ of carriers (electrons) is shown in FIG. I _D -V _GS curve.

From FIG. 6, it can be seen that the example shows higher electron mobility than the comparative example 1. Specifically, in Comparative Example 1, μ = 8 (cm ² / V · s), whereas in the example, μ = 20 (cm ² / V · s). . From this, as described above, in the present embodiment (example), it was confirmed that the mobility of electrons was improved as a result of suppressing traveling scattering with respect to electrons as compared with Comparative Example 1.

  Furthermore, in the thin film transistor 1 of this embodiment, as illustrated in FIG. 1, the pair of source / drain regions 12SD in the oxide semiconductor layer 12 and the formation region of the gate electrode 141 are separated from each other. Thus, unlike the comparative example 2, the formation of parasitic capacitance composed of the oxide semiconductor layer 12 (source / drain region 12SD), the gate insulating film 131, and the gate electrode 141 is avoided.

  In addition, in the thin film transistor 1, the access resistance to the channel is reduced in the oxide semiconductor layer 12 including the carrier traveling layer 121 and the carrier supply layer 122 as described above. A structure (LDD structure) is not required, and a simple structure is sufficient.

  As described above, in this embodiment, since the oxide semiconductor layer 12 is formed of a multilayer film including the carrier traveling layer 121 and the carrier supply layer 122 that form the channel, the oxide semiconductor layer 12 has a complicated structure as in the past. The mobility of carriers can be improved by suppressing the traveling scattering for carriers and the access resistance for channels. In addition, since the source / drain region 12SD and the formation region of the gate electrode 141 in the oxide semiconductor layer 12 are separated from each other, formation of parasitic capacitance is achieved while reducing the access resistance to the channel as described above. Can be avoided. Therefore, in spite of a simple structure, it is possible to achieve both improvement in carrier (electron) mobility and avoidance of formation of parasitic capacitance, and the operation speed of the transistor can be easily improved.

  In addition, since the carrier concentration of the oxide semiconductor layer 12 as a whole can be controlled by the position and thickness of the carrier supply layer 122, the concentration of donors or acceptors, and the like, unlike the conventional single-layer channel structure, precise Oxygen partial pressure control becomes unnecessary. Therefore, it is possible to suppress variation in transistor characteristics (in-plane variation on the substrate surface and variation for each manufacturing lot) as compared with the conventional case, and it is possible to improve the yield in manufacturing.

  Furthermore, when forming the oxide semiconductor layer 12 having such a multilayer film structure, for example, it is only necessary to switch the target (adjust the oxygen partial pressure during film formation) in a single sputtering apparatus. The influence on the manufacturing process of the conventional single layer structure is small, and an increase in manufacturing cost can be minimized.

<Modification of the first embodiment>
Subsequently, modified examples (modified examples 1 and 2) of the first embodiment will be described. In addition, the same code | symbol is attached | subjected to the same thing as the component in 1st Embodiment, and description is abbreviate | omitted suitably.

[Modification 1]
FIG. 7 illustrates a cross-sectional configuration of a thin film transistor (thin film transistor 1A) according to the first modification. The thin film transistor 1A of the present modification includes the oxide semiconductor layer 12A instead of the oxide semiconductor layer 12 in the thin film transistor 1 of the first embodiment, and other configurations are the same.

  The oxide semiconductor layer 12A includes a low resistance layer 120 in addition to the carrier traveling layer 121 and the carrier supply layer 122 described so far. The low resistance layer 120 is formed by reducing the resistance of the pair of source / drain regions 12SD in the carrier traveling layer 121 and the carrier supply layer 122. That is, the source / drain region 12SD in the oxide semiconductor layer 12A is the low resistance layer 120. Such a resistance reduction process can be realized by, for example, plasma irradiation using hydrogen gas or argon gas in a plasma CVD apparatus.

  With this configuration, in this modification, the resistivity (access resistance) of the source / drain region 12SD can be further reduced without increasing the mask.

[Modification 2]
FIG. 8A illustrates a cross-sectional configuration of a thin film transistor (thin film transistor 1B) according to the second modification. 8B illustrates an energy band structure example in the layer structure (the oxide semiconductor layer 12B, the gate insulating film 131, and the gate electrode 141) in the vicinity of the oxide semiconductor layer 12B in the thin film transistor 1B according to the second modification. It is a representation.

  A thin film transistor 1B according to the present modification includes the oxide semiconductor layer 12B instead of the oxide semiconductor layer 12 in the thin film transistor 1 according to the first embodiment, and other configurations are the same.

  Specifically, as illustrated in FIG. 8A, in the oxide semiconductor layer 12 </ b> B, the stacking order of the carrier traveling layer 121 and the carrier supply layer 122 is reversed as compared with the oxide semiconductor layer 12. . That is, the oxide semiconductor layer 12B of the present modification is configured by a multilayer film (two-layer structure) in which the carrier supply layer 122 and the carrier traveling layer 121 are stacked in this order from the substrate 11 side. In other words, like the oxide semiconductor layer 12, the oxide semiconductor layer 12B is also configured using a single heterostructure having one carrier supply layer 122 and one carrier travel layer 121.

  Further, as shown in FIG. 8B, in the thin film transistor 1B as well, like the thin film transistor 1, the conduction band lower end level Ec2 of the semiconductor layer in the carrier supply layer 122 is the conduction band of the semiconductor layer in the carrier traveling layer 151. It is set to be higher in energy than the lower end level Ec1 (Ec2> Ec1). In this case as well, the energy band structure on the valence band side may be any structure.

  With this configuration, also in this modification, the same effect can be obtained by the same operation as that of the first embodiment. In the present modification, as in the first modification, the low resistance layer 120 may be provided in the source / drain region 12SD of the oxide semiconductor layer 12B.

<Second Embodiment>
Next, a second embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same component as the said 1st Embodiment, and description is abbreviate | omitted suitably.

  FIG. 9 illustrates a cross-sectional configuration of a thin film transistor (thin film transistor 1C) according to the second embodiment. The thin film transistor 1C of the present embodiment includes the oxide semiconductor layer 12C instead of the oxide semiconductor layer 12 in the thin film transistor 1 of the first embodiment, and other configurations are the same. .

  The oxide semiconductor layer 12C is configured by a multilayer film (a two-layer structure) in which a carrier supply layer 122 and a carrier travel layer 121 are sequentially stacked from the substrate 11 side, similarly to the oxide semiconductor layer 12B of Modification 2 described above. Yes. However, in the oxide semiconductor layer 12C, unlike the oxide semiconductor layers 12, 12A, and 12B described so far, the carrier traveling layer 121 is provided only in the region where the gate electrode 141 is formed. Specifically, the carrier supply layer 122 is formed from the region where the gate electrode 141 is formed to the pair of source / drain regions 12SD, while the carrier traveling layer 121 is selectively formed in the region where the gate electrode 141 is formed. ing.

  The thin film transistor 1C can be manufactured, for example, as follows. FIG. 10 is a cross-sectional view showing an example of a process for manufacturing the thin film transistor 1C.

  First, as shown in FIG. 10A, the oxide semiconductor layer 12 (carrier supply layer 122, carrier traveling layer 121) is formed on the entire surface of the substrate 11 by the same method as in the first embodiment. A gate insulating film 131 and a film to be the gate electrode 141 are formed in this order.

  Next, as illustrated in FIG. 10B, the carrier traveling layer 121, the gate insulating film 131, and the gate electrode 141 are patterned, for example, in a batch so as to have the same shape. Subsequently, as shown in FIG. 10C, the carrier supply layer 122 is patterned into a desired shape.

  Next, as shown in FIG. 10D, an interlayer insulating film 15 is formed and patterned in the same manner as in the first embodiment, and then source / drain electrodes 16A and 16B are formed. Thus, the top gate type thin film transistor 1C shown in FIG. 9 is completed.

  Also in this embodiment having such a configuration, the same effect can be obtained by the same operation as in the first embodiment. That is, in spite of a simple structure, it is possible to achieve both improvement of carrier mobility and avoidance of formation of parasitic capacitance, and the operation speed of the transistor can be easily improved.

  In the present embodiment, the low resistance layer 120 may be provided in the source / drain region 12SD of the oxide semiconductor layer 12C as in the first modification.

<Third Embodiment>
Subsequently, a third embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same component as the said 1st Embodiment, and description is abbreviate | omitted suitably.

  FIG. 11 illustrates a cross-sectional configuration of a thin film transistor (thin film transistor 1D) according to the third embodiment. The thin film transistor 1D of the present embodiment further includes a low resistance layer 17 described below in the thin film transistor 1 of the first embodiment, and the other configurations are the same.

  The low resistance layer 17 is provided between at least the source / drain region 12SD in the oxide semiconductor layer 12 and the source / drain electrodes 16A and 16B. Specifically, here, the oxide semiconductor layer 12 is provided in a region including the pair of source / drain regions 12SD (a region excluding the formation region of the gate electrode 141). The low resistance layer 17 is made of a material (for example, an oxide semiconductor or a conductor such as a metal) having a lower resistivity than the carrier traveling layer 121 and the carrier supply layer 122.

  The thin film transistor 1D can be manufactured as follows, for example. 12 and 13 are sectional views showing an example of a process for manufacturing the thin film transistor 1D.

  First, as illustrated in FIG. 12A, the oxide semiconductor layer 12 (the carrier traveling layer 121 and the carrier supply layer 122) and the film that becomes the low resistance layer 17 are collectively put on the substrate 11 in this order. Patterning.

  Next, as shown in FIG. 12B, the photoresist film 10 is formed by patterning in a region excluding the region where the gate insulating film 131 and the gate electrode 141 are formed. Subsequently, as shown in FIG. 12C, the low resistance layer 17 is formed by patterning using the photoresist film 10.

  Next, as shown in FIG. 13A, the film to be the gate insulating film 131 and the gate electrode 141 is formed in this order on the entire surface of the photoresist film 10 with the photoresist film 10 remaining. Form a film.

  Next, as shown in FIG. 13B, the gate insulating film 131 and the gate electrode 141 are each patterned and formed into a desired shape by using, for example, a lift-off method.

  Next, as shown in FIG. 13C, an interlayer insulating film 15 is formed and patterned in the same manner as in the first embodiment, and then source / drain electrodes 16A and 16B are formed. Thus, the top gate type thin film transistor 1D shown in FIG. 11 is completed.

  Also in this embodiment having such a configuration, the same effect can be obtained by the same operation as in the first embodiment. That is, in spite of a simple structure, it is possible to achieve both improvement of carrier mobility and avoidance of formation of parasitic capacitance, and the operation speed of the transistor can be easily improved.

  In the present embodiment, since the low resistance layer 17 is provided, the resistivity of the source / drain region 12SD can be further reduced.

  Also in this embodiment, as in the first and second modifications, the low resistance layer 120 is provided in the source / drain region 12SD of the oxide semiconductor layer 12, or the carrier traveling layer 121 and the carrier supply layer are provided. The stacking order of 122 may be reversed.

<Fourth embodiment>
Subsequently, a fourth embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same component as the said 1st Embodiment, and description is abbreviate | omitted suitably.

  FIG. 14 illustrates a cross-sectional configuration of a thin film transistor (thin film transistor 1E) according to the fourth embodiment. The thin film transistor 1E of the present embodiment includes a gate electrode 142, a gate insulating film 132, an oxide semiconductor layer 12, and a channel protective film 18 in this order on a substrate 11, and an interlayer insulating film 15 and source / drain electrodes 16A, 16B is provided. That is, the thin film transistor 1E of the present embodiment is a so-called bottom gate type (reverse staggered structure) thin film transistor, unlike the top gate type (staggered structure) thin film transistor described so far.

  The gate electrode 142 and the gate insulating film 132 are made of the same material as that of the gate electrode 141 and the gate insulating film 131, respectively.

  The channel protective film 18 is for protecting the channel region in the oxide semiconductor layer 12 and is made of, for example, an insulating film material containing silicon.

  The thin film transistor 1E can be manufactured, for example, as follows. That is, first, after the gate electrode 142 is patterned on the substrate 11, the gate insulating film 132 is formed on the entire surface of the gate electrode 142. Thereafter, in the same manner as in the first embodiment, the oxide semiconductor layer 12, the interlayer insulating film 15, and the source / drain electrodes 16A and 16B are formed, and the channel protective film 18 is formed by using, for example, a plasma CVD method. Form. Thus, the bottom gate type thin film transistor 1E shown in FIG. 14 is completed.

  Also in the present embodiment, the same effect can be obtained by the same operation as in the first embodiment. That is, in spite of a simple structure, it is possible to achieve both improvement of carrier mobility and avoidance of formation of parasitic capacitance, and the operation speed of the transistor can be easily improved.

  Also in this embodiment, as in the first and second modifications, the low resistance layer 120 is provided in the source / drain region 12SD of the oxide semiconductor layer 12, or the carrier traveling layer 121 and the carrier supply layer are provided. The stacking order of 122 may be reversed.

<Modification of Fourth Embodiment>
Subsequently, a modification (Modification 3) of the fourth embodiment will be described. In addition, the same code | symbol is attached | subjected to the same thing as the component in 4th Embodiment, and description is abbreviate | omitted suitably.

[Modification 3]
FIG. 15 illustrates a cross-sectional configuration of a thin film transistor (thin film transistor 1F) according to Modification 3. In the thin film transistor 1F of the present modification, the channel protective film 18 is also used as the interlayer insulating film 15 in the thin film transistor 1 of the fourth embodiment (when the channel protective film 18 is formed, the interlayer insulating film is also formed collectively. The other configurations are the same.

  The thin film transistor 1F can be manufactured, for example, as follows. That is, the channel protective film 18 is removed only in a portion (source / drain region 12SD) where the junction between the source / drain electrodes 16A and 16B and the oxide semiconductor layer 12 (carrier supply layer 122) is required, and in other regions. Sets the mask pattern so that the channel protective film 18 remains. Other than that, it is formed in the same manner as in the fourth embodiment. Thus, the bottom gate type thin film transistor 1F shown in FIG. 15 is completed.

  With this configuration, in this modification, the insulating property between the gate electrode 142 and the source / drain electrodes 16A and 16B can be reduced without forming an interlayer insulating film by using two insulating films (gate insulating film 132 and channel protection). It can be enhanced by the membrane 18).

  Also in this modification, as in Modifications 1 and 2, the low resistance layer 120 is provided in the source / drain region 12SD of the oxide semiconductor layer 12, or the carrier running layer 121 and the carrier supply layer 122 are provided. The stacking order may be reversed.

<Fifth embodiment>
Subsequently, a fifth embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same component as the said 1st and 4th embodiment, and description is abbreviate | omitted suitably.

  FIG. 16 illustrates a cross-sectional configuration of a thin film transistor (thin film transistor 1G) according to the fifth embodiment. A thin film transistor 1G in this embodiment includes a gate electrode 142 (second gate electrode), a gate insulating film 132 (second gate insulating film), an oxide semiconductor layer 12, and a gate insulating film 131 (first insulating film) over a substrate 11. 1 gate insulating film) and a gate electrode 141 (first gate electrode) in this order. The thin film transistor 1G also includes an interlayer insulating film 15 and source / drain electrodes 16A and 16B. That is, the thin film transistor 1G of the present embodiment is a so-called dual gate type thin film transistor, unlike the top gate type (staggered structure) and bottom gate type (reverse staggered structure) thin film transistors described so far.

  The thin film transistor 1G can be manufactured, for example, as follows. That is, first, similarly to the fourth embodiment, the gate electrode 142 is patterned on the substrate 11, and then the gate insulating film 132 is formed on the entire surface of the gate electrode 142. Thereafter, as in the first embodiment, the oxide semiconductor layer 12, the gate insulating film 131, the gate electrode 141, the interlayer insulating film 15, and the source / drain electrodes 16A and 16B are formed. Thus, the dual gate type thin film transistor 1G shown in FIG. 16 is completed.

  Also in the present embodiment, the same effect can be obtained by the same operation as in the first embodiment. That is, in spite of a simple structure, it is possible to achieve both improvement of carrier mobility and avoidance of formation of parasitic capacitance, and the operation speed of the transistor can be easily improved.

  In this embodiment mode, since the dual gate structure is employed, the threshold voltage of the transistor can be arbitrarily adjusted.

  Also in this embodiment, as in the first and second modifications, the low resistance layer 120 is provided in the source / drain region 12SD of the oxide semiconductor layer 12, or the carrier traveling layer 121 and the carrier supply layer are provided. The stacking order of 122 may be reversed.

<Modification common to each embodiment and each modification>
Next, modified examples (modified examples 4 and 5) common to the first to fifth embodiments and modified examples 1 to 3 described so far will be described. In addition, the same code | symbol is attached | subjected to the same thing as the component in these embodiment etc., and description is abbreviate | omitted suitably.

[Modifications 4 and 5]
FIG. 17A illustrates an energy band structure example in the layer structure (the oxide semiconductor layer 12H, the gate insulating film 131, and the gate electrode 141) in the vicinity of the oxide semiconductor layer 12H in the thin film transistor (thin film transistor 1H) according to the fourth modification. It is a representation. FIG. 17B illustrates an energy band structure in a layer structure (the oxide semiconductor layer 12I, the gate insulating film 131, and the gate electrode 141) in the vicinity of the oxide semiconductor layer 12I in the thin film transistor (thin film transistor 1I) according to the fifth modification. An example is shown.

  The thin film transistors 1H and 1I according to these modifications 4 and 5 are different from the thin film transistors described so far, and use holes as carriers. Specifically, the thin film transistors 1H and 1I correspond to those in which oxide semiconductor layers 12H and 12I using holes as carriers are provided instead of the oxide semiconductor layers 12 and the like using electrons as carriers. Other configurations are the same as those in the above embodiment.

  Specifically, the oxide semiconductor layer 12H according to Modification 4 illustrated in FIG. 17A includes a multilayer film (a two-layer structure) in which a carrier travel layer 123 and a carrier supply layer 124 are stacked in this order from the substrate 11 side. ). On the other hand, the oxide semiconductor layer 12I according to the modified example 5 illustrated in FIG. 17B includes a multilayer film (two-layer structure) in which the carrier supply layer 124 and the carrier traveling layer 123 are stacked in this order from the substrate 11 side. Has been. That is, these oxide semiconductor layers 12H and 12I are each configured using a single heterostructure having one carrier supply layer 124 and one carrier travel layer 123.

The carrier supply layer 124 is an oxide semiconductor layer that plays a role of supplying carriers (here, holes) to the carrier traveling layer 123. Examples of the oxide semiconductor constituting the carrier supply layer 124 include Al _x Cu _y O _{1.5x + 0.5y} (x, y: integer).

The carrier travel layer 123 is an oxide semiconductor layer for allowing carriers (holes) supplied from the carrier supply layer 124 to travel between the source / drain electrodes 16A and 16B. That is, in this carrier running layer 123, as in the carrier running layer 121, channels in the thin film transistors 1H and 1I are formed in the region near the interface with the carrier supply layer 124 (constitute the channel). . Examples of the oxide semiconductor constituting the carrier traveling layer 123 include Cu ₂ O and NiO.

  17A and 17B, in the oxide semiconductor layers 12H and 12I according to the modification examples 4 and 5, the valence band upper end level Ev4 of the semiconductor layer in the carrier supply layer 124 is The valence band upper end level Ev3 of the semiconductor layer in the carrier traveling layer 123 is set to be higher in energy (Ev4> Ev3). In this case, the energy band structure on the conduction band side may have any structure. Further, the symbol “h” in the figure schematically shows holes as carriers.

  With such a configuration, in the thin film transistors 1H and 1I of the modified examples 4 and 5, carriers (holes h) are supplied from the carrier supply layer 124 to the carrier traveling layer 123, and the carrier supply layer 124 in the carrier traveling layer 123 Holes h are accumulated in a region near the interface. In other words, in the oxide semiconductor layers 12H and 12I, the region that supplies the hole h (carrier supply layer 124) and the region in which the hole h actually travels (the interface between the carrier supply layer 124 in the carrier traveling layer 123). (Regions in the vicinity) are spatially separated along the thickness direction.

  Therefore, also in Modifications 4 and 5, the same effect can be obtained by the same operation as in the above-described embodiment and the like. That is, in spite of a simple structure, it is possible to achieve both improvement in carrier (hole) mobility and avoidance of formation of parasitic capacitance, and the operation speed of the transistor can be easily improved.

  In these modified examples 4 and 5, similarly to the modified examples 1 and 2, the low resistance layer 120 is provided in the source / drain regions 12SD of the oxide semiconductor layers 12H and 12I, or the carrier traveling layer is provided. The stacking order of 123 and the carrier supply layer 124 may be reversed.

<Application example>
Subsequently, application examples of the thin film transistors (thin film transistors 1, 1A to 1I) according to the first to fifth embodiments and the first to fifth modifications to the display device and the electronic device will be described.

[Display device]
FIG. 18 illustrates a configuration example of a display device (display device 3 configured using an organic EL element) used as an organic EL display. The display device 3 includes, for example, a display region 30 in which a plurality of pixels PXLC including organic EL elements (organic electroluminescent elements) as display elements are arranged in a matrix on a thin film transistor substrate (the substrate 11 described above). Have. Around the display area 30, there are a horizontal selector (HSEL) 31 as a signal line driving circuit, a write scanner (WSCN) 32 as a scanning line driving circuit, and a power scanner (DSCN) 33 as a power line driving circuit. Is provided.

  In the display area 30, a plurality (n integers) of signal lines DTL1 to DTLn are arranged in the column direction, and a plurality (m integers) of scanning lines WSL1 to WSLm and power supply lines DSL1 to DSLm are respectively arranged in the row direction. Has been placed. Each pixel PXLC (one of pixels corresponding to red (R), green (G), and blue (B)) is provided at the intersection of each signal line DTL and each scanning line WSL. Each signal line DTL is connected to a horizontal selector 31, and a video signal is supplied from the horizontal selector 31 to each signal line DTL. Each scanning line WSL is connected to the write scanner 32, and a scanning signal (selection pulse) is supplied from the write scanner 32 to each scanning line WSL. Each power supply line DSL is connected to the power supply scanner 33, and a power supply signal (control pulse) is supplied from the power supply scanner 33 to each power supply line DSL.

  FIG. 19 illustrates a circuit configuration example in the pixel PXLC. Each pixel PXLC has a pixel circuit 40 including an organic EL element 3D. The pixel circuit 40 is an active driving circuit having a sampling transistor 3A and a driving transistor 3B, a storage capacitor element 3C, and an organic EL element 3D. These transistors 3A and 3B are constituted by thin film transistors (thin film transistors 1 and 1A to 1I) of the above-described embodiment and the like.

  Sampling transistor 3A has its gate connected to corresponding scanning line WSL, one of its source and drain connected to corresponding signal line DTL, and the other connected to the gate of driving transistor 3B. The drive transistor 3B has a drain connected to the corresponding power supply line DSL and a source connected to the anode of the organic EL element 3D. The cathode of the organic EL element 3D is connected to the ground wiring 3H. The ground wiring 3H is wired in common to all the pixels PXLC. The storage capacitor element 3C is disposed between the source and gate of the driving transistor 3B.

  The sampling transistor 3A conducts according to the scanning signal (selection pulse) supplied from the scanning line WSL, thereby sampling the signal potential of the video signal supplied from the signal line DTL and holding it in the storage capacitor element 3C. Is. The driving transistor 3B is supplied with a current from a power supply line DSL set to a predetermined first potential (not shown), and changes the driving current to an organic EL element according to the signal potential held in the holding capacitor element 3C. Supply to 3D. The organic EL element 3D emits light with a luminance corresponding to the signal potential of the video signal by the driving current supplied from the driving transistor 3B.

  In the display device 3, the sampling transistor 3A is turned on in accordance with the scanning signal (selection pulse) supplied from the scanning line WSL, whereby the signal potential of the video signal supplied from the signal line DTL is sampled, and the storage capacitor It is held in the element 3C. In addition, a current is supplied from the power supply line DSL set to the first potential to the driving transistor 3B, and the driving current is changed to the organic EL element 3D (red, green and red) according to the signal potential held in the holding capacitor element 3C. To each blue organic EL element). Each organic EL element 3D emits light with a luminance corresponding to the signal potential of the video signal by the supplied drive current. Thereby, the display device 3 performs video display based on the video signal.

(Configuration Example 1 of Display Device)
Here, FIG. 20 illustrates a cross-sectional configuration of the display device (display device 3-1) according to the configuration example 1 of the display device 3 described above. As shown in the figure, the display device 3-1 is a bottom emission type (so-called bottom) in which display light (emission light) Lout from the organic EL element 3 </ b> D is emitted from the lower surface (surface on the substrate 11 side) side. Emission type) organic EL display device. In this display device 3-1, each of the sampling transistor 3A and the driving transistor 3B is configured by the thin film transistor of the above-described embodiment (here, as an example, a top gate type thin film transistor 1). On these thin film transistors, an inter-pixel insulating film 342, a common electrode 361, and a protective layer 343 are provided in this order, and are sealed with a sealing substrate 37. In the organic EL element 3D, an organic layer 35 including a light emitting layer is provided between a pixel electrode and a common electrode 361 described below.

  Further, in the display device 3-1, the oxide semiconductor layer 12 (the carrier travel layer 121 and the carrier supply layer 122) in the sampling transistor 3A extends to function as one electrode in the storage capacitor element 3C. Yes. That is, at least one of the multilayer films in the oxide semiconductor layer 12 (here, both layers) also serves as an electrode in the storage capacitor element 3C. Further, the carrier traveling layer 121 of the oxide semiconductor layer 12 in the driving transistor 3B selectively extends to function as a pixel electrode in the organic EL element 3D. That is, at least one of the multilayer films in the oxide semiconductor layer 12 (here, only the carrier travel layer 121) also serves as a pixel electrode in the organic EL element 3D as a display element.

  Note that an interlayer insulating film 341 (15) in a region sandwiched between the gate electrode 141 and the source / drain electrodes 16A and 16B may also be added as a storage capacitor. In addition, with respect to the pixel electrode in the light emitting portion (organic EL element 3D), the transmittance of the light emitting portion can be improved by leaving only one of the oxide semiconductor layers 12 (here, the carrier traveling layer 121). it can. For example, the source / drain electrodes 16A and 16B are formed using a laminated structure of molybdenum and aluminum that can be etched with a mixed acid composed of phosphoric acid, nitric acid, and acetic acid, and the carrier supply layer 122 is formed of, for example, IGZO or the carrier traveling layer 121. Is formed of ITO, for example. Thus, the carrier supply layer 122 can be removed simultaneously with the patterning of the source / drain electrodes 16A and 16B. Alternatively, the carrier supply layer 122 may be removed by etching when the inter-pixel insulating film 342 is patterned.

In the display device 3-1 having such a configuration, a TFT substrate can be manufactured by five times of mask exposure by forming the thin film transistors in the above-described embodiments in the following order.
(1) Patterning formation of carrier running layer 121 and carrier supply layer 122 (2) Batch patterning formation of gate electrode 141 and gate insulating film 131 (3) Patterning formation of interlayer insulating film 341 (15) (4) Source / drain electrodes Formation of 16A, 16B and wiring (signal line DTL and power supply line DSL) (5) Formation of inter-pixel insulating film 342

(Configuration example 2 of display device)
FIG. 21 illustrates a cross-sectional configuration of a display device (display device 3-2) according to the configuration example 2 of the display device 3 described above. In the display device 3-2, as shown in the drawing, the display light (emission light) Lout from the organic EL element 3D is emitted from the upper surface (surface on the sealing substrate 37 side) side. This is a so-called top emission type organic EL display device. In the display device 3-2, the sampling transistor 3 </ b> A and the driving transistor 3 </ b> B are each configured by the thin film transistor of the above-described embodiment (here, as an example, a top gate type thin film transistor 1). Further, a planarization film 344, a pixel electrode 362, an inter-pixel insulating film 342, a common electrode 361, and a protective layer 343 are provided in this order on these thin film transistors, and are sealed by a sealing substrate 37. Yes. In the organic EL element 3D, an organic layer 35 including a light emitting layer is provided between the pixel electrode 362 and the common electrode 361.

  Further, in the display device 3-2, the oxide semiconductor layer 12 (the carrier traveling layer 121 and the carrier supply layer 122) in the driving transistor 3B extends to function as one electrode in the storage capacitor element 3C. Yes. That is, at least one of the multilayer films in the oxide semiconductor layer 12 (here, both layers) also serves as an electrode in the storage capacitor element 3C. Note that an interlayer insulating film 341 (15) in a region sandwiched between the gate electrode 141 and the source / drain electrodes 16A and 16B may also be added as a storage capacitor.

In the display device 3-2 having such a configuration, a TFT substrate can be manufactured by seven times of mask exposure by making the formation order of the thin film transistors in the above-described embodiment and the like as follows.
(1) Patterning formation of carrier running layer 121 and carrier supply layer 122 (2) Batch patterning formation of gate electrode 141 and gate insulating film 131 (3) Patterning formation of interlayer insulating film 341 (15) (4) Source / drain electrodes Formation of 16A, 16B and wiring (signal line DTL and power supply line DSL) (5) Patterning formation of flattening film 344 (6) Patterning formation of common electrode 361 (7) Formation of inter-pixel insulating film 342

(Configuration Example 3 of Display Device)
FIG. 22 illustrates a cross-sectional configuration of a display device (display device 3-3) according to the configuration example 3 of the display device 3 described above. In the display device 3-3 as well, as shown in the drawing, display light (emission light) Lout from the organic EL element 3D is emitted from the upper surface (surface on the sealing substrate 37 side) side. This is a type (so-called top emission type) organic EL display device. In the display device 3-3, the sampling transistor 3A and the driving transistor 3B are each configured by the thin film transistor of the above-described embodiment (here, as an example, a bottom-gate thin film transistor 1F). Further, a planarization film 344, a pixel electrode 362, an inter-pixel insulating film 342, a common electrode 361, and a protective layer 343 are provided in this order on these thin film transistors, and are sealed by a sealing substrate 37. Yes. In the organic EL element 3D, an organic layer 35 including a light emitting layer is provided between the pixel electrode 362 and the common electrode 361.

  Here, although not shown in the figure, the oxide semiconductor layer 12 (at least one of the carrier traveling layer 121 and the carrier supply layer 122) in the sampling transistor 3A or the driving transistor 3B extends to hold the storage capacitor element. You may make it function also as one electrode in 3C. That is, at least one of the multilayer films in the oxide semiconductor layer 12 may also serve as an electrode in the storage capacitor element 3C. Further, an interlayer insulating film may be inserted so as to be sandwiched between the planarization film 344 and the source / drain electrodes 16A and 16B.

[Electronics]
Next, an application example of the display device described above to an electronic device will be described. The display device can be applied to electronic devices in various fields such as television devices, digital cameras, notebook personal computers, portable terminal devices such as mobile phones, and video cameras. In other words, the display device can be applied to electronic devices in various fields that display a video signal input from the outside or a video signal generated inside as an image or video.

(module)
The display device is incorporated into various electronic devices such as application examples 1 to 5 described later, for example, as a module shown in FIG. In this module, for example, an area 210 exposed from the sealing substrate 50 is provided on one side of the substrate 11, and the wiring of the horizontal selector 31, the light scanner 32, and the power scanner 33 is extended to the exposed area 210. A connection terminal (not shown) is formed. The external connection terminal may be provided with a flexible printed circuit (FPC) 220 for signal input / output.

(Application example 1)
FIG. 24 illustrates an appearance of a television device to which the display device is applied. This television apparatus has, for example, a video display screen unit 300 including a front panel 310 and a filter glass 320, and the video display screen unit 300 is constituted by the display device.

(Application example 2)
FIG. 25 shows an appearance of a digital camera to which the display device is applied. The digital camera includes, for example, a flash light emitting unit 410, a display unit 420, a menu switch 430, and a shutter button 440, and the display unit 420 includes the display device.

(Application example 3)
FIG. 26 shows an appearance of a notebook personal computer to which the display device is applied. The notebook personal computer has, for example, a main body 510, a keyboard 520 for inputting characters and the like, and a display unit 530 for displaying an image. The display unit 530 is constituted by the display device.

(Application example 4)
FIG. 27 shows the appearance of a video camera to which the display device is applied. This video camera includes, for example, a main body 610, a subject photographing lens 620 provided on the front side surface of the main body 610, a start / stop switch 630 at the time of photographing, and a display 640. And this display part 640 is comprised by the said display apparatus.

(Application example 5)
FIG. 28 shows an appearance of a mobile phone to which the display device is applied. This mobile phone is obtained by connecting, for example, an upper housing 710 and a lower housing 720 with a connecting portion (hinge portion) 730, and includes a display 740, a sub-display 750, a picture light 760, and a camera 770. . Of these, the display 740 or the sub-display 750 is constituted by the display device.

<Other variations>
Although the present invention has been described with the embodiment, the modification, and the application example, the present invention is not limited to the embodiment and the like, and various modifications are possible.

  For example, in the above embodiment and the like, the case where the oxide semiconductor layer has a single heterostructure (two-layer structure) has been described. However, the present invention is not limited to this, and for example, the oxide semiconductor layer has a double heterostructure (three-layer structure). (The above structure) may be used.

  In the application example described above, a display device (organic EL display device) configured using an organic EL element has been described as an application example of the thin film transistor of the present invention to a display device. However, the present invention is limited to this case. Absent. In other words, the thin film transistor of the present invention is a display device other than an organic EL display device (for example, a liquid crystal display device using a liquid crystal element as a display element, or a light emitting diode (LED) as a display element. It is also possible to apply to an LED display device configured by using a).

  Further, the material and thickness of each layer described in the above embodiments and the like, or the film formation method and film formation conditions are not limited, and other materials and thicknesses may be used, or other film formation methods and film formation may be used. It is good also as film | membrane conditions.

DESCRIPTION OF SYMBOLS 1,1A-1I ... Thin-film transistor, 11 ... Substrate, 12, 12A-12C, 12H, 12I ... Oxide semiconductor layer, 12SD ... Source-drain region, 120 ... Low resistance layer, 121, 123 ... Carrier travel layer, 122 , 124 ... carrier supply layer, 131, 132 ... gate insulating film, 141, 142 ... gate electrode, 15 ... interlayer insulating film, 16A, 16B ... source / drain electrode, 17 ... low resistance layer, 18 ... channel protective film, 3 , 3-1 to 3-3... Display device, 3A... Sampling transistor, 3B... Driving transistor, 3C .. holding capacitor element, 3D... Organic EL element (organic electroluminescence element), 3H. Area 31 ... Horizontal selector 32 ... Write scanner 33 ... Power supply scanner 341 ... Interlayer insulating film 342 ... Inter-pixel insulating film 343 ... Protection , 344 ... flattening film, 35 ... organic layer, 361 ... common electrode, 362 ... pixel electrode, 37 ... sealing substrate, 40 ... pixel circuits, E _F ... Fermi energy, Ec0, EC1 to EC4 ... conduction band quasi Ev0, Ev1 to Ev4 ... valence band top level, e ... electron, h ... hole, PXLC ... pixel, DTL ... signal line, WSL ... scanning line, DSL ... power line, Lout ... display light (emission light) .

Claims (15)

A gate electrode;
An oxide semiconductor layer composed of a multilayer film including a carrier traveling layer constituting a channel and a carrier supply layer for supplying carriers to the carrier traveling layer;
A gate insulating film provided between the gate electrode and the oxide semiconductor layer;
A pair of electrodes to be a source and a drain,
A thin film transistor in which a source / drain region and a formation region of the gate electrode in the oxide semiconductor layer are separated from each other. 2. The thin film transistor according to claim 1, wherein both the carrier traveling layer and the carrier supply layer are formed from a region where the gate electrode is formed to the source / drain region. The thin film transistor according to claim 2, further comprising a low resistance layer between at least the source / drain region and the pair of electrodes in the oxide semiconductor layer. The carrier supply layer is formed from the gate electrode formation region to the source / drain region,
The thin film transistor according to claim 1, wherein the carrier traveling layer is selectively formed in a formation region of the gate electrode. The thin film transistor according to any one of claims 1 to 4, wherein the source / drain regions in the oxide semiconductor layer are low-resistance layers. The conduction band bottom level or valence band top level of the semiconductor layer in the carrier supply layer is higher in energy than the conduction band bottom level or valence band top level of the semiconductor layer in the carrier transit layer. The thin film transistor according to any one of claims 1 to 4. The carrier is an electron;
The thin film transistor according to claim 6, wherein a conduction band lower level in the carrier supply layer is energetically higher than a conduction band lower level in the carrier traveling layer. The carrier is a hole;
The thin film transistor according to claim 6, wherein a valence band upper level in the carrier supply layer is energetically higher than a valence band upper level in the carrier traveling layer. The thin film transistor according to any one of claims 1 to 4, wherein the oxide semiconductor layer, the gate insulating film, and the gate electrode are provided in this order on a substrate. The thin film transistor according to any one of claims 1 to 4, wherein the gate electrode, the gate insulating film, and the oxide semiconductor layer are provided in this order on a substrate. First and second gate electrodes are provided as the gate electrodes,
As the gate insulating film, first and second gate insulating films are provided,
The second gate electrode, the second gate insulating film, the oxide semiconductor layer, the first gate insulating film, and the first gate electrode are provided in this order on a substrate. Item 5. The thin film transistor according to any one of items 4. A display element and a thin film transistor for driving the display element;
The thin film transistor
A gate electrode;
An oxide semiconductor layer composed of a multilayer film including a carrier traveling layer constituting a channel and a carrier supply layer for supplying carriers to the carrier traveling layer;
A gate insulating film provided between the gate electrode and the oxide semiconductor layer;
A pair of electrodes to be a source and a drain, and
A display device, wherein a source / drain region and a formation region of the gate electrode in the oxide semiconductor layer are separated from each other. The display element and the storage capacitor element are provided for each of a plurality of pixels,
The display device according to claim 12, wherein at least one of the multilayer films in the oxide semiconductor layer also serves as a pixel electrode in the display element or an electrode in the storage capacitor element. The display device according to claim 12, wherein the display element is configured using an organic EL element. A display device having a display element and a thin film transistor for driving the display element;
The thin film transistor
A gate electrode;
An oxide semiconductor layer composed of a multilayer film including a carrier traveling layer constituting a channel and a carrier supply layer for supplying carriers to the carrier traveling layer;
A gate insulating film provided between the gate electrode and the oxide semiconductor layer;
A pair of electrodes to be a source and a drain, and
An electronic apparatus in which a source / drain region and a formation region of the gate electrode in the oxide semiconductor layer are separated from each other.

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