JP2012178376A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that a leakage current in a gate part can be reduced, but manufacturing of a semiconductor device is difficult due to restriction of processes and stable reduction of gate leakage currents is difficult.SOLUTION: A semiconductor device includes: a substrate; a semiconductor function layer formed on the substrate and including two-dimensional carrier gas; first and second main electrodes formed on the semiconductor function layer separately from each other; a control electrode formed between the first and second main electrodes on the semiconductor function layer; and a metal oxide film formed between the semiconductor function layer and the control electrode. A crystal lattice on a junction interface between the metal oxide film and the semiconductor function layer is discontinuous.

Description

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device used as a switching element and a manufacturing method thereof.

A high electron mobility transistor (HEMT) using a gallium nitride (GaN) compound semiconductor is known. Since HEMT has a low on-resistance and a high breakdown voltage, it is used in a switching power supply circuit for power conversion. When a HEMT is used as a switching element in a switching power supply circuit, a normally-off (enhancement) type HEMT is required in consideration of ease of control and safety.

Patent Document 1 discloses a conventional semiconductor device that can reduce a leakage current when a normally-off HEMT is operated, that is, when a positive gate bias is applied to a gate electrode. As shown in FIG. 3, the conventional semiconductor device 100 includes a substrate 101, a buffer layer 102, a GaN layer 103 (electron transit layer), an AlGaN layer 104 (electron supply layer), and an InGaN layer 105 (barrier layer). Have a configuration. A source electrode 106 and a drain electrode 107 are formed on the AlGaN layer 104, and a gate electrode 108 that forms a Schottky junction is formed on the InGaN layer 105.

In the conventional semiconductor device 100, since the lattice constant (a-axis lattice constant) in the horizontal plane of the InGaN layer 105 is larger than that of the GaN layer 103, in-plane compressive strain occurs. Therefore, the piezo effect works so that positive charges are generated on the (0001) plane side (the upper side in the figure) of the InGaN layer 105. Therefore, as the distance from the interface between the gate electrode 108 and the InGaN layer 105 increases, the barrier height perceived by electrons increases, and the conventional semiconductor device 100 can reduce the gate leakage current at the Schottky junction during the normally-off HEMT operation. .

JP 2002-17087 A

By the way, in the conventional semiconductor device 100, the InGaN layer 105 must be coherently grown on the AlGaN layer 104 in order to generate the piezoelectric effect by the InGaN layer 105. That is, the InGaN layer 105 needs to grow while maintaining the continuity of the lattice at the junction interface with the AlGaN layer 104 due to distortion of the crystal lattice. Therefore, in the process of forming the InGaN layer 105, a limited process such as an epitaxial growth method must be used. In addition, in order to sufficiently reduce the leakage current, it is necessary to form the InGaN layer 105 with a sufficient thickness. In order to prevent the occurrence of dislocation due to the lattice distortion, the InGaN layer 105 has a critical thickness. It must be formed in the following limited range.

As described above, the conventional normally-off type semiconductor device can reduce the leakage current in the gate portion, but is difficult to manufacture due to process limitations, and it is difficult to stably reduce the gate leakage current.

According to one aspect of the present invention, a substrate, a semiconductor functional layer formed on the substrate and having a two-dimensional carrier gas, and first and second main layers formed on the semiconductor functional layer so as to be separated from each other. An electrode, a control electrode formed between the first and second main electrodes on the semiconductor functional layer, and a metal oxide film formed between the semiconductor functional layer and the control electrode, A semiconductor device is provided in which a crystal lattice at a junction interface between the metal oxide film and the semiconductor functional layer is discontinuous.
According to another aspect of the present invention, a step of preparing a substrate and Al _x In _y Ga _1-xy N (where 0 ≦ x <1, 0 ≦ y ≦ 1, 0) are provided on the substrate. ≦ x + y ≦ 1) forming a carrier traveling layer, and Al _a In _b Ga _1-ab N (where 0 <a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b) on the carrier traveling layer Forming a carrier supply layer including ≦ 1, x <a) to obtain a semiconductor functional layer, forming the first and second main electrodes on the semiconductor functional layer apart from each other, and the semiconductor A semiconductor comprising: a step of forming a metal oxide film between the first and second main electrodes on the functional layer so that a crystal lattice is discontinuous; and a step of forming a control electrode on the metal oxide film A method of manufacturing a device is provided.

According to the present invention, there is provided a normally-off type semiconductor device that is easy to manufacture and can stably reduce the gate leakage current.

It is sectional drawing which shows the structure of the semiconductor device which concerns on embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device.

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is the material, shape, structure, and arrangement of component parts. Etc. are not specified below. The technical idea of the present invention can be variously modified within the scope of the claims.

FIG. 1 is a cross-sectional view showing the structure of a semiconductor device 10 according to an embodiment of the present invention. A semiconductor device 10 according to an embodiment of the present invention includes a substrate 11, a semiconductor functional layer 19 formed on the substrate 11, a source electrode (first main electrode) 16 and a drain formed on the semiconductor functional layer 19. An electrode (second main electrode) 17, a gate electrode 18 (control electrode) formed on the semiconductor functional layer 19, a metal oxide film 15 formed between the semiconductor functional layer 19 and the control electrode 18, Is provided. The crystal lattice at the junction interface between the metal oxide film 15 and the semiconductor functional layer 19 is formed to be discontinuous.

Further, in the semiconductor device 10 according to the embodiment of the present invention, the substrate 11, the buffer layer 12, the electron transit layer 13 (carrier transit layer), the electron supply layer 14 (carrier supply layer), and the metal oxide film 15 are laminated. It has a configuration. A source electrode 16 and a drain electrode 17 are formed on the electron supply layer 14, and a gate electrode 18 is formed on the metal oxide film 15. The electron transit layer 13 and the electron supply layer 14 in the present embodiment constitute a semiconductor functional layer 19. In addition, the electron transit layer 13 and the electron supply layer 14 form a heterojunction, and a two-dimensional electron gas (2DEG) serving as a main current path of the HEMT is near the heterojunction interface of the electron transit layer 13. It is formed.

The substrate 11 is made of a semiconductor such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or an insulator such as sapphire or ceramic. The substrate 11 in the present embodiment is made of a silicon substrate that can easily increase the diameter and contribute to the cost reduction of the semiconductor device 10.

The buffer layer 12 is formed on the substrate 11 and is provided to alleviate the lattice mismatch between the substrate 11 and the semiconductor functional layer 19 and to increase the thickness of the semiconductor functional layer 19. In FIG. 1, the buffer layer 12 is illustrated as one layer, but the buffer layer 12 may be formed of a plurality of layers. For example, the buffer layer 12 may be a multilayer buffer in which first layers made of aluminum nitride (AlN) and second layers made of gallium nitride (GaN) are alternately stacked. When the compound semiconductor device 10 operates as a HEMT, the buffer layer 12 may be omitted because the buffer layer 12 is not directly related to the operation of the HEMT. Further, as the material of the buffer layer 12, a nitride semiconductor other than AlN and GaN, or a III-V group compound semiconductor may be employed. A structure in which the substrate 11 and the buffer layer 12 are combined can also be regarded as a substrate. The structure and arrangement of the buffer layer 12 are determined according to the material of the substrate 11 and the semiconductor functional layer 19 and the like.

The electron transit layer 13 is a carrier transit layer in the present invention, and may be referred to as a channel layer. The electron transit layer 13 can be formed directly on the substrate 11, but is formed via the buffer layer 12 in this embodiment. Further, the electron transit layer 13 in the present embodiment is composed of undoped GaN, _Al was added conductivity type impurities such as Si _{x In y Ga 1-x-} y N (0 ≦ x <1,0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). In addition, undoped here means that the impurity is not added intentionally.

The electron supply layer 14 is a carrier supply layer in the present invention, and may be referred to as a barrier layer. The electron supply layer 14 in the present embodiment is formed directly on the electron transit layer 13, but may be formed via a known spacer layer containing AlGaN or AlN. Further, the electron supply layer 14 in the present embodiment is made of undoped Al _0.3 Ga _0.7 N having a larger band gap than the electron transit layer 13, but Al doped with a conductivity type impurity such as Si. _a In _b Ga _1-ab N (0 <a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1, x <a) can also be used.

The electron transit layer 13 and the electron supply layer 14 constitute a semiconductor functional layer 19 having a heterojunction interface. A two-dimensional electron gas is formed near the heterojunction interface of the electron transit layer 13. The two-dimensional electron gas is a two-dimensional carrier gas in the present invention. That is, the semiconductor functional layer 19 may be configured such that holes (holes) serve as carriers instead of electrons.

The metal oxide film 15 is formed between the semiconductor functional layer 19 and the gate electrode 18 in order to reduce gate leakage current and increase the gate threshold value of the semiconductor device 10. The metal oxide film 15 in this embodiment has a single layer structure containing nickel oxide (NiOx), but a single layer containing iron oxide (FeOx), cobalt oxide (CoOx), manganese oxide (MnOx), and copper oxide (CuOx). It may have a layer or multilayer structure. The metal oxide film 15 is formed so that the lattice becomes discontinuous at the interface with the electron supply layer 14 so as to reduce the stress acting between the metal oxide film 15 and the electron supply layer 14. The metal oxide film 15 has a crystal structure including dislocations at a density of 1 × 10 ⁹ cm ⁻² or more, or an amorphous (amorphous) structure or a polycrystalline structure.

The source electrode 16 and the drain electrode 17 are the first and second main electrodes in the present invention, and are formed on the semiconductor functional layer 19 with the metal oxide film 15 interposed therebetween and spaced apart from each other. In this embodiment, the source electrode 16 and the drain electrode 17 are formed on the electron supply layer 14 by a laminated structure of titanium (Ti) and aluminum (Al) so as to be in ohmic contact with the electron supply layer 14. A well-known contact layer may be formed between the electron supply layer 14 and the source electrode 16 and between the electron supply layer 14 and the drain electrode 17. Alternatively, the electron supply layer 14 may be removed by etching so as to expose the electron transit layer 13 where the electrode is formed, and the source electrode 16 and the drain electrode 17 may be formed in ohmic contact with the electron transit layer 13.

The gate electrode 18 is a control electrode in the present invention, and is formed on the semiconductor functional layer 19 via the metal oxide film 15 between the source electrode 16 and the drain electrode 17. The gate electrode 18 in this embodiment is disposed adjacent to the metal oxide film 15 and includes a stacked structure of nickel (Ni), titanium (Ti), and aluminum (Al). The gate electrode 18 controls the carrier concentration of the two-dimensional electron gas immediately below the gate electrode 18 according to the bias voltage applied thereto, and conducts / cuts off the current path between the source electrode 16 and the drain electrode 17.

2A to 2D are process cross-sectional views illustrating the method for manufacturing the semiconductor device 10 according to the embodiment of the present invention.
First, a substrate 11 made of a single crystal silicon substrate is placed in a chamber of a CVD (chemical vapor deposition) apparatus, and a source gas is supplied into the chamber while heating the substrate 11. As the source gas in the present embodiment, trimethylgallium (TMG), trimethylaluminum (TMA), and ammonia (NH ₃ ) are used. A buffer layer 12 having a multilayer structure in which AlN layers and GaN layers are alternately stacked is formed on the substrate 11 by appropriately controlling the supply amount, flow rate, and the like of the source gas, and an electron transit layer 13 including a GaN layer. And a semiconductor functional layer 19 having an electron supply layer 14 including an Al _0.3 Ga _0.7 N layer is formed on the buffer layer 12 (FIG. 2A). The AlN layer and the GaN layer constituting the buffer layer 12 are each formed to a thickness of 1 to 30 nm, the electron transit layer 13 is formed to a thickness of 1 to 10 μm, and the electron supply layer 14 is thinner than the electron transit layer 13 to 5 to 5 nm. It is formed to a thickness of 50 nm.

Next, the substrate 11 (wafer) on which the semiconductor functional layer 19 obtained in the above process is formed is placed in a chamber of a sputtering apparatus, and sputtering using titanium as a target and sputtering using aluminum as a target are continuously performed. Do. By this sputtering process, a metal film 20 having a uniform thickness and a Ti / Al laminated structure is formed on the surface of the semiconductor functional layer 19. Thereafter, a mask 21 for patterning the metal film 20 is formed on the metal film 20 (FIG. 2B). The mask 21 is selected from well-known oxide films and photoresist materials, and is formed corresponding to the positions where the source electrode 16 and the drain electrode 17 are formed.

Next, a part of the metal film 20 is removed by wet etching, and the source electrode 16 and the drain electrode 17 are formed on the surface of the semiconductor functional layer 19. After removing the mask 21, a mask 22 for forming the metal oxide film 15 is formed on the surfaces of the semiconductor functional layer 19, the source electrode 16 and the drain electrode 17. The mask 22 is selected from well-known oxide films and photoresist materials, and is formed corresponding to the position where the metal oxide film 15 is formed. That is, a part of the semiconductor functional layer 19 is exposed by the opening of the mask 22. Thereafter, the substrate 11 (wafer) on which the mask 22 is formed is placed in a chamber of a reactive sputtering apparatus, and sputtering is performed using nickel as a target in an oxygen atmosphere. By this sputtering process, a metal oxide film 23 having a uniform thickness and containing NiOx is formed on the surfaces of the mask 22 and a part of the semiconductor functional layer 19 (FIG. 2C). According to the oxygen concentration in the chamber, a metal oxide film 23 having a composition such as NiO or NiO ₂ is obtained. The thickness of the metal oxide film 23 is set to about 3 to 1000 nm, preferably about 10 to 500 nm. When the metal oxide film 23 is thinner than 3 nm, the normally-off characteristic and the gate leakage current reduction effect may be weakened. When the metal oxide film 23 is thicker than 1000 nm, the switching characteristics such as the turn-on speed may be deteriorated.

Next, the metal oxide film 23 formed on the surface of the mask 22 is removed together with the mask 22 by a lift-off process, and the metal oxide film 15 is formed on the surface of the semiconductor functional layer 19. Since the metal oxide film 15 according to the present embodiment is formed by a sputtering process, it is formed discontinuously with respect to the crystal lattice of the semiconductor functional layer 19. Thereafter, the gate electrode 18 is formed on the metal oxide film 15 by the same process (patterning process) as the source electrode 16 and the drain electrode 17, and the semiconductor device 10 according to the present embodiment is obtained (FIG. 2D). ).

The semiconductor device 10 according to the present embodiment has the following operational effects.
(1) Since the metal oxide film 15 containing nickel oxide has a high hole concentration according to its oxygen concentration, the potential immediately below the metal oxide film 15 and the gate electrode 18 is raised, and the metal oxide film 15 directly below the metal oxide film 15 and the gate electrode. The generation of a two-dimensional electron gas in the electron transit layer 13 immediately below 18 is suppressed. That is, the channel between the source electrode 16 and the drain electrode 17 is divided in a state where a gate bias is not applied to the gate electrode 18 (normally). Therefore, no current flows between the main electrodes of the semiconductor device 10 during normal operation.
On the other hand, when a gate bias higher than the threshold voltage is applied to the gate electrode 18 in a state where the potential of the drain electrode 17 is higher than the potential of the source electrode 16, the electron transit layer 13 immediately below the metal oxide film 15 and immediately below the gate electrode 18. A channel is formed. Accordingly, the channel that has been disconnected at the time of normality is conducted, the semiconductor device 10 is turned on, and a current flows between the source electrode 16 and the drain electrode 17. As described above, the semiconductor device 10 according to the present embodiment has normally-off (enhancement) characteristics useful as a switching element in the switching power supply circuit.
(2) Since the metal oxide film 15 can be regarded as an oxide film having p-type conductivity as described above, a pn junction is formed between 2DEG formed in the semiconductor functional layer 19. Compared with a conventional semiconductor device having a Schottky gate structure, gate leakage current during operation of the semiconductor device can be reduced.
(3) Since the normally-off characteristic of the semiconductor device according to this embodiment is obtained by increasing the oxygen concentration of the metal oxide film 15, it affects the continuity of the lattice at the junction interface between the metal oxide film 15 and the semiconductor functional layer 19. Not. Therefore, the semiconductor device according to this embodiment has stable characteristics as compared with the conventional semiconductor device and can be manufactured by an easy manufacturing process.
(4) The metal oxide film 15 does not need to be coherently grown on the semiconductor functional layer 19 and can be formed easily by a manufacturing method such as sputtering, which can be easily increased. . Therefore, the gate leakage current can be suppressed by increasing the resistance value of the metal oxide film 15 while having good normally-off characteristics.

The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Substrate 12 Buffer layer 13 Electron transit layer 14 Electron supply layer 15 Metal oxide film 16 Source electrode 17 Drain electrode 18 Gate electrode 19 Semiconductor functional layer

Claims (5)

A substrate, a semiconductor functional layer formed on the substrate and having a two-dimensional carrier gas, first and second main electrodes formed on the semiconductor functional layer so as to be spaced apart from each other, and on the semiconductor functional layer A control electrode formed between the first and second main electrodes, and a metal oxide film formed between the semiconductor functional layer and the control electrode,
A semiconductor device, wherein a crystal lattice at a junction interface between the metal oxide film and the semiconductor functional layer is discontinuous. The semiconductor device according to claim 1, wherein the metal oxide film has a single layer or a stacked structure including at least one of nickel oxide, iron oxide, cobalt oxide, manganese oxide, and copper oxide. The semiconductor device according to claim 1, wherein the metal oxide film has a thickness of 3 to 1000 nm. The semiconductor functional layer includes a carrier traveling layer including Al _x In _y Ga _1-xy N (where 0 ≦ x <1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), and Al _a In _b Ga _{1. And a} carrier supply layer containing _-a-bN (where 0 <a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1, x <a). A semiconductor device according to claim 1. Preparing a substrate;
Forming a carrier traveling layer containing Al _x In _y Ga _1-xy N (where 0 ≦ x <1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) on the substrate;
Forming a carrier supply layer containing Al _a In _b Ga _1-ab N (where 0 <a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1, x <a) on the carrier travel layer; Obtaining a semiconductor functional layer;
Forming the first and second main electrodes on the semiconductor functional layer separately from each other;
Forming a metal oxide film between the first and second main electrodes on the semiconductor functional layer so that a crystal lattice is discontinuous;
Forming a control electrode on the metal oxide film.

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