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JP2012182241A - Coupling conductor and semiconductor device using the same - Google Patents

Coupling conductor and semiconductor device using the same Download PDF

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JP2012182241A
JP2012182241A JP2011042992A JP2011042992A JP2012182241A JP 2012182241 A JP2012182241 A JP 2012182241A JP 2011042992 A JP2011042992 A JP 2011042992A JP 2011042992 A JP2011042992 A JP 2011042992A JP 2012182241 A JP2012182241 A JP 2012182241A
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electrode
semiconductor device
gate
lead
external extraction
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Eiji Yasuda
英司 安田
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Panasonic Corp
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Panasonic Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a trench gate, which achieves reduction in lead out resistance of the gate and a higher working speed.SOLUTION: The present semiconductor device is electrically connected with one end of a lead terminal 30R of a lead frame 30 via a coupling conductor 15. The coupling conductor is made of a Cu foil and includes a body part 15M, a lead connection part 15R contacting the lead terminal 30R and connected to the lead terminal 30R, finger parts 15F contacting a source pad of a trench MOSFET (chip), and a coupling part 15B integrating tips of the finger parts 15F in a space part. By using this coupling conductor, highly reliable mounting at low resistance can be achieved even in the case where a gate pad 35g as a second external lead out electrode is extended and formed between source electrodes 35s included in a first external lead out electrode.

Description

本発明は、連結導体及びこれを用いた半導体装置に係り、特にトレンチ構造のＭＯＳＦＥＴのソース電極とリードとの接続などに用いられる帯状の連結導体（クリップ）の構造に関する。   The present invention relates to a connecting conductor and a semiconductor device using the connecting conductor, and more particularly to a structure of a strip-like connecting conductor (clip) used for connecting a source electrode and a lead of a MOSFET having a trench structure.

近年、携帯電話をはじめとした電子機器における低消費電力化、高機能化及び高速化に伴い、それに搭載される半導体装置も低消費電力化、高速化が要求されてきている。一般的に電子機器のロードスイッチ及びＤＣ−ＤＣコンバータ等に用いられているトランジスタも、それらに対応するためにオン抵抗の小さなものが要求されている。トランジスタのオン抵抗の低減をはかるためには、個々のデバイスを微細化して、単位面積あたりに配置するトランジスタの密度を大きくすることが、一つの方法としてあげられる。具体的には、例えば、トレンチにゲート電極を形成した縦型ＭＯＳＦＥＴにおいて、トランジスタを形成しているトレンチをストライプ状に配置して、トレンチの幅を微細化すると共に、隣接するトレンチ間のピッチを小さくすることでトランジスタ密度を大きくすることが出来る。この構造はトレンチを格子状に設けた構造と比較して単にセル面積当たりのゲート酸化膜の面積が低減されるため、ゲートドレイン間の寄生容量を低減することができるものである。   In recent years, with the reduction in power consumption, higher functionality, and higher speed in electronic devices such as mobile phones, semiconductor devices mounted on the electronic devices have been required to have lower power consumption and higher speed. Transistors generally used in load switches and DC-DC converters for electronic devices are also required to have low on-resistance in order to cope with them. In order to reduce the on-resistance of a transistor, one method is to miniaturize each device and increase the density of the transistors arranged per unit area. Specifically, for example, in a vertical MOSFET in which a gate electrode is formed in a trench, the trenches in which the transistors are formed are arranged in a stripe shape to reduce the width of the trench and to increase the pitch between adjacent trenches. The transistor density can be increased by reducing the transistor density. In this structure, the area of the gate oxide film per cell area is simply reduced as compared with the structure in which the trenches are provided in a lattice shape, so that the parasitic capacitance between the gate and drain can be reduced.

一例として、図１３および図１４に示すように、半導体基板１内に深さＴｈ，幅ＴＷの多数のトレンチＴを配設し、このトレンチＴ内にＭＯＳＦＥＴを配設したものがある（たとえば特許文献１）。この構造では、半導体基板の表面の一部にゲートパッド３５ｇが形成され、トレンチＴに多結晶シリコンを充填して形成されるゲート電極（多結晶シリコンゲート）３３は、半導体基板の周縁に沿って形成されるゲート周辺配線を含む集電層３５ｇｌによって、このゲートパッド３５ｇに接続される。ここではゲート周辺配線である集電層３５ｇｌの下層に多結晶シリコンからなる下地配線３３ｇｌが形成されている。 As an example, as shown in FIGS. 13 and 14, a plurality of trenches T having a depth T h and a width T W are provided in a semiconductor substrate 1, and MOSFETs are provided in the trenches T ( For example, Patent Document 1). In this structure, a gate pad 35g is formed on a part of the surface of the semiconductor substrate, and a gate electrode (polycrystalline silicon gate) 33 formed by filling the trench T with polycrystalline silicon extends along the periphery of the semiconductor substrate. The gate pad 35g is connected by a current collecting layer 35gl including a gate peripheral wiring to be formed. Here, a base wiring 33gl made of polycrystalline silicon is formed under the current collecting layer 35gl which is a gate peripheral wiring.

この半導体装置では、図１４（ａ）および（ｂ）に示すように半導体層上に複数のトレンチラインが形成され、その内部に充填された多結晶シリコンからなるゲート電極３３の終端部は半導体基板周縁部に形成された集電リング電極ｇｌに直接接続している。集電リング電極ｇｌは多結晶シリコン層からなる下地層３３ｇｌとアルミウム層からなる集電層３５ｇｌとで構成されている。ソース領域３２ｓを構成するＮ型拡散領域はトレンチラインに接するようにその両端のエピタキシャル層中に形成されている。また、ソース領域３２ｓを構成するＮ型拡散層とソース電極(パッド)３５ｓを構成する金属配線が電気的に接続している領域の開口端すなわちソースコンタクト開口部が、トレンチライン上に設けられている。
そして、ストライプ状のゲート電極と直交するゲート引出用の橋渡し電極３５Ｂを設けることで交差部でのゲート抵抗Ｒｇを低減できるように構成している。 In this semiconductor device, as shown in FIGS. 14A and 14B, a plurality of trench lines are formed on the semiconductor layer, and the terminal portion of the gate electrode 33 made of polycrystalline silicon filled therein is formed on the semiconductor substrate. It is directly connected to the current collecting ring electrode gl formed on the peripheral edge. The current collecting ring electrode gl is composed of a base layer 33gl made of a polycrystalline silicon layer and a current collecting layer 35gl made of an aluminum layer. N-type diffusion regions constituting the source region 32s are formed in the epitaxial layers at both ends so as to be in contact with the trench line. In addition, an opening end of a region where the N-type diffusion layer constituting the source region 32s and the metal wiring constituting the source electrode (pad) 35s are electrically connected, that is, a source contact opening is provided on the trench line. Yes.
Then, the gate resistance Rg at the intersecting portion can be reduced by providing the gate lead-out bridging electrode 35B orthogonal to the stripe-shaped gate electrode.

また、多結晶シリコンよりなるゲート電極３３を素子表面に引出し、ソース配線やドレイン配線と平行に延びるゲート配線を設ける。このゲート配線に、多結晶シリコンより重抵抗が小さいアルミニウムなどの導電材料よりなる裏打ち配線を電気的に接続し、ゲート抵抗を低減する方法も提案されている（特許文献２）。   Further, a gate electrode 33 made of polycrystalline silicon is led out to the element surface, and a gate wiring extending in parallel with the source wiring and the drain wiring is provided. A method of reducing the gate resistance by electrically connecting a backing wiring made of a conductive material such as aluminum having a lower heavy resistance than that of polycrystalline silicon to the gate wiring has been proposed (Patent Document 2).

さらにまた、ソース配線とソース電極の接続位置を最適にすることにより、各トランジスタのオン/オフ特性を向上する方法も提案されている（特許文献３）。   Furthermore, a method for improving the on / off characteristics of each transistor by optimizing the connection position between the source wiring and the source electrode has been proposed (Patent Document 3).

また、半導体チップをパッケージに実装するに際しても低容量化が大きな課題となっている。半導体装置の製造工程のうち、実装工程の一例は、以下のとおりである。まず、所望の素子領域および配線の形成されたウエハから切り出された半導体チップは、銅を主成分とする板状体を加工して形成され、アイランド部（半導体素子搭載部）と、このアイランド部に先端が近接するように形成されたリード端子からなるリード部とを備えたリードフレームのアイランド部に搭載される。次に、半導体チップの表面上に形成された素子電極は、金線やアルミニウム線などの連結導体を用いて、アイランド部の周縁に近接して設けられたリード端子と電気的に接続される。その後、半導体チップ及びリードフレームは、リード端子の先端の一部を残して、樹脂等で封止されてパッケージ化され、半導体装置となる。ここでパッケージとは、リードを含むリードフレームと、封止樹脂とをあわせたものをいうこととする。   In addition, when mounting a semiconductor chip on a package, a reduction in capacitance is a major issue. Of the semiconductor device manufacturing processes, an example of a mounting process is as follows. First, a semiconductor chip cut out from a wafer in which a desired element region and wiring are formed is formed by processing a plate-shaped body mainly composed of copper, and an island portion (semiconductor element mounting portion) and the island portion are formed. The lead frame is mounted on an island portion of a lead frame having a lead portion formed of a lead terminal formed so that the tip is close to the lead portion. Next, the element electrode formed on the surface of the semiconductor chip is electrically connected to a lead terminal provided in the vicinity of the periphery of the island portion using a connecting conductor such as a gold wire or an aluminum wire. Thereafter, the semiconductor chip and the lead frame are packaged by being sealed with a resin or the like, leaving a part of the tip of the lead terminal, thereby forming a semiconductor device. Here, the package means a combination of a lead frame including leads and a sealing resin.

ここで、半導体チップとリードとの接続に、ボンディングワイヤと呼ばれる金線やアルミニウム線などの連結導体を用いた場合、１本あたりの線径が数十から数百μｍ程度である。オン抵抗を低減するためには、数十から数百本の金線やアルミニウム線などを用いる必要があり、コストの増大や組立工程の複雑化を招く。   Here, when a connecting conductor such as a gold wire or an aluminum wire called a bonding wire is used for connection between the semiconductor chip and the lead, the wire diameter per one is about several tens to several hundreds μm. In order to reduce the on-resistance, it is necessary to use several tens to several hundreds of gold wires, aluminum wires, and the like, which increases the cost and complicates the assembly process.

そのため、特許文献４には、一例を図１５に断面図、図１６に斜視図で示すように、アルミニウムからなる板状の連結導体１５を用いて、半導体チップ１とリードフレーム３０を電気的に接続する方法が記載されている。ソース電極３５ｓに接続されたソースパッド３６とリードフレーム３０とを連結導体１５で電気的に接続される。ここで多結晶シリコン膜からなるゲート電極３３に接続されたゲートパッド３５ｇはボンディングワイヤ１６を介してリード端子に接続される。３４は層間絶縁膜、３６はソースパッドを構成するニッケル層、３７は半田層である。２０は樹脂パッケージである。なお半田層を用いることなく直接超音波接続することも可能である。   Therefore, in Patent Document 4, as shown in a cross-sectional view in FIG. 15 and a perspective view in FIG. 16, the semiconductor chip 1 and the lead frame 30 are electrically connected using a plate-like connecting conductor 15 made of aluminum. It describes how to connect. The source pad 36 connected to the source electrode 35 s and the lead frame 30 are electrically connected by the connecting conductor 15. Here, the gate pad 35 g connected to the gate electrode 33 made of the polycrystalline silicon film is connected to the lead terminal via the bonding wire 16. 34 is an interlayer insulating film, 36 is a nickel layer constituting a source pad, and 37 is a solder layer. Reference numeral 20 denotes a resin package. Direct ultrasonic connection is also possible without using a solder layer.

このように、銅（半田付け接続用）またはアルミニウム（超音波接続用）からなる板状の連結導体を用いることで、パッケージの占めるオン抵抗の低減が可能であり、１ミリΩ以下の抵抗を実現できる。さらには、放熱性の観点から見れば、金線やアルミニウム線に比べて熱伝導度が高くなるため、半導体チップからリードフレームへの放熱性が良くなり、より高い電流容量を実現できる。   Thus, by using a plate-like connecting conductor made of copper (for soldering connection) or aluminum (for ultrasonic connection), the on-resistance occupied by the package can be reduced, and a resistance of 1 milliohm or less is achieved. realizable. Furthermore, from the viewpoint of heat dissipation, the thermal conductivity is higher than that of a gold wire or aluminum wire. Therefore, heat dissipation from the semiconductor chip to the lead frame is improved, and a higher current capacity can be realized.

特開２００４−３１３８６号公報JP 2004-31386 A 特開２００５−１２０１９号公報Japanese Patent Laid-Open No. 2005-12019 特開２００９−１４１００７号公報JP 2009-141007 A 特開２００２−３１４０１８（第１６頁、図２）JP2002-314018 (page 16, FIG. 2)

特許文献１においては、橋渡し電極が多結晶シリコンである場合、多結晶シリコンのシート抵抗が大きいためゲート抵抗を下げるのに限界があった。
図１７にゲート抵抗のフィンガー長依存性を示す。図中縦軸はゲート抵抗、横軸はフィンガー長（μｍ）である。図中実線ａは橋渡し電極が多結晶シリコンの場合、実線ｂは橋渡し電極がアルミニウムの場合を示す。 In Patent Document 1, when the bridging electrode is polycrystalline silicon, there is a limit to lowering the gate resistance because the sheet resistance of polycrystalline silicon is large.
FIG. 17 shows the finger length dependency of the gate resistance. In the figure, the vertical axis represents the gate resistance, and the horizontal axis represents the finger length (μm). In the figure, a solid line a indicates a case where the bridging electrode is polycrystalline silicon, and a solid line b indicates a case where the bridging electrode is aluminum.

この図から明らかなように、橋渡し電極が多結晶シリコンの場合は、アルミニウムに比べシート抵抗が高く、橋渡し効果が少なくなりゲート抵抗が高くなっていることがわかる。このためゲート抵抗低減のためには、橋渡し電極としてはシート抵抗の低いアルミニウム層を用いるのが望ましいことがわかる。   As is apparent from this figure, when the bridging electrode is polycrystalline silicon, the sheet resistance is higher than that of aluminum, the bridging effect is reduced, and the gate resistance is increased. Therefore, it can be seen that it is desirable to use an aluminum layer having a low sheet resistance as the bridging electrode in order to reduce the gate resistance.

ただしアルミニウム層を橋渡し電極として用いた場合、図１８（ａ）及び（ｂ）に多結晶シリコン層及びアルミニウム層の平面図を示すように、アルミニウム層はソース電極３５ｓとしても使用しているため、ソース電極が分断されることになる。   However, when the aluminum layer is used as a bridging electrode, the aluminum layer is also used as the source electrode 35s, as shown in the plan views of the polycrystalline silicon layer and the aluminum layer in FIGS. 18 (a) and (b). The source electrode is divided.

このため、このソース電極が分断されたＭＯＳＦＥＴを組み立てるためには、この分断されたソース電極のすべてを接続する必要があるため、組み立ての制約を受けるという問題がある。   For this reason, in order to assemble a MOSFET in which the source electrode is divided, it is necessary to connect all of the divided source electrodes, and thus there is a problem that the assembly is restricted.

本発明は、前記実情に鑑みてなされたもので、トレンチゲートを有する半導体装置に関して、ソース抵抗の上昇を抑制しつつ、ゲートの配線抵抗の低減を図り、動作速度の高速化を目的とするものである。
また本発明は、外部接続用の電極が複数の領域に分かれている場合にも、短絡の恐れなく確実な接続を実現することの可能な連結導体すなわちクリップを提供することを目的とする。 The present invention has been made in view of the above circumstances, and aims to reduce the wiring resistance of the gate and increase the operation speed of a semiconductor device having a trench gate while suppressing an increase in source resistance. It is.
It is another object of the present invention to provide a connecting conductor, that is, a clip capable of realizing a reliable connection without fear of a short circuit even when an external connection electrode is divided into a plurality of regions.

上記目的を解決するために、本発明は、外部接続用のリードに接続される本体部と、前記本体部に連接され、複数の領域に分割され、それぞれが半導体基板の電極パッドに接続されるフィンガー部と、を備えた連結導体であって、外部接続用のリードと半導体基板とを接続する。   In order to solve the above-described object, the present invention provides a main body connected to a lead for external connection, and is connected to the main body, divided into a plurality of regions, each connected to an electrode pad of a semiconductor substrate. A connecting conductor having a finger portion for connecting a lead for external connection and the semiconductor substrate.

また本発明は、前記連結導体であって、前記フィンガー部の先端に接続され、前記フィンガー部の先端を一体化する連結部とを備えている。   Moreover, this invention is the said connection conductor, Comprising: It is connected to the front-end | tip of the said finger part, The connection part which integrates the front-end | tip of the said finger part is provided.

また本発明は、前記連結導体が、連続的に、縦方向に連結されたことを特徴とする。   Further, the present invention is characterized in that the connecting conductors are continuously connected in the vertical direction.

また本発明は、第１の主面と前記第１の主面に対向する第２の主面とを有する半導体基板と、前記半導体基板の前記第１の主面に形成された、第１及び第２の外部取り出し電極と、外部接続用のリードと、前記外部接続用のリードと前記半導体基板とを接続する連結導体と、前記外部接続用のリードの一部を残して封止される封止部とを備えた半導体装置であって、前記連結導体が、前記外部接続用のリードに接続される本体部と、前記本体部に連接され、複数の領域に分割され、それぞれが前記半導体基板の前記第１の外部取り出し電極に接続されるフィンガー部と、を備え、前記フィンガー部が前記第１の外部取り出し電極の形状に対応し、前記第２の外部取り出し電極上を避けて形成される。   According to another aspect of the present invention, there is provided a semiconductor substrate having a first main surface and a second main surface facing the first main surface, and a first and a second main surface formed on the first main surface of the semiconductor substrate. A second external extraction electrode; a lead for external connection; a connecting conductor for connecting the lead for external connection and the semiconductor substrate; and a seal that is sealed except for a part of the lead for external connection. A semiconductor device including a stop portion, wherein the connecting conductor is connected to the external connection lead, and is connected to the main body portion and divided into a plurality of regions, each of which is the semiconductor substrate A finger portion connected to the first external extraction electrode, the finger portion corresponding to the shape of the first external extraction electrode, and formed on the second external extraction electrode. .

また本発明は、前記半導体装置であって、前記フィンガー部の先端に接続され、前記フィンガー部の先端を一体化する連結部を備えたものを含む。   Moreover, this invention is the said semiconductor device, Comprising: The thing provided with the connection part connected to the front-end | tip of the said finger part and integrating the front-end | tip of the said finger part is included.

また本発明は、前記半導体装置であって、前記第１の外部取り出し電極が複数の領域を有するものを含む。   The present invention also includes the semiconductor device, wherein the first external extraction electrode has a plurality of regions.

また本発明は、前記半導体装置であって、前記第１の外部取り出し電極が前記第２の外部取り出し電極によって、複数の領域に分割されたものを含む。   Further, the present invention includes the semiconductor device, wherein the first external extraction electrode is divided into a plurality of regions by the second external extraction electrode.

また本発明は、前記半導体装置であって、前記半導体基板の前記第１の主面に形成された第１の半導体領域と、前記第１の主面に形成された複数のトレンチと、前記トレンチ内に充填された多結晶シリコン層からなるゲート電極と、前記トレンチに直交する方向に形成され、前記トレンチ間をつなぐ、多結晶シリコン層からなる橋渡し電極と、前記半導体基板の周縁に沿って形成され、前記ゲート電極及び前記橋渡し電極に接続される集電リング電極と、前記第１の主面に形成され、前記第１の半導体領域にコンタクトする第１の電極と、第１の金属層からなり、前記第１の電極に接続される第１の外部取り出し電極と、第２の金属層からなり、前記ゲート電極に接続される第２の外部取り出し電極とが、前記第１の主面上に並置された半導体装置であって、前記第１の外部取り出し電極は一体的に形成されており、前記橋渡し電極の表面の少なくとも一部が前記第２の金属層で構成されたものを含む。   The present invention is also the semiconductor device, wherein a first semiconductor region formed on the first main surface of the semiconductor substrate, a plurality of trenches formed on the first main surface, and the trench A gate electrode made of a polycrystalline silicon layer filled therein, a bridging electrode made of a polycrystalline silicon layer formed in a direction orthogonal to the trench and connecting the trenches, and formed along the periphery of the semiconductor substrate A current collecting ring electrode connected to the gate electrode and the bridging electrode, a first electrode formed on the first main surface and in contact with the first semiconductor region, and a first metal layer. A first external extraction electrode connected to the first electrode and a second external extraction electrode made of a second metal layer and connected to the gate electrode on the first main surface. Semiconductors juxtaposed to An apparatus, said first external lead electrodes are formed integrally, including those in which at least part of the surface of the bridging electrode is composed of the second metal layer.

また本発明は、前記半導体装置であって、前記トレンチはストライプ状に形成されており、前記橋渡し電極は前記ストライプ状の前記トレンチに対して直交するように設けられており、前記第１の外部取り出し電極は、括れ部を有し、前記括れ部に前記第２の外部取り出し電極が形成され、前記フィンガー部は前記第２の外部取り出し電極を避けて接続されたものを含む。   The present invention is also the semiconductor device, wherein the trench is formed in a stripe shape, and the bridging electrode is provided so as to be orthogonal to the stripe-shaped trench, The extraction electrode includes a constricted portion, the second external extraction electrode is formed on the constricted portion, and the finger portion includes a connection connected to avoid the second external extraction electrode.

以上のように、本発明の連結導体によれば、外部接続用のリードに接続される本体部と、前記本体部に連接され、複数の領域に分割され、それぞれが半導体基板の外部接続電極に接続されるフィンガー部と、を備えた連結導体で、外部接続用のリードと半導体基板とを接続するため、複数の外部接続電極が入り込んで存在したり、分割された状態で存在したりする場合にも、短絡のおそれなく、外部取り出し抵抗の低減をはかるとともに、信頼性の高い実装が可能となる。また、幅広の帯状導体を用いた場合にも可撓性が高いため、外部接続電極に対し良好な接続が可能となる。
また、本発明の半導体装置によれば、上記連結導体を用いているため、短絡のおそれなく、外部取り出し抵抗の低減をはかるとともに、信頼性の高い実装が可能となる。また、幅広の帯状導体を用いた場合にも可撓性が高いため、外部接続電極に対し良好な接続が可能となる。 As described above, according to the connection conductor of the present invention, the main body connected to the lead for external connection and the main body connected to the main body are divided into a plurality of regions, and each is connected to the external connection electrode of the semiconductor substrate. When connecting externally connected leads and a semiconductor substrate with a connecting conductor provided with a finger part to be connected, a plurality of external connection electrodes may exist in a divided state or in a divided state In addition, it is possible to reduce the external extraction resistance without causing a short circuit and to achieve a highly reliable mounting. In addition, when a wide strip conductor is used, the flexibility is high, so that a good connection to the external connection electrode is possible.
Further, according to the semiconductor device of the present invention, since the connecting conductor is used, the external extraction resistance can be reduced and the mounting can be performed with high reliability without fear of a short circuit. In addition, when a wide strip conductor is used, the flexibility is high, so that a good connection to the external connection electrode is possible.

本発明の実施の形態１に係る半導体装置を示す図、（ａ）は、半導体装置表面の多結晶シリコン層のレイアウトを示す図、（ｂ）は同半導体装置表面のアルミニウム層のレイアウトを示す図、（ｃ）は第１の金属層のみを示す図The figure which shows the semiconductor device which concerns on Embodiment 1 of this invention, (a) is a figure which shows the layout of the polycrystalline-silicon layer on the surface of a semiconductor device, (b) is the figure which shows the layout of the aluminum layer on the surface of the semiconductor device (C) is a figure which shows only a 1st metal layer. 図１（ｂ）のＡ−Ａ断面図A-A cross-sectional view of FIG. 本発明の実施の形態１の半導体装置の実装構造を示す図The figure which shows the mounting structure of the semiconductor device of Embodiment 1 of this invention 図３のＢ-Ｂ断面図BB sectional view of FIG. 本実施の形態１における連結導体を示す図、（ａ）は上面図、（ｂ）は断面図The figure which shows the connection conductor in this Embodiment 1, (a) is a top view, (b) is sectional drawing. 同連結導体の切断前の状態を示す図The figure which shows the state before cutting | disconnection of the connection conductor 本発明の実施の形態２に係る半導体装置を示す図、（ａ）は、半導体装置表面の多結晶シリコン層のレイアウトを示す図、（ｂ）は同半導体装置表面のアルミニウム層のレイアウトを示す図、（ｃ）は第１の金属層のみを示す図The figure which shows the semiconductor device which concerns on Embodiment 2 of this invention, (a) is a figure which shows the layout of the polycrystalline-silicon layer on the surface of a semiconductor device, (b) is the figure which shows the layout of the aluminum layer on the surface of the semiconductor device (C) is a figure which shows only a 1st metal layer. 本発明の実施の形態３に係る半導体装置を示す図、（ａ）は、半導体装置表面の多結晶シリコン層のレイアウトを示す図、（ｂ）は同半導体装置表面のアルミニウム層のレイアウトを示す図、（ｃ）は第１の金属層のみを示す図The figure which shows the semiconductor device which concerns on Embodiment 3 of this invention, (a) is a figure which shows the layout of the polycrystalline-silicon layer on the surface of a semiconductor device, (b) is the figure which shows the layout of the aluminum layer on the surface of the semiconductor device (C) is a figure which shows only a 1st metal layer. 本発明の実施の形態４に係る半導体装置を示す図、（ａ）は、半導体装置表面の多結晶シリコン層のレイアウトを示す図、（ｂ）は同半導体装置表面のアルミニウム層のレイアウトを示す図、（ｃ）は第１の金属層のみを示す図The figure which shows the semiconductor device which concerns on Embodiment 4 of this invention, (a) is a figure which shows the layout of the polycrystalline-silicon layer on the surface of a semiconductor device, (b) is the figure which shows the layout of the aluminum layer on the surface of the semiconductor device (C) is a figure which shows only a 1st metal layer. 本発明の実施の形態５に係る半導体装置の実装状態を示す図The figure which shows the mounting state of the semiconductor device which concerns on Embodiment 5 of this invention. 本発明の実施の形態５に係る半導体装置の連結導体を示す図、（ａ）は上面図、（ｂ）は断面図The figure which shows the connection conductor of the semiconductor device which concerns on Embodiment 5 of this invention, (a) is a top view, (b) is sectional drawing. 本発明の実施の形態５に係る半導体装置の断面図Sectional drawing of the semiconductor device which concerns on Embodiment 5 of this invention. 従来例の半導体装置を示す図The figure which shows the semiconductor device of a prior art example （ａ）および（ｂ）は従来例の半導体装置を示す図(A) And (b) is a figure which shows the semiconductor device of a prior art example 従来例の半導体装置を示す図The figure which shows the semiconductor device of a prior art example 従来例の半導体装置を示す図The figure which shows the semiconductor device of a prior art example 多結晶シリコンとアルミニウムとのフィンガー長とゲート抵抗との関係を示す特性図Characteristic diagram showing the relationship between the finger length and gate resistance of polycrystalline silicon and aluminum 従来例の半導体装置を示す図、（ａ）は、半導体装置表面の多結晶シリコン層のレイアウトを示す図、（ｂ）は同半導体装置表面のアルミニウム層のレイアウトを示す図The figure which shows the semiconductor device of a prior art example, (a) is a figure which shows the layout of the polycrystalline-silicon layer on the surface of a semiconductor device, (b) is the figure which shows the layout of the aluminum layer on the surface of the semiconductor device

以下本発明の実施の形態について、図面を参照しながら説明する。
（実施の形態１）
図１（ａ）は、本発明の実施の形態１における半導体装置表面の多結晶シリコン層のレイアウトを示す図、図１（ｂ）は同半導体装置表面の第１および第２の金属層であるアルミニウム層のレイアウトを示す図である。図１（ｃ）は第２の金属層のみを示す図である。図２は図１（ｂ）のＡ−Ａ断面図である。図３は、この半導体装置の実装構造を示す図である。図４は図３のＢ−Ｂ断面図である。図５は本実施の形態１における連結導体を示す図、図６は同連結導体の切断前の状態を示す図である。 Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1A is a diagram showing a layout of a polycrystalline silicon layer on the surface of a semiconductor device in Embodiment 1 of the present invention, and FIG. 1B is a first metal layer and a second metal layer on the surface of the semiconductor device. It is a figure which shows the layout of an aluminum layer. FIG. 1C shows only the second metal layer. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a diagram showing a mounting structure of the semiconductor device. 4 is a cross-sectional view taken along line BB in FIG. FIG. 5 is a view showing the connecting conductor in the first embodiment, and FIG. 6 is a view showing a state before the connecting conductor is cut.

この半導体装置は、ストライプ状のトレンチＴに対して直交するように橋渡し電極３３Ｂが設けられたトレンチＭＯＳＦＥＴを構成するものであり、第１の外部取り出し電極を構成するソースパッド３６は一体的に形成されており、ソース電極３５ｓは、括れ部ｋを有し、括れ部ｋに第２の外部取り出し電極としてのゲートパッド３５ｇが伸張して形成され、この橋渡し電極の表面の少なくとも一部がソース電極３５ｓと同一の金属層であるアルミニウム層で構成されたことを特徴とする。つまり橋渡し電極３３Ｂの表面にアルミニウム層からなるゲートパッド３５ｇの伸張部であるゲート集電電極３５Ｔが積層されている。そしてトレンチのすべてが、このトレンチＭＯＳＦＥＴチップの端部を除く中間部の少なくとも一点でゲートパッド３５ｇを構成する第２の外部取り出し電極と交差しており、ゲート電極３３ｇのうち第２の外部取出し電極すなわち第２の金属層から露呈する領域の長さＦｃがフィンガー長Ｆ０の２倍を超えないようになっており、ゲート集電電極３５Ｔあるいはゲートパッド３５ｇとの距離を低減し、ゲート抵抗の低減をはかるものである。ここでフィンガー長とは橋渡し電極３３Ｂ間のゲート電極長をいうものとする。又ソースパッド３５ｓはほぼ対称となるように形成されている。本実施の形態では、ゲート集電電極３５Ｔ間のフィンガー長Ｆｃ、すなわち、多結晶シリコン層単層の橋渡し電極３３Ｂの最大長さＦｃｍａｘは１．３７ｍｍとなっている。ここでゲート電極３３ｇ間のフィンガー長は０．４５ｍｍである。 This semiconductor device constitutes a trench MOSFET provided with a bridging electrode 33B so as to be orthogonal to the stripe-shaped trench T, and a source pad 36 constituting a first external extraction electrode is formed integrally. The source electrode 35s has a constricted portion k, and a gate pad 35g as a second external extraction electrode is formed on the constricted portion k so as to extend. At least a part of the surface of the bridging electrode is a source electrode. It is characterized by comprising an aluminum layer which is the same metal layer as 35s. That is, the gate current collecting electrode 35T, which is an extended portion of the gate pad 35g made of an aluminum layer, is laminated on the surface of the bridging electrode 33B. All of the trenches intersect with the second external extraction electrode constituting the gate pad 35g at at least one point of the intermediate portion excluding the end of the trench MOSFET chip, and the second external extraction electrode of the gate electrode 33g. That is, the length F c of the region exposed from the second metal layer does not exceed twice the finger length F 0 , the distance from the gate current collecting electrode 35T or the gate pad 35g is reduced, and the gate resistance It is intended to reduce this. Here, the finger length refers to the gate electrode length between the bridging electrodes 33B. The source pad 35s is formed to be almost symmetrical. In the present embodiment, the finger length F c between the gate collector electrodes 35T, that is, the maximum length F cmax of the bridging electrode 33B of the single polycrystalline silicon layer is 1.37 mm. Here, the finger length between the gate electrodes 33g is 0.45 mm.

すなわちこの半導体装置は、この半導体基板の第１の主面Ｓ１に形成された複数のトレンチＴと、このトレンチＴ内に充填された多結晶シリコン層からなるゲート電極３３と、このトレンチＴ間をつなぐようにトレンチＴに直交する方向に形成され、トレンチ間をつなぐ多結晶シリコン層からなる橋渡し電極３３Ｂと、半導体基板の周縁に沿って形成され、ゲート電極３３及び橋渡し電極３３Ｂに接続される集電リング電極ｇｌ（多結晶シリコン層からなる下地層３３ｇｌとアルミウム層からなる集電層３５ｇｌ）と、この第１の主面Ｓ１に形成され、第１の半導体領域としてのソース領域３２ｓにコンタクトする第１の電極としてのアルミニウム製のソース電極３５ｓとを具備している。また、第１の電極としてのソース電極３５ｓに接続されるソースパッド３６と、第２の外部取り出し電極としてのゲートパッドとが、第１の主面Ｓ１上に並置されている。そして橋渡し電極３３Ｂの少なくとも一部が第２の金属層で構成され、トレンチＴのすべてが、少なくとも一点で第２の金属層と交差し導通するように構成されている。ここでは第１の金属層および第２の金属層は同一の金属層で構成されており、ここではアルミニウム層である。   That is, the semiconductor device includes a plurality of trenches T formed in the first main surface S1 of the semiconductor substrate, a gate electrode 33 made of a polycrystalline silicon layer filled in the trench T, and the trench T. A bridging electrode 33B formed of a polycrystalline silicon layer that is formed in a direction orthogonal to the trench T and is connected between the trenches, and a collector electrode that is formed along the periphery of the semiconductor substrate and is connected to the gate electrode 33 and the bridging electrode 33B. An electric ring electrode gl (a base layer 33gl made of a polycrystalline silicon layer and a current collecting layer 35gl made of an aluminum layer) and a first main surface S1 are formed and contacted with a source region 32s as a first semiconductor region. And an aluminum source electrode 35s as a first electrode. Further, a source pad 36 connected to the source electrode 35s as the first electrode and a gate pad as the second external extraction electrode are juxtaposed on the first main surface S1. At least a part of the bridging electrode 33B is composed of the second metal layer, and all of the trenches T are configured to cross and conduct with the second metal layer at least at one point. Here, the first metal layer and the second metal layer are composed of the same metal layer, which is an aluminum layer here.

次にこの半導体装置の実装構造について説明する。この半導体装置においては、図４に実装状態を示すように、このトレンチＭＯＳＦＥＴは、リードフレーム３０のリード端子３０Ｒの一端に連結導体１５を介して電気的に接続されている。図５（ａ）にこの連結導体の上面図、図５（ｂ）に断面図を示す。この連結導体は、銅（Ｃｕ箔）からなる板状体で構成され、本体部１５Ｍと、リード端子Ｒに当接し、リード端子３０Ｒに接続されるリード接続部１５Ｒと、トレンチＭＯＳＦＥＴ（チップ）のソースパッドに当接するフィンガー部１５Ｆと、フィンガー部１５Ｆの先端を空間部で一体化する連結部１５Ｂとで構成されている。
このトレンチＭＯＳＦＥＴは、リードフレーム３０の島状電極である半導体素子搭載部３０ｓの上に形成されている。そして、連結導体１５のフィンガー部１５Ｆがソースパッド３６に融着され、リード接続部１５Ｒがリードフレーム３０のリード端子３０Ｒの一端に電気的に接続されている。ゲートパッド３５ｇは、ボンディングワイヤ１６によってリード端子３０Ｐに接続されている。なお、トレンチＭＯＳＦＥＴと半導体素子搭載部３０ｓは、半田層を介して電気的に接続されている。そしてエポキシ樹脂からなる封止樹脂で封止されパッケージ２０を構成している。なお封止樹脂は本来不透明であるため、実際には内部は見えていないが、この例では、説明のために内部が見えるようにしている。 Next, the mounting structure of the semiconductor device will be described. In this semiconductor device, as shown in FIG. 4, the trench MOSFET is electrically connected to one end of a lead terminal 30 </ b> R of the lead frame 30 via a connecting conductor 15. FIG. 5A shows a top view of the connecting conductor, and FIG. 5B shows a cross-sectional view. This connecting conductor is composed of a plate-like body made of copper (Cu foil), and is connected to the main body portion 15M, the lead connection portion 15R in contact with the lead terminal R and connected to the lead terminal 30R, and the trench MOSFET (chip). It is comprised by the finger part 15F which contact | abuts a source pad, and the connection part 15B which integrates the front-end | tip of the finger part 15F in a space part.
The trench MOSFET is formed on a semiconductor element mounting portion 30 s that is an island-shaped electrode of the lead frame 30. The finger portion 15F of the connecting conductor 15 is fused to the source pad 36, and the lead connection portion 15R is electrically connected to one end of the lead terminal 30R of the lead frame 30. The gate pad 35g is connected to the lead terminal 30P by the bonding wire 16. The trench MOSFET and the semiconductor element mounting portion 30s are electrically connected via a solder layer. The package 20 is then sealed with a sealing resin made of an epoxy resin. Since the sealing resin is originally opaque, the inside is not actually seen, but in this example, the inside is made visible for explanation.

図６は装着前の連結導体を示す図であり、多数の連結導体が長手方向に帯状に連結されている。この連結導体の製造に際しては、銅板などの板状体を打ち抜き加工することにより形成した後、リードおよび半導体基板の接続部に融着し、折り曲げ加工を行い、切断する。このように連結導体材料は、連続形態で形成されているため、実装に際しても作業性が良好で信頼性の高いものとなっている。この連結部１５Ｂが存在することで、連続的に位置ずれのない連結導体を形成することが可能となる。   FIG. 6 is a view showing a connecting conductor before mounting, and a large number of connecting conductors are connected in a strip shape in the longitudinal direction. In manufacturing the connection conductor, a plate-like body such as a copper plate is formed by punching, and then fused to the connection portion between the lead and the semiconductor substrate, and then bent and cut. As described above, since the connecting conductor material is formed in a continuous form, it has good workability and high reliability in mounting. Due to the presence of the connecting portion 15B, it is possible to form a connecting conductor that is not continuously displaced.

ここでソース電極３５ｓはアルミニウムで構成されているため、リード端子３０Ｒと超音波接続によって電気的に接続することができる。この連結導体１５は、高い伝導率と熱伝導性の機能と、電気的な接続を簡便にする機能の２つの機能を有す。したがって、このトレンチＭＯＳＦＥＴが動作する時のパッケージの占めるオン抵抗を低減でき、また、トレンチＭＯＳＦＥＴで発生する熱を効率良く外部に放出することが出来る。また、連結導体を銅に代えてアルミニウムとすることにより、連結導体１５でソースパッド３５ｓとリード接続部１５Ｒとを電気的に接続する際、超音波接合により容易に接合可能であるため、半田接合を用いる場合に比べて、工法を簡素化することができる。   Here, since the source electrode 35s is made of aluminum, it can be electrically connected to the lead terminal 30R by ultrasonic connection. The connecting conductor 15 has two functions, that is, a function of high conductivity and thermal conductivity and a function of simplifying electrical connection. Therefore, the on-resistance occupied by the package when the trench MOSFET operates can be reduced, and the heat generated in the trench MOSFET can be efficiently discharged to the outside. In addition, when the connecting conductor 15 is made of aluminum instead of copper, when the source pad 35s and the lead connecting portion 15R are electrically connected by the connecting conductor 15, it can be easily joined by ultrasonic joining. The construction method can be simplified as compared with the case of using.

このトレンチＭＯＳＦＥＴは、ゲート幅が５ｍであるとき、ゲート抵抗は２．０Ω、オン抵抗は３．７ｍΩであった。このように本実施の形態のトレンチＭＯＳＦＥＴによれば、オン抵抗を低く維持しつつゲート抵抗の低減を図ることができる。
ここでソース配線抵抗は０．３ｍΩ、デバイス抵抗は３ｍΩ、クリップ抵抗は０．４ｍΩであった。 The trench MOSFET had a gate resistance of 2.0Ω and an on-resistance of 3.7 mΩ when the gate width was 5 m. As described above, according to the trench MOSFET of the present embodiment, the gate resistance can be reduced while the on-resistance is kept low.
Here, the source wiring resistance was 0.3 mΩ, the device resistance was 3 mΩ, and the clip resistance was 0.4 mΩ.

本実施の形態によれば、ソースパッド（ソース電極）を構成する第１の外部取り出し電極と、ゲート電極に接続される第２の外部取り出し電極とが、第１の主面Ｓ１上に並置された半導体装置であって、第１の外部取り出し電極であるソースパッドは一体的に形成されており、橋渡し電極の表面の少なくとも一部が第２の金属層で構成されているため、ゲート集電電極によりフィンガー長が、どの部分でも従来例に比べて、短くなっており、ゲート抵抗の低減を図ることができる。従って高速化を図ることが可能となる。
また、ソースパッドは、括れ部を有し、この括れ部に第２の外部取り出し電極であるゲート集電電極が形成されているため、最大限にゲート取出し抵抗を低減することができる。 According to the present embodiment, the first external extraction electrode constituting the source pad (source electrode) and the second external extraction electrode connected to the gate electrode are juxtaposed on the first main surface S1. Since the source pad as the first external extraction electrode is integrally formed and at least a part of the surface of the bridging electrode is composed of the second metal layer, the gate current collector The finger length of any part is shorter than that of the conventional example due to the electrodes, and the gate resistance can be reduced. Therefore, it is possible to increase the speed.
Further, since the source pad has a constricted portion, and the gate current collecting electrode as the second external extraction electrode is formed in the constricted portion, the gate extraction resistance can be reduced to the maximum.

さらにまた、ここでリードと半導体チップとの接続に用いられる連結導体は、外部接続用のリードに接続される本体部１５Ｍと、本体部１５Ｍに連接され、複数の領域に分割され、それぞれが半導体基板の電極パッドに接続されるフィンガー部１５Ｆと、フィンガー部１５Ｆの先端に接続され、フィンガー部１５Ｆの先端を一体化する連結部１５Ｂとを備えているため、ソースパッドが複数の領域に分割されていたり、あるいは変形領域をなしていたりする場合にも、良好に電気的および物理的接触を達成することが可能となる。   Furthermore, the connecting conductor used for connecting the lead and the semiconductor chip here is connected to the main body 15M connected to the lead for external connection and the main body 15M, and is divided into a plurality of regions, each of which is a semiconductor. Since the finger portion 15F connected to the electrode pad of the substrate and the connecting portion 15B connected to the tip of the finger portion 15F and integrating the tip of the finger portion 15F are provided, the source pad is divided into a plurality of regions. It is possible to satisfactorily achieve electrical and physical contact even in the case where the contact point is formed or a deformation region is formed.

また本発明は、連結導体を、連続的に、縦方向に連結した条材として用いるようにすれば、実装作業性が容易となる。   Further, according to the present invention, if the connecting conductor is continuously used as the strip material connected in the vertical direction, the mounting workability becomes easy.

なお前記実施の形態では、連結導体は銅箔で構成したが、銅箔に限定されるものではない。例えば、この連結導体は、２層構造で構成され厚さ０．１ｍｍ程度の銅板に、厚さ０．０５ｍｍ程度のアルミニウム箔を接合し、所望の形状に切断して形成される。アルミニウムは超音波接合が容易であり、加工性も良好である。銅は導電性が高く、機械的強度も高いという特徴を有する。   In the above embodiment, the connecting conductor is made of copper foil, but is not limited to copper foil. For example, this connecting conductor is formed by joining an aluminum foil having a thickness of about 0.05 mm to a copper plate having a two-layer structure and having a thickness of about 0.1 mm, and cutting it into a desired shape. Aluminum is easy to ultrasonically bond and has good workability. Copper is characterized by high electrical conductivity and high mechanical strength.

また、この連結導体としては、第１の導体としての銅板に、スパッタリングやＣＶＤ法などを用いた薄膜形成によって第２の導体としてのアルミニウム薄膜を形成してもよいしまた、めっき法を用いてもよい。   As the connecting conductor, an aluminum thin film as the second conductor may be formed on the copper plate as the first conductor by forming a thin film using sputtering, CVD, or the like, or by using a plating method. Also good.

以上、本発明の実施の形態１に係る半導体装置について説明したが、本発明は、この実施の形態に限定されるものではない。   Although the semiconductor device according to the first embodiment of the present invention has been described above, the present invention is not limited to this embodiment.

例えば、前記実施の形態１において、第１および第２の金属層としてはアルミニウム層を用いたが、アルミニウムを主成分とする金属、銀、金、ニッケル、チタンなどの金属を用いてもよい。第１および第２の金属層としては、融点が低く超音波接合が容易であるものが望ましいが、リード端子３０Ｒあるいはソース電極３５ｓとの密着性の良好な材料であれば、必ずしも同一材料でなくてもよい。また、必要に応じて半田を介在させるようにしてもよい。   For example, although the aluminum layers are used as the first and second metal layers in the first embodiment, metals such as silver, gold, nickel, and titanium may be used. As the first and second metal layers, those having a low melting point and easy ultrasonic bonding are preferable. However, the first and second metal layers are not necessarily the same material as long as the materials have good adhesion to the lead terminal 30R or the source electrode 35s. May be. Moreover, you may make it interpose a solder as needed.

また前記実施の形態では、連結導体は直線状で段差をなすように折り曲げて構成したが、湾曲形状をなすように構成してもよい。例えば半導体素子搭載部３０ｓがリード端子３０Ｒの端面よりも低い位置に配置され、接続すべき素子電極とリードフレームのリードの高さが同一である場合には、接続導体は湾曲面を構成せず、平坦面であってもよい。   Moreover, in the said embodiment, although the connection conductor was bent and comprised so that a level | step difference might be made, you may comprise so that a curved shape may be made. For example, when the semiconductor element mounting portion 30s is disposed at a position lower than the end face of the lead terminal 30R and the element electrode to be connected and the lead frame have the same lead height, the connecting conductor does not form a curved surface. It may be a flat surface.

（実施の形態２）
図７（ａ）は、本発明の実施の形態２における半導体装置表面の多結晶シリコン層のレイアウトを示す図、図７（ｂ）は同半導体装置表面の第１および第２の金属層であるアルミニウム層のレイアウトを示す図である。図７（ｃ）は第２の金属層のみを示す図である。 (Embodiment 2)
FIG. 7A shows a layout of the polycrystalline silicon layer on the surface of the semiconductor device according to the second embodiment of the present invention, and FIG. 7B shows the first and second metal layers on the surface of the semiconductor device. It is a figure which shows the layout of an aluminum layer. FIG. 7C shows only the second metal layer.

この半導体装置は、図７（ｃ）に示すように、ゲート集電電極３５Ｔの先端がこの半導体装置の端部を除く中間部で、トレンチＴと平行な成分を有し、中継点を構成するように構成される。
すなわち、第２の外部取り出し電極であるゲート集電電極３５Ｔは、トレンチに平行に形成された平行成分と、前記平行成分の先端で前記平行成分に直交する垂直成分とを備え、Ｔ字状電極を構成する。またこの半導体装置は、前記実施の形態１と同様、ストライプ状のトレンチＴに対して直交するように橋渡し電極３３Ｂが設けられたトレンチＭＯＳＦＥＴを構成するものであり、第１の外部取り出し電極を構成するソースパッド３６は一体的に形成されており、ソース電極３５ｓは、括れ部ｋを有し括れ部ｋに第２の外部取り出し電極としてのゲートパッド３５ｇが伸張して形成され、この橋渡し電極の表面の少なくとも一部がソース電極３５ｓと同一の金属層であるアルミニウム層で構成される。
図７（ｃ）からも明らかなように、本実施の形態によればゲート集電電極３５Ｔが、ゲートパッドを除いて、チップの上下左右対称に形成されており、ゲート集電電極間のフィンガー長Ｆc、すなわち、多結晶シリコン層単層の橋渡し電極３３Ｂの最大長さＦcmaxは１．８３ｍｍとなっている。ここでもゲート電極３３ｇ間のフィンガー長Ｆ０は０．４５ｍｍである。 In this semiconductor device, as shown in FIG. 7C, the tip of the gate current collecting electrode 35T is an intermediate portion excluding the end portion of the semiconductor device, and has a component parallel to the trench T to form a relay point. Configured as follows.
That is, the gate collecting electrode 35T, which is the second external extraction electrode, includes a parallel component formed in parallel to the trench and a vertical component orthogonal to the parallel component at the tip of the parallel component. Configure. Further, as in the first embodiment, this semiconductor device constitutes a trench MOSFET provided with a bridging electrode 33B so as to be orthogonal to the stripe-shaped trench T, and constitutes a first external extraction electrode. The source pad 36 is integrally formed, and the source electrode 35s is formed by extending a gate pad 35g as a second external extraction electrode at the constricted portion k and having the constricted portion k. At least a part of the surface is composed of an aluminum layer that is the same metal layer as the source electrode 35s.
As is clear from FIG. 7C, according to the present embodiment, the gate current collecting electrode 35T is formed symmetrically in the vertical and horizontal directions of the chip except for the gate pad. The length F c , that is, the maximum length F cmax of the bridging electrode 33B of the single polycrystalline silicon layer is 1.83 mm. Here, the finger length F 0 between the gate electrodes 33g is 0.45 mm.

このトレンチＭＯＳＦＥＴは、ゲート幅が５ｍであるとき、ゲート抵抗は１．５Ω、オン抵抗は３．５ｍΩであった。このように本実施の形態のトレンチＭＯＳＦＥＴによれば、オン抵抗を低く維持しつつゲート抵抗の低減を図ることができる。
ここでソース配線抵抗は０．１ｍΩ、デバイス抵抗は３ｍΩ、連結導体の抵抗は０．４ｍΩであった。
他の構成については前記実施の形態と同様であるため、ここでは説明を省略する。
実装に際しても、前記実施の形態１と同様である。
上記構成によれば、取り出し抵抗の低減を図ることができ、高速で信頼性の高い半導体装置を提供することが可能となる。 The trench MOSFET had a gate resistance of 1.5Ω and an on-resistance of 3.5 mΩ when the gate width was 5 m. As described above, according to the trench MOSFET of the present embodiment, the gate resistance can be reduced while the on-resistance is kept low.
Here, the source wiring resistance was 0.1 mΩ, the device resistance was 3 mΩ, and the connection conductor resistance was 0.4 mΩ.
Since other configurations are the same as those of the above-described embodiment, description thereof is omitted here.
The mounting is the same as in the first embodiment.
According to the above configuration, it is possible to reduce the extraction resistance, and it is possible to provide a high-speed and highly reliable semiconductor device.

（実施の形態３）
図８（ａ）は、本発明の実施の形態３における半導体装置表面の多結晶シリコン層のレイアウトを示す図、図８（ｂ）は同半導体装置表面の第１および第２の金属層であるアルミニウム層のレイアウトを示す図である。図８（ｃ）は第２の金属層のみを示す図である。 (Embodiment 3)
FIG. 8A shows a layout of the polycrystalline silicon layer on the surface of the semiconductor device according to the third embodiment of the present invention, and FIG. 8B shows the first and second metal layers on the surface of the semiconductor device. It is a figure which shows the layout of an aluminum layer. FIG. 8C shows only the second metal layer.

この半導体装置は、図８（ｃ）に示すように、ゲート集電電極３５Ｔは基本的に前記実施の形態１と同様、トレンチのすべてが、前記半導体装置の端部を除く中間部の少なくとも一点でゲート集電電極と交差し導通するように構成されており、かつ前記実施の形態２と同様、前記ゲート集電電極３５Ｔの先端がこの半導体装置の端部を除く中間部で、トレンチと平行な成分を有し、中継点を構成するように構成される。
すなわち、第２の外部取り出し電極は、前記トレンチに平行に形成された平行成分と、前記平行成分の先端で前記平行成分に直交する垂直成分とを備え、Ｔ字状電極を構成する。ここでもソースパッドが括れ部ｋを有し、この括れ部ｋにゲート集電電極が伸張するように構成される。他部については前記実施の形態１および２と同様でありここでは説明を省略する。
このようにして、本実施の形態によればゲート集電電極３５Ｔが、ほぼ点対称に形成されており、ゲート集電電極間のフィンガー長Ｆc、すなわち、多結晶シリコン層単層の橋渡し電極３３Ｂの最大長さＦcmaxは１．３７ｍｍとなっている。ここでもゲート電極３３ｇ間のフィンガー長Ｆ０は０．４５ｍｍである。 In this semiconductor device, as shown in FIG. 8C, the gate current collecting electrode 35T is basically the same as in the first embodiment, in which all of the trenches are at least one point in the intermediate portion excluding the end portion of the semiconductor device. In the same manner as in the second embodiment, the tip of the gate current collecting electrode 35T is an intermediate portion excluding the end portion of the semiconductor device and parallel to the trench. It has such a component and is configured to constitute a relay point.
That is, the second external extraction electrode includes a parallel component formed in parallel with the trench and a vertical component orthogonal to the parallel component at the tip of the parallel component, and constitutes a T-shaped electrode. Here again, the source pad has a constricted portion k, and the gate current collecting electrode extends in the constricted portion k. Other parts are the same as those in the first and second embodiments, and the description thereof is omitted here.
In this way, according to the present embodiment, the gate current collecting electrode 35T is formed to be substantially point-symmetric, and the finger length F c between the gate current collecting electrodes, that is, the bridging electrode of a single polycrystalline silicon layer The maximum length F cmax of 33B is 1.37 mm. Here, the finger length F 0 between the gate electrodes 33g is 0.45 mm.

このトレンチＭＯＳＦＥＴは、ゲート幅が５ｍであるとき、ゲート抵抗は１．２Ω、オン抵抗は３．６ｍΩであった。このように本実施の形態のトレンチＭＯＳＦＥＴによれば、オン抵抗を低く維持しつつゲート抵抗の低減を図ることができる。
ここでソース配線抵抗は０．２ｍΩ、デバイス抵抗は３ｍΩ、連結導体の抵抗は０．４ｍΩであった。
他の構成については前記実施の形態と同様であるため、ここでは説明を省略する。
実装に際しても、前記実施の形態１と同様である。
このようにゲート集電電極として、中継点を形成することで、ソース抵抗の増大を抑制しつつ、より集電性を高めゲート取出し抵抗を低減することが可能となる。 The trench MOSFET had a gate resistance of 1.2Ω and an on-resistance of 3.6 mΩ when the gate width was 5 m. As described above, according to the trench MOSFET of the present embodiment, the gate resistance can be reduced while the on-resistance is kept low.
Here, the source wiring resistance was 0.2 mΩ, the device resistance was 3 mΩ, and the connection conductor resistance was 0.4 mΩ.
Since other configurations are the same as those of the above-described embodiment, description thereof is omitted here.
The mounting is the same as in the first embodiment.
Thus, by forming a relay point as the gate current collecting electrode, it is possible to further increase the current collecting performance and reduce the gate extraction resistance while suppressing an increase in the source resistance.

（実施の形態４）
図９（ａ）は、本発明の実施の形態４における半導体装置表面の多結晶シリコン層のレイアウトを示す図、図９（ｂ）は同半導体装置表面の第１および第２の金属層であるアルミニウム層のレイアウトを示す図である。図９（ｃ）は第２の金属層のみを示す図である。 (Embodiment 4)
FIG. 9A shows a layout of the polycrystalline silicon layer on the surface of the semiconductor device according to the fourth embodiment of the present invention, and FIG. 9B shows the first and second metal layers on the surface of the semiconductor device. It is a figure which shows the layout of an aluminum layer. FIG. 9C shows only the second metal layer.

この半導体装置は、図９（ｃ）に示すように、ゲート集電電極３５Ｔはゲート電極３３ｇと直交する成分のみであり、ソース電極３５ｓの括れ部ｋを極力小さく抑えたものである。
すなわち、第２の外部取り出し電極は、前記トレンチに平行に形成された平行成分と、前記平行成分の先端で前記平行成分に直交する垂直成分とを備え、Ｔ字状電極を構成する。ここでもソースパッドが括れ部ｋを有し、この括れ部ｋにゲート集電電極３５Ｔが伸張するように構成される。
このようにして、本実施の形態によればゲート集電電極３５Ｔが、ゲートパッドを除いてほぼ上下左右対称に形成されており、ゲート集電電極間のフィンガー長Ｆc、すなわち、多結晶シリコン層単層の橋渡し電極３３Ｂの最大長さＦcmaxは１．８３ｍｍとなっている。ここでもゲート電極３３ｇ間のフィンガー長Ｆoは０．４５ｍｍである。 In this semiconductor device, as shown in FIG. 9C, the gate current collecting electrode 35T has only a component orthogonal to the gate electrode 33g, and the constricted portion k of the source electrode 35s is suppressed as much as possible.
That is, the second external extraction electrode includes a parallel component formed in parallel with the trench and a vertical component orthogonal to the parallel component at the tip of the parallel component, and constitutes a T-shaped electrode. Again, the source pad has a constricted portion k, and the gate collecting electrode 35T is configured to extend to the constricted portion k.
In this manner, according to the present embodiment, the gate current collecting electrode 35T is formed substantially vertically and horizontally symmetrical except for the gate pad, and the finger length F c between the gate current collecting electrodes, that is, polycrystalline silicon. The maximum length F cmax of the single-layer bridging electrode 33B is 1.83 mm. Again, the finger length F o between the gate electrodes 33g is 0.45 mm.

このトレンチＭＯＳＦＥＴは、ゲート幅が５ｍであるとき、ゲート抵抗は３．５Ω、オン抵抗は３．５ｍΩであった。このように本実施の形態のトレンチＭＯＳＦＥＴによれば、オン抵抗を低く維持しつつ、若干ではあるがゲート抵抗の低減を図ることができる。ここでソース配線抵抗は０．１ｍΩ、デバイス抵抗は３ｍΩ、連結導体の抵抗は０．４ｍΩであった。
他の構成については前記実施の形態と同様であるため、ここでは説明を省略する。
実装に際しても、前記実施の形態１と同様である。
このように上記構成によれば、ゲート集電電極として、フィンガーに平行な成分と垂直な成分とを有するＴ字状の中継点を形成することで、ソース抵抗の増大を抑制しつつ、より集電性を高めゲート取出し抵抗を低減することが可能となる。 The trench MOSFET had a gate resistance of 3.5Ω and an on-resistance of 3.5 mΩ when the gate width was 5 m. As described above, according to the trench MOSFET of the present embodiment, the gate resistance can be slightly reduced while maintaining the on-resistance low. Here, the source wiring resistance was 0.1 mΩ, the device resistance was 3 mΩ, and the connection conductor resistance was 0.4 mΩ.
Since other configurations are the same as those of the above-described embodiment, description thereof is omitted here.
The mounting is the same as in the first embodiment.
As described above, according to the above configuration, the gate collecting electrode is formed with a T-shaped relay point having a component parallel to the finger and a component perpendicular to the finger, thereby suppressing an increase in source resistance and further collecting current. It is possible to increase the electrical property and reduce the gate extraction resistance.

(実施の形態５)
次にこの半導体装置の実装構造の変形例について説明する。この半導体装置においては、図１０に実装状態を示すように、このトレンチＭＯＳＦＥＴは、リードフレーム３０のリード端子３０Ｒの一端に連結導体１５を介して電気的に接続されている。図１１（ａ）にこの連結導体の上面図、図１１（ｂ）に断面図を示す。図１２は連結導体１５を含む半導体チップの断面を示す図である。この連結導体は、図５（ａ）および（ｂ）と図６とに示した、前記実施の形態１の連結導体に比べ、フィンガー部１５Ｆの先端を空間部で一体化する連結部１５Ｂが無く、フィンガー部１５Ｆの先端が自由状態となっている点で実施の形態１と異なるのみであり、他については適宜変形可能である。すなわち、この連結導体は銅（Ｃｕ箔）からなる板状体で構成され、本体部１５Ｍと、リード端子３０Ｒに当接し、リード端子３０Ｒに接続されるリード接続部１５Ｒと、トレンチＭＯＳＦＥＴ（チップ）のソースパッドに当接するフィンガー部１５Ｆとで構成されている。
このトレンチＭＯＳＦＥＴは、リードフレーム３０の島状電極である半導体素子搭載部３０ｓの上に形成されている。そして、連結導体１５のフィンガー部１５Ｆがソースパッド３６に融着され、リード接続部１５Ｒがリードフレーム３０のリード端子３０Ｒの一端に電気的に接続されている。ゲートパッド３５ｇは、ボンディングワイヤ１６によってリード端子３０Ｐに接続されている。なお、トレンチＭＯＳＦＥＴと半導体素子搭載部３０ｓは、半田層を介して電気的に接続されている。そしてエポキシ樹脂からなる封止樹脂で封止されパッケージ２０を構成している。なお封止樹脂は本来不透明であるため、実際には内部は見えていないが、この例においても、説明のために内部が見えるようにしている。 (Embodiment 5)
Next, a modified example of the mounting structure of the semiconductor device will be described. In this semiconductor device, as shown in FIG. 10, the trench MOSFET is electrically connected to one end of a lead terminal 30 </ b> R of the lead frame 30 via a connecting conductor 15. FIG. 11A shows a top view of the connecting conductor, and FIG. 11B shows a cross-sectional view. FIG. 12 is a view showing a cross section of the semiconductor chip including the connecting conductor 15. Compared with the connection conductor of the first embodiment shown in FIGS. 5 (a) and 5 (b) and FIG. 6, this connection conductor has no connection portion 15B that integrates the tips of the finger portions 15F in the space portion. The finger part 15F is different from the first embodiment only in that the tip of the finger part 15F is in a free state, and the other parts can be appropriately modified. That is, the connecting conductor is formed of a plate-shaped body made of copper (Cu foil), and is in contact with the main body portion 15M, the lead terminal 30R and connected to the lead terminal 30R, and a trench MOSFET (chip). The finger portion 15F is in contact with the source pad.
The trench MOSFET is formed on a semiconductor element mounting portion 30 s that is an island-shaped electrode of the lead frame 30. The finger portion 15F of the connecting conductor 15 is fused to the source pad 36, and the lead connection portion 15R is electrically connected to one end of the lead terminal 30R of the lead frame 30. The gate pad 35g is connected to the lead terminal 30P by the bonding wire 16. The trench MOSFET and the semiconductor element mounting portion 30s are electrically connected via a solder layer. The package 20 is then sealed with a sealing resin made of an epoxy resin. Since the sealing resin is inherently opaque, the inside is not actually seen, but in this example, the inside is made visible for explanation.

この構成によれば、連結導体の剛性が低いため、接合工程において若干作業性が低下するが、本実施の形態においても前記実施の形態１と同様の効果を奏功する。本実施の形態においても、例えば、ソース電極３５ｓはアルミニウムで構成されているため、リード端子３０Ｒと半田接続によって電気的に接続することができる。ここでは、ソース電極３５ｓは、ニッケル層からなるソースパッド３６を介して連結導体１５に半田接続される。この連結導体１５は、高い伝導率と熱伝導性の機能と、電気的な接続を簡便にする機能の２つの機能を有す。したがって、このトレンチＭＯＳＦＥＴが動作する時のパッケージの占めるオン抵抗を低減でき、また、トレンチＭＯＳＦＥＴで発生する熱を効率良く外部に放出することが出来る。また、連結導体１５でソースパッド３６とリード接続部１５Ｒとを電気的に接続する際、連結導体１５を銅に代えてアルミニウムリボンを用いることにより、超音波接合により容易に接合可能であるため、半田接合を用いる場合に比べて、工法を簡素化することができる。   According to this configuration, since the rigidity of the connecting conductor is low, workability is slightly reduced in the joining step, but the same effect as in the first embodiment is also achieved in this embodiment. Also in the present embodiment, for example, since the source electrode 35s is made of aluminum, it can be electrically connected to the lead terminal 30R by solder connection. Here, the source electrode 35s is solder-connected to the connecting conductor 15 via the source pad 36 made of a nickel layer. The connecting conductor 15 has two functions, that is, a function of high conductivity and thermal conductivity and a function of simplifying electrical connection. Therefore, the on-resistance occupied by the package when the trench MOSFET operates can be reduced, and the heat generated in the trench MOSFET can be efficiently discharged to the outside. In addition, when the source pad 36 and the lead connection portion 15R are electrically connected by the connection conductor 15, the connection conductor 15 can be easily bonded by ultrasonic bonding by using an aluminum ribbon instead of copper. The construction method can be simplified as compared with the case where solder bonding is used.

なお、半導体チップについては前記実施の形態１乃至４のいずれを用いてもよい。   For the semiconductor chip, any of the first to fourth embodiments may be used.

又、図５及び図１１に示したようなフィンガー部を有する連結導体を用いることにより、図１８（ｂ）に示したようにソースパッドが完全に複数の領域に分離された構造の場合にも、接触性よく実装することが可能である。すなわち、第１の外部取り出し電極を構成するソース電極(ソースパッド)が、第２の外部取り出し電極を構成するゲートパッドで複数の領域に分離されている場合にも、この連結導体のフィンガー部で効率よく接続することが可能である。
又、前記実施の形態では縦型トレンチＭＯＳＦＥＴについて説明したが、ＩＧＢＴなどトレンチゲートを有する縦型の半導体装置であれば適用可能である。 Further, by using a connecting conductor having finger portions as shown in FIGS. 5 and 11, the source pad is completely separated into a plurality of regions as shown in FIG. 18B. It is possible to mount with good contact. That is, even when the source electrode (source pad) that constitutes the first external extraction electrode is separated into a plurality of regions by the gate pad that constitutes the second external extraction electrode, It is possible to connect efficiently.
Further, although the vertical trench MOSFET has been described in the above embodiment, any vertical semiconductor device having a trench gate such as an IGBT can be applied.

以上説明してきたように、本発明によれば、ソース抵抗を抑制しつつ、ゲート抵抗の低減を図ることができるため、高速でかつ消費電力の小さい半導体装置を提供することができることから、リチウムイオン二次電池の充電制御回路をはじめ、小型の電子機器への適用が可能である。   As described above, according to the present invention, since the gate resistance can be reduced while suppressing the source resistance, a high-speed semiconductor device with low power consumption can be provided. It can be applied to small electronic devices including secondary battery charge control circuits.

Ｓ１ 第１の主面
Ｓ２ 第２の主面
１５ 連結導体
１５Ｒ リード接続部
１５Ｍ 連結導体本体部
１５Ｆ フィンガー部
１５Ｂ 連結部
３０ リードフレーム
３０Ｒ リード端子
３０ｓ 半導体素子搭載部
３３Ｂ 橋渡し電極
ｋ 括れ部
３５ｇ ゲートパッド
３５ｓ ソース電極
３５Ｔ ゲート集電電極
３６ ソースパッド S1 1st main surface S2 2nd main surface 15 Connection conductor 15R Lead connection part 15M Connection conductor main-body part 15F Finger part 15B Connection part 30 Lead frame 30R Lead terminal 30s Semiconductor element mounting part 33B Bridging electrode k Constriction part 35g Gate pad 35s Source electrode 35T Gate current collecting electrode 36 Source pad

Claims (9)

外部接続用のリードに接続される本体部と、
前記本体部に連接され、複数の領域に分割され、それぞれが半導体基板の電極パッドに接続されるフィンガー部と、
を備え、外部接続用のリードと半導体基板とを接続する連結導体。 A main body connected to a lead for external connection;
Finger portions connected to the body portion, divided into a plurality of regions, each connected to an electrode pad of a semiconductor substrate;
And a connecting conductor for connecting the lead for external connection and the semiconductor substrate. 請求項１に記載の連結導体であって、
前記フィンガー部の先端に接続され、前記フィンガー部の先端を一体化する連結部とを備えた連結導体。 The connecting conductor according to claim 1,
A connecting conductor that is connected to the tip of the finger part and includes a connecting part that integrates the tip of the finger part. 請求項１または２に記載の複数の連結導体が、連続的に、縦方向に連結された連結導体。   A connection conductor in which a plurality of connection conductors according to claim 1 or 2 are continuously connected in a vertical direction. 第１の主面と前記第１の主面に対向する第２の主面とを有する半導体基板と、
前記半導体基板の前記第１の主面に形成された、第１及び第２の外部取り出し電極と、
外部接続用のリードと、
前記外部接続用のリードと前記半導体基板とを接続する連結導体と、
前記外部接続用のリードの一部を残して封止される封止部とを備えた半導体装置であって、
前記連結導体が、
前記外部接続用のリードに接続される本体部と、
前記本体部に連接され、複数の領域に分割され、それぞれが前記半導体基板の前記第１の外部取り出し電極に接続されるフィンガー部と、
を備え、前記フィンガー部が前記第１の外部取り出し電極の形状に対応し、前記第２の外部取り出し電極上を避けて形成された半導体装置。 A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
First and second external extraction electrodes formed on the first main surface of the semiconductor substrate;
Lead for external connection,
A connecting conductor connecting the lead for external connection and the semiconductor substrate;
A semiconductor device comprising a sealing portion that is sealed leaving a part of the external connection lead,
The connecting conductor is
A main body connected to the external connection lead;
Finger parts connected to the main body part, divided into a plurality of regions, each connected to the first external extraction electrode of the semiconductor substrate;
And the finger portion corresponds to the shape of the first external extraction electrode and is formed so as to avoid the second external extraction electrode. 請求項１に記載の半導体装置であって、
前記連結導体が、
前記フィンガー部の先端に接続され、前記フィンガー部の先端を一体化する連結部を備えた半導体装置。 The semiconductor device according to claim 1,
The connecting conductor is
A semiconductor device comprising a connecting portion connected to the tip of the finger portion and integrating the tip of the finger portion. 請求項５に記載の半導体装置であって、
前記第１の外部取り出し電極が複数の領域を有する半導体装置。 The semiconductor device according to claim 5,
A semiconductor device in which the first external extraction electrode has a plurality of regions. 請求項６に記載の半導体装置であって、
前記第１の外部取り出し電極が前記第２の外部取り出し電極によって、複数の領域に分割された半導体装置。 The semiconductor device according to claim 6,
A semiconductor device in which the first external extraction electrode is divided into a plurality of regions by the second external extraction electrode. 請求項６に記載の半導体装置であって、
前記半導体基板の前記第１の主面に形成された第１の半導体領域と、
前記第１の主面に形成された複数のトレンチと、前記トレンチ内に充填された多結晶シリコン層からなるゲート電極と、
前記トレンチに直交する方向に形成され、前記トレンチ間をつなぐ、多結晶シリコン層からなる橋渡し電極と、
前記半導体基板の周縁に沿って形成され、前記ゲート電極及び前記橋渡し電極に接続される集電リング電極と、
前記第１の主面に形成され、前記第１の半導体領域にコンタクトする第１の電極と、
第１の金属層からなり、前記第１の電極に接続される第１の外部取り出し電極と、第２の金属層からなり、前記ゲート電極に接続される第２の外部取り出し電極とが、前記第１の主面上に並置された半導体装置であって、
前記第１の外部取り出し電極は一体的に形成されており、
前記橋渡し電極の表面の少なくとも一部が前記第２の金属層で構成された半導体装置。 The semiconductor device according to claim 6,
A first semiconductor region formed on the first main surface of the semiconductor substrate;
A plurality of trenches formed in the first main surface; and a gate electrode made of a polycrystalline silicon layer filled in the trenches;
A bridging electrode made of a polycrystalline silicon layer formed in a direction perpendicular to the trench and connecting the trenches;
A current collecting ring electrode formed along the periphery of the semiconductor substrate and connected to the gate electrode and the bridging electrode;
A first electrode formed on the first main surface and in contact with the first semiconductor region;
A first external extraction electrode made of a first metal layer and connected to the first electrode, and a second external extraction electrode made of a second metal layer and connected to the gate electrode, A semiconductor device juxtaposed on the first main surface,
The first external extraction electrode is integrally formed;
A semiconductor device in which at least a part of a surface of the bridging electrode is constituted by the second metal layer. 請求項８に記載の半導体装置であって、
前記トレンチはストライプ状に形成されており、
前記橋渡し電極は前記ストライプ状の前記トレンチに対して直交するように設けられており、
前記第１の外部取り出し電極は、括れ部を有し、
前記括れ部に前記第２の外部取り出し電極が形成され、
前記フィンガー部は前記第２の外部取り出し電極を避けて接続された半導体装置。 The semiconductor device according to claim 8,
The trench is formed in a stripe shape,
The bridging electrode is provided to be orthogonal to the stripe-shaped trench,
The first external extraction electrode has a constricted portion,
The second external extraction electrode is formed in the constricted portion;
The finger unit is a semiconductor device connected to avoid the second external extraction electrode.
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US8872257B1 (en) 2013-05-21 2014-10-28 Kabushiki Kaisha Toshiba Semiconductor device
JP2017103400A (en) * 2015-12-03 2017-06-08 富士電機株式会社 Semiconductor device
CN110945662A (en) * 2017-05-18 2020-03-31 通用电气公司 Integrated gate resistor for semiconductor power conversion device
CN111095545A (en) * 2017-09-05 2020-05-01 新电元工业株式会社 Semiconductor device with a plurality of semiconductor chips
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8872257B1 (en) 2013-05-21 2014-10-28 Kabushiki Kaisha Toshiba Semiconductor device
US9111771B2 (en) 2013-05-21 2015-08-18 Kabushiki Kaisha Toshiba Semiconductor device
US9401398B2 (en) 2013-05-21 2016-07-26 Kabushiki Kaisha Toshiba Semiconductor device including transistor
JP2017103400A (en) * 2015-12-03 2017-06-08 富士電機株式会社 Semiconductor device
CN110945662A (en) * 2017-05-18 2020-03-31 通用电气公司 Integrated gate resistor for semiconductor power conversion device
CN110945662B (en) * 2017-05-18 2024-04-23 通用电气公司 Integrated gate resistor for semiconductor power conversion device
CN111095545A (en) * 2017-09-05 2020-05-01 新电元工业株式会社 Semiconductor device with a plurality of semiconductor chips
CN111095545B (en) * 2017-09-05 2023-10-20 新电元工业株式会社 Semiconductor device with a semiconductor device having a plurality of semiconductor chips
EP3832705A4 (en) * 2018-11-30 2021-09-15 Hitachi Metals, Ltd. ELECTRICAL CONNECTOR, ELECTRICAL CONNECTOR STRUCTURE AND METHOD FOR MANUFACTURING THE ELECTRICAL CONNECTOR
US12176315B2 (en) 2018-11-30 2024-12-24 Hitachi Metals, Ltd. Electrical connection member, electrical connection structure, and method for manufacturing electrical connection member

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