JP2012104664A - Semiconductor device and manufacturing method therefor, solid state image sensor, electronic information apparatus - Google Patents

Abstract

Randomization is achieved by reducing defects near a source side gate end caused by ion implantation damage on a source side gate end of a transistor by a simpler manufacturing process without increasing the transistor gate area as in the prior art. Effectively reduce noise.
Only the N-type diffusion layer 11 in the drain-side LDD region sinks under the other end of the gate electrode 6, and the N-type diffusion layer 11 in the drain-side LDD region overlaps the gate electrode 6 in plan view. However, the N-type diffusion layer 12 in the LDD region on the source side does not sink under one end of the gate electrode 6, and the N-type diffusion layer 12 in the LDD region on the source side overlaps the gate electrode 6 in plan view. In other words, the N-type diffusion layer 12 in the LDD region on the source side is formed apart from one end of the gate electrode 6.
[Selection] Figure 1

Description

  The present invention provides a semiconductor device including an amplifier circuit having one or a plurality of MOS transistors, a method for manufacturing the same, a plurality of light receiving units that photoelectrically convert image light from a subject, and a signal charge from each light receiving unit. A solid-state imaging device such as a CMOS image sensor that amplifies the potential corresponding to the pixel as an imaging signal for each pixel by the amplifier circuit, for example, a digital video camera and a digital still using the solid-state imaging device as an image input device in an imaging unit The present invention relates to an electronic information device such as a digital camera such as a camera, an image input camera such as a surveillance camera, a scanner device, a facsimile device, a television telephone device, and a mobile phone device with a camera.

  A CMOS image sensor as this type of conventional solid-state imaging device has an initial stage amplification transistor for each pixel, and the transistor configuration is shown in FIGS. 8 and 9 of Patent Document 1 and FIG. 10 of Patent Document 2. Will be described in detail.

  FIG. 8 is a pixel configuration diagram of 4TR in the conventional solid-state imaging device disclosed in Patent Document 1, in which (a) shows a planar layout, and (b) shows an AA line in (a). A cross-sectional structure is shown.

As shown in FIGS. 8A and 8B, in the conventional solid-state imaging device 100, a predetermined region on the surface of the semiconductor substrate 101 has a vertically long, substantially rectangular N ^- type constituting the photodiode PD. A diffusion region 102 is formed. The N ⁻ -type diffusion region 102 has a shape in which one corner of a rectangle is cut off in plan view, and the gate electrode of the transfer transistor Ttr having a substantially right-angled isosceles triangle shape in the portion from which the corner is cut off ( A transfer gate electrode) Tg is disposed.

Further, on the opposite side of the substantially rectangular diffusion region 102 of the gate electrode (transfer gate electrode) Tg of the transfer transistor Ttr, a strip-like diffusion region 103 constituting the reset transistor Rtr is disposed. A gate electrode Rg of the reset transistor Rtr is disposed in the central portion of the strip diffusion region 103. Further, one end side (the lower side in the drawing) portion 103 a of the belt-like diffusion region 103 is disposed so as to be close to the side inclined portion 102 a of the N ⁻ -type diffusion region 102. A transfer gate selection line Gs for applying a transfer signal TX to the gate electrode is connected to one end of the transfer gate electrode Tg via a contact hole Cgs.

Here, the diffusion region 103 constituting the reset transistor Rtr is an N-type diffusion region selectively formed on the P-type semiconductor substrate 101, and one end portion of the diffusion region 103 is a signal charge read from the photodiode PD. Is formed in a following diffusion region (FD region) 103a. A P ⁻ type diffusion region 104 is formed between the N type diffusion region 102 and the N type diffusion region 103, and this P ⁻ type diffusion region 104 becomes a channel region of the transfer transistor Ttr. On top of this, a transfer gate Tg made of N-type polysilicon is disposed via a gate insulating film 104a.

  On the semiconductor substrate 101, a strip-shaped N-type diffusion region 105 extending in the vertical direction on the paper surface is disposed in parallel so as to face the strip-shaped N-type diffusion region 103 constituting the reset transistor Rtr. A gate electrode Ag made of N-type polysilicon constituting the amplification transistor Atr is disposed on one end side (lower side of the drawing) of the N-type diffusion region 105 via a gate insulating film 105a. On the other end side (upper side of the drawing) of the N-type diffusion region 105, the gate electrode Sg constituting the selection transistor Str is disposed.

  An oxide isolation region Rc is provided between the FD region 103a and the N-type diffusion region 105. The FD region 103a and the gate electrode Ag of the amplification transistor Atr are electrically connected by a metal wiring Mw, and one end of the metal wiring Mw is connected to the FD region 103a through a contact hole Cf1, and the metal wiring Mw The other end is connected to the gate electrode Ag via the contact hole Cf2.

  In this case, the gate area at the gate electrode Ag of the source follower transistor constituting the amplification transistor Atr is configured to be relatively larger than the gate areas of the reset transistor Rtr and the selection transistor Str. Thereby, it is possible to reduce the influence of random noise generated in the source follower transistor and obtain a high-quality image.

  FIG. 9 is a longitudinal sectional view showing a configuration example of a source follower transistor constituting the amplification transistor Atr in FIG. 8, (a) is a longitudinal sectional view when there is a channel stop region, and (b) is a channel stop region. FIG.

  As shown in FIG. 9A, in the source follower transistor 110A, a P well layer 111 is provided on the semiconductor substrate 110, and a gate electrode 113 is provided on the P well layer 111 through a gate insulating film 112. . Side walls are formed on both side surfaces of the gate electrode 113, and N-type diffusion layers 114 and 115 as source / drain regions are formed on the semiconductor substrate 110 on both sides of each side wall. N-type diffusion layers 114a and 115a are formed inside the N-type diffusion layers 114 and 115 and directly below the side walls, respectively, to form an LDD region. Further, a P-type channel stop region 116 is provided so as to cover these N-type diffusion layers 114, 114a, and a P-type channel stop region 117 is provided so as to cover the N-type diffusion layers 115, 115a. .

  FIG. 9B shows a case where the source follower transistor 110B does not have the P-type channel stop regions 116 and 117 of FIG. 9A. In any case, the lengths X and Y of the N-type diffusion layers 114a and 115a directly below the sidewalls inside the N-type diffusion layers 114 and 115 are equal to each other, and the positions of the N-type diffusion layers 114 and 115 with respect to the gate electrode 113 and The positions of the mold diffusion layers 114a and 115a are also symmetrical.

  FIG. 10 shows an example of left-right asymmetry between the source side and the drain side in the cross-sectional structure of the transistor.

  FIG. 10 is a longitudinal sectional view of a conventional transistor showing a left-right asymmetric case disclosed in Patent Document 2. In FIG.

  As shown in FIG. 10, in a conventional transistor 200, a channel region 202 is formed on a semiconductor substrate 201, and a gate electrode 204 is formed on the channel region 202 through a gate insulating film 203.

  An extension region 205 is formed in the semiconductor substrate 201 on the source side of the gate electrode 204. A source region 206 is formed on the semiconductor substrate 201 on the source side of the gate electrode 204 via an extension region 205.

  An LDD region 207 is formed in the semiconductor substrate 201 on the drain side of the gate electrode 204. In the semiconductor substrate 201 on the drain side of the gate electrode 204, a drain region 208 is formed through an LDD region 207. The concentration of the extension region 205 is higher than that of the LDD region 207, and the extension region 205 is formed shallower than the LDD region 207.

  Further, in Non-Patent Document 1, when a defect on the surface of the semiconductor substrate immediately below the gate electrode of the transistor (a site where electrons are temporarily captured or emitted) exists near the gate end, the defect is random depending on the current direction. It is disclosed that it becomes difficult to influence noise.

JP 2009-212248 A JP 2010-109138 A

Kenichi Abe, et al. "Asymmetry of RTS Characteristics Along Source-Drain Direction and Statistical Analysis of Process-Induced RTS, 2009 IEEE Internally Reliable PTS. 996-1001, Montreal, Quebec, April 2009.

  However, in the conventional configuration disclosed in Patent Document 1, in order to reduce the influence of random noise generated in the source follower transistor, the gate area of the source follower transistor is relative to that of other transistors. However, this makes it difficult to reduce the pixel area in response to the demand for higher pixels. In particular, when the gate width W is limited by the photodiode arrangement, an attempt to increase the gate area requires that the gate length be increased, thereby reducing the capability of the source follower transistor.

  In addition, the above-described conventional configuration disclosed in Patent Document 2 only shows a case where the source side and the drain side are asymmetrical, and the reduction in mutual conductance is suppressed to improve the performance of the transistor. This is an object, and is completely different from the one that reduces the influence of random noise as in Patent Document 1 described above. Further, the concentration of the extension region 205 is higher than that of the LDD region 207, and the extension region 205 is formed shallower than the LDD region 207. When manufacturing this, in order to control the impurity ion implantation concentration, it is necessary to perform the photolithography process and the impurity ion implantation process separately from the extension region 205 and the LDD region 207, and the manufacturing process increases. It is complicated.

  Further, in Non-Patent Document 1, when a defect on the surface of the semiconductor substrate immediately below the gate electrode of the transistor (a site where electrons are temporarily captured or emitted) is present near the gate end, the defect may depend on the current direction. It is only disclosed that it becomes difficult to influence random noise, and by deliberately reducing only defects near the gate end of the source side, random noise can be effectively reduced. There is no mention or suggestion.

  The present invention solves the above-described conventional problems, and does not increase the transistor gate area as in the prior art, and the source side gate generated by ion implantation damage at the source side gate end of the transistor in a simpler manufacturing process. Semiconductor device capable of effectively reducing random noise by reducing defects near the edge and manufacturing method thereof, solid-state imaging device using this semiconductor device as an amplification transistor, and using this solid-state imaging device as an image input device An object of the present invention is to provide an electronic information device such as a camera-equipped mobile phone device used in an imaging unit.

  In the semiconductor device of the present invention, a source side LDD region is disposed between one end side of the gate electrode and the source region, and a drain side LDD region is disposed between the other end side of the gate electrode and the drain region. Of the LDD region on the source side and the LDD region on the drain side, only the LDD region on the drain side goes under the other end of the gate electrode, so that the LDD region on the gate electrode and the drain side is viewed in plan view. The above-mentioned purpose is achieved by this.

  Preferably, in the semiconductor device of the present invention, the source-side LDD region does not sink under one end of the gate electrode, and the one end of the gate electrode and the LDD region on the source side overlap in plan view. Not done.

  Further preferably, in the semiconductor device of the present invention, the source-side LDD region is formed shorter in the gate length direction than the drain-side LDD region.

  Further preferably, in the semiconductor device of the present invention, the source-side LDD region is formed apart from one end of the gate electrode in plan view.

  Further preferably, in the semiconductor device of the present invention, a channel stop region is formed on at least the drain side of the source side and the drain side, and the channel stop region on the source side and the channel stop on the drain side are formed. Only the drain-side channel stop region of the region sinks under the other end of the gate electrode, and the gate electrode and the drain-side channel stop region overlap in plan view.

  Further preferably, in the semiconductor device of the present invention, the source-side channel stop region does not sink under one end of the gate electrode, and the gate electrode and the source-side channel stop region overlap in plan view. Not.

  Further preferably, in the semiconductor device of the present invention, the source-side channel stop region is formed apart from one end of the gate electrode in plan view.

  Further preferably, in the semiconductor device of the present invention, the source-side channel stop region is formed shorter in the gate length direction than the drain-side channel stop region.

  Further preferably, the semiconductor device of the present invention is a source follower transistor constituting an amplification transistor.

  In the solid-state imaging device of the present invention, a plurality of light receiving units that photoelectrically convert incident light to provide an image are provided in a matrix in the row direction and the column direction, and each signal charge from the plurality of light receiving units is imaged for each pixel. An amplification transistor for amplifying as a signal is provided, and the semiconductor device of the present invention is used as the amplification transistor, thereby achieving the object.

  Preferably, the solid-state imaging device of the present invention is a CMOS solid-state imaging device or a CCD solid-state imaging device.

  Furthermore, preferably, each pixel in the solid-state imaging device of the present invention is adjacent to each of the plurality of light receiving units, and a charge transfer transistor that transfers a signal charge from the light receiving unit to a charge voltage conversion unit, A signal readout circuit that converts the voltage of the signal charge transferred to the charge-voltage conversion unit by the charge transfer transistor, amplifies the signal by the amplification transistor according to the converted voltage, and reads out the image pickup signal for each pixel; .

  Further preferably, in the solid-state imaging device of the present invention, for each of the plurality of light receiving units in the column direction, a plurality of vertical charge transfer units that transfer the signal charges read from the plurality of light receiving units in the vertical direction; A horizontal charge transfer unit that horizontally transfers each signal charge transferred by the plurality of vertical charge transfer units, and each signal charge that has been transferred from the horizontal charge transfer unit is voltage-converted, and the converted voltage is converted into the converted voltage. And a signal output unit that is amplified by the amplification transistor and output as an imaging signal for each pixel.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing the above-described semiconductor device according to the present invention, which has a tilt angle θ1 on the drain side of the gate electrode after the formation of the gate electrode, and the source side of the gate electrode. LDD region forming step of forming an LDD region on the source side shorter in the gate length direction than the LDD region on the drain side by performing ion implantation of the LDD region at the tilt angle θ1 at which shadowing by the gate electrode occurs This achieves the above object.

  Preferably, the tilt angle θ1 in the method for manufacturing a semiconductor device of the present invention is an inclination of 4 to 10 degrees toward the drain side.

  Further preferably, after the LDD region forming step in the semiconductor device manufacturing method of the present invention, the gate electrode has a tilt angle θ2 on the drain side, and shadowing by the gate electrode occurs on the source side of the gate electrode. A channel stop region forming step of performing ion implantation of the channel stop region at the tilt angle θ2 to form the channel stop region on at least the drain side of the drain side and the source side.

  More preferably, the tilt angle θ2 in the method for manufacturing a semiconductor device of the present invention is larger than the tilt angle θ1.

  More preferably, the tilt angle θ2 in the method for manufacturing a semiconductor device of the present invention is an inclination of 10 to 60 degrees toward the drain side.

  Further preferably, before the LDD region forming step in the method of manufacturing a semiconductor device of the present invention, a well layer forming step of forming a well layer by ion implantation on the semiconductor substrate, and a gate insulating film on the well layer And a gate electrode forming step of forming a gate electrode through the gate electrode.

  Further preferably, in the method of manufacturing a semiconductor device according to the present invention, after the LDD region forming step or the channel stop region forming step, the side wall is formed on each side surface of the gate electrode in the gate length direction. And a source / drain formation step of forming a drain region and a source region by performing ion implantation on both sides of the gate electrode on which the sidewall is formed.

  The electronic information device of the present invention uses the solid-state imaging device of the present invention as an image input device in an imaging unit, and thereby achieves the above object.

  With the above configuration, the operation of the present invention will be described below.

  In the present invention, a source-side LDD region is disposed between one end side of the gate electrode and the source region, and a drain-side LDD region is disposed between the other end side of the gate electrode and the drain region. Only the LDD region on the side sinks under the other end of the gate electrode, and the LDD region on the drain side overlaps with the gate electrode.

  As a result, only the drain-side LDD region sinks under the other end of the gate electrode, the gate electrode and the drain-side LDD region overlap in plan view, and the source-side LDD region is under one end of the gate electrode. Since the gate electrode and the LDD region on the source side do not overlap in plan view, the gate electrode is shaded because of an angle in the ion implantation direction, and the end portion of the gate electrode on the source region side In this case, the ion implantation damage at the end of the gate electrode on the source region side is suppressed and defects are also suppressed, so that the manufacturing process can be simplified without increasing the transistor gate area as in the prior art. In the process, defects in the vicinity of the source-side gate end caused by ion implantation damage at the source-side gate end of the transistor are intentionally reduced. Ri, it is possible to reduce random noise effectively.

  As described above, according to the present invention, only the drain-side LDD region sinks under the other end of the gate electrode, the drain-side LDD region overlaps the gate electrode in plan view, and the source-side LDD region Since the source side LDD region does not overlap with the gate electrode in plan view, and the source side LDD region is formed apart from the one end of the gate electrode. Random noise can be achieved by deliberately reducing defects near the source side gate end caused by ion implantation damage on the source side gate end of the transistor without increasing the transistor gate area as in the past. Can be effectively reduced.

It is a longitudinal cross-sectional view of the source follower transistor in the CMOS type solid-state image sensor of Embodiment 1 of the present invention. 2A and 2B are longitudinal sectional views for explaining an LDD diffusion layer forming step in the method for manufacturing the source follower transistor of FIG. 1, wherein FIG. FIG. It is a longitudinal cross-sectional view of the source follower transistor in the CMOS type solid-state image sensor of Embodiment 2 of this invention. 4A and 4B are longitudinal sectional views for explaining an LDD diffusion layer forming step in the method for manufacturing the source follower transistor of FIG. 3, wherein FIG. FIG. FIG. 4 is a longitudinal sectional view for explaining a channel stop region forming step in the method for manufacturing the source follower transistor of FIG. 3, wherein (a) is a longitudinal sectional view during ion implantation of the channel stop region, and (b) is the channel stop. It is a longitudinal cross-sectional view after area | region ion implantation. It is a longitudinal cross-sectional view of the source follower transistor which shows the modification of the CMOS type solid-state image sensor of Embodiment 2 of this invention. It is a block diagram which shows the schematic structural example of the electronic information apparatus which used the CMOS type solid-state image sensor of Embodiment 1, 2 of this invention for the imaging part as Embodiment 3 of this invention. It is a pixel block diagram of 4TR in the conventional solid-state image sensor currently disclosed by patent document 1, (a) shows the planar layout, (b) shows the structure of the AA line cross section of (a). Show. FIG. 9 is a longitudinal sectional view showing a configuration example of a source follower transistor constituting the amplification transistor Atr in FIG. 8, where (a) is a longitudinal sectional view when there is a channel stop region, and (b) is a longitudinal section when there is no channel stop region. FIG. It is a longitudinal cross-sectional view of the conventional transistor which shows the example of the left-right asymmetric currently disclosed by patent document 2. FIG.

  In the following, as Embodiments 1 and 2 of the semiconductor device and the manufacturing method thereof according to the present invention, a MOS transistor and a manufacturing method thereof will be described, and a solid-state imaging device using the MOS transistor as an amplification transistor for signal output will be described. A third embodiment of an electronic information device such as a mobile phone device with a camera using the solid-state imaging device according to the first or second embodiment as an image input device in an imaging unit will be described in detail with reference to the drawings. In addition, each thickness, length, etc. of the structural member in each figure are not limited to the structure to illustrate from a viewpoint on drawing preparation.

(Embodiment 1)
FIG. 1 is a longitudinal sectional view of a source follower transistor in a CMOS type solid-state imaging device according to Embodiment 1 of the present invention.

  As shown in FIG. 1, in the source follower transistor 2 constituting the amplification transistor in the CMOS type solid-state imaging device 1 of Embodiment 1, a P well layer 4 is provided on an N type semiconductor substrate 3. A gate electrode 6 is provided through a gate insulating film 5. Side walls 7 and 8 are formed on both side surfaces of the gate electrode 6 in the channel length direction, and the N-type as a drain region is formed on the surface portion of the P well layer 4 on both sides of the side walls 7 and 8, respectively. A diffusion layer 9 is formed, and an N-type diffusion layer 10 as a source region is formed. N-type diffusion layers 11 and 12 are formed on the inner side between the N-type diffusion layers 9 and 10 and directly below the sidewalls 7 and 8, respectively, thereby constituting each LDD region.

  As a characteristic configuration of the source follower transistor 2 of the first embodiment, the N-type diffusion layer 11 in the LDD region on the drain region side is submerged (overlapped) directly below the gate electrode 6, but the LDD on the source region side. The N-type diffusion layer 12 in the region does not go under the gate electrode 6 (does not overlap), and is in an offset state. That is, only the N-type diffusion layer 11 in the drain-side LDD region enters under the other end of the gate electrode 6, and the N-type diffusion layer 11 in the drain-side LDD region overlaps the gate electrode 6 in plan view. The N-type diffusion layer 12 in the source-side LDD region does not sink under one end of the gate electrode 6, and the N-type diffusion layer 12 in the source-side LDD region does not overlap the gate electrode 6 in plan view. An N-type diffusion layer 12 in the source side LDD region is formed apart from one end of the gate electrode 6.

  Further, the relationship between the LDD width (X) of the N-type diffusion layer 11 in the LDD region on the drain side and the LDD width (Y) of the N-type diffusion layer 12 in the LDD region on the source region side is the drain region in the gate length direction. Side width (X)> Source region side width (Y).

  The effect by the characteristic structure of this Embodiment 1 is demonstrated. Charge traps due to defects existing at the silicon / oxide film interface between the P well layer 4 and the gate insulating film 5 of the semiconductor substrate 3 below the gate electrode 6 that cause random noise are generated by the source / drain of the gate electrode 6. When present at the end on the region side, random noise occurs only when a defect exists at the end of the gate electrode on the source region side. In this case, when a defect exists at the end of the gate electrode on the drain region side, it does not cause random noise. Thus, random noise can be reduced if only defects at the end of the gate electrode on the source region side among the defects generated at the end of the gate electrode 6 on the source region side / drain region side are suppressed. Therefore, in the first embodiment, as the characteristic configuration, only the N-type diffusion layer 11 in the drain-side LDD region enters under the other end of the gate electrode 6, and the N-type diffusion layer in the drain-side LDD region. 11 overlaps with the gate electrode 6 in plan view, and the N-type diffusion layer 12 in the LDD region on the source side does not sink under one end of the gate electrode 6, and the N-type diffusion layer 12 in the LDD region on the source side The N-type diffusion layer 12 in the LDD region on the source side is formed apart from one end of the gate electrode 6 without overlapping the electrode 6 in plan view.

  A method for manufacturing the source follower transistor 2 having the above configuration will be described in detail with reference to FIGS. 2 (a) and 2 (b).

  2 is a longitudinal sectional view for explaining an LDD diffusion layer forming step in the method for manufacturing the source follower transistor 2 of FIG. 1, wherein FIG. 2 (a) is a longitudinal sectional view at the time of LDD ion implantation, and FIG. It is a longitudinal cross-sectional view after the LDD ion implantation.

  As shown in FIG. 2A, a P well layer 4 is formed on an N-type semiconductor substrate 3 by an ion implantation process, a gate insulating film 5 is formed on the P well layer 4, and a signal is formed on the gate insulating film 5. A gate electrode 6 for charge transfer is formed. After the gate electrode 6 is formed, LDD ion implantation is performed from the direction inclined from the drain side by the tilt angle θ1 (from the upper left to the lower right). In this case, the tilt angle θ1 tilted toward the drain side is 4 to 10 degrees, but here, ion implantation is performed with a tilt of 7 degrees toward the drain side.

  As a result, as shown in FIG. 2B, the N-type diffusion layer 11a in the LDD region on the drain region side and the N-type diffusion layer 12a in the LDD region on the source region side are formed. In this case, since the ion implantation direction is tilted to the drain side by the tilt angle θ1, the source region side is shadowed by the gate electrode 6 so that the N-type diffusion layer 12a in the LDD region on the source region side is The N type diffusion layer 12 a in the LDD region on the source side is separated from the end portion of the gate electrode 6 in a state offset from the end portion.

  Next, after forming the sidewalls 7 and 8 on both side surfaces of the gate electrode 6 in the channel length (gate length) direction, ion implantation is performed in a self-aligned manner by the sidewalls, as shown in FIG. An N-type diffusion layer 9 as a drain region and an N-type diffusion layer 10 as a source region are formed.

  As a result, the N-type diffusion layer 12 in the LDD region on the source region side does not overlap the end portion of the gate electrode 6 but is offset from the end portion of the gate electrode 6. The transistor 2 can be formed.

  As described above, the method of manufacturing the source follower transistor 2 as a semiconductor device includes a P well layer forming step of forming an P well layer 4 by ion implantation on the N-type semiconductor substrate 3, and gate insulation on the P well layer 4. A gate electrode forming step of forming the gate electrode 6 through the film 5, and the tilt angle θ1 having a tilt angle θ1 on the drain side of the gate electrode 6 and causing shadowing by the gate electrode 6 on the source side of the gate electrode 6 The LDD region is ion-implanted to form a source-side LDD region shorter in the gate length direction than the drain-side LDD region, and sidewalls 7 on both side surfaces of the gate electrode 6 in the gate length direction. , 8 respectively, and ion implantation is performed on both sides of the gate electrode 6 on which the sidewalls 7 and 8 are formed. And a source / drain forming step of forming an in region and a source region.

  As described above, according to the first embodiment, as described above, even if an ion implantation defect exists in the end channel region of the gate electrode 6 on the drain region 9 side, it is difficult to cause random noise. By forming the N-type diffusion layer 12 in the LDD region on the side in an offset state spaced from the end of the gate electrode 6, no ion implantation defect occurs in the end channel region of the gate electrode 6 on the source region side Thus, only the ion implantation defects in the end channel region of the gate electrode 6 on the source region side can be suppressed, and random noise can be achieved without degrading the characteristics of the source follower transistor 2 constituting the first stage amplification transistor for each pixel. Can be reduced. By reducing the random noise, it is possible to improve the image quality of the image displayed on the display screen based on the imaging signal from the CMOS solid-state imaging device 1 of the first embodiment. Therefore, it is not necessary to reduce the probability of existence of defects by reducing the gate electrode 6 in the gate length direction in order to reduce random noise, as in the prior art. It is possible to improve the resolution of the image signal included in the imaging region.

(Embodiment 2)
When the gate length of the transistor is long, it is not necessary, but when the gate length is short, a channel stop region for suppressing the short channel effect is necessary. However, in the first embodiment, the channel stop region is not used. As described above, in the second embodiment, a case where this channel stop region is used will be described.

  FIG. 3 is a longitudinal sectional view of a source follower transistor in the CMOS solid-state imaging device according to the second embodiment of the present invention.

  As shown in FIG. 3, in the source follower transistor 2 </ b> A constituting the amplification transistor in the CMOS type solid-state imaging device 1 </ b> A of the second embodiment, a P well layer 4 is provided on the N type semiconductor substrate 3. A gate electrode 6 is provided through a gate insulating film 5. Side walls 7 and 8 are formed on both side surfaces of the gate electrode 6 in the channel length direction (gate length direction), and drains are respectively formed on the surface portions of the P well layer 4 on both sides of the side walls 7 and 8. An N-type diffusion layer 9 as a region is formed, and an N-type diffusion layer 10 as a source region is formed. N-type diffusion layers 11 and 12 are formed on the inner side between the N-type diffusion layers 9 and 10 and directly below the sidewalls 7 and 8, respectively, thereby forming an LDD region. Further, a P-type channel stop region 13 is provided so as to cover the N-type diffusion layer 9 in the drain region and the N-type diffusion layer 11 in the LDD region from below, and the N-type diffusion layer 10 and the LDD region in the source region are provided. The P-type channel stop region 14 is provided only under the N-type diffusion layer 12. The P-type channel stop region 13 completely covers the N-type diffusion layers 9 and 11 from below and is submerged directly under the gate electrode 6. However, the P-type channel stop region 14 completely extends the N-type diffusion layer 10 from below. Although covered, only a part of the lower surface of the N-type diffusion layer 12 in the LDD region is covered, and it does not go under the gate electrode 6, and the N-type diffusion layer 12 is not covered by the gate electrode 6 in plan view. Separated from the end.

  As a characteristic configuration of the source follower transistor 2A according to the second embodiment, the N-type diffusion layer 11 in the LDD region on the drain region side is buried under the gate electrode 6 (overlapping in plan view). The N-type diffusion layer 12 in the LDD region on the side does not go under the gate electrode 6 (does not overlap in a plan view) and is in an offset state separated from the end of the gate electrode 6 in a plan view. Yes. The relationship between the width (X) of the N-type diffusion layer 11 in the LDD region on the drain region side and the width (Y) of the N-type diffusion layer 12 in the LDD region on the source region side is the drain region side in the gate length direction. The width of the N-type diffusion layer 11 (X)> the width of the N-type diffusion layer 12 on the source region side (Y). Furthermore, the channel stopper region 13 extends only below the gate electrode 6 from the N-type diffusion layer 11 in the LDD region only on the drain region side, and on the source region side from the N-type diffusion layer 12 in the LDD region. There is no channel stop region extending downward.

  Further, as a characteristic configuration of the source follower transistor 2A of the second embodiment, only the drain side channel stop region 13 of the drain side channel stop region 13 and the source side channel stop region 14 is the other end of the gate electrode 6. The gate electrode 6 and the channel stop region 13 on the drain side overlap with each other in plan view. In this case, the source-side channel stop region 14 does not sink under one end of the gate electrode 6, and the gate electrode 6 and the source-side channel stop region 14 do not overlap in plan view. Separated from the edge. Although not shown here, the channel stop region 14 on the source side is formed shorter than the channel stop region 14 on the drain side in the gate length direction.

  A method of manufacturing the source follower transistor 2A having the above configuration will be described in detail with reference to FIGS. 4A and 4B and FIGS. 5A and 5B.

  4A and 4B are longitudinal sectional views for explaining an LDD diffusion layer forming step in the method for manufacturing the source follower transistor 2A of FIG. 3, wherein FIG. 4A is a longitudinal sectional view at the time of LDD ion implantation, and FIG. It is a longitudinal cross-sectional view after the LDD ion implantation. FIG. 5 is a longitudinal sectional view for explaining a channel stop region forming step in the method for manufacturing the source follower transistor 2A of FIG. 3, wherein (a) is a longitudinal sectional view at the time of channel implantation of the channel stop region. ) Is a longitudinal sectional view after ion implantation of the channel stop region.

  First, as shown in FIG. 4A, a P well layer 4 is formed on an N-type semiconductor substrate 3 by an ion implantation process, a gate insulating film 5 is formed on the P well layer 4, and then a gate insulating film 5 is formed. A gate electrode 6 for charge transfer is formed thereon. After the gate electrode 6 is formed, LDD ion implantation is performed from the direction inclined by the tilt angle θ1 toward the drain region (from the upper left to the lower right). In this case, the tilt angle θ1 tilted toward the drain side is 4 to 10 degrees, but here, ion implantation is performed with a tilt of 7 degrees toward the drain side.

  As a result, as shown in FIG. 4B, the N-type diffusion layer 11a in the LDD region on the drain region side and the N-type diffusion layer 12a in the LDD region on the source region side are formed. In this case, since the ion implantation direction is tilted toward the drain region by the tilt angle θ1, the source region side is shadowed by the gate electrode 6, and therefore the N-type diffusion layer 12a in the LDD region on the source region side is It is formed in an offset state separated from.

  Next, as shown in FIG. 5A, ions are implanted into the channel stop region from a direction (upper left to lower right) inclined by a tilt angle θ2 (θ2> θ1) toward the drain region. In this case, the tilt angle θ2 tilted toward the drain side of the ion implantation for forming the channel stop regions 13 and 14 is 10 to 60 degrees (more preferably 20 to 40 degrees) in the actual example of the channel stop layer implantation conditions. Here, however, ion implantation is performed at an inclination of 30 degrees toward the drain side. The tilt angle θ2 is larger than the tilt angle θ1.

  As a result, as shown in FIG. 5B, the channel stopper region 13 is formed so as to cover the lower position of the N-type diffusion layer 11a in the LDD region on the drain region side, and the N-type in the LDD region on the source region side. The channel stopper region 14 is formed so as to cover a part of the diffusion layer 12a except for the tip at the lower position. In this case, since the ion implantation direction is tilted toward the drain side by the tilt angle θ2, the source region side is shadowed by the gate electrode 6, so that the LDD region is formed on the source region side like the channel stopper region 14. A channel stop region extending below the gate electrode 6 rather than the N-type diffusion layer 12a is not formed.

  Subsequently, after forming the sidewalls 7 and 8 on both side surfaces of the gate electrode 6 in the channel length (gate length) direction, ion implantation is performed in a self-aligned manner by the sidewalls, as shown in FIG. An N-type diffusion layer 9 as a drain region and an N-type diffusion layer 10 as a source region are formed.

  As a result, the N-type diffusion layer 12 in the LDD region on the source region side does not overlap with the gate electrode 6, and the source follower transistor 2 </ b> A of the second embodiment in the offset state separated from the end of the gate electrode 6 can be obtained. Can be formed.

  As described above, the method of manufacturing the source follower transistor 2 as a semiconductor device includes a P well layer forming step of forming an P well layer 4 by ion implantation on the N-type semiconductor substrate 3, and gate insulation on the P well layer 4. A gate electrode forming step of forming the gate electrode 6 through the film 5, and the tilt angle θ1 having a tilt angle θ1 on the drain side of the gate electrode 6 and causing shadowing by the gate electrode 6 on the source side of the gate electrode 6 Then, the LDD region is ion-implanted to form a source-side LDD region that is shorter in the gate length direction than the drain-side LDD region, and a tilt angle θ2 (θ2> θ1 on the drain side of the gate electrode 6). ), And channel stop regions 13 and 14 at a tilt angle θ2 at which shadowing by the gate electrode 6 occurs on the source region side of the gate electrode 6. A channel stop region forming step of forming the channel stop region 13 on the drain region side and forming the channel stop region 14 on the source region side, and both sides of the gate electrode 6 in the gate length direction. Side wall forming step for forming side walls 7 and 8 on the surface, and source / drain formation for forming a drain region and a source region by performing ion implantation on both sides of the gate electrode 6 on which the side walls 7 and 8 are formed Process.

  As described above, according to the second embodiment, only the N-type diffusion layer 11 in the drain-side LDD region enters under the other end of the gate electrode 6, and the N-type diffusion layer 11 in the drain-side LDD region becomes the gate electrode. 6, the N-type diffusion layer 12 in the source-side LDD region does not sink under one end of the gate electrode 6, and the N-type diffusion layer 12 in the source-side LDD region is planar with the gate electrode 6. The N-type diffusion layer 12 in the LDD region on the source side is formed apart from one end of the gate electrode 6 without overlapping. Thereby, ion implantation defects do not occur in the end channel region of the gate electrode 6 on the source region side. Similarly, the channel stop region 14 on the source region side is also formed in an offset state spaced from the end portion of the gate electrode 6, so that no ion implantation defects occur in the end channel region of the gate electrode on the source region side. Each of these effects can intentionally suppress only a defect at the end of the gate electrode 6 on the source region side, and the characteristic of the source follower transistor 2A constituting the first stage amplification transistor for each pixel is not deteriorated. Thus, random noise can be reduced, and the image quality of the image displayed on the display screen can be improved based on the imaging signal from the CMOS solid-state imaging device 1A of the second embodiment. Thereby, it is not necessary to enlarge the gate electrode 6 in the gate length direction particularly for reducing random noise, and the pixel area can be reduced to include more pixels in the imaging area.

  In the second embodiment, a P-type channel stop region 13 is provided so as to cover the N-type diffusion layer 9 in the drain region and the N-type diffusion layer 11 in the LDD region from below, and the N-type diffusion layer 10 in the source region. Although the case where the P-type channel stop region 14 is provided in the lower part of the N-type diffusion layer 12 in the LDD region has been described, the present invention is not limited to this, and the P-type channel stop region is provided on the source region side as shown in FIG. 14 may be omitted. In short, at the time of ion implantation, the gate electrode 6 and the source region side are covered with a resist mask, ion implantation of impurities is performed, and the P-type channel stop region 13 is formed only on the drain region side of the N-type diffusion layer 9 and the LDD region. The N-type diffusion layer 11 can be formed so as to cover from below. In this case, as a modification of the source follower transistor 2A constituting the amplification transistor in the CMOS type solid-state imaging device 1A of Embodiment 2, a source follower transistor 2B constituting the amplification transistor in the CMOS type solid-state imaging device 1B can be obtained. .

  Here, the CMOS type solid-state imaging device 1, 1A, or 1B having a different cross-sectional configuration such as the source follower transistor 2, 2A, or 2B that has no channel stop region or is only on the drain region side will be described in more detail. .

That is, when each pixel portion of the CMOS type solid-state imaging device 1, 1A, or 1B is made to correspond to the solid-state imaging device 100 of FIG. 8, a photodiode PD ( A light receiving portion) is formed. Adjacent to the N ⁻ type diffusion region 102 of the photodiode PD, a charge transfer unit 104 of the charge transfer transistor Ttr for transferring the signal charge from the photodiode PD to the floating diffusion unit 103a (charge voltage conversion unit) is provided. It has been. On the charge transfer portion 104, a gate electrode Tg as an extraction electrode is provided via a gate insulating film 104a. This is a charge transfer transistor Ttr described later. Further, the signal charge transferred to the floating diffusion portion 103a for each photodiode PD is voltage-converted, and is amplified by the amplification transistor Atr in accordance with the converted voltage, and output to the signal line as an imaging signal for each pixel portion. A signal readout circuit. In addition to the above-described charge transfer transistor Ttr and amplification transistor Atr, this signal readout circuit includes a reset transistor Rtr that resets the voltage of the floating diffusion portion 103a to a predetermined voltage before charge voltage conversion for each imaging screen, and an amplification transistor Atr And a selection transistor Str for outputting the image pickup signal amplified in step 1 to the signal line at a predetermined timing. The amplification transistor Atr in this case corresponds to the source follower transistor 2, 2A or 2B.

  As described above, in the CMOS type solid-state imaging device 1, 1A or 1B, a plurality of light receiving units are provided in a matrix in the matrix direction as a photoelectric conversion unit for each pixel unit in each of the plurality of pixel units. Adjacently, a charge transfer transistor Ttr for transferring signal charges from each light receiving portion to the charge voltage converting portion (floating diffusion portion 103a) and a charge voltage converting portion (floating diffusion) by the charge transfer transistor Ttr for each light receiving portion. The signal charge transferred to the unit 103a) is converted into a voltage, and is read out as an imaging signal for each pixel unit by being amplified by an amplification transistor in accordance with the converted voltage. In the floating diffusion unit 103a, the voltage of the floating diffusion unit 103a (charge voltage conversion unit) is reset in advance to a predetermined voltage (usually a power supply voltage) by the reset transistor Rtr before the signal charge is transferred and converted into voltage. It has become.

  In the first and second embodiments, the case where the present invention is applied to the source follower transistor 2, 2A, or 2B of the CMOS solid-state imaging device 1, 1A, or 1B has been described. The present invention can also be applied to an amplification transistor of a type solid-state imaging device. That is, in the CCD type solid-state imaging device, the signal charge is read from each light receiving portion constituting each pixel, and after the vertical and horizontal charge transfer, the signal charge is converted into a voltage and amplified in accordance with the converted voltage. The present invention may be applied to a source follower transistor that constitutes the amplification transistor. For example, a CCD solid-state imaging device includes a plurality of vertical charge transfer units, each of which receives a signal charge read from a plurality of light receiving units in the vertical direction, and a plurality of vertical charge transfer units. A horizontal charge transfer unit in which each signal charge transferred by the charge transfer unit is transferred in the horizontal direction, and a signal charge transferred from the horizontal charge transfer unit is voltage-converted. And a signal output unit that is amplified and output as an imaging signal for each pixel.

  In the first and second embodiments, the present invention will be described with respect to the CMOS solid-state image sensor 1, 1A or 1B, and may be a CCD solid-state image sensor instead of the CMOS solid-state image sensor 1, 1A or 1B. As described above, in the CMOS solid-state imaging device 1, 1A, or 1B, an amplification transistor is provided for each pixel, and in the CCD solid-state imaging device, one amplification transistor that finally amplifies each signal charge. Since the direction of the source and drain of these amplification transistors is constant, it is suitable for applying the present invention. The present invention can be easily applied to other electronic circuits such as an integrated circuit other than the solid-state imaging device as long as the direction of the source / drain of the amplification transistor is constant.

(Embodiment 3)
FIG. 7 is a block diagram illustrating a schematic configuration example of an electronic information device using the CMOS solid-state imaging device 1, 1A, or 1B of Embodiments 1 and 2 of the present invention as an imaging unit as Embodiment 3 of the present invention. .

  In FIG. 7, the electronic information device 90 of the third embodiment is a solid that obtains a color image signal by performing predetermined signal processing on the imaging signal from the CMOS solid-state imaging device 1, 1 </ b> A, or 1 </ b> B of the first and second embodiments. An imaging device 91, a memory unit 92 such as a recording medium that can record data after processing the color image signal from the solid-state imaging device 91 for predetermined recording, and the color image signal from the solid-state imaging device 91. Display unit 93 such as a liquid crystal display device that can display on a display screen such as a liquid crystal display screen after predetermined signal processing for display, and predetermined signal processing for color image signals from this solid-state imaging device 91 for communication The communication unit 94 such as a transmission / reception device that can perform communication processing after printing and the color image signal from the solid-state imaging device 91 is subjected to predetermined print signal processing for printing and then printing processing is performed. And an image output unit 95 such as a printer to ability. The electronic information device 90 is not limited to this, but in addition to the solid-state imaging device 91, at least one of a memory unit 92, a display unit 93, a communication unit 94, and an image output unit 95 such as a printer. You may have.

  As described above, the electronic information device 90 includes, for example, a digital camera such as a digital video camera and a digital still camera, an in-vehicle camera such as a surveillance camera, a door phone camera, and an in-vehicle rear surveillance camera, and a video phone camera. An electronic device having an image input device such as an image input camera, a scanner device, a facsimile device, a camera-equipped mobile phone device, and a portable terminal device (PDA) is conceivable.

  Therefore, according to the third embodiment, based on the color image signal from the solid-state imaging device 91, it can be displayed on the display screen, or can be printed out on the paper by the image output unit 95. (Printing), communicating this as communication data in a wired or wireless manner, performing a predetermined data compression process in the memory unit 92 and storing it in a good manner, or performing various data processings satisfactorily Can do.

  As mentioned above, although this invention has been illustrated using preferable Embodiment 1-3 of this invention, this invention should not be limited and limited to this Embodiment 1-3. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments 1 to 3 of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention provides a semiconductor device including an amplifier circuit having one or a plurality of MOS transistors, a method for manufacturing the same, a plurality of light receiving units that photoelectrically convert image light from a subject, and a signal charge from each light receiving unit. A solid-state image sensor such as a CMOS type image sensor that amplifies the potential corresponding to 1 as an image pickup signal for each pixel by an amplifier circuit, for example, a digital video camera and a digital still camera using the solid-state image sensor as an image input device in an image pickup unit In the field of electronic information equipment such as digital cameras such as digital cameras, image input cameras such as surveillance cameras, scanner devices, facsimile devices, television telephone devices, and mobile phone devices with cameras, only the LDD region on the drain side is the other side of the gate electrode. Underneath the edge, the drain side LDD region is in plan view with the gate electrode. The source-side LDD region does not sink under one end of the gate electrode, the source-side LDD region does not overlap the gate electrode in plan view, and the source-side LDD region is one end of the gate electrode. Therefore, the defects near the source side gate end caused by ion implantation damage to the source side gate end of the transistor can be removed by a simple manufacturing process without increasing the transistor gate area as in the prior art. By reducing, random noise can be reduced effectively.

1, 1A, 1B CMOS type solid-state imaging device 2, 2A, 2B Source follower transistor (amplification transistor)
3 N-type semiconductor substrate 4 P well layer 5 Gate insulating film 6 Gate electrode 7, 8 Side wall 9 N-type diffusion layer in drain region 10 N-type diffusion layer in source region 11, 11a N-type diffusion in LDD region on drain region side Layers 12, 12a N-type diffusion layer in the LDD region on the source region side 13 Channel stop region on the drain region side 14 Channel stop region on the source region side (X) N-type diffusion layer in the LDD region on the drain region side (Y) Source region N-type diffusion layer in the LDD region on the side θ1 Tilt angle tilted toward the drain side during LDD ion implantation θ2 Tilt angle tilted toward the drain side during ion implantation 90 Electronic information equipment 91 Solid-state imaging device 92 Memory unit 93 Display unit 94 Communication 95 Image output unit

Claims (21)

  A source side LDD region is disposed between one end side of the gate electrode and the source region, a drain side LDD region is disposed between the other end side of the gate electrode and the drain region, and the LDD region on the source side is disposed. Of the region and the drain side LDD region, only the drain side LDD region is buried under the other end of the gate electrode, and the gate electrode and the drain side LDD region overlap in plan view apparatus.   2. The semiconductor device according to claim 1, wherein the source-side LDD region does not sink under one end of the gate electrode, and the one end of the gate electrode does not overlap the source-side LDD region in plan view.   The semiconductor device according to claim 1, wherein the source-side LDD region is formed shorter in the gate length direction than the drain-side LDD region.   The semiconductor device according to claim 1, wherein the source-side LDD region is formed apart from one end of the gate electrode in plan view.   A channel stop region is formed on at least the drain side of the source side and the drain side, and only the channel stop region on the drain side of the channel stop region on the source side and the channel stop region on the drain side 2. The semiconductor device according to claim 1, wherein the gate electrode and the drain-side channel stop region overlap each other in plan view under the other end of the gate electrode.   6. The semiconductor device according to claim 5, wherein the source-side channel stop region does not sink under one end of the gate electrode, and the gate electrode and the source-side channel stop region do not overlap in plan view.   The semiconductor device according to claim 5, wherein the channel stop region on the source side is formed apart from one end of the gate electrode in plan view.   6. The semiconductor device according to claim 5, wherein the channel stop region on the source side is formed shorter in the gate length direction than the channel stop region on the drain side.   The semiconductor device according to claim 1, wherein the semiconductor device is a source follower transistor constituting an amplification transistor. A plurality of light-receiving portions that photoelectrically convert incident light to provide an image are provided in a matrix in the row direction and the column direction, and an amplification transistor that amplifies each signal charge from the plurality of light-receiving portions as an image pickup signal for each pixel is provided. And
A solid-state imaging device using the semiconductor device according to claim 1 as the amplification transistor.   The solid-state imaging device according to claim 10, which is a CMOS solid-state imaging device or a CCD solid-state imaging device. Each of the pixels is
Adjacent to each of the plurality of light receiving parts, a charge transfer transistor for transferring a signal charge from the light receiving part to a charge voltage converting part,
A signal readout circuit that converts the voltage of the signal charge transferred to the charge-voltage conversion unit by the charge transfer transistor, amplifies the signal by the amplification transistor according to the converted voltage, and reads out the image pickup signal for each pixel; The solid-state imaging device according to claim 11.   For each of the plurality of light receiving units in the column direction, a plurality of vertical charge transfer units that transfer the signal charges read from the plurality of light receiving units in the vertical direction, and each of the charge transferred by the plurality of vertical charge transfer units A horizontal charge transfer unit that transfers the signal charge in the horizontal direction, and each signal charge transferred from the horizontal charge transfer unit is voltage-converted, and is amplified by the amplification transistor according to the conversion voltage and is The solid-state imaging device according to claim 11, further comprising: a signal output unit that outputs a signal as an imaging signal. A method for manufacturing the semiconductor device according to claim 1,
After the formation of the gate electrode, the LDD region is ion-implanted at the tilt angle θ1 having a tilt angle θ1 on the drain side of the gate electrode and causing shadowing by the gate electrode on the source side of the gate electrode, A method of manufacturing a semiconductor device, comprising: an LDD region forming step of forming the source-side LDD region shorter in the gate length direction than the drain-side LDD region.   The method of manufacturing a semiconductor device according to claim 14, wherein the tilt angle θ <b> 1 is an inclination of 4 to 10 degrees toward the drain side. After the LDD region forming step,
A channel stop region is ion-implanted at the tilt angle θ2 having a tilt angle θ2 on the drain side of the gate electrode, and shadowing by the gate electrode is generated on the source side of the gate electrode. The method of manufacturing a semiconductor device according to claim 14, further comprising a channel stop region forming step of forming the channel stop region on at least the drain side of the source side.   17. The method of manufacturing a semiconductor device according to claim 16, wherein the tilt angle [theta] 2 is larger than the tilt angle [theta] 1.   18. The method of manufacturing a semiconductor device according to claim 16, wherein the tilt angle θ <b> 2 is an inclination of 10 to 60 degrees toward the drain. Before the LDD region forming step,
A well layer forming step of forming a well layer by ion implantation on a semiconductor substrate;
The method for manufacturing a semiconductor device according to claim 14, further comprising a gate electrode forming step of forming a gate electrode on the well layer via a gate insulating film. After the LDD region forming step or the channel stop region forming step,
A sidewall forming step of forming sidewalls on both side surfaces of the gate electrode in the gate length direction;
17. The method of manufacturing a semiconductor device according to claim 14, further comprising: a source / drain forming step of forming a drain region and a source region by performing ion implantation on both sides of the gate electrode on which the sidewall is formed.   An electronic information device using the solid-state imaging device according to claim 10 as an image input device in an imaging unit.

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