JP2012113476A - Data storage device, memory control device, and memory control method - Google Patents

Abstract

An object of the present invention is to provide a data storage device that can reliably generate error correction code data without deteriorating write processing efficiency even when there is a channel for which valid data cannot be prepared.
According to an embodiment, a data storage device includes a write controller, an error correction controller, and a data controller. The write controller writes data in parallel to each of the non-volatile memories of a plurality of channels. The error correction controller generates error correction code data using data prepared for each channel before the write operation by the write controller. The data controller prepares the initial value data of the non-volatile memory as data to be used for the generation process of the error correction controller for a channel for which data to be written to the non-volatile memory is not prepared.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a data storage device using a nonvolatile memory as a storage medium.

  In recent years, development of an SSD (solid state drive) using a NAND-type flash memory (hereinafter sometimes simply referred to as a flash memory) as a data storage device as a storage medium has been promoted. .

  In general, in SSD, a multi-channel write operation for writing data in parallel to each flash memory provided in a plurality of channels is performed. During this write operation, error correction code data (or parity data) that can be subjected to error checking and correction (ECC) between channels is generated using data (user data) written to each channel. This error correction code data is stored in the flash memory of the ECC channel set from among a plurality of channels.

JP 2002-163243 A

  In a conventional SSD, when there is a channel that cannot prepare effective data as a write target among all channels during a multi-channel write operation, a kind of interpolation data is prepared to generate error correction code data. There is a need. In this case, the interpolation data is written to the flash memory of the channel by the multi-channel write operation. This write operation for writing interpolated data causes an increase in write processing time related to the write access speed and an increase in the number of writes related to the life of the flash memory, which causes a decrease in write processing efficiency.

  Therefore, an object of the present invention is to provide a data storage device that can reliably generate error correction code data without deteriorating write processing efficiency even when there is a channel in which valid data cannot be prepared.

  According to the embodiment, the data storage device includes a write control unit, an error correction control unit, and a data control unit. The write control means writes data in parallel to each of the non-volatile memories of a plurality of channels. The error correction control means generates error correction code data using data prepared for each channel before the write operation by the write control means. The data control means prepares the initial value data of the nonvolatile memory as data to be used for the generation process of the error correction control means for a channel for which data to be written to the nonvolatile memory is not prepared.

The block diagram for demonstrating the structure of the data storage apparatus regarding embodiment. 1 is a block diagram for explaining a configuration of a flash memory controller according to an embodiment. FIG. The conceptual diagram for demonstrating the write operation regarding embodiment. 6 is a flowchart for explaining a write operation according to the embodiment.

  Embodiments will be described below with reference to the drawings.

[Configuration of data storage device]
FIG. 1 is a block diagram illustrating a configuration of a data storage device according to the embodiment.

  As shown in FIG. 1, the data storage device of the embodiment is an SSD (solid state drive), and is a buffer memory comprising an SSD controller 10, a NAND flash memory (flash memory) 20, and a DRAM (dynamic random access memory). 21.

  The flash memory 20 is an SSD data storage medium, and includes a plurality of flash memory chips. The SSD of this embodiment is a multi-channel system of 4 channels CH0 to CH3 for convenience, and has flash memories 201 to 204 corresponding to the channels CH0 to CH3, respectively.

  The SSD controller 10 includes a flash memory controller 11, a buffer manager module 12, a host interface controller 13, and a subsystem module 14.

  The flash memory controller 11 executes read / write operation control and data transfer control of the flash memories 201 to 204 for each of the channels CH0 to CH3 (see FIG. 2). The buffer manager module 12 controls the buffer memory 21 and controls data transfer with the buffer memory. The host interface controller 13 controls the transfer of data and commands between the host system 30 and the SSD via the host interface 15. The host system 30 is, for example, a CPU of a personal computer or various digital devices.

  The subsystem module 14 is composed of a microprocessor (MPU) and executes the overall control of the SSD controller 10. The subsystem module 14 outputs, for example, commands necessary for data write operation and read operation to the flash memory controller 11 in accordance with commands from the host system 30.

(Configuration of flash memory controller)
As shown in FIG. 2, the flash memory controller 11 includes a data transfer controller (also referred to as an IOPS acceleration engine module) 100 and a memory controller for each of the channels CH0 to CH3 (hereinafter referred to as a NAND controller for convenience). 101 to 104 and an inter-channel parity controller (hereinafter referred to as an ECC controller) 110.

  The data transfer controller 100 executes data transfer control and operation control for the NAND controllers 101 to 104 and the ECC controller 110. The NAND controllers 101 to 104 execute read / write access control and data transfer control for the flash memories 201 to 204 for the channels CH0 to CH3, respectively.

  As will be described later, the ECC controller 110 generates error correcting code data that can be subjected to error correction and correction (ECC) between channels. Error correction code data (hereinafter referred to as ECC data) is, for example, parity data, and is used for error correction processing between channels by the ECC controller 110.

[Operation of flash memory controller]
First, a normal write operation in a multi-channel SSD will be described.

  In the multi-channel SSD, the SSD controller 10 transfers data to be written stored in the buffer memory 21 to the flash memory controller 11 in response to a write command issued from the host system 30.

  In the flash memory controller 11, as shown in FIG. 2, when valid data is prepared as a write target for each of the channels CH <b> 0 to CH <b> 3, the data transfer controller 100 sends a data transfer control signal 120 to the NAND controllers 101 to 104. To instruct data transfer for a write operation. The NAND controllers 101-104 transfer the prepared data to the flash memories 201-204. Thereby, the prepared data is written in parallel to the flash memories 201 to 204 for the channels CH0 to CH3.

  In this embodiment, the data transferred from the buffer manager module 12 is prepared as valid data in the NAND controllers 101 to 103 of the channels CH0 to CH2. This data is user data transferred from the host system 30 and stored in the buffer memory 21.

  On the other hand, ECC data (parity data) generated by the ECC controller 110 is prepared as valid data in the NAND controller 104 of the channel CH3. Accordingly, when data is written in parallel to the other flash memories 201 to 203, ECC data is written to the flash memory 204 of the channel CH3.

  The ECC controller 110 uses each user data prepared in the NAND controllers 101 to 103 of the channels CH0 to CH2 to generate ECC data used for error correction processing between channels, and sends it to the NAND controller 104 of the channel CH3. Forward.

  Next, the write operation and ECC data generation processing of this embodiment will be described with reference to the flowcharts of FIGS.

  In the present embodiment, a case of a write operation when a flash command is issued will be described. As shown in FIG. 4, when a normal write command is issued, the above-described normal write operation is executed (block 405).

  The flash command is issued from the MPU of the subsystem module 14 to protect data that has not been written in the flash memories 201 to 204, for example, when the power is turned off (YES in block 400). When a flash command is issued, the flash memory controller 11 forcibly causes each channel to execute a write operation even when there is a channel for which valid data is not prepared as a write target.

  In the flash memory controller 11, the data transfer controller 100 detects a channel (here, CH2) in which valid data is not prepared as a write target among the channels CH0 to CH2 (block 401). As described above, the channel CH3 is a channel to which ECC data is assigned as valid data.

  FIG. 3 is a conceptual diagram showing the write operation for each step (STEP1, STEP2, STEP3) when the flash command is issued. That is, in step STEP1, user data 301 and 302 are prepared as valid data in the NAND controllers 101 and 102 of the channels CH0 and CH1, respectively. On the other hand, in the NAND controller 103 of the channel CH2, user data is not prepared, and there is no valid data to be written.

  The ECC controller 110 generates ECC data in response to the issuance of the flash command, and executes a process of transferring it to the NAND controller 104 of the channel CH3 (step STEP2). At this time, the ECC controller 110 is notified from the data transfer controller 100 that the preparation of data of the channels CH0 to CH2 has been completed. Thus, the ECC controller 110 can generate ECC data and transfer it to the NAND controller 104 of the channel CH3 before the write operation to the flash memories 201 to 204 is performed.

  The data transfer controller 100 prepares initial value data for the NAND controller 103 of the channel CH2 for which user data is not prepared (block 402). This initial value data is the storage state of the flash memory immediately after the erasing process, and is normally all 1 stored value. In the SSD, an erasure process is executed before writing data to the flash memory. Therefore, immediately before the write operation, the flash memory is in a state where the initial value (all 1) is stored.

  When the preparation of user data to be written and initial value data is completed in the channels CH0 to CH2, the ECC controller 110 generates ECC data using these data (block 403). That is, as shown in FIG. 3, the ECC controller 110 generates ECC data using user data 301, 302 and initial value data 303, which are valid data of the channels CH0 and CH1, and generates a NAND controller of the channel CH3. It transfers to 104 (step STEP2).

  The data transfer controller 100 outputs a data transfer control signal 120 to the NAND controllers 101, 102, and 104 of the channels CH0, CH1, and CH3 to instruct data transfer for a write operation (block 404).

  That is, as shown in FIG. 3, the NAND controllers 101, 102, 104 transfer the prepared data 301, 302 and ECC data to the flash memories 201, 202, 204 (step STEP3). As a result, the prepared data 301, 302 and ECC data are written in parallel to the flash memories 201, 202, 204 of the channels CH0, CH1, CH3.

  Here, as shown in FIG. 3, since no valid data is prepared as a write target in the channel CH2, the write operation is not executed in the flash memory 203 of the channel CH2. That is, the flash memory 203 of the channel CH2 is in a storage state immediately after the erasing process, that is, a state in which initial value data is stored.

  The ECC controller 110 corrects errors between channels using ECC data stored in the flash memory 204 of the channel CH3 when data is read from the flash memories 201 to 204 of the channels CH0 to CH3 by the read operation. Processing can be executed.

  As described above, according to the present embodiment, in a multi-channel SSD, for example, even when there is a channel for which valid data (user data) to be written is not prepared when a flash command is issued, In contrast, initial value data is prepared as interpolation data. Thereby, the ECC controller 110 can generate ECC data effective for error correction processing between channels using the effective data and initial value data prepared in each channel.

  Furthermore, in this embodiment, when data is written in parallel to the flash memory of each channel, it is not necessary to perform a write operation for a channel (CH2) for which valid data to be written is not prepared. That is, since the data prepared for the channel (CH2) is the initial value data, the write access to the flash memory (203) becomes unnecessary. Accordingly, the write operation of the channel (CH2) can be omitted in the multi-channel write operation, and as a result, the speed of the write operation can be increased. In addition, since the number of writes to the flash memory can be reduced, there is an effect that the life of the flash memory can be extended.

  That is, when arbitrary data other than the initial value data is prepared as interpolation data, in order to generate ECC data effective for error correction processing between channels, the arbitrary data is stored in the flash memory (203) of the channel (CH2). It is necessary to write to. In the present embodiment, initial value data that does not need to be written to the flash memory (203) is used as the interpolation data, so that the write operation can be omitted. In other words, the initial value data is data that can be read from the flash memory without executing the write operation.

  In short, by using the initial value data as the interpolation data, the write processing time related to the write access speed can be reduced and the number of writes related to the life of the flash memory can be reduced. Improvements can be made.

  In the present embodiment, the initial value data is prepared by the data transfer controller 100, but a configuration prepared by the ECC controller 110 as fixed data in advance may be used. In this case, the ECC controller 110 uses the initial value data prepared in advance as the interpolation data of the channel (CH2) in response to the notification of the channel (CH2) for which data is not prepared from the data transfer controller 100. ECC data is generated.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 ... SSD controller, 11 ... Flash memory controller,
12 ... Buffer manager module, 13 ... Host interface controller,
14 ... subsystem module, 15 ... host interface,
20, 201-204 ... NAND type flash memory, 21 ... buffer memory (DRAM),
30 ... Host system, 100 ... Data transfer controller,
101-104 ... Memory controller (NAND controller),
110: Inter-channel parity controller (ECC controller).

Claims (10)

Write control means for writing data in parallel to each of the non-volatile memories of a plurality of channels;
Error correction control means for generating error correction code data using data prepared for each channel before the write operation by the write control means;
A data storage device comprising data control means for preparing initial value data of the nonvolatile memory as data to be used for generation processing of the error correction control means for a channel for which data to be written to the nonvolatile memory is not prepared . The data control means includes
The data storage device according to claim 1, wherein stored value data after erasure processing on the nonvolatile memory is used as the initial value data. A non-volatile memory channel in which the error correction code data is written among the plurality of channels is set,
The light control means includes
The data to be written and the error correction code data are written in parallel to a nonvolatile memory of each channel except for a channel in which the data to be written is not prepared. The data storage device according to any one of the above. The data control means includes
4. The data storage device according to claim 1, wherein when the write control unit executes a write control according to a flash command, a process for preparing the initial value data is executed. 5. The data control means includes
5. The apparatus according to claim 1, further comprising means for notifying the error correction control means that preparation of the data to be written and the initial value data has been completed as data necessary for generating the error correction code data. The data storage device according to any one of the above. A memory control device applied to a data storage device having a non-volatile memory of a plurality of channels,
Write control means for writing data in parallel to the nonvolatile memories of the plurality of channels;
Error correction control means for generating error correction code data using data prepared for each channel before the write operation by the write control means;
Data control means for preparing data to be written in the nonvolatile memory for each channel with respect to the write control means and preparing initial value data in the nonvolatile memory for a channel in which the data to be written cannot be prepared. Memory control device. The data control means includes
The memory control device according to claim 6, wherein stored value data after erasure processing for the nonvolatile memory is used as the initial value data. A non-volatile memory channel in which the error correction code data is written among the plurality of channels is set,
The light control means includes
The data of the write target and the error correction code data are written in parallel to a nonvolatile memory of each channel except a channel where the data of the write target is not prepared. The memory control device according to any one of the above. The data control means includes
9. The memory control device according to claim 6, wherein when the write control unit executes a write control according to a flash command, a process for preparing the initial value data is executed. 10. A memory control method applied to a data storage device having a non-volatile memory of a plurality of channels,
In order to write data to each nonvolatile memory of a plurality of channels in parallel, prepare data to be written for each channel,
For the channel for which the data to be written is not prepared, prepare initial value data of the nonvolatile memory,
A memory control method for generating error correction code data using write target data and the initial value data prepared for each channel.

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