JP2012231224A - Detection circuit for detecting damage to semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To be able to directly detect damage to an element being monitored.SOLUTION: Monitoring wiring is installed in the vicinity of a semiconductor element being monitored. Clock output means for outputting a predetermined clock is connected to one end of the monitoring wiring, and monitoring means is connected to the other end of the monitoring wiring. The monitoring means is caused to monitor propagation of the clock output from the clock output means to the monitoring wiring. When it is detected that propagation of the clock has ceased, the monitoring means is caused to output a damage notification signal notifying that the semiconductor element being monitored has been damaged.

Description

  The present invention relates to a technique for detecting destruction of a semiconductor element constituting an output buffer circuit of an amplifier and a protection circuit between power supplies.

  For example, when a power supply fault or ground fault occurs in an output buffer circuit of a class D amplifier that drives a load such as a speaker, an excess is caused in a semiconductor element such as an output transistor constituting the output buffer circuit or a diode constituting a protection circuit between power supplies. A current flows, and these semiconductor elements may be destroyed. Various techniques for detecting the destruction of a semiconductor element or the occurrence of an overcurrent that destroys the semiconductor element have been proposed in the past. Examples of the techniques include those disclosed in Patent Document 1 and Patent Document 2. It is done. In Patent Document 1, a potential difference between a source and a drain of a semiconductor element to be monitored is detected and compared with a predetermined threshold value. If the former exceeds the latter, the semiconductor element is turned off as a certain short circuit has occurred. The technology to make is disclosed. Patent Document 2 discloses a technique for detecting the temperature of a semiconductor element to be monitored by a temperature detection circuit, and cutting off a current flowing through the semiconductor element when a temperature rise of the semiconductor element is detected by the temperature detection circuit. Has been.

JP 2002-171140 A JP 2001-168286 A

  However, the techniques disclosed in Patent Document 1 and Patent Document 2 detect the occurrence of an event that can cause destruction of a semiconductor element such as an overcurrent or abnormal heat generation. It does not directly detect what happened. For this reason, there is a problem that when it is required to notify an external device that a semiconductor element (or a device including the semiconductor element) has actually been destroyed, the request cannot be met.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique that makes it possible to directly detect the destruction of a semiconductor element to be monitored.

  In order to solve the above problems, the present invention provides a monitor wiring laid near the semiconductor element to be monitored, a clock output means connected to one end of the monitor wiring and outputting a clock to the monitor wiring, A means for monitoring the propagation of a clock connected to the other end of the monitor wiring and outputted by the clock output means, and notifies the destruction of the semiconductor element when it is detected that the propagation of the clock is interrupted. And a monitoring circuit for outputting a breakdown detection signal, and a detection circuit for detecting breakdown of a semiconductor element.

  It is generally known that when a semiconductor element is destroyed by an overcurrent or the like, it generates abnormal heat or explodes around it. The monitoring wiring of the detection circuit of the present invention is laid in the vicinity of a semiconductor element to be monitored (for example, an output transistor constituting an output stage of an amplifier, a diode constituting a protection circuit between power supplies, etc.). For this reason, when the semiconductor element is destroyed by an overcurrent or the like, the semiconductor element may be melted due to abnormal heat generation, partially broken due to the explosion of the semiconductor element, or cut by debris scattered by the explosion. The monitor wiring is disconnected due to various causes. When the monitor wiring is disconnected, the clock output from the clock output means does not propagate to the monitoring means, and the monitoring means outputs the destruction detection signal. As described above, according to the detection circuit of the present invention, it is possible to directly detect disconnection of the monitoring wiring (that is, destruction of the semiconductor element to be monitored) through the presence or absence of the propagation of the clock. Only when the element is actually destroyed, emergency processing such as emergency stop of the amplifier can be executed.

  In a more preferred aspect, the clock output means and the monitoring means are formed in a chip area different from the semiconductor element to be monitored. In general, the protection circuit between power supplies and the output transistor are often formed in a high-breakdown-voltage element region, and the high-breakdown-voltage element region is formed on the outer periphery of a semiconductor chip, and a low voltage composed of a semiconductor element having a lower operating voltage is provided inside An element region is often formed. For this reason, if the clock output means and the monitoring means are formed in the low-voltage element region, these means are formed at positions distant from the monitored element, and these means are each a semiconductor element to be monitored. It becomes possible not to get involved in the destruction of. Needless to say, even when the above-described means and the semiconductor element to be monitored are formed in the same chip region, it is preferable to form these means at positions away from the semiconductor element to be monitored. This is to prevent the above means from being involved in the destruction of the semiconductor element to be monitored.

  In a further preferred aspect, the clock output means and the monitoring means have different operating voltages. For example, when the output transistor constituting the output stage of the class D amplifier is to be monitored, if the operating voltage of the clock output means is equal to the operating voltage of the output transistor, the pulse generated by the PWM oscillation circuit is used as the clock. Can be used.

It is a figure which shows an example of the semiconductor chip containing the detection circuit 31 of one Embodiment of this invention. 3 is a diagram illustrating a configuration example of the detection circuit 31. FIG. 3 is a diagram illustrating an example of a signal waveform in each part of the detection circuit 31. FIG.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1A is a diagram illustrating an example of a semiconductor chip including a detection circuit 31 according to an embodiment of the present invention. This semiconductor chip is a digital amplifier that drives a load such as a speaker, for example. As shown in FIG. 1A, in the direction from the center of the chip to the outside, a low-voltage element region 30, a high-voltage element region 20, and It has a PAD region 10.

  In the PAD region 10, an output PAD, a power supply PAD, a power protection circuit (all not shown), and the like are formed. The inter-power supply protection circuit is, for example, interposed between a high-potential power line and a low-potential power line for supplying an operating voltage to the digital amplifier, and a current flows from the low-potential power line to the high-potential power line. It is a diode that regulates the flow of water. In the high breakdown voltage element region 20, an output transistor (indicated as “PMOS” or “NMOS” in FIG. 1A) constituting an output buffer circuit serving as an output stage of the digital amplifier is formed. In the element region 30, a detection circuit 31 for detecting the destruction of the diode and the output transistor is formed. As shown in FIG. 1A, in this embodiment, the detection circuit 31 is formed in a chip region different from the semiconductor element to be monitored, and this is one of the features of this embodiment. Since the detection circuit 31 of this embodiment is formed in a chip region different from the semiconductor element to be monitored, it is formed at a position away from the output transistor to be monitored. For this reason, even when the semiconductor element to be monitored is destroyed, the detection circuit 31 is not involved in the destruction of the semiconductor element to be monitored and is not damaged.

As shown in FIG. 1A, the detection circuit 31 is connected to two systems of monitoring wirings 40-1 and 40-2 for detecting destruction of the inter-power supply protection circuit and the output transistor. As shown in FIG. 1A, the monitor wirings 40-1 and 40-2 are wired between the PAD region 10 and the high-breakdown-voltage element region 20 and along the periphery of the output transistor. That is, the monitor wirings 40-1 and 40-2 are laid in the vicinity of the semiconductor element to be monitored. In this way, the monitoring wirings 40-1 and 40-2 are laid in the vicinity of the semiconductor element to be monitored because when the inter-power supply protection circuit or the output transistor is destroyed, it is involved in the destruction and is disconnected. This is to make it happen. For example, when an excessively large current flows through the semiconductor element to be monitored and abnormal heat is generated, the monitoring wirings 40-1 and 40-2 are fused by the heat. Further, if the semiconductor element to be monitored is broken by surrounding and exploding, a part of the monitoring wirings 40-1 and 40-2 may be lost due to being caught in the explosion, or fragments scattered by the explosion. Disconnected by. In the present embodiment, the case where the monitor wirings 40-1 and 40-2 are wired as shown in FIG. 1A will be described. However, the purpose (that is, the breakage of the semiconductor element to be monitored is involved in disconnection). Any layout is possible as long as the wiring layout can achieve this. For example, the layout shown in FIG. As shown in FIGS. 1A and 1B, in the region between the PAD region 10 and the high breakdown voltage device region 20, the monitor wiring is extended so as to extend along the semiconductor element to be monitored. On the other hand, the wiring between the high breakdown voltage element region 20 and the low voltage element region 30 is not made such wiring because the current output to the outside in the portion of the high breakdown voltage element region 20 close to the PAD region 10. This is because the semiconductor element is likely to be concentrated and the semiconductor element is likely to be destroyed. On the other hand, the current is not concentrated in the region close to the low-voltage element region 30, and the semiconductor element is hardly destroyed. The detection circuit 31 of the present embodiment directly detects that the monitored semiconductor element is actually destroyed by detecting disconnection of the monitor wiring 40-1 or 40-2.
Hereinafter, the configuration and operation of the detection circuit 31 will be mainly described.

  FIG. 2 is a diagram illustrating a configuration example of the detection circuit 31. In FIG. 2, only the configuration for detecting the presence or absence of disconnection of the monitor wiring 40-1 is illustrated, but the disconnection of the monitor wiring 40-2 can be detected by the same configuration. . As shown in FIG. 2, the detection circuit 31 includes a high voltage element circuit 310A, a low voltage element circuit 310B, and a level shift circuit 310C. The high breakdown voltage element circuit 310A is a circuit that operates with the same power supply system as the output transistor. As shown in FIG. 2, high withstand voltage element circuit 310A includes N-channel field effect transistors 312N and 314N, P-channel field effect transistors 316P, 318P and 320P, AND gate 322, output buffer 324, inverter 326, Is included.

  A pulse generated by a PWM oscillation circuit (not shown) for driving the digital amplifier is supplied as a clock CLK1 to one input terminal of the AND gate 322, and a power-down signal PDN is supplied to the other input terminal. Here, the power-down signal PDN is a signal that is linked to the operation and stop of the digital amplifier. When the digital amplifier is operating, the power-down signal PDN is at a high level, and conversely, the digital amplifier is stopped. Then, the power-down signal PDN becomes a low level. One end of the monitor wiring 40-1 is connected to the output terminal of the AND gate 322. Therefore, when the digital amplifier is in operation, the clock CLK1 is sent from the AND gate 322 to the monitor wiring 40-1. In this manner, the AND gate 322 serves as a clock output unit that outputs a predetermined clock (clock CLK1 in this embodiment) to the monitor wiring 40-1.

  The other end of the monitor wiring 40-1 is connected to the input terminal of the output buffer 324. Therefore, in the state where the digital amplifier is operating (that is, the state where the power down signal PDN is at a high level), the clock CLK1 is output from the output buffer 324 unless the monitor wiring 40-1 is disconnected. The On the other hand, when the monitor wiring 40-1 is disconnected, the output signal of the output buffer 324 is stuck to the High level. The reason is as follows.

  P-channel field effect transistors 320P and 318P are interposed in series between the input terminal of the output buffer 324 and a high potential power supply line (not shown) for supplying an operating voltage to the digital amplifier. As shown in FIG. 2, the P-channel field effect transistor 318P and the P-channel field effect transistor 316P constitute a current mirror circuit (hereinafter referred to as a first current mirror circuit). On the other hand, a power-down signal PDN that has been inverted by inverter 326 is applied to the gate of P-channel field effect transistor 320P. Therefore, the P-channel field effect transistor 320P is always kept on while the digital amplifier is operating.

  The P-channel field effect transistor 316P and the N-channel field effect transistor 314N are inserted in series between a high potential power line and a low potential power line for supplying an operating voltage to the digital amplifier. As shown in FIG. 2, the gate of the P-channel field effect transistor 316P is connected to the common connection point of the drains of the P-channel field effect transistor 316P and the N-channel field effect transistor 314N. The gate of the P-channel field effect transistor 318P is connected. Thus, the first current mirror circuit is formed by the P-channel field effect transistors 316P and 318P.

  As shown in FIG. 2, the N-channel field effect transistor 314N forms a current mirror circuit (hereinafter referred to as a second current mirror circuit) together with the N-channel field effect transistor 312N. More specifically, the source of the N-channel field effect transistor 312N is connected to the low-potential power supply line, and the drain is connected to a constant current source (not shown) that outputs the reference current IREF. The gate of the N-channel field effect transistor 312N is connected to the same drain, and the gate of the N-channel field effect transistor 314N is also connected to the same drain. Therefore, the reference current IREF output from the constant current source is supplied to the drain-source current of the N-channel field effect transistor 314N (ie, the drain-source current of the P-channel field effect transistor 316P) by the second current mirror circuit. And the gate voltage of the P-channel field effect transistor 318P is adjusted by the first current mirror circuit so that a drain-source current equal to the reference current IREF flows, and the P-channel field effect transistor 318P is turned on. . As described above, since the P-channel field effect transistor 320P is always on while the digital amplifier is in operation, the potential of the input terminal of the output buffer 324 is in a state where the monitor wiring 40-1 is disconnected. Is substantially equal to the potential of the high potential power supply line. As a result, when the monitor wiring 40-1 is disconnected, the output signal A of the output buffer 324 is stuck to the high level.

  The output signal A of the high withstand voltage element circuit 310A (more precisely, the output buffer 324 of the same circuit) is given to the low voltage element circuit 310B through the level shift by the level shift circuit 310C. As shown in FIG. 2, the low voltage element circuit 310B includes an AND gate 342, D-flip flops (indicated as “DF” in FIG. 2) 344 and 346, an inverter 348, an emergency stop processing circuit 350, Is included.

  The power down signal PDN is applied to one input terminal of the AND gate 342, and the output signal A of the output buffer 324 is applied to the other input terminal through a level shift by the level shift circuit 310C. The output terminal of the AND gate 342 is connected to the reset terminal rn of the D-flip flop 344. As shown in FIG. 2, the reset terminal rn of the D-flip flop 344 is active low, and the D-flip flop 344 is reset when the output signal of the AND gate 342 changes from the high level to the low level. Since the output signal of the AND gate 342 is a logical product signal of the power down signal PDN and the output signal A of the output buffer 324, the power down signal PDN is always maintained at a high level when the digital amplifier is operating. In this state, the output signal of the AND gate 342 is equal to the output signal A of the output buffer 324. Therefore, in a state where the digital amplifier is in operation, the D-flip flop 344 is reset in synchronization with the output signal A switching from the high level to the low level.

  The data input terminal d of the D flip-flop 344 is connected to a high potential power line for supplying an operating voltage (voltage lower than the operating voltage of the digital amplifier) to the low voltage element circuit 310B, and the clock terminal c Is supplied with a clock CLK2 having a longer cycle than the clock CLK1. Note that the operating voltage of the low-voltage element circuit 310B may be generated from the operating voltage of the digital amplifier using a regulator or the like. The D flip-flop 344 holds the signal value of the signal input to the data input terminal d every time the clock CLK2 rises while the output signal of the AND gate 342 is at the high level, and corresponds to the held signal value. Processing to output the output signal B is performed. When the output signal of the AND gate 342 changes from the High level to the Low level, the D-flip flop 344 resets the held signal value to zero.

  The data input terminal d of the D flip-flop 346 is supplied with the output signal B of the D flip-flop 344, the clock terminal c is supplied with the clock CLK2, and the reset terminal rn is supplied with the power down signal PDN. It is done. Similarly to the reset terminal rn of the D-flip flop 344, the reset terminal rn of the D-flip flop 346 is also low active. Therefore, the D flip-flop 346 is reset when the power-down signal PDN is switched from the high level to the low level, while the power-down signal PDN is at the high level (that is, when the digital amplifier operates). The resetting is not performed while the signal value of the output signal B is held and output in synchronization with the rising edge of the clock CLK2. As shown in FIG. 2, the output signal of D-flip flop 346 is inverted by inverter 348 and applied to emergency stop processing circuit 350 as destruction detection signal OUT_N.

The emergency stop processing circuit 350 is an emergency stop signal (for example, a signal for forcibly turning off the output transistor or the like) for emergency stop of the digital amplifier when the destruction detection signal OUT_N is changed from the High level to the Low level. ) And an emergency stop process for notifying that the semiconductor element to be monitored has been destroyed. That is, in the present embodiment, the change in the signal level of the breakdown detection signal OUT_N from the high level to the low level means that the monitored semiconductor element is destroyed, and the emergency stop processing circuit 350 is excluded from the low voltage element circuit 310B. The portion monitors the propagation of the clock output to the monitoring wiring 40-1 by the clock output means, and notifies the destruction of the semiconductor element to be monitored when it is detected that the propagation of the clock has stopped. It plays the role of a monitoring means for outputting a destruction detection signal.
The above is the configuration of the detection circuit 31.

  Next, the operation of the detection circuit 31 will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of a signal waveform in each part of the detection circuit 31. More specifically, FIG. 3A shows a signal at each part of the detection circuit 31 when the monitoring wiring 40-1 is not broken (that is, when the semiconductor element to be monitored is not broken). FIG. 3B is a diagram illustrating an example of a waveform, and FIG. 3B is a signal waveform in each part of the detection circuit 31 when the monitoring wiring 40-1 is disconnected (that is, when the element to be monitored is destroyed). It is a figure which shows an example. Although not shown in both FIGS. 3A and 3B, the power-down signal PDN is maintained at a high level.

  Under the condition that the monitor wiring 40-1 is not disconnected, as shown in FIG. 3A, the clock CLK1 is supplied from the AND gate 322 to the output buffer 324 via the monitor wiring 40-1, The clock CLK1 itself is output from the output buffer 324 as the output signal A. On the other hand, in the low voltage element circuit 310B, when the power down signal PDN is at a high level, the output signal A is given to the reset terminal of the D flip-flop 344. Under the condition that the monitor wiring 40-1 is not disconnected, as shown in FIG. 3A, the output signal A is equal to the clock CLK1, and periodically switches between the high level and the low level. While the signal level of the output signal A is high level, the D-flip flop 344 performs processing to hold and output the signal value of the signal input to the data input terminal every time the clock CLK2 rises. When the signal level of the output signal A is switched from the high level to the low level, the D-flip flop 344 is reset.

  As a result, as shown in FIG. 3A, the output signal B of the D-flip flop 344 rises in synchronization with the rise of the clock CLK2 during the period when the clock CLK1 is at the high level, and the output signal A (clock CLK1) falls in synchronization with switching from High level to Low level. As described above, since the clock CLK2 has a longer period than the clock CLK1, the output signal B is always at the Low level when the clock CLK2 rises next time. For this reason, the high-level signal value is not held in the D-flip flop 346 under the condition that the disconnection in the monitor wiring 40-1 does not occur. That is, the output signal of the D-flip flop 346 does not become a high level and the breakdown detection signal OUT_N does not become a low level under a situation where no disconnection occurs in the monitor wiring 40-1. Accordingly, the emergency stop process is not executed by the emergency stop processing circuit 350 under the situation where the monitor wiring 40-1 is not disconnected.

  On the other hand, when the semiconductor element to be monitored is destroyed and the monitoring wiring 40-1 is disconnected due to the destruction, the output signal A of the output buffer 324 is stuck to the high level. In this state, the D-flip flop 344 is not reset. Since the D-flip flop 344 is not reset, the signal value held at the rising edge of the first clock CLK2 is continuously held after the breakdown occurs. As a result, when the clock CLK2 rises next time, the output signal B of the D-flip flop 344 is at a high level, and the output signal of the D-flip flop 346 is also at a high level. As a result, the destruction detection signal OUT_N becomes low level, and the emergency stop processing circuit 350 executes emergency stop processing.

  As described above, according to the present embodiment, it is possible to directly detect the destruction of the semiconductor element to be monitored by detecting the disconnection of the monitor wiring 40-1 (or 40-2). An emergency stop process such as stopping the drive of the amplifier can be executed only when the semiconductor element is actually destroyed.

Although one embodiment of the present invention has been described above, the following modifications may of course be added to this embodiment.
(1) In the above-described embodiment, the operating voltage of the clock output means and the operating voltage of the monitoring means are different from each other.
(2) In the above-described embodiment, the clock output means and the monitoring means are formed in the low-voltage element region. Thus, even when the clock output means and the monitoring means are formed in the same chip area as the monitoring target element, both the clock output means and the monitoring means can be formed at positions away from the monitoring target element. Needless to say, it is preferable. This is to prevent these means from being involved in the destruction of the element to be monitored.
(3) In the embodiment described above, two systems of monitoring wiring are connected to one detection circuit 31, but only one system of monitoring wiring may be connected to the detection circuit 31, or three or more systems. But of course.

  DESCRIPTION OF SYMBOLS 10 ... PAD area | region, 20 ... High voltage | pressure-resistant element area | region, 30 ... Low voltage element area | region, 31 ... Detection circuit, 40-1, 40-2 ... Monitoring wiring, 310A ... High voltage | pressure-resistant element circuit, 310B ... Low voltage element circuit, 310C ... Level shift circuit, 312N, 314N ... N channel field effect transistor, 316P, 318P, 320P ... P channel field effect transistor, 322, 342 ... AND gate, 326, 348 ... Inverter, 324 ... Output buffer, 344, 346 ... D-flip-flop, 350... Emergency stop processing circuit.

Claims (3)

Monitoring wiring laid near the semiconductor element to be monitored;
A clock output means connected to one end of the monitor wiring and outputting a clock to the monitor wiring;
A means for monitoring the propagation of a clock connected to the other end of the monitor wiring and outputted by the clock output means, and notifies the destruction of the semiconductor element when it is detected that the propagation of the clock is interrupted. Monitoring means for outputting a destruction detection signal to the effect;
A detection circuit comprising:   The detection circuit according to claim 1, wherein the clock output unit and the monitoring unit are formed in a chip area different from the semiconductor element to be monitored. The detection circuit according to claim 1, wherein the clock output unit and the monitoring unit have different operating voltages.

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