JP2013045789A - Manufacturing method of silicon carbide semiconductor device - Google Patents
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Abstract
【課題】炭化ケイ素(000−1)面にウェット雰囲気で酸化されたゲート絶縁膜の上に、ポリシリコンを不活性ガスを使用した減圧CVD法で成膜しても、界面準位密度の増加を抑制し、MOS界面特性の劣化を防止して、炭化ケイ素半導体装置の品質を高める。
【解決手段】炭化ケイ素半導体の(000−1)面から0°ないし8°傾いた面からなる半導体領域上に接するようにゲート絶縁膜を形成し、減圧CVD法を用いて、ゲート絶縁膜上に接するようにポリシリコンのゲート導電膜を成膜する際、不活性ガスを供給しながら安定化させる目標炉内温度を450℃以上550℃以下にするとともに、原料ガスを注入しながらポリシリコンのゲート導電膜の生成を行う工程、さらには、このゲート導電膜の生成終了後、原料ガスを不活性ガスに置換する工程を含め、炉内温度を一貫してこの目標炉内温度に維持した。
【選択図】図1Increase in interface state density even when polysilicon is formed on a gate insulating film oxidized in a wet atmosphere on a silicon carbide (000-1) surface by a low pressure CVD method using an inert gas. To suppress the deterioration of the MOS interface characteristics and improve the quality of the silicon carbide semiconductor device.
A gate insulating film is formed so as to be in contact with a semiconductor region having a surface inclined by 0 ° to 8 ° with respect to a (000-1) plane of a silicon carbide semiconductor, and is formed on the gate insulating film by using a low pressure CVD method. When the polysilicon gate conductive film is formed in contact with the substrate, the target furnace temperature to be stabilized while supplying an inert gas is set to 450 ° C. or more and 550 ° C. or less, and the polysilicon gas is injected while injecting the source gas. The furnace temperature was consistently maintained at the target furnace temperature, including the step of generating the gate conductive film, and the step of replacing the source gas with an inert gas after the generation of the gate conductive film.
[Selection] Figure 1
Description
本発明は炭化ケイ素基板を使用した半導体装置の製造方法に関わり、特にゲート絶縁膜の上に減圧CVD法で導電膜を成膜する工程に特徴を有する、炭化ケイ素半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device using a silicon carbide substrate, and more particularly to a method for manufacturing a silicon carbide semiconductor device characterized by a step of forming a conductive film on a gate insulating film by a low pressure CVD method.
炭化ケイ素基板を用いた半導体デバイスの研究開発が進められている。炭化ケイ素はシリコンと同様に熱酸化で絶縁膜を形成可能であるが、結晶面や酸化方法によってMOS界面のチャネル移動度が異なるという特性がある。
炭化ケイ素基板の(000−1)面はウェット雰囲気で酸化すると(0001)面に比べ高いチャネル移動度を示すとされている。なお、チャネル移動度を代替的に評価する指標として界面準位密度があり、一般的には、界面準位密度が小さい方がチャネル移動度は大きくなる傾向が知られている。
Research and development of semiconductor devices using silicon carbide substrates are underway. Silicon carbide can form an insulating film by thermal oxidation like silicon, but has a characteristic that the channel mobility at the MOS interface differs depending on the crystal plane and the oxidation method.
It is said that the (000-1) plane of a silicon carbide substrate exhibits higher channel mobility than the (0001) plane when oxidized in a wet atmosphere. Note that an interface state density is an alternative index for evaluating channel mobility. Generally, it is known that the channel mobility tends to increase as the interface state density decreases.
このような炭化ケイ素基板を用いた半導体デバイスの製造方法に関し、下記特許文献1には、界面準位密度を低下させるために、炭化ケイ素(000−1)面をウェット雰囲気で酸化することにより高いチャネル移動度を得る方法が示されており、具体的には、ゲート酸化後に水素あるいは水蒸気雰囲気中でアニールを行っている。 With regard to a method for manufacturing a semiconductor device using such a silicon carbide substrate, Patent Document 1 listed below shows a high value by oxidizing the silicon carbide (000-1) surface in a wet atmosphere in order to reduce the interface state density. A method for obtaining channel mobility is shown. Specifically, annealing is performed in a hydrogen or water vapor atmosphere after gate oxidation.
炭化ケイ素基板の(000−1)面をウェット雰囲気で酸化して得られたMOS界面の界面準位密度は、後工程の不活性ガス雰囲気での熱処理、例えばメタルのオーミックコンタクトを形成するための不活性ガス中のアニールで大きくなり、MOS界面特性が劣化することが知られている。
すなわち、ウェット雰囲気の酸化で界面準位密度が低減されるのは、水素あるいは水酸基が界面準位を終端するためであるといわれているが、不活性ガス中のアニールにより、終端している水素あるいは水酸基が脱離することにより界面準位密度が大きくなり、MOS界面特性が劣化するものと推測されている。
The interface state density of the MOS interface obtained by oxidizing the (000-1) surface of the silicon carbide substrate in a wet atmosphere is a heat treatment in an inert gas atmosphere in a later step, for example, for forming an ohmic contact of metal. It is known that the MOS interface characteristics deteriorate due to an increase in annealing in an inert gas.
That is, it is said that the interface state density is reduced by oxidation in a wet atmosphere because hydrogen or a hydroxyl group terminates the interface state, but the hydrogen terminated by annealing in an inert gas. Alternatively, it is presumed that the interface state density is increased by desorption of the hydroxyl group, and the MOS interface characteristics are deteriorated.
この熱アニールによるMOS界面特性劣化は、炭化ケイ素(0001)面上に作製したMOSデバイスでは発生しないため、炭化ケイ素(000−1)面上と(0001)面上のMOSデバイスではデバイスプロセスに異なった工夫が必要となる。 This MOS interface characteristic degradation due to thermal annealing does not occur in MOS devices fabricated on the silicon carbide (0001) surface, so the device process differs between the MOS devices on the silicon carbide (000-1) surface and the (0001) surface. Need to be devised.
ところで、ゲート絶縁膜の上に形成される導電膜(ゲート電極)としては、アルミニウムなどの金属、ポリシリコンあるいはポリシリコンと金属との溶融材料などが用いられるが、ポリシリコンを用いる場合、減圧CVD法を用いてゲート絶縁膜上に形成される。減圧CVD法では、反応炉内を真空ポンプで減圧して原料ガス(反応ガス)としてシランガス(SiH4)を流し、膜厚の均一性を図っている。その際、所望の成膜速度が得られるよう、最適温度とされる600℃前後の成膜温度で形成していた。 By the way, as the conductive film (gate electrode) formed on the gate insulating film, a metal such as aluminum, polysilicon, or a molten material of polysilicon and metal is used. It is formed on the gate insulating film using a method. In the low pressure CVD method, the inside of a reaction furnace is depressurized with a vacuum pump, and silane gas (SiH 4 ) is supplied as a source gas (reaction gas) to achieve a uniform film thickness. At that time, the film was formed at a film forming temperature of about 600 ° C., which is the optimum temperature, so as to obtain a desired film forming speed.
同一の条件で(000−1)面をウェット雰囲気で酸化して得られたMOS界面に対し、ゲート電極を減圧CVD法で堆積したポリシリコンとした場合の界面準位密度が、ゲート電極を常温で蒸着したアルミニウムとした場合の界面準位密度よりも大きくなる問題がある。
これは、実際の減圧CVD炉でのポリシリコン成膜では、SiH4を流してポリシリコンを成膜する前に、温度を安定化するため、不活性ガスを流して所定時間保持したり、成膜後にSiH4を不活性ガスで置換するプロセスが含まれることが原因と考えられる。つまり、実質、不活性ガス中での高温の熱処理が含まれることになり、これが、終端している水素あるいは水酸基を脱離させ、界面準位密度を増加させる要因となっていると考えられる。
With respect to the MOS interface obtained by oxidizing the (000-1) plane in a wet atmosphere under the same conditions, the interface state density when the gate electrode is polysilicon deposited by the low pressure CVD method is There is a problem that it becomes larger than the interface state density in the case of using aluminum deposited by the above method.
In polysilicon film formation in an actual low pressure CVD furnace, in order to stabilize the temperature before flowing SiH 4 to form polysilicon, an inert gas is flowed to keep it for a predetermined time. The cause is considered to include a process of replacing SiH 4 with an inert gas after film formation. In other words, it is considered that a high-temperature heat treatment in an inert gas is substantially included, and this is considered to be a factor of desorbing the terminating hydrogen or hydroxyl group and increasing the interface state density.
そこで、本発明の目的は、炭化ケイ素(000−1)面にウェット雰囲気で酸化されたゲート絶縁膜の上に、ポリシリコンを不活性ガスを使用した減圧CVDで成膜しても、界面準位密度の増加を抑制し、成膜効率を維持しながらMOS界面特性の劣化を防止する炭化ケイ素半導体装置の製造プロセスを提供することにある。 Therefore, an object of the present invention is to form an interface state even if polysilicon is formed on the gate insulating film oxidized in a wet atmosphere on the silicon carbide (000-1) surface by low pressure CVD using an inert gas. An object of the present invention is to provide a manufacturing process of a silicon carbide semiconductor device that suppresses an increase in unit density and prevents deterioration of MOS interface characteristics while maintaining film formation efficiency.
上記の課題を解決するため、本発明においては、次のような半導体装置の製造方法を採用した。すなわち、
(1)半導体領域上に接するようにゲート絶縁膜を形成する工程と、該ゲート絶縁膜上に接するように、ポリシリコンのゲート導電膜を減圧CVD法を用いて炉内で成膜する工程とを有する半導体装置の製造方法において、前記半導体領域は、炭化ケイ素半導体の(000−1)面から0°ないし8°傾いた面からなる領域であり、前記ゲート絶縁膜の形成工程の少なくとも一部に、水分を含むガス中での熱酸化工程を含み、前記ゲート導電膜の成膜工程において、不活性ガスを供給しながら安定化させる目標炉内温度を450℃以上550℃以下にするとともに、原料ガスを注入しながら前記ポリシリコンのゲート導電膜の生成を行う工程、さらには、前記ポリシリコンのゲート導電膜の生成終了後、前記原料ガスを前記不活性ガスに置換する工程を含め、炉内温度を一貫して前記目標炉内温度に維持した。
In order to solve the above problems, the present invention employs the following semiconductor device manufacturing method. That is,
(1) forming a gate insulating film in contact with the semiconductor region; forming a polysilicon gate conductive film in contact with the gate insulating film in a furnace by using a low pressure CVD method; In the method of manufacturing a semiconductor device having the above structure, the semiconductor region is a region formed by a plane inclined by 0 ° to 8 ° from the (000-1) plane of the silicon carbide semiconductor, and at least a part of the step of forming the gate insulating film. And a thermal oxidation step in a gas containing moisture, and in the film formation step of the gate conductive film, the target furnace temperature to be stabilized while supplying an inert gas is set to 450 ° C. or higher and 550 ° C. or lower, The step of generating the polysilicon gate conductive film while injecting the source gas, and further, after the generation of the polysilicon gate conductive film is completed, the source gas is replaced with the inert gas. The furnace temperature was consistently maintained at the target furnace temperature.
(2)前記減圧CVD法によるシリコンゲート導電膜形成において、原料ガスにシラン(SiH4)あるいはジシラン(SiH8)が含まれるようにした。 (2) In forming the silicon gate conductive film by the low pressure CVD method, the source gas contains silane (SiH 4 ) or disilane (SiH 8 ).
(3)前記ゲート絶縁膜を成膜する工程を、水分を含まない乾燥酸素中で熱酸化を行った後、水分を含むガス中での熱酸化を組み合わせた工程とした。 (3) The step of forming the gate insulating film is a step in which thermal oxidation is performed in dry oxygen not containing moisture and then thermal oxidation in a gas containing moisture is combined.
(4)前記ゲート絶縁膜を成膜する工程を、絶縁膜を堆積させた後、水分を含むガス中での熱酸化を組み合わせた工程とした。 (4) The step of forming the gate insulating film is a step in which after the insulating film is deposited, thermal oxidation in a gas containing moisture is combined.
本発明により、水分を含むガス中での熱酸化工程により、炭化ケイ素半導体の(000−1)面上に形成したゲート絶縁膜の上に、減圧CVD法を用いてシリコンゲート電極を成膜するときに、目標炉内温度を450℃以上550℃以下にするとともに、原料ガスを注入しながらポリシリコンのゲート導電膜の生成を行う工程、さらには、ポリシリコンのゲート導電膜の生成終了後、原料ガスを不活性ガスに置換する工程を含め、炉内温度を一貫してこの目標炉内温度に維持することにより、ポリシリコンのゲート導電膜を生成するための全工程において、不活性ガス中での高温アニールに伴うMOS界面準位密度の増加を確実に抑制し、相応の成膜効率を確保ながら、高いチャネル移動度を達成することができる。 According to the present invention, a silicon gate electrode is formed on a gate insulating film formed on a (000-1) plane of a silicon carbide semiconductor by a low pressure CVD method by a thermal oxidation process in a gas containing moisture. In some cases, the target furnace temperature is set to 450 ° C. or higher and 550 ° C. or lower, and the process of generating the polysilicon gate conductive film while injecting the raw material gas is performed. In the entire process for producing a polysilicon gate conductive film by maintaining the furnace temperature consistently at the target furnace temperature, including the step of replacing the source gas with an inert gas, Therefore, it is possible to reliably suppress an increase in the MOS interface state density accompanying the high-temperature annealing at, and to achieve high channel mobility while ensuring appropriate film formation efficiency.
以下、図面を参照しつつ本発明の実施例について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
図1は炭化ケイ素半導体装置の一例として、MOSキャパシタの構成を示す図であり、その製造プロセスを以下に示す。
[ステップ1]
結晶構造が4H−SiCの(000−1)基板1(0〜8°オフ基板)にドナー密度1E16cm3程度のn型エピタキシャル膜2を、5〜10μm成長させ、洗浄した後、水分と酸素を含むガス中で1000℃のウェット酸化を30分行い、厚さ約50nmの絶縁膜3を形成した。
FIG. 1 is a diagram showing a configuration of a MOS capacitor as an example of a silicon carbide semiconductor device, and a manufacturing process thereof will be described below.
[Step 1]
An n-type
[ステップ2]
次に、ゲート電極4としてポリシリコン膜の形成を行う。
ポリシリコンの成膜は以下のような工程で行った。まず、後述する所定の目標炉内温度に保たれた減圧CVD炉に、ゲート絶縁膜3が形成された炭化ケイ素基板を導入した後、炉内温度をこの目標炉内温度に安定させるために、不活性ガスとしてN2を1080sccm(基準温度0℃に換算した場合に毎分1080cc)流しながら30分保持した。
[Step 2]
Next, a polysilicon film is formed as the gate electrode 4.
The polysilicon film was formed by the following process. First, in order to stabilize the furnace temperature at the target furnace temperature after introducing the silicon carbide substrate on which the gate insulating film 3 is formed into a low-pressure CVD furnace maintained at a predetermined target furnace temperature described later, The inert gas was held for 30 minutes while flowing N 2 at 1080 sccm (1080 cc per minute when converted to a reference temperature of 0 ° C.).
次に、この目標炉内温度を維持したまま、キャリアガスとして、N2を220sccm流しながら、ポリシリコン成膜のためにSiH4を1000sccm、ドーピングガスとしてPH3を80sccm導入し、リンドープされたポリシリコンを500nmの膜厚になるまで成膜した。なお、製膜時の圧力は50Paに保った。成膜後はSiH4とPH3の供給を止め、目標炉内温度を保持したまま炉内にN2を800sccm流して置換した後、取り出した。
本実施例では反応ガスとして、シラン(SiH4)を使用したが、ジシラン(SiH8)を使用してもよい。また不活性ガスとしてN2を用いているが、ArやHeでも良い。
Next, while maintaining this target furnace temperature, while introducing N 2 as a carrier gas at 220 sccm, SiH 4 was introduced at 1000 sccm for forming a polysilicon film, and PH 3 was introduced as a doping gas at 80 sccm, and phosphorus-doped poly Silicon was deposited until the film thickness reached 500 nm. The pressure during film formation was kept at 50 Pa. After film formation, the supply of SiH 4 and PH 3 was stopped, N 2 was passed through the furnace at 800 sccm while maintaining the target furnace temperature, and the film was taken out.
In this embodiment, silane (SiH 4 ) is used as the reaction gas, but disilane (SiH 8 ) may be used. Further, N 2 is used as the inert gas, but Ar or He may be used.
[ステップ3]
ゲート電極4を形成後、電気測定用のアルミニウムパッド5を抵抗加熱蒸着で310nm形成し、フォトリソグラフィとエッチングでパターニングした後、アルミニウム裏面電極6を抵抗加熱蒸着により700nm形成した。
[Step 3]
After forming the gate electrode 4, an aluminum pad 5 for electrical measurement was formed to 310 nm by resistance heating vapor deposition, and after patterning by photolithography and etching, an aluminum back electrode 6 was formed to 700 nm by resistance heating vapor deposition.
ポリシリコンゲート電極の成膜温度がMOS界面特性に与える影響を調べた結果を以下に示す。ポリシリコンゲート電極の成膜をさまざまな温度条件で行い、530℃と570℃の2条件の結果を図2に示す。ポリシリコンの成膜速度は成膜温度に依存するため、500nmの膜厚を得るためには、530℃の場合は470分、570℃の場合は155分の成膜時間が必要であった。
完成したMOSキャパシタをC−V測定し、界面準位密度を算出したところ、図2に示すようにポリシリコンを530℃で成膜した場合の方が、570℃で成膜した場合に比べて界面準位密度が低くなった。
これは、ポリシリコン成膜温度を低くすることにより、ポリシリコン形成工程での熱処理によるMOS界面劣化が抑えられたためであると考えられる。界面準位密度とMOSFETのチャネル移動度は相関関係があることがわかっているので、本発明を用いることにより、高いチャネル移動度を持った炭化ケイ素(000−1)面上のMOSFETを作製することができる。
The results of investigating the influence of the polysilicon gate electrode deposition temperature on the MOS interface characteristics are shown below. The polysilicon gate electrode is formed under various temperature conditions, and the results under two conditions of 530 ° C. and 570 ° C. are shown in FIG. Since the polysilicon film formation rate depends on the film formation temperature, a film formation time of 470 minutes at 530 ° C. and 155 minutes at 570 ° C. was required to obtain a film thickness of 500 nm.
When the completed MOS capacitor was measured by CV and the interface state density was calculated, as shown in FIG. 2, the case where the polysilicon was formed at 530 ° C. was compared with the case where the polysilicon was formed at 570 ° C. The interface state density was lowered.
This is considered to be because the MOS interface deterioration due to the heat treatment in the polysilicon forming process was suppressed by lowering the polysilicon film forming temperature. Since it is known that the interface state density and the channel mobility of the MOSFET have a correlation, by using the present invention, a MOSFET on a silicon carbide (000-1) plane having a high channel mobility is manufactured. be able to.
なお、SiH4の熱分解は400℃程度から始まるため、ポリシリコンの成膜には少なくとも400℃以上の温度が必要であるが、成膜温度が低くなればなるほど、成膜速度は遅くなるため、実用的なプロセスに適用するためには、450℃以上の成膜温度が必要となる。
一方、実験の結果、MOS界面の劣化を有効に抑制し、高いチャネル移動度を実現するためには、550℃以下とすることが有効であることが判明した。
したがって、不活性ガスとしてN2を供給しながら目標炉内温度を450℃以上550℃以下に安定させた上で、シランガス及びドーピングガスとしてのPH3を注入しながらポリシリコンのゲート導電膜の生成を行う際、さらには、ポリシリコンのゲート導電膜の生成終了後、シラン(SiH4)をN2に置換する工程を含め、炉内温度を常時450℃以上550℃に維持することが、高いチャネル移動度と成膜速度の観点から、最適なものであることがわかる。すなわち、成膜速度と、得ようとする界面準位密度(図2)との設計上の目標値に基づいて、ポリシリコンの成膜温度を450℃以上550℃以下の範囲から最適温度を選定すればよい。
なお、本実施例では成膜されたシリコンをポリシリコン(多結晶シリコン)と便宜上呼んでいるが、530℃前後の成長温度ではシリコンの結晶化は進んでおらず、アモルファス(非晶質)シリコン成分が多く含まれている。ただし、アモルファスが多く含まれていても、ゲート電極特性には影響を及ぼさない。
Since the thermal decomposition of SiH 4 starts at about 400 ° C., a temperature of at least 400 ° C. is necessary for the film formation of polysilicon, but the film formation speed decreases as the film formation temperature decreases. In order to apply to a practical process, a film forming temperature of 450 ° C. or higher is required.
On the other hand, as a result of experiments, it has been found that it is effective to set the temperature to 550 ° C. or lower in order to effectively suppress the deterioration of the MOS interface and realize high channel mobility.
Therefore, while the target furnace temperature is stabilized to 450 ° C. or higher and 550 ° C. or lower while supplying N 2 as an inert gas, a polysilicon gate conductive film is formed while injecting silane gas and PH 3 as a doping gas. In addition, after the generation of the polysilicon gate conductive film is completed, the furnace temperature is always maintained at 450 ° C. or higher and 550 ° C., including the step of replacing silane (SiH 4 ) with N 2. From the viewpoint of channel mobility and film formation rate, it can be seen that this is optimal. That is, the optimum temperature is selected from the range of 450 ° C. or more and 550 ° C. or less based on the design target value of the film formation rate and the interface state density to be obtained (FIG. 2). do it.
In this embodiment, the deposited silicon is referred to as polysilicon (polycrystalline silicon) for convenience, but the crystallization of silicon does not proceed at a growth temperature of around 530 ° C., and amorphous (amorphous) silicon. Contains many ingredients. However, even if a large amount of amorphous is contained, the gate electrode characteristics are not affected.
この例では、ウェット酸化によりゲート絶縁膜を形成しているが、本発明はゲート絶縁膜形成工程の一部に水分を含むガスを用いた場合にも適用できる。例えば、乾燥酸素による熱酸化の後に水分を含むガス中で再酸化してゲート絶縁膜を形成する工程や、CVD法によって酸化膜あるいは窒化膜を堆積させた後に水分を含むガス中で再酸化させる工程、あるいは水分を含むガス中で熱酸化した後にCVD法によって酸化膜あるいは窒化膜を堆積させる工程によってゲート絶縁膜を形成した場合にも本発明を適用できる。 In this example, the gate insulating film is formed by wet oxidation, but the present invention can also be applied to the case where a gas containing moisture is used in a part of the gate insulating film forming step. For example, a process of forming a gate insulating film by re-oxidizing in a gas containing moisture after thermal oxidation with dry oxygen, or re-oxidizing in a gas containing moisture after depositing an oxide film or nitride film by a CVD method The present invention can also be applied to the case where the gate insulating film is formed by a process or a process of thermally oxidizing in a gas containing moisture and then depositing an oxide film or a nitride film by a CVD method.
本実施例ではゲート電極のポリシリコンは成膜と同時にドーピングされているが、ドーピングされていない状態で成膜し、後に熱拡散あるいはイオン注入によりドーピングを行ってもよい。また、ポリシリコンの成膜後に金属を積層し、熱アニールによってシリサイドメタルを形成してもよい。 In this embodiment, the polysilicon of the gate electrode is doped at the same time as the film formation, but the film may be formed in an undoped state and then doped by thermal diffusion or ion implantation. Alternatively, a metal may be laminated after the polysilicon film is formed, and a silicide metal may be formed by thermal annealing.
以上説明したように、本発明によれば、水分を含むガス中での熱酸化工程により、炭化ケイ素半導体の(000−1)面上に形成したゲート絶縁膜の上に、減圧CVD法を用いてゲート導電膜を成膜する工程において、不活性ガスを供給しながら安定化させる目標炉内温度を450℃以上550℃以下にするとともに、原料ガスを注入しながらポリシリコンのゲート導電膜の生成を行う工程、さらには、ポリシリコンのゲート導電膜の生成終了後、原料ガスを不活性ガスに置換する工程を含め、炉内温度を一貫してこの目標炉内温度に維持することにより、不活性ガスを使用しながらも、ある程度の成膜効率を維持しつつ、ゲート導電膜生成時の界面準位密度を確実に低減することができるので、安全かつ低コストで品質の高い半導体装置の製造を可能にするプロセスとして広く採用されることが期待できる。 As described above, according to the present invention, the low pressure CVD method is used on the gate insulating film formed on the (000-1) plane of the silicon carbide semiconductor by the thermal oxidation process in the gas containing moisture. In the step of forming the gate conductive film, the target furnace temperature to be stabilized while supplying the inert gas is set to 450 ° C. or higher and 550 ° C. or lower, and the polysilicon gate conductive film is formed while the source gas is injected. In addition, after the formation of the polysilicon gate conductive film is completed, the furnace temperature is consistently maintained at the target furnace temperature, including the step of replacing the source gas with an inert gas. While using an active gas, it is possible to reliably reduce the interface state density at the time of generating the gate conductive film while maintaining a certain degree of film formation efficiency. It can be expected to be widely adopted as a process that allows for granulation.
1 n型4H−SiC(000−1)基板
2 n型エピタキシャル膜
3 絶縁膜
4 ゲート電極
5 アルミニウムパッド
6 アルミニウム裏面電極
1 n-type 4H-SiC (000-1) substrate 2 n-type epitaxial film 3 insulating film 4 gate electrode 5 aluminum pad 6 aluminum back electrode
Claims (4)
前記半導体領域は、炭化ケイ素半導体の(000−1)面から0°ないし8°傾いた面からなる領域であり、
前記ゲート絶縁膜の形成工程の少なくとも一部に、水分を含むガス中での熱酸化工程を含み、
前記ゲート導電膜の成膜工程において、不活性ガスを供給しながら安定化させる目標炉内温度を450℃以上550℃以下にするとともに、原料ガスを注入しながら前記ポリシリコンのゲート導電膜の生成を行う工程、さらには、前記ポリシリコンのゲート導電膜の生成終了後、前記原料ガスを前記不活性ガスに置換する工程を含め、炉内温度を一貫して前記目標炉内温度に維持したことを特徴とする炭化ケイ素半導体装置の製造方法。 A semiconductor having a step of forming a gate insulating film so as to be in contact with a semiconductor region and a step of forming a polysilicon gate conductive film in a furnace by using a low pressure CVD method so as to be in contact with the gate insulating film In the device manufacturing method,
The semiconductor region is a region composed of a plane inclined by 0 ° to 8 ° from the (000-1) plane of the silicon carbide semiconductor,
At least part of the step of forming the gate insulating film includes a thermal oxidation step in a gas containing moisture,
In the film formation process of the gate conductive film, the target furnace temperature to be stabilized while supplying an inert gas is set to 450 ° C. or higher and 550 ° C. or lower, and the polysilicon gate conductive film is generated while the source gas is injected. And, after the formation of the polysilicon gate conductive film, the furnace temperature is consistently maintained at the target furnace temperature, including the step of replacing the source gas with the inert gas. A method for manufacturing a silicon carbide semiconductor device, comprising:
3. The silicon carbide semiconductor according to claim 1, wherein the step of forming the gate insulating film is a step of combining the thermal oxidation in a gas containing moisture after depositing the insulating film. Device manufacturing method.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0927457A (en) * | 1995-07-12 | 1997-01-28 | Sony Corp | Thin film depositing method |
| JPH10178009A (en) * | 1996-12-19 | 1998-06-30 | Sony Corp | Method for manufacturing semiconductor device |
| WO2007102281A1 (en) * | 2006-03-07 | 2007-09-13 | National Institute Of Advanced Industrial Science And Technology | Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device |
| JP2008507846A (en) * | 2004-07-23 | 2008-03-13 | アプライド マテリアルズ インコーポレイテッド | Nanocrystalline silicon deposition using a single wafer chamber |
| JP2008211178A (en) * | 2007-02-27 | 2008-09-11 | Cree Inc | Insulated gate bipolar transistor with current suppression layer |
| JP2008244456A (en) * | 2007-02-28 | 2008-10-09 | Denso Corp | Silicon carbide semiconductor device and manufacturing method thereof |
| JP2009266871A (en) * | 2008-04-22 | 2009-11-12 | Panasonic Corp | Silicon carbide semiconductor device and method of manufacturing same |
-
2011
- 2011-08-22 JP JP2011180200A patent/JP2013045789A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0927457A (en) * | 1995-07-12 | 1997-01-28 | Sony Corp | Thin film depositing method |
| JPH10178009A (en) * | 1996-12-19 | 1998-06-30 | Sony Corp | Method for manufacturing semiconductor device |
| JP2008507846A (en) * | 2004-07-23 | 2008-03-13 | アプライド マテリアルズ インコーポレイテッド | Nanocrystalline silicon deposition using a single wafer chamber |
| WO2007102281A1 (en) * | 2006-03-07 | 2007-09-13 | National Institute Of Advanced Industrial Science And Technology | Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device |
| JP2008211178A (en) * | 2007-02-27 | 2008-09-11 | Cree Inc | Insulated gate bipolar transistor with current suppression layer |
| JP2008244456A (en) * | 2007-02-28 | 2008-10-09 | Denso Corp | Silicon carbide semiconductor device and manufacturing method thereof |
| JP2009266871A (en) * | 2008-04-22 | 2009-11-12 | Panasonic Corp | Silicon carbide semiconductor device and method of manufacturing same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014203904A1 (en) * | 2013-06-21 | 2014-12-24 | 富士電機株式会社 | Manufacturing method for silicon carbide semiconductor device |
| JP2015005669A (en) * | 2013-06-21 | 2015-01-08 | 独立行政法人産業技術総合研究所 | Method for manufacturing silicon carbide semiconductor device |
| US9960040B2 (en) | 2013-06-21 | 2018-05-01 | Fuji Electric Co., Ltd. | Manufacturing method of silicon carbide semiconductor device |
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