JP2013077893A - Semiconductor integrated circuit device and communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a data transfer rate while maintaining the downward compatibility of specifications, in a semiconductor integrated circuit device and a communication system corresponding to SLIM bus (R) specifications and the like.SOLUTION: For example, an interface circuit for a SLIM bus has an SDR mode and a DDR mode. A channel (CH_A) of the DDR mode is constructed when communication is performed between interface circuits having the DDR mode, in a data region DATSP in a frame according to the SLIM bus (R) specifications. In the channel of the DDR mode, each interface circuit generates therein an internal clock signal having a frequency twice as high as that of a clock signal on the SLIM bus to transfer a data signal on the SLIM bus at a rate twice as high as that of the clock signal on the SLIM bus on the basis of the internal clock signal.

Description

  The present invention relates to a semiconductor integrated circuit device and a communication system, and more particularly, to a technology effective when applied to a semiconductor integrated circuit device and a communication system to which a SLIMbus (Serial Low-power Inter-chip Media Bus) (registered trademark) standard is applied. .

  For example, Patent Document 1 discloses a method of variably setting the data rates of the first segment and the second segment on the ring in a local communication system including a ring network. Patent Document 2 discloses an operation of changing a clock frequency using a “gear” setting in a communication system to which the SLIMbus (registered trademark) standard is applied. Non-Patent Document 1 shows a detailed structure example of a frame having 192 slots in the SLIMbus (registered trademark) standard.

JP-T-2001-511971 US Patent Application Publication No. 2008/0205453

SLIMbus Specification, Version1.01, 2008

  For example, a SLIMbus (registered trademark) standard as described in Non-Patent Document 1 and Patent Document 2 is known as a communication standard for mobile phones. The SLIMbus (registered trademark) standard is a serial communication standard mainly defined for the purpose of transmission / reception of audio signals in a mobile phone, and is characterized by a low transfer rate compared to other communication standards. It has become. Specifically, using isochronous transfer as a basic protocol, a data transfer rate of 28.8 Mbps is realized at the maximum speed by using two lines of a clock line and a data line.

  In order to reduce the size of a mobile phone, it is desired to apply the SLIMbus (registered trademark) standard to most of circuit blocks that perform serial communication. However, the circuit block may include a circuit block responsible for processing such as a wireless local area network (LAN) or Bluetooth (registered trademark). In recent years, the bandwidth of wireless LAN and Bluetooth (registered trademark) has been greatly improved, for example, 100 Mbps, and the speed performance of the SLIMbus (registered trademark) standard may be exceeded. For this reason, it is desired to improve the bandwidth by extending the SLIMbus (registered trademark) standard. The simplest way to improve the bandwidth is to increase the clock frequency. However, when the clock frequency is increased, there is a possibility that backward compatibility cannot be maintained with respect to an existing device conforming to the SLIMbus (registered trademark) standard.

  The present invention has been made in view of the above, and one of its purposes is a semiconductor integrated circuit device corresponding to the SLIMbus (registered trademark) standard and a communication system including the semiconductor integrated circuit device. It is to improve data transfer speed while maintaining compatibility. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  The semiconductor integrated circuit device according to the present embodiment includes a serial interface circuit (SLMBIF) connected to a serial data bus (DAT) and a clock bus (CLK) to which a first clock signal having a first frequency is transmitted. Here, the serial interface circuit has a first mode (DDR mode or the like) and a second mode (SDR mode). In the first mode, 2 N (N is an integer of 1 or more) data is sequentially transmitted to the serial data bus within a cycle of the first clock signal (CLK), and the first clock signal (CLK) Within the period of one cycle, 2 to the Nth power (N is an integer of 1 or more) pieces of data are sequentially received from the serial data bus. On the other hand, in the second mode, one data is transmitted to the serial data bus within one cycle of the first clock signal (CLK), and one data is transmitted within one cycle of the first clock signal. Is received from the serial data bus.

  By using such a configuration, when the communication partner via the serial data bus and the clock bus corresponds to the first mode without changing the clock frequency of the clock bus, high-speed communication is performed using the first mode. If the first mode is not supported, low-speed communication can be performed using the second mode. As a result, it is possible to improve the data transfer speed while maintaining backward compatibility such as SLIMbus (registered trademark) standard.

  In the semiconductor integrated circuit device according to the present embodiment, more specifically, the serial data bus (DAT) transmits the NRZI signal, and the serial interface circuit (SLMBIF) includes the first clock generation circuit. And a control circuit, a selection circuit, first to third flip-flop circuits, and first and second arithmetic circuits. The first clock generation circuit (CKGH, CKGS) includes a second clock signal having the same first frequency as the first clock signal (CLK) and an Nth power of 2 times the second clock signal (N is an integer of 1 or more). And a third clock signal having a frequency of The control circuit (DSRCTL) sets the internal state to the first mode (DDR mode or the like) or the second mode (SDR mode). The selection circuit (SEL) selects the third clock signal in the first mode and the second clock signal in the second mode, and outputs the selected clock signal as the internal clock signal (CK). The first flip-flop circuit (FF3) latches data on the serial data bus (DAT) at the first edge that is one of the rising edge and the falling edge of the internal clock signal. The first arithmetic circuit (EOR1) performs an exclusive OR operation between predetermined transmission data (TXDAT) and the output of the first flip-flop circuit. The second flip-flop circuit (FF1) latches the output of the first arithmetic circuit at the second edge, which is the other of the rising edge and the falling edge of the internal clock signal, and transmits it to the serial data bus. The third flip-flop circuit (FF4) latches the output of the first flip-flop circuit at the first edge of the internal clock signal. The second arithmetic circuit (EOR2) restores received data (RXDAT) by performing an exclusive OR operation on the output of the first flip-flop circuit and the output of the third flip-flop circuit.

  The effects obtained by the representative embodiments of the invention disclosed in the present application will be briefly described. In the semiconductor integrated circuit device and the communication system including the semiconductor integrated circuit device, backward compatibility such as SLIMbus (registered trademark) standard is achieved. The data transfer speed can be improved while maintaining the same.

In the communication system by Embodiment 1 of this invention, it is the schematic which shows an example of the structure. FIG. 2 is a block diagram illustrating a schematic configuration example of a main part of a high-frequency signal processing chip for a mobile phone in the communication system of FIG. 1. (A) is a block diagram showing a schematic configuration example of a main part of a microphone part in the communication system of FIG. 1, and (b) is a block diagram showing a schematic configuration example of a main part of a speaker part in the communication system of FIG. FIG. (A), (b) is a conceptual diagram which shows the structural example of the flame | frame which flows on the SLIM bus | bath in the communication system of FIG. FIG. 5 is a schematic diagram illustrating an example of operation waveforms for one slot on the SLIM bus corresponding to FIGS. 4 (a) and 4 (b), respectively. FIG. 6 is an explanatory diagram showing an example of problems associated with the operation methods of FIGS. 4 and 5. FIG. 4B is a modified example of FIG. 4B, and is a conceptual diagram showing a structural example of a frame flowing on the SLIM bus in the communication system of FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration example of a main part of an interface circuit included in a host device on a SLIM bus in the communication system of FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration example of a main part of an interface circuit included in a slave device on a SLIM bus in the communication system of FIG. 1. FIG. 10 is a waveform diagram illustrating a main operation example in the interface circuit of FIGS. 8 and 9. FIG. 8 is a flowchart showing an example of an initial setting method in the operation method of FIG. 7. (A), (b) is a conceptual diagram which shows the example of a respectively different structure of the flame | frame which flows on the SLIM bus | bath in the communication system by Embodiment 2 of this invention. FIG. 10 is a waveform diagram showing a detailed operation example of FIGS. 8 and 9 when the operation method of FIG. In the communication system by Embodiment 3 of this invention, it is a conceptual diagram which shows the structural example of the frame which flows on the SLIM bus | bath. FIG. 15 is a flowchart showing an example of a channel arrangement determination method in the operation method of FIG. (A) is a conceptual diagram which shows the structural example of the frame which flows on the SLIM bus in the communication system by Embodiment 4 of this invention, (b) is 1 on SLIM bus corresponding to (a). It is the schematic which shows the operation waveform example for a slot. (A) is a block diagram showing a partial schematic configuration example when the SLIMbus (registered trademark) standard is applied in the communication system (mobile phone system) according to Embodiment 1 of the present invention. , (A) is a block diagram when SLIMbus (registered trademark) standard is not applied. FIG. 17A is an explanatory diagram showing a structure example of a frame flowing on the SLIM bus in FIG. (A) is a figure which shows an example of the actual operation waveform on the SLIM bus in FIG. 17 (a), (b) is an example of the arbitration function performed using the operation waveform of (a). FIG. FIG. 18A is a circuit diagram illustrating a configuration example of a main part of an interface circuit included in a host device on a SLIM bus in FIG. FIG. 18A is a circuit diagram illustrating a configuration example of a main part of an interface circuit included in a slave device on the SLIM bus in FIG.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . In the embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated as a MOS transistor) may be used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), but a non-oxide film is excluded as a gate insulating film. Not what you want. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<< Outline of SLIMbus (Registered Trademark) Standard >>
First, an outline of the SLIMbus (registered trademark) standard, which is a premise of the present invention, will be described. However, the semiconductor integrated circuit device and the communication system according to the present embodiment are not necessarily limited to the SLIMbus (registered trademark) standard, and can be similarly applied to similar serial communication standards. FIG. 17 (a) is a block diagram showing a partial schematic configuration example when the SLIMbus (registered trademark) standard is applied to the communication system (mobile phone system) according to Embodiment 1 of the present invention. (B) is a comparative example of FIG. 17 (a), and is a block diagram when SLIMbus (registered trademark) standard is not applied.

  The cellular phone system shown in FIG. 17B includes, for example, a system LSI (SOC) configured by one semiconductor chip and a plurality of external components (WLANBK ′, BTBK ′, CP, SPKBK1 ′, SPKBK2 ′, MICBK ′). WLANBK 'is an external part including an antenna for a wireless local area network (LAN), for example, and BTBK' is an external part including an antenna for Bluetooth (registered trademark), for example. The CP is an external component (for example, an IC card) having a serial communication function. SPKBK1 'and SPKBK2' are external parts including, for example, incoming and voice speakers, and MICBK 'is an external part including a microphone and the like.

  The SOC includes a processor unit CPU, a direct memory access controller DMAC, and a plurality of control circuits (WLANCT, BTCT, SCI, SPKCT1, SPKCT2, MICCT) connected to each other by a bus BS. WLANCT is a control circuit for a wireless LAN, and transmits and receives a high-frequency signal (for example, 2.4 GHz band, etc.) to and from an external component WLANBK 'via an external terminal of the SOC, for example. The BTCT is a control circuit for Bluetooth (registered trademark), and for example, transmits and receives a high-frequency signal (for example, 2.4 GHz band) to and from the external component BTBK ′ via an external terminal of the SOC. The SCI is a control circuit (interface circuit) for serial communication, and performs serial communication with an external component CP via an external terminal of the SOC. SPKCT1 and SPKCT2 are audio output control circuits that drive SPKBK1 'and SPKBK2' via the external terminals of the SOC based on predetermined audio information. The MICCT is a voice input control circuit that receives a voice signal from the MICBK 'via an external terminal of the SOC and performs predetermined signal processing.

  As the example of FIG. 17B shows, the number of external terminals of the system LSI (SOC) increases as the number of mobile phone systems such as wireless LAN compatible and Bluetooth (registered trademark) compatible increases. There is a risk that miniaturization of the mobile phone system may be difficult. Therefore, it is beneficial to apply the SLIMbus (registered trademark) standard as shown in FIG. The mobile phone system shown in FIG. 17A includes, for example, a microcomputer MCU composed of a single semiconductor chip and a plurality of external components (WLANBK, BTBK) connected to the MCU via the SLIM bus SLMBS. CP, SPKBK1, SPKBK2, MICBK).

  The WLANBK includes, for example, a wireless LAN antenna and a high-frequency signal processing chip WLANIC. The WLANIC performs, for example, frequency conversion, modulation / demodulation processing between a baseband and a high-frequency band (for example, 2.4 GHz band). A circuit to perform, an interface circuit for the SLIM bus, and the like. The BTBK includes, for example, an antenna for Bluetooth (registered trademark) and a high-frequency signal processing chip BTIC. The BTIC, for example, performs frequency conversion, modulation / demodulation between a baseband and a high frequency band (for example, 2.4 GHz band). A circuit for processing and the like, an interface circuit for the SLIM bus, and the like are provided. The CP includes a SLIM bus interface circuit in addition to a circuit having a predetermined function. Each of SPKBK1 and SPKBK2 includes a speaker and its control chips SPKIC1 and SPKIC2, and each of SPKIC1 and SPKIC2 includes an interface circuit for a SLIM bus in addition to a digital / analog conversion circuit and an amplifier circuit. The MICBK includes a microphone and its control chip MICIC. The MICIC includes an interface circuit for a SLIM bus in addition to an analog / digital conversion circuit and an amplifier circuit.

  The MCU includes a processor unit CPU, a direct memory access controller DMAC, an interface circuit SLMBIF for the SLIM bus, and the like that are connected to each other via a bus BS. The SLMBIF is connected to the above-described external SLIM bus SLMBS, and performs protocol conversion between the SLMBS and the BS inside the MCU. Here, the SLMBS includes one clock wiring (clock signal) CLK and one data wiring (data signal) DAT for performing serial communication. Therefore, by using the configuration example shown in FIG. 17A, the number of MCU external terminals can be reduced as compared with the case of FIG. Since the external terminal of the MCU needs to have a certain physical size in order to ensure electrical connection, the reduction of the external terminal is effective for downsizing the entire system. For example, as the number of functions of the mobile phone system increases, it becomes easier to reduce the size of the entire system as the number of external terminals is reduced.

  FIG. 18 is an explanatory diagram showing a structure example of a frame flowing on the SLIM bus in FIG. On the SLIM bus SLMBS, as shown in FIG. 18 and Non-Patent Document 1 described above, data transfer is performed in units called frame FRMs composed of continuous 192 slots SLT. As shown in FIG. 18, one slot SLT includes, for example, four cells (actually variably settable) cells CL0 to CL3, where the data signal DAT in one cycle period of the clock signal CLK is one cell CL. Composed. In addition, a subframe SFRM is configured by a plurality of consecutive slots SLT (in this example, eight slots are actually variably settable). As seen in time series, serial data transfer is performed in the order of slot [0], slot [1],..., Slot [191] as shown in FIG.

  Here, in each subframe SFRM, the first half (two in this case) SLTs are allocated to the control area CTLSP used for transmission and reception of control information, and the second half (six in this case) SLTs are assigned. It is assigned to a data area DATSP used for transmission / reception of data information. When performing data transfer, a channel is established in DATSP using a predetermined channel (referred to as a message channel) that exists in the CTLSP in advance. Then, the transmitting side and the receiving side transmit and receive data based on the timing specific to each channel while sharing the information on the channel. A channel consists of a series of slot SLTs called segments. At the time of channel establishment, “number of slots from which the first segment starts from the beginning of the frame FRM (segment offset)”, “how many slots the segment length”, “how many slots the segment interval” is set It is possible.

  In the example of FIG. 18, the external component MICBK in FIG. 17A is the transmission side (referred to as the source) and the microcomputer MCU is the reception side (referred to as the sink), and the MCU is the transmission side and the external A channel B (CH_B) having the component SPKBK2 as a receiving side is established. CH_A settings are “segment offset = 5”, “segment length = 2”, “segment interval = 16”, and CH_B settings are “segment offset = 7”, “segment length = 2”, “segment interval” = 64 ". The control area CTLSP includes a framing channel including a frame synchronization symbol (SLT [0]) and frame information (SLT [96]), and a guide channel (SLT [1] and SLT [8]). The message channel described above is assigned to other locations. In the frame information, the shape of the frame including the setting of the subframe length described above is held, and the guide channel is used when sharing the status of the message.

  FIG. 19A is a diagram showing an example of an actual operation waveform on the SLIM bus in FIG. 17A, and FIG. 19B is a diagram illustrating an operation waveform of FIG. 19A. It is explanatory drawing showing an example of the arbitration function to be called. As shown in FIG. 19A, data transfer is performed on the SLIM bus SLMBS using an NRZI (Non Return to Zero Invert) signal. At the time of data transmission, output toward the data wiring DAT is performed in synchronization with the rising edge of the clock signal CLK. At this time, when the transmission data TXDAT is ‘1’, the data on the DAT is driven to be inverted, and when TXDAT is ‘0’, the data on the DAT is held. On the other hand, when data is received, DAT is fetched in synchronization with the falling edge of CLK. At this time, when the data on the DAT is inverted compared to the previous cycle, the received data RXDAT is determined to be “1”, and when the data on the DAT is not inverted, the RXDAT is determined to be “0”. Is done.

  In the SLIMbus (registered trademark) standard, each device on the SLIM bus SLMBS can transmit a message using the message channel described above. In order to prevent simultaneous transmission of messages from a plurality of devices at this time, in the SLIMbus (registered trademark) standard, as shown in FIG. 19B, an arbitration function using a combination of the above-described NRZI signal and wired OR logic. Is equipped. The overall control of the arbitration operation is performed by a device called an active manager responsible for bus control, and the device is normally assigned to the MCU in FIG. In FIG. 19B, INT_MCU corresponds to an interrupt signal directed to the MCU, and INT_DEVa to INT_DEVx are generated by each device corresponding to each external component (WLANBK, BTBK,...) In FIG. Each corresponds to an interrupt signal.

  Here, the device that wants to transmit the message serially transmits the unique identification number assigned to it as an interrupt signal on the data wiring DAT. For example, it is assumed that INT_DEVa (identification number) is “010” and INT_DEVb (identification number) is “011”, and these are simultaneously transmitted in order from the first bit (here, the right end). In this case, DAT inversion driving is performed by INT_DEVb in the first bit, DAT inversion driving is performed by INT_DEVa and INT_DEVb in the second bit, and DAT holding operation is performed in the third bit. As a result, “011” is obtained as the logical value of INT_MCU, and a message transmission right is given to the device corresponding to INT_DEVb. That is, for example, when each identification number is set to “000” to “111”, “111” has the highest priority, followed by “110”, “101”,..., “000”. become.

  FIG. 20 is a circuit diagram showing a configuration example of a main part of the interface circuit provided in the host device on the SLIM bus in FIG. FIG. 21 is a circuit diagram showing a configuration example of a main part of the interface circuit included in the slave device on the SLIM bus in FIG. The host device is called an active framer and is a device that supplies a clock signal on a bus to form a frame structure. The device can be changed as appropriate, but is normally assigned to the MCU shown in FIG. A slave device is called a non-active framer, and is a device that is supplied with a clock signal via a bus and operates in synchronization with the clock signal. The device is a device other than the host device on the bus, and corresponds to, for example, a device other than the MCU in FIG.

  The interface circuit SLMBIF (Host) shown in FIG. 20 includes flip-flop circuits FF1 to FF5, output buffer circuits OBF1 and OBF2, input buffer circuit IBF1, EXOR (exclusive OR) operation circuits EOR1 and EOR2, and bus holding. A circuit BSKP is provided. First, the configuration related to the transmission system will be described. The IBF 1 receives the data wiring DAT on the SLIM bus SLMBS and outputs it to the FF 3. The FF 3 captures the output of the IBF 1 in synchronization with the falling edge of the internal clock signal CK generated inside the device. EOR1 performs an EXOR operation on the output of FF3 and transmission data TXDAT.

  FF1 takes in the output of EOR1 in synchronization with the rising edge of the internal clock signal CK. The FF2 takes in the output enable signal OE in synchronization with the rising edge of the CK. OBF1 is controlled in an active state / inactive state according to the output of FF2 (that is, OE), and in the active state (that is, OE is in an enabled state), the output of FF1 is transmitted to the data line DAT on the SLIM bus SLMBS However, the transmission is not performed in the inactive state (that is, the OE is disabled). The OBF 2 supplies the CK to the clock wiring CLK on the SLMBS. BSKP maintains the logic level of DAT. In this way, the DAT data is captured at the falling edge of CK, the EXOR operation of the data and TXDAT is performed, and the result is sent to the DAT at the next rising edge, as shown in FIG. Thus, the NRZI signal can be output on the DAT.

  Next, a configuration related to the reception system will be described. The FF4 takes in the output signal of the FF3 described above in synchronization with the falling edge of the internal clock signal CK. EOR2 performs an EXOR operation on the output of FF3 and the output of FF4. The FF 5 takes the output of the EOR 2 again at the rising edge of CK and outputs the reception data RXDAT. In this way, the DAT data in the current cycle and the DAT data in the previous cycle are fetched at the falling edge of CK, and the EXOR operation is performed, as shown in FIG. The received data (logical value) can be discriminated from the NRZI signal.

  On the other hand, the interface circuit SLMBIF (Slave) shown in FIG. 21 has a configuration in which the output buffer circuit OBF2 in FIG. 20 is replaced with the input buffer circuit IBF2. Since the configuration other than this is the same as that of FIG. 20, detailed description thereof is omitted. The IBF 2 receives the clock wiring CLK on the SLIM bus SLMBS and outputs an internal clock signal CK. Then, as in the case of FIG. 20, the flip-flop circuits FF1 to FF5 operate in synchronization with the CK.

<< Overall Configuration of Communication System According to this Embodiment >>
FIG. 1 is a schematic diagram showing an example of the configuration of a communication system according to Embodiment 1 of the present invention. A communication system RFSYS shown in FIG. 1 is a mobile phone system, for example, and includes a wiring board (for example, a ceramic board) MBD, external components (SPKBK1, SPKBK2, MICBK), a cable CBL, and antennas ANT1 to ANT4. Yes. A plurality of semiconductor chips (semiconductor integrated circuit devices or devices) (MCU, WLANIC, BTIC, SCIIC, MEMSIC, MODIC, PWIC, GPSIC, NFCIC) are mounted on the MBD, and each semiconductor chip depends on a wiring pattern on the MBD. They are connected to each other by the formed SLIM bus SLMBS. The SLMBS has a clock wiring CLK and a data wiring DAT. Each semiconductor chip includes a SLIM bus interface circuit SLMBIF at a connection portion with the SLMBS in common. The MCU is a microcomputer or the like, and includes a processor unit CPU and a SLIM bus interface circuit SLMBIF connected by a bus BS.

  MODIC is a high-frequency signal processing chip for mobile phones typified by GSM (Global System for Mobile Communications), W-CDMA (Wideband Code Division Multiple Access), and the like, and is used to transmit and receive data between SLMBS and an external ANT1 Take on. FIG. 2 is a block diagram showing a schematic configuration example of the main part of the high-frequency signal processing chip for mobile phone in the communication system of FIG. The high-frequency signal processing chip MODIC shown in FIG. 2 includes ADC, DAC, FLT / PGA, MIX_TX, MIX_RX, VCO_TX, VCO_RX, PA, LNA, ANTSW / DPX and the like in addition to the SLIM bus interface circuit SLMBIF2. The ADC is an analog / digital conversion circuit, and the DAC is a digital / analog conversion circuit. FLT is a filter circuit, and PGA is a programmable gain amplifier circuit. MIX_TX and MIX_RX are transmission and reception mixer circuits, respectively. VCO_TX and VCO_RX are transmission and reception oscillation circuits, respectively. PA is a power amplifier circuit, and LNA is a low noise amplifier circuit. ANTSW is an antenna switch circuit, and DPX is a duplexer circuit.

  In such a configuration example, at the time of transmission operation, first, the SLMBIF 2 acquires a digital signal serving as transmission data via the SLMBS, and the DAC converts the digital signal into an analog signal. Next, MIX_TX up-converts (converts to frequency) the DAC output signal to a predetermined high frequency band (for example, 850 MHz band, 2 GHz band, etc.) using a local oscillation signal from VCO_TX, and additionally adds quadrature modulation (IQ Modulation) and the like. The PA amplifies the output signal from the MIX_TX and sends it to the ANT1 via the ANTSW and / or DPX.

  On the other hand, at the time of reception operation, first, a high frequency signal received by ANT1 is input to LNA via ANTSW and / or DPX, and is amplified by LNA. Next, the MIX_RX down-converts (frequency conversion) the output signal of the LNA to the baseband using the local oscillation signal from the VCO_RX, and additionally performs quadrature demodulation (IQ demodulation) and the like. Subsequently, the FLT / PGA performs unnecessary harmonic component removal and amplitude adjustment on the output signal of the MIX_RX, and the ADC converts the output signal of the FLT / PGA into a digital signal. The SLMBIF 2 sends this digital signal as received data to the SLMBS. Here, PA and ANTSW / DPX are provided in the MODIC, but these may be provided outside the MODIC depending on circumstances.

  In FIG. 1, WLANIC is a high-frequency signal processing chip for wireless LAN, and BTIC is a high-frequency signal processing chip for Bluetooth (registered trademark). WLANIC is responsible for transmission / reception between SLMBS and external ANT2, and BTIC is responsible for transmission / reception between SLMBS and external ANT3. These specific configurations and operations are almost the same as those of the above-described MODIC. However, in practice, a slight difference may occur in the configuration and operation depending on the modulation / demodulation method and the difference in the frequency band to be used. For example, when FSK (Frequency Shift Keying) is used as a modulation method, a signal obtained by directly modulating VCO_TX without inputting MIX_TX may be input to PA. The GPSIC is a high-frequency signal processing chip for GPS, processes a received signal from an external ANT4, and outputs it to the SLMBS. The specific configuration and operation are substantially the same as those of the receiving part in the above-described MODIC. However, in practice, a slight difference may occur depending on the demodulation method, the frequency band to be used, and the like.

  SCIIC is, for example, a serial communication control chip such as a JTAG controller, and is responsible for transmission / reception (protocol conversion) between SLMBS and an external debug port DBGPT. The MEMSIC is a control chip for various sensors, and is responsible for transmission and reception between the SLMBS and an external sensor (not shown). The PWIC is a power supply control chip that supplies power to each semiconductor chip on the MBD. For example, the PWIC cuts off or restores power supply to a predetermined semiconductor chip based on an instruction via the SLMBS. NFCIC is a control chip for low-power wireless communication (so-called RFID (Radio Frequency IDentification)), which wirelessly transmits data input from SLMBS via SLMBIF via an antenna (not shown). The detected received data is sent to SLMBS via SLMBIF.

  The external component SPKBK1 is a speaker component for incoming calls provided with a speaker control chip SPKIC1, and the external component SPKBK2 is a speaker component for calls provided with a speaker control chip SPKIC2. The external component MICBK is a microphone component for a call provided with a microphone control chip MICIC. Each semiconductor chip (semiconductor integrated circuit device or device) (SPKIC1, SPKIC2, MICIC) is mutually connected to the SLMBS on the wiring board MBD via a cable (for example, a flat cable) CBL having a built-in SLIM bus. It is connected. The SPKIC1, SPKIC2, and MICIC are commonly provided with a SLIM bus interface circuit SLMBIF at a connection portion with the CBL.

  3A is a block diagram illustrating a schematic configuration example of the main part of the microphone component in the communication system of FIG. 1, and FIG. 3B is a schematic configuration of the main part of the speaker component in the communication system of FIG. It is a block diagram which shows an example. 3A includes a microphone control chip MICIC and a microphone MIC. The MICIC includes a SLIM bus interface circuit SLMBIF3, an analog / digital conversion circuit ADC, and an amplifier circuit AMP. The MIC generates an electrical signal corresponding to the input voice, and the AMP amplifies the electrical signal. The ADC converts the output signal of the AMP into a digital signal, and the SLMBIF 3 sends the digital signal to the SLIM bus on the CBL.

  A speaker component SPKBK shown in FIG. 3B corresponds to SPKBK1 and SPKBK2 in FIG. 1, and includes a speaker control chip SPKIC and a speaker SPK. The SPKIC includes a SLIM bus interface circuit SLMBIF4, a sound processing circuit ADPCM, a digital / analog conversion circuit DAC, and an amplifier circuit AMP. The SLMBIF 4 takes in a digital signal input via the CBL, and the ADPCM performs expansion on the digital signal (for example, a compressed digital audio signal). The ADC converts the digital signal from ADPCM into an analog signal, and the AMP amplifies the analog signal to drive the SPK.

  When the configuration example described in FIGS. 1 to 3 is used, as described in FIG. 17, for example, the number of external terminals of the microcomputer MCU can be reduced, and the MCU and each semiconductor chip (WLANIC, BTIC) on the wiring board MBD. , SCIIC,...) Can be simplified. Further, the connection wiring between the MCU (MBD) and the external component (SPKBK1, SPKBK2, MICBK) can be simplified. As a result, the mobile phone system can be downsized. However, in particular, a wireless LAN (WLANIC) or Bluetooth (registered trademark) (BTIC) may require a data transfer rate of, for example, several hundred Mbps, and the cellular phone (MODIC) also improves the data rate. Is making great strides. As a result, the data transfer rate of 28.8 Mbps defined in the SLIMbus (registered trademark) standard may be insufficient in speed performance. Therefore, the extension of the SLIMbus (registered trademark) standard is desired. At this time, for example, if a method of simply increasing the clock frequency on the SLIM bus is used, there is a risk that backward compatibility cannot be maintained. Therefore, it is beneficial to use the SLIM bus operation method according to the present embodiment described later.

<< SLIM bus operation method according to this embodiment [1] >>
FIGS. 4A and 4B are conceptual diagrams showing an example of the structure of a frame flowing on the SLIM bus in the communication system of FIG. FIG. 5 is a schematic diagram showing an example of operation waveforms for one slot on the SLIM bus corresponding to FIGS. 4 (a) and 4 (b). 4A and 4B show a part of the frame structure corresponding to the frame structure described in FIG. In this example, channel A (CH_A) and channel B (CH_B) are established in the data area DATSP, and the segment length of each channel (the length of a series of slot groups) is set to “3”. Has been. Here, in the communication system according to the present embodiment, as an operation mode of the SLIM bus, in addition to the SDR mode as shown in FIG. 4A, a DDR (Double Data Rate) mode as shown in FIG. It is the main feature to have.

  The frame structure shown in FIG. 4A is the same as the frame structure shown in FIG. 18, and each slot SLT is composed of four cells CL as shown in the SDR mode of FIG. Bit data is allocated. In the SDR mode shown in FIG. 5, one slot (slot data) “DA0” in FIG. 4A is illustrated, and “DA0” corresponds to 4 cells of 4-bit cell data DA0 [ 3], DA0 [2], DA0 [1], DA0 [0]. On the other hand, the frame structure shown in FIG. 4B is an extension of the frame structure shown in FIG. 18, and here, the case where the channel A (CH_A) operates in the DDR mode is shown.

  The frame structure shown in FIG. 4B is a structure in which double information (for example, DA0a, DA0b) is included in one slot (slot data) (for example, DA0) in FIG. 4A. Specifically, as shown in the DDR mode of FIG. 5, 2-bit data is allocated in one cell CL using both edges of the clock signal CLK. In the DDR mode shown in FIG. 5, the cell data DA0 [3] in the SDR mode is replaced with the extended cell data DA0a [3], DA0b [3], and thereafter the cell data DA0 [0] in the SDR mode is changed to the extended cell. Data DA0a [0] and DA0b [0] are replaced.

  When such an operation method is used, the operation frequency of the data signal DAT is doubled as the clock frequency without increasing the frequency of the clock signal CLK on the SLIM bus, as shown in FIG. The data transfer rate can be doubled compared to the above. That is, the data signal DAT on the SLIM bus corresponding to the data area DATSP for a certain period is used only by a specific device (source device and sink device) and does not affect other devices on the bus. On the other hand, the clock signal CLK on the SLIM bus affects all devices on the bus.

  Therefore, by utilizing this property, the frequency of the clock signal CLK on the SLIM bus is fixed, and when communication between devices corresponding to the DDR mode is performed, for example, twice in each device based on CLK. An internal clock signal may be generated, and data transmission / reception may be performed using the internal clock signal in a state where the operating frequency of only the data signal DAT is doubled. Specifically, for example, in FIGS. 20 and 21 described above, an internal clock signal that is twice the clock signal CLK may be supplied to each of the flip-flop circuits FF1 to FF5. Further, for example, when a communication partner of a device having both the DDR mode and the SDR mode is compatible only with the SDR mode, both may communicate using the SDR mode. As a result, it is possible to increase the data transfer rate while maintaining backward compatibility according to the SLIMbus (registered trademark) standard.

  However, as described in FIG. 19A, data transfer on the SLIM bus is performed using the NRZI signal. For this reason, if the operation method described in FIGS. 4 and 5 is used, the following situation may occur. FIG. 6 is an explanatory diagram showing an example of problems associated with the operation methods of FIGS. 4 and 5. In FIG. 6, after device A (DEVa) transmits data DA2 to the SLIM bus using DDR mode, device B (DEVb) subsequently transmits data DB0 on the SLIM bus using SDR mode. Is going. That is, FIG. 6 shows a joint portion between “DA2b” and “DB0” in FIG.

  DEVa is NRZI on the data line DAT in synchronization with the rising edge and falling edge of the clock signal CLK according to the transmission data TXDAT2a [2], 2b [2], ..., 2a [0], 2b [0]. Signal data DA2a [2], 2b [2],..., 2a [0], 2b [0] are sent in order. At this time, the final data DA2b [0] of the segment is output from the falling edge of CLK. On the other hand, as described in FIG. 20 and FIG. 21, DEVb takes in the DAT data using the falling edge of CLK accompanying this DA2b [0], and the EXOR operation result of the data and transmission data TXDAT0 [3] Based on the above, the first data DB0 [3] of the segment is sent to DAT at the next rising edge of CLK. However, since DA2b [0] is transmitted by DEVa at the time of capturing DAT data, the captured data of DAT becomes an indefinite value “X”, and DEVb may not transmit a correct NRZI signal. There is. Although the transmission operation has been described as an example here, the same problem may occur with respect to the reception operation.

<< SLIM bus operation method according to this embodiment [2] >>
7 is a modified example of FIG. 4B, and is a conceptual diagram showing a structural example of a frame flowing on the SLIM bus in the communication system of FIG. In order to solve the problem described with reference to FIG. 6, it is beneficial to use an operation method as shown in FIG. The operation method of FIG. 7 is that when the device in the DDR mode (channel B (CH_B)) is operated following the device in the DDR mode (channel A (CH_A)), the last slot data (DA2, DA2) of each segment in the DDR mode is operated. DA5, DA8,...) Are transmitted in the SDR mode. Thus, when the device in the SDR mode sends the first data (DB0, DB3, DB6,...) Of each segment from the rising edge of the clock signal, the data on the data line DAT at the falling edge of the clock signal immediately before that. Data can be captured correctly. As can be seen from FIG. 7, since data other than the last slot data is transmitted in the DDR mode in the DDR mode, the data transfer rate can be improved as compared with the case where only the SDR mode is used.

<< Details of SLIM Bus Interface Circuit >>
FIG. 8 is a circuit diagram showing a configuration example of a main part of an interface circuit included in a host device on the SLIM bus in the communication system of FIG. FIG. 9 is a circuit diagram showing a configuration example of a main part of an interface circuit included in a slave device on the SLIM bus in the communication system of FIG. As described with reference to FIGS. 20 and 21, the host device typically corresponds to the microcomputer MCU of FIG. 1, and the slave devices are the other devices (WLANIC, BTIC,...) In FIG. , SPKIC2, MICIC).

  The SLIM bus interface circuit SLMBIF (Host) shown in FIG. 8 includes flip-flop circuits FF1 to FF5, output buffer circuits OBF1 and OBF2, input buffer circuit IBF1, EXOR (exclusive OR) operation circuits EOR1 and EOR2, And a bus holding circuit BSKP, and in addition, a clock control circuit CKCTL1. That is, as compared with the configuration example of FIG. 20, CKCTL1 is added and the input source of OBF2 is changed. Hereinafter, a part overlapping with FIG. 20 will be described briefly, and the description will be made paying attention to a difference from FIG.

  CKCTL1 includes a DDR / SDR mode control circuit DSRCTL, a clock generation circuit CKGH, and a selector circuit SEL. The CKGH generates a clock signal having a frequency twice that of a one-time clock signal. DSRCTL controls enable (assert) / disable (negate) of the DDR mode enable signal DDREN. The SEL outputs a double clock signal from the CKGH as the internal clock signal CK when the DDREN is enabled (here, “1”), and when the DDREN is disabled (here, “0”). At this time, a clock signal of 1 time from CKGH is output as CK. Regardless of DDREN, OBF2 inputs a clock signal of 1 time from CKGH and supplies it to clock wiring CLK on SLIM bus SLMBS.

  In the transmission operation, the data of the data wiring DAT on the SLMBS is taken into the FF3 at the falling edge of CK, and the data and the transmission data TXDAT are subjected to an EXOR operation. Then, this EXOR operation result is taken into FF1 at the rising edge of CK and sent to DAT on SLMBS via OBF1. On the other hand, during the reception operation, an EXOR operation is performed on the output of FF3 described above and the output of FF3 in the previous cycle (that is, the output of FF4). Then, this EXOR operation result is taken into the FF 5 at the rising edge of CK and becomes reception data RXDAT.

  The interface circuit SLMBIF (Slave) shown in FIG. 9 has a configuration in which the above-described CKCTL1 in FIG. 8 is replaced with the clock control circuit CKCTL2, and OBF2 is replaced with the input buffer circuit IBF2. Since the configuration other than this is the same as that of FIG. 8, detailed description thereof is omitted. The IBF 2 receives the clock wiring CLK on the SLIM bus SLMBS as an input. CKCTL2 includes a DDR / SDR mode control circuit DSRCTL similar to CKCTL1 and a selector circuit SEL, in which CKGH of CKCTL1 is replaced with a clock generation circuit CKGS. Unlike CKGH described above, CKGS generates a clock signal having the same frequency (1 times) as CLK and a clock signal having twice that frequency based on the output of IBF2. The SEL selects this 1 or 2 times clock signal according to the DDR mode enable signal DDREN from the DSRCTL, and outputs it as the internal clock signal CK. Although not particularly limited, CKGH and CKGS are configured by, for example, a PLL (Phase Locked Loop) circuit or the like.

  FIG. 10 is a waveform diagram showing a main operation example in the interface circuit of FIGS. In FIG. 10, for example, the operation waveform examples of FIG. 8 and FIG. 9 corresponding to around “DA0a” to “DA2” in FIG. 7 are shown. Further, the description will be made assuming that the transmission data TXDAT at this time is all “1”. 10, the first slot (SLT) corresponds to “DA0a” and “DA0b” in FIG. 7, the second SLT corresponds to “DA1a” and “DA1b” in FIG. 7, and the third SLT corresponds to “DA2” in FIG. The DDR / SDR mode control circuit DSRCTL of FIGS. 8 and 9 controls the DDR mode enable signal DDREN to “1” during this period in order to operate the first and second SLTs in the DDR mode as described in FIG. Further, in order to operate the third SLT in the SDR mode, DDREN during this period is controlled to '0'. Accordingly, an internal clock signal CK having a frequency twice that of the clock signal CLK on the SLIM bus is generated at the first SLT and the second SLT, and CK having the same frequency as CLK is generated at the third SLT.

  First, the transmission operation will be described. At the first SLT, when transmitting the first data in synchronization with the internal clock signal CK, the data line DAT is synchronized with the falling edge of CK in the previous clock cycle C0 using the flip-flop circuit FF3 in advance. Are latched. Then, the EXOR operation result of the output of FF3 and the transmission data TXDAT is sent to DAT in synchronization with the rising edge of CK in the next clock cycle C1 (first clock cycle of the first SLT). Similarly, in the continuous transmission period in the DDR mode, for example, when data is transmitted in the third clock cycle C3 of the first SLT, the FF3 synchronizes with the falling edge of CK in the previous clock cycle C2. DAT data is latched. Then, the EXOR operation result of the output of FF3 and the transmission data TXDAT is sent to DAT in synchronization with the rising edge of CK in the next clock cycle C3.

  Next, the reception operation will be described. At the 1st SLT, when receiving the first data in synchronization with CK, the DAT data in the previous clock cycle C0 is latched in synchronization with the falling edge of CK in the previous clock cycle C0 using FF3 in advance. Is done. The latch data is latched by the FF 4 in synchronization with the falling edge of CK in the next clock cycle C1 (first clock cycle of the first SLT). In C1, the DAT data in the current clock cycle C1 is latched by FF3 in synchronization with the falling edge of CK. Then, the EXOR operation result of the latch data of the previous clock cycle C0 (output of FF4) and the latch data of the current clock cycle C1 (output of FF3) is the clock cycle C2 next to CK (the second clock cycle of the 1SLT). ) Is transmitted to the inside as received data RXDAT in synchronization with the rising edge.

  Similarly, in the continuous reception period in the DDR mode, for example, when data is received in the third clock cycle C3 of the first SLT, the FF3 synchronizes with the falling edge of CK in the previous clock cycle C2. DAT data is latched. The latch data is latched by the FF 4 in synchronization with the falling edge of CK in the next clock cycle C3. Further, in C3, the DAT data of the current clock cycle C3 is latched by FF3 in synchronization with the falling edge of CK. Then, the EXOR operation result of the latch data (FF4 output) of the previous clock cycle C2 and the latch data (FF3 output) of the current clock cycle C3 is the clock cycle C4 (fourth clock cycle of the first SLT) next to CK. ) Is transmitted to the inside as RXDAT in synchronization with the rising edge.

  Here, in the transmission operation and the reception operation of FIG. 10, the third SLT operates in the SDR mode as described above. Therefore, when another device transmits data in the clock cycle Cn + 1 following the third SLT (that is, when, for example, “DB0” in FIG. 7 is transmitted), the other device is in the previous clock cycle Cn. Data in the data line DAT can be reliably latched in synchronization with the falling edge of its own internal clock signal CK. That is, since Cn is in the SDR mode, DAT data transition is not performed in synchronization with the falling edge of the clock signal CLK. As a result, the data transfer rate can be improved without causing the problem described with reference to FIG. Here, all the clock cycles in the last slot of each segment are set to the SDR mode. However, in principle, only the last clock cycle (Cn in FIG. 10) in the last slot may be in the SDR mode. . However, as long as it is limited to the SLIMbus (registered trademark) standard, data processing is performed in units of slots. Therefore, as shown in FIG. 10, it is desirable to use an operation method in which the DDR mode and the SDR mode are not mixed in one slot.

<< Initial setting method of SLIM bus operation method [2] >>
FIG. 11 is a flowchart showing an example of an initial setting (config) method in the operation method of FIG. In the SLIMbus (registered trademark) standard, as described with reference to FIG. 18, it is possible to perform communication initial setting (configuration) in advance using a message channel in the control area CTLSP. Therefore, in this embodiment, the host device (active manager) (typically, the MCU in FIG. 1) supports the DDR mode for the target slave device (device other than the MCU in FIG. 1) on the SLIM bus. Whether or not the message channel is inquired in advance, and the channel is constructed based on the result.

  Here, as a premise, it is assumed that the host device is compatible with the DDR mode, and each slave device holds information on the presence / absence of support for the DDR mode in a setting bit called “User Information Element”. Shall. In addition, it is assumed that a “NEXT_DDR_CHANNEL” message is newly provided as an instruction for operating the slave device in the DDR mode. Further, each slave device performs data transmission / reception with the host device. In FIG. 11, step S200 consisting of steps S201 to S206 is a configuration flow generally performed in the SLIMbus (registered trademark) standard, and step S100 consisting of steps S101 to S104 is associated with the operation method of the present embodiment. Newly added.

  In FIG. 11, first, the host device issues a “User Information Element” transmission command to the slave device of the communication partner by using a “REQUEST_INFORMATION” message (S101). Next, the host device receives the “REPLAY_INFORMATION” message including the information of “User Information Element” from the target slave device (S102). Subsequently, the host device determines whether or not the target slave device is compatible with the DDR mode based on the information of S102 (S103). If the host device is compatible with the DDR mode, the host device transmits a “NEXT_DDR_CHANNEL” message to the target slave device, and then proceeds to S201 (S104). On the other hand, if the DDR mode is not supported, the process proceeds to S201 as it is.

  In S201, the host device transmits a “CONNECT_SOURCE” or “CONNECT_SINK” message to the target slave device. The target slave device that has received the “CONNECT_SOURCE” message performs a data transmission operation on the channel, and the target slave device that has received the “CONNECT_SINK” message performs a data reception operation on the channel. Next, the host device transmits a “NEXT_DEFINE_CHANNEL” message to the target slave device (S202). The “NEXT_DEFINE_CHANNEL” message is for indicating a channel number.

  Subsequently, the host device transmits a “NEXT_DEFINE_CONTENT” or “CHANGE_CONTENT” message to the target slave device (S203). These messages are for indicating the channel arrangement (segment offset, segment length, segment interval) as described in FIG. Next, the host device transmits a “NEXT_ACTIVATE_CHANNEL” message to the target slave device (S204). The “NEXT_ACTIVATE_CHANNEL” message is for instructing to activate the channel (begin data transfer) at the next reconfiguration boundary. Thereafter, a “RECONFIG_NOW” message is transmitted and received between the host device and the target slave device to determine a reconfiguration boundary (frame boundary (strictly, a boundary of 8 frame groups called superframes)) (S205). A channel is established (S206).

  Accordingly, for example, the target slave device that has received the “NEXT_DDR_CHANNEL” message in S104 described above communicates with the host device using the DDR mode as illustrated in FIGS. 7 and 10 in the channel established in S206. I do. On the other hand, the target slave device that has not received the “NEXT_DDR_CHANNEL” message in S104 communicates with the host device using the normal SDR mode in the channel established in S206. In this way, by adding the flow of step S100, the target slave device can maintain the backward compatibility of the SLIMbus (registered trademark) standard (that is, the data transmission / reception operation using the SDR mode and the configuration flow associated therewith). It can be used only when the DDR mode is supported. Here, the communication partner of the slave device is the host device, but it is of course possible to set it to another slave device. In this case, as in the case of FIG. 11, the host device inquires of both slave devices whether or not the DDR mode is supported, and if both are compatible, a “NEXT_DDR_CHANNEL” message is transmitted to both. Good.

  As described above, by using the semiconductor integrated circuit device and the communication system according to the first embodiment, it is possible to improve the data transfer speed while maintaining backward compatibility such as SLIMbus (registered trademark) standard. Become.

(Embodiment 2)
In the second embodiment, an operation method in the case where channels in the DDR mode are continuous will be described as a modified example of the operation method in FIG. 12 (a) and 12 (b) are conceptual diagrams showing different structural examples of frames flowing on the SLIM bus in the communication system according to the second embodiment of the present invention. FIG. 13 is a waveform diagram showing a detailed operation example of FIGS. 8 and 9 when the operation method of FIG. 12B is used. The communication system according to the second embodiment includes, for example, the configuration example shown in FIG. 1 described above, and the SLIM bus interface circuit SLMBIF as shown in FIGS. 8 and 9 in each device (semiconductor integrated circuit device). Is provided. The frame structure shown in FIGS. 12A and 12B is different from the frame structure of FIG. 7 described above in that the DDR mode is applied to the channel B (CH_B).

  In the frame structure shown in FIG. 12A, the SDR mode is applied to the last slot (DB2, DB5, DB8,...) Of each segment in CH_B as in the case of channel A (CH_A). On the other hand, in the frame structure shown in FIG. 12B, the SDR mode is applied to the last slot (DB2, DB5, DB8,...) Of each segment in CH_B, but the last slot of each segment in CH_A. Even DDR mode is applied. For example, as shown in FIG. 10, it is assumed that the DDR mode enable signal DDREN is enabled only during the slot period in which the DDR mode is applied. In this case, in FIG. 12A, in order to output the first data of each segment on the CH_B side (for example, data of the first clock cycle in “DB0a”), the last slot (for example, each segment on the CH_A side) It is necessary to apply the SDR mode to DA2) so that data on the data wiring DAT can be detected.

  However, as shown in FIG. 12B, for example, as shown in FIG. 12B, by enabling DDREN from the slot period immediately before the slot period in which the DDR mode is actually applied, as shown in FIG. The DDR mode can be applied to the last slot of the segment. In FIG. 13, using the interface circuit SLMBIF shown in FIGS. 8 and 9, the transmission operation using the DDR mode is performed in CH_A as shown in FIG. 12B, and then the DDR mode is also performed in CH_B. A transmission operation using is performed. Here, as shown in FIG. 13, the transmission operation in the DDR mode in CH_B is performed from the first SLT of the segment made up of 3SLT (the first clock cycle C01 in the slot), but prior to that, in CH_A From the last slot (third SLT), DDREN is driven to the enable state ('1').

  In this case, when the first data is transmitted in synchronization with the internal clock signal CK at the first SLT of CH_B, the flip-flop circuit FF3 is used in advance to synchronize with the falling edge of CK in the previous clock cycle C00. Thus, the data on the data line DAT is latched. At this time, since the CK has a frequency twice that of the clock signal CLK in accordance with the enable state of DDREN, as shown in FIG. 13, DAT transition is not performed at the timing of the falling edge of CK in C00. It becomes possible to accurately latch DAT data. Then, the EXOR operation result of the output of FF3 and the transmission data TXDAT is sent to DAT in synchronization with the rising edge of CK in the next clock cycle C01 (first clock cycle of the first SLT).

  In CH_B, in this example, since the control area CTLSP follows the last slot of each segment, the last slot is set to the SDR mode. As described above, when the operation method as shown in FIGS. 12B and 13 is used, the data transfer rate can be further improved as compared with the case of FIG. However, there is a need to enable DDRREN in advance (that is, CK is doubled outside the original range), and it may be difficult to apply depending on the situation of the subsequent slot as in the case of CH_B. For this reason, it becomes necessary to determine the status of the previous and subsequent slots, and there is a risk that the actual control and the determination of whether or not to apply will be complicated. From this point of view, it is desirable to use a system as shown in FIG.

  As described above, by using the semiconductor integrated circuit device and the communication system according to the second embodiment, it is possible to improve the data transfer speed while maintaining backward compatibility such as SLIMbus (registered trademark) standard. Become.

(Embodiment 3)
In the third embodiment, another modification of the operation method of FIG. 7 described above will be described. FIG. 14 is a conceptual diagram showing a structure example of a frame flowing on the SLIM bus in the communication system according to the third embodiment of the present invention. The communication system according to the third embodiment includes, for example, the configuration example as shown in FIG. 1 described above, and the SLIM bus interface circuit SLMBIF as shown in FIGS. 8 and 9 in each device (semiconductor integrated circuit device). Is provided. The frame structure shown in FIG. 14 is different from the frame structure of FIG. 7 described above in that the last slot of each segment in channel A (CH_A) is not the SDR mode but is a blank slot (that is, data on the data line DAT during the slot period). Is continuously maintained). By making the last slot a blank slot, the data transfer rate is reduced as compared with the case of FIG. 7, but the data transfer rate may be increased as compared with the case of only the SDR mode, and as shown in FIG. It is possible to easily solve such problems.

  In the operation method shown in FIG. 14, the host device (active manager) appropriately sets the channel arrangement (segment offset, segment length, segment interval) as described in FIG. 18 using the same flow as in FIG. This can be easily realized. That is, the channel arrangement may be determined so that a blank slot exists between the channel in the DDR mode and the channel assigned to the subsequent stage. A specific example will be described. FIG. 15 is a flowchart showing an example of a channel allocation determination method in the operation method of FIG.

  The flow shown in FIG. 15 is performed, for example, after a channel parameter (channel arrangement) based on the SDR mode is once created by the host device (S301) and then updated. At this time, the channel arrangement has been created in the host device, but the actual setting (instruction for the target device) has not yet been performed. In this state, the host device first confirms whether or not the target device is compatible with the DDR mode using a flow such as S101 to S103 described in FIG. 11 (S302). If not supported, the process proceeds to S308 to complete the creation (update) of the channel parameter, and if supported, the process proceeds to S303.

  In S303, the host device checks whether or not there is one or more slots after the segment of the target device in the currently created channel parameter. If there is a vacancy, as shown in FIG. 14, the current channel parameter is simply changed to the DDR mode, and the process proceeds to S308 to complete the creation (update) of the channel parameter. Specifically, for example, the DDR mode is set for the target device by a process such as S104 in FIG. On the other hand, if there is no space in S303, the process proceeds to S304.

  In S304, the host device confirms whether or not the segment of the target device can be advanced by one slot in the currently created channel parameter. If it can be advanced, the segment offset value is changed to a value smaller by one slot (S309), and the process proceeds to S308 to complete the creation (update) of the channel parameters. Specifically, for example, the DDR mode is set for the target device by a process such as S104 in FIG. 11, and then the segment offset value after change is set for the target device by a process such as S203. . The case where the segment can be advanced by 1 slot is, for example, a case where there is a space of 1 slot or more before the segment of the target device. On the other hand, if it cannot be advanced in S304, the process proceeds to S305.

  In S305, the host device determines whether or not the segment length of the target device can be shortened by one slot in the currently created channel parameter. If it can be shortened, the segment length is changed to a value smaller by one slot (S310), and the process proceeds to S308 to complete the creation (update) of the channel parameters. Specifically, for example, the DDR mode is set for the target device by a process such as S104 in FIG. 11, and then the changed segment length value is set for the target device by a process such as S203. Whether or not the segment length is shortened is determined according to, for example, the segment length of the current channel parameter. That is, when the segment length is “2” in the SDR mode and when the segment length is “1” in the DDR mode, the data transfer speed is the same. In this case, communication may be performed in the SDR mode. On the other hand, if it cannot be shortened in S305, the process proceeds to S306.

  In S306, the host device confirms whether or not there is an empty slot area having a size capable of moving the segment of the target device in any of the data areas on the frame in the currently created channel parameter. . If there is an empty slot area, the segment of the target device is moved to the empty slot area (S311), the process proceeds to S303, and the above-described processing is repeated. On the other hand, if there is no empty slot area in S306, the DDR mode is abandoned (S307), and the process proceeds to S308 to complete the creation (update) of the channel parameters. Thus, the application is performed only when the DDR mode operation method as shown in FIG. 14 is applicable, and when it is not, the operation in the normal SDR mode is performed. That is, backward compatibility with the SLIMbus (registered trademark) standard is maintained.

  As described above, by using the semiconductor integrated circuit device and the communication system according to the third embodiment, it is possible to improve the data transfer speed while maintaining backward compatibility such as SLIMbus (registered trademark) standard. Become. Here, assuming a SLIMbus (registered trademark) standard, a blank of at least one slot period is secured. However, in principle, it is sufficient that a blank of one clock cycle or more can be secured.

(Embodiment 4)
In the fourth embodiment, still another modification of the operation method of FIG. 7 described above will be described. FIG. 16 (a) is a conceptual diagram showing an example of the structure of a frame flowing on the SLIM bus in the communication system according to the fourth embodiment of the present invention, and FIG. 16 (b) corresponds to FIG. 16 (a). It is the schematic which shows the example of an operation | movement waveform for 1 slot on the SLIM bus | bath to perform. The frame structure shown in FIG. 16A is different from the frame structure of FIG. 7 described above in that the slots other than the last slot of each segment in channel A (CH_A) are not in DDR mode but in QDR (Quad Data Rate) mode. Is different. In FIG. 16A, the last slot of each segment is in the SDR mode as in the operation method of FIG. 7, but may be a blank slot as described in FIG.

  The frame structure shown in FIG. 16A is, for example, four times as much information (same as DA0) in FIG. 4A compared to the frame structure shown in FIG. For example, DA0a, DA0b, DA0c, DA0d) are included. Specifically, as shown in FIG. 16B, four cells CL are provided corresponding to four cycles of the clock signal CLK in each slot SLT in the QDR mode, and one cell CL is provided. 4 bits of data are assigned to. Compared with the SDR mode in FIG. 5, the cell data DA0 [3] in FIG. 5 is expanded cell data DA0 (a [3], b [3], c [3], d [3]) in FIG. In the same manner, the cell data DA0 [0] in FIG. 5 is changed to the extended cell data DA0 (a [0], b [0], c [0], d [0]) in FIG. It has been replaced.

  When such an operation method is used, the data transfer rate can be further improved as compared with the case of the DDR mode while maintaining the backward compatibility of the SLIMbus (registered trademark) standard as in the case of the DDR mode. That is, N = 1 in the case of the DDR mode, N = 2 in the case of the QDR mode, and data of 2 N (N = 1, 2, 3,...) In one cell (one cycle of CLK). Can be expanded sequentially so that the data transfer rate can be improved sequentially. Note that the communication system according to the fourth embodiment includes, for example, the configuration example as shown in FIG. 1 described above, and the SLIM bus interface circuit substantially similar to that in FIGS. With SLMBIF. However, in order to correspond to the QDR mode, the clock generation circuits CKGH and CKGS in FIGS. 8 and 9 generate a clock signal four times the CLK.

  As described above, by using the semiconductor integrated circuit device and the communication system according to the fourth embodiment, it is possible to improve the data transfer speed while maintaining backward compatibility such as SLIMbus (registered trademark) standard. Become.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  The semiconductor integrated circuit device and the communication system according to the present embodiment are particularly effective when applied to a mobile phone semiconductor chip and a mobile phone system to which SLIMbus (Serial Low-power Inter-chip Media Bus) (registered trademark) standard is applied. However, the present invention is not limited to this, and can be widely applied to various serial communication systems having clock wiring and data wiring.

ADC Analog / digital conversion circuit ADPCM audio processing circuit AMP amplifier circuit ANT1 antenna ANTSW antenna switch circuit BS bus BSKP bus holding circuit BTCT Bluetooth (registered trademark) control circuit BTIC Bluetooth (registered trademark) high frequency signal processing chip BTIC high frequency signal processing Chip CBL Cable CK Internal clock signal CKCTL Clock control circuit CKGH, CKGS Clock generation circuit CL Cell CLK Clock wiring (clock signal)
CPU Processor unit CTLSP Control area DAC Digital / analog conversion circuit DAT Data wiring (data signal)
DATSP data area DBGPT debug port DDREN DDR mode enable signal DEV device DMAC direct memory access controller DPX duplexer circuit DSRCTL DDR / SDR mode control circuit EOR EXOR (exclusive OR) operation circuit FF flip-flop circuit FLT filter circuit FRM frame IBF input buffer Circuit LNA Low noise amplifier circuit MBD Wiring board MCU Microcomputer MEMSIC Control chip for various sensors MIC Microphone MICCT Control circuit for voice input MICIC Microphone control chip MICIC Control chip MIX Mixer circuit MODIC Mobile phone high frequency signal processing chip NFCIC Low power wireless communication Control chip OBF output buffer circuit OE output enable signal PA power amplifier circuit PGA programmable gain amplifier circuit PWIC power supply control chip RFSYS communication system RXDAT reception data SCI serial communication control circuit SCIIC serial communication control chip SEL selector circuit SFRM subframe SLMBIF SLIM bus interface circuit SLMBS SLIM bus SLT slot SOC system LSI
SPK speaker SPKCT control circuit for audio output SPKIC speaker control chip SPKIC control chip TXDAT transmission data VCO oscillation circuit WLANBK, BTBK, CP, SPKBK1, SPKBK2, MICBK, WLANBK ', BTBK', SPKBK1 ', SPMBK2' WLANCT Wireless LAN Control Circuit WLANIC High Frequency Signal Processing Chip WLANIC High Frequency Signal Processing Chip for Wireless LAN

Claims (19)

A serial interface circuit connected to a serial data bus and a clock bus to which a first clock signal having a first frequency is transmitted;
The serial interface circuit includes:
Within the period of one cycle of the first clock signal, 2 N (N is an integer of 1 or more) data is sequentially transmitted to the serial data bus, and 2 data is transmitted within the period of one cycle of the first clock signal. A first mode for sequentially receiving N-th power (N is an integer equal to or greater than 1) pieces of data from the serial data bus;
The first data is transmitted to the serial data bus within one cycle of the first clock signal, and the first data is received from the serial data bus within one cycle of the first clock signal. A semiconductor integrated circuit device comprising two modes. The semiconductor integrated circuit device according to claim 1.
The data on the serial data bus is an NRZI signal,
The serial interface circuit sequentially transmits or receives data to and from the serial data bus in the first to Mth (M is an integer of 2 or more) successive clock cycles of the first clock signal. The semiconductor integrated circuit device operates in the first mode in the first clock cycle and operates in the second mode in the Mth clock cycle. The semiconductor integrated circuit device according to claim 2.
The serial interface circuit includes:
Receiving the first clock signal from the clock bus, a second clock signal having the same first frequency as the first clock signal, and a third having a frequency of N times the second clock signal. A first clock generation circuit for generating a clock signal;
A first selection circuit for selecting the second clock signal in the second mode, selecting the third clock signal in the first mode, and outputting the first clock signal as a first internal clock signal;
A plurality of first flip-flop circuits that transmit or receive data to or from the serial data bus;
The semiconductor integrated circuit device, wherein the first internal clock signal is supplied to the plurality of first flip-flop circuits. The semiconductor integrated circuit device according to claim 3.
2. The semiconductor integrated circuit device according to claim 1, wherein the serial data bus and the clock bus correspond to a SLIMbus (registered trademark) standard. The semiconductor integrated circuit device according to claim 4.
The serial interface circuit holds first information indicating that it has the first mode,
The semiconductor integrated circuit device according to claim 1, wherein the first information can be read out to the serial data bus by a message channel defined by a SLIMbus (registered trademark) standard. The semiconductor integrated circuit device according to claim 5.
The serial interface circuit has a period of consecutive J (J is an integer greater than or equal to 2) slots, with one continuous clock cycle (K being an integer greater than or equal to 2) of the first clock signal as one slot. To transmit or receive data to or from the serial data bus, and operate in the second mode in the Jth slot, which is the last slot in the J slots, from the first slot (J-1 The semiconductor integrated circuit device operates in the first mode in the first slot. The semiconductor integrated circuit device according to claim 6.
The semiconductor integrated circuit device further includes:
A first frequency conversion circuit for up-converting data received by the serial interface circuit to a frequency band for wireless communication;
A semiconductor integrated circuit device comprising: a second frequency conversion circuit that down-converts data having a frequency band for wireless communication to a predetermined frequency band and outputs the data to the serial interface circuit. The semiconductor integrated circuit device according to claim 2.
The serial interface circuit includes:
A first clock generation circuit for generating a fourth clock signal having the first frequency and a fifth clock signal having a frequency that is N times the second clock frequency of the fourth clock signal;
A second selection circuit for selecting the fourth clock signal in the second mode, selecting the fifth clock signal in the first mode, and outputting the second clock signal as a second internal clock signal;
A plurality of second flip-flop circuits that transmit or receive data to and from the serial data bus;
The fourth clock signal is output to the clock bus as the first clock signal,
The semiconductor integrated circuit device, wherein the second internal clock signal is supplied to the plurality of second flip-flop circuits. A serial interface circuit connected to a serial data bus for transmitting an NRZI signal and a clock bus for transmitting a first clock signal having a first frequency;
The serial interface circuit includes:
Generating a second clock signal having the same first frequency as the first clock signal and a third clock signal having a frequency of N times the second clock signal (N is an integer of 1 or more). A first clock generation circuit;
A control circuit for setting the internal state to the first mode or the second mode;
A selection circuit that selects the third clock signal in the first mode, selects the second clock signal in the second mode, and outputs the second clock signal as an internal clock signal;
A first flip-flop circuit that latches data on the serial data bus at a first edge that is one of a rising edge and a falling edge of the internal clock signal;
A first arithmetic circuit that performs an exclusive OR operation between predetermined transmission data and the output of the first flip-flop circuit;
A second flip-flop circuit that latches an output of the first arithmetic circuit at a second edge that is the other of a rising edge and a falling edge of the internal clock signal, and transmits the latched signal to the serial data bus;
A third flip-flop circuit that latches the output of the first flip-flop circuit at the first edge of the internal clock signal;
A semiconductor integrated circuit device comprising: a second arithmetic circuit that restores received data by performing an exclusive OR operation on the output of the first flip-flop circuit and the output of the third flip-flop circuit. The semiconductor integrated circuit device according to claim 9.
The serial interface circuit sequentially transmits or receives data to and from the serial data bus in the first to Mth (M is an integer of 2 or more) successive clock cycles of the first clock signal. And
The semiconductor integrated circuit device, wherein the control circuit sets the first mode in the first clock cycle and sets the second mode in the Mth clock cycle. The semiconductor integrated circuit device according to claim 10.
2. The semiconductor integrated circuit device according to claim 1, wherein the serial data bus and the clock bus correspond to a SLIMbus (registered trademark) standard. The semiconductor integrated circuit device according to claim 11.
The serial interface circuit has a period of consecutive J (J is an integer greater than or equal to 2) slots, with one continuous clock cycle (K being an integer greater than or equal to 2) of the first clock signal as one slot. To send or receive data to or from the serial data bus,
The control circuit sets the second mode in the Jth slot, which is the last slot in the J slots, and sets the first mode in the (J−1) th slot from the first slot. A semiconductor integrated circuit device. A serial data bus;
A clock bus through which a first clock signal of a first frequency is transmitted;
A first device including a first serial interface circuit connected to the serial data bus and the clock bus;
A second device including a second serial interface circuit connected to the serial data bus and the clock bus;
A third device including a third serial interface circuit connected to the serial data bus and the clock bus;
The first serial interface circuit supplies the first clock signal to the clock bus;
The second and third serial interface circuits are supplied with the first clock signal from the clock bus,
The first and second serial interface circuits are:
Within the period of one cycle of the first clock signal, 2 N (N is an integer of 1 or more) data is sequentially transmitted to the serial data bus, and 2 data is transmitted within the period of one cycle of the first clock signal. A first mode for sequentially receiving N-th power (N is an integer equal to or greater than 1) pieces of data from the serial data bus;
The first data is transmitted to the serial data bus within one cycle of the first clock signal, and the first data is received from the serial data bus within one cycle of the first clock signal. Two modes,
The communication system, wherein the first serial interface circuit operates in the first mode for at least a part of a period when communicating with the second serial interface circuit. The communication system according to claim 13,
The third serial interface circuit includes the second mode without including the first mode,
The communication system, wherein the first serial interface circuit always operates in the second mode when communicating with the third serial interface circuit. The communication system according to claim 13,
The communication system, wherein the serial data bus and the clock bus correspond to a SLIMbus (registered trademark) standard. The communication system according to claim 15,
The second serial interface circuit includes:
Receiving the first clock signal from the clock bus, a second clock signal having the same first frequency as the first clock signal, and a third having a frequency of N times the second clock signal. A first clock generation circuit for generating a clock signal;
A first selection circuit for selecting the second clock signal in the second mode, selecting the third clock signal in the first mode, and outputting the first clock signal as a first internal clock signal;
A plurality of first flip-flop circuits that transmit or receive data to or from the serial data bus;
The first internal clock signal is supplied to the plurality of first flip-flop circuits;
The first serial interface circuit includes:
A second clock generation circuit for generating a fourth clock signal having the first frequency and a fifth clock signal having a frequency that is N times the second clock frequency of the fourth clock signal;
A second selection circuit for selecting the fourth clock signal in the second mode, selecting the fifth clock signal in the first mode, and outputting the second clock signal as a second internal clock signal;
A plurality of second flip-flop circuits that transmit or receive data to and from the serial data bus;
The fourth clock signal is output to the clock bus as the first clock signal,
The communication system, wherein the second internal clock signal is supplied to the plurality of second flip-flop circuits. The communication system according to claim 16, wherein
The second serial interface circuit holds first information indicating that it has the first mode,
The communication system, wherein the first serial interface circuit reads the first information through the serial data bus using a message channel defined by a SLIMbus (registered trademark) standard. The communication system according to claim 16, wherein
The data on the serial data bus is an NRZI signal,
The first serial interface circuit includes consecutive K (J is an integer equal to or greater than 2) slots, with one continuous clock cycle (K being an integer equal to or greater than 2) of the first clock signal as one slot. In this period, communication is performed via the serial data bus for the second serial interface circuit, and the J-th slot which is the last slot among the J slots operates in the second mode. The (J-1) th slot from the first slot operates in the first mode. The communication system according to claim 16, wherein
The data on the serial data bus is an NRZI signal,
The first serial interface circuit includes consecutive K (J is an integer equal to or greater than 2) slots, with one continuous clock cycle (K being an integer equal to or greater than 2) of the first clock signal as one slot. In the period, communication is performed via the serial data bus for the second serial interface circuit, and then the third serial interface circuit is targeted for a period of I slots (I is an integer of 1 or more). Communication is performed via the serial data bus, and there is one between the J-th slot, which is the last slot in the J slots, and the first slot, which is the first slot in the I slots. When the above empty slots can be secured, the communication system operates in the first mode during the period of the J slots.

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