JP2013093491A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

A semiconductor device excellent in ion migration resistance and a method for manufacturing the same are provided.
A semiconductor device according to an embodiment includes a conductor base plate, a first adhesive disposed on the conductor base plate, a semiconductor chip disposed on the first adhesive and bonded to the conductor base plate, and the conductor base plate. The second adhesive is disposed on the outer periphery of the joint surface between the semiconductor chip and the conductor base plate, and covers the first adhesive. The first adhesive contains a conductive metal component, and the second adhesive The adhesive does not contain a conductive metal component.
[Selection] Figure 2

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for mounting an electronic component such as a semiconductor chip.

  Conventionally, as a method for realizing miniaturization of a microwave semiconductor device, for example, there is a method using a monolithic microwave integrated circuit (MMIC). In such an MMIC, the MMIC substrate is bonded onto the conductor base plate using an adhesive having electrical conductivity or thermal conductivity.

JP 2004-43608 A JP-A-4-336451

  Epoxy adhesives that do not contain conductive fillers have high moisture resistance. On the other hand, an epoxy adhesive containing Ag or the like as a conductive filler in an epoxy resin has high thermal conductivity, but contains Ag and thus easily causes ion migration.

  The problem to be solved by the present embodiment is to provide a semiconductor device excellent in ion migration resistance and a manufacturing method thereof.

  The semiconductor device according to the present embodiment includes a conductor base plate, a semiconductor chip, a first adhesive, a semiconductor chip, and a second adhesive. The first adhesive is disposed on the conductor base plate. The semiconductor chip is disposed on the first adhesive and bonded to the conductor base plate. The second adhesive is disposed on the outer periphery of the joint surface between the semiconductor chip and the conductor base plate, and covers the first adhesive. The first adhesive contains a conductive metal component, and the second adhesive does not contain a conductive metal component.

It is a figure which illustrates the semiconductor device which concerns on embodiment, Comprising: The typical bird's-eye view at the time of applying MMIC as a semiconductor chip. The typical cross-section figure along the II line | wire of FIG. The figure for demonstrating the phenomenon which a conductive metal component ionizes and precipitates by ion migration, and grows on a nonmetallic component. Typical cross-section FIG. (1) explaining 1 process of the manufacturing process in the manufacturing method of the semiconductor device which concerns on embodiment. Typical cross-section FIG. (2) explaining 1 process of the manufacturing process in the manufacturing method of the semiconductor device which concerns on embodiment. Typical cross-section FIG. (3) explaining 1 process of the manufacturing process in the manufacturing method of the semiconductor device which concerns on embodiment. Typical cross-section FIG. (4) explaining 1 process of the manufacturing process in the manufacturing method of the semiconductor device which concerns on embodiment. Typical cross-section FIG. (5) explaining 1 process of the manufacturing process in the manufacturing method of the semiconductor device which concerns on embodiment. Typical cross-section FIG. (6) explaining 1 process of the manufacturing process in the manufacturing method of the semiconductor device which concerns on embodiment. (A) The enlarged view of the typical plane pattern structure of the semiconductor chip mounted in the semiconductor device which concerns on embodiment, (b) The enlarged view of J part of Fig.10 (a). It is a structural example of the semiconductor chip mounted in the semiconductor device which concerns on embodiment, Comprising: Typical sectional structure drawing which follows the II-II line | wire of FIG.10 (b).

  Next, embodiments will be described with reference to the drawings. In the following, the same elements are denoted by the same reference numerals to avoid duplication of explanation and to simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and the embodiment does not specify the arrangement of each component as described below. This embodiment can be modified in various ways within the scope of the claims.

  1 is a diagram illustrating a semiconductor device according to an embodiment, and a schematic bird's-eye view structure in the case where an MMIC is applied as a semiconductor chip 24 is represented as shown in FIG. 1 and is taken along a line II in FIG. A schematic cross-sectional structure is expressed as shown in FIG.

  The semiconductor device according to the embodiment includes a conductor base plate 200, a first adhesive 40 disposed on the conductor base plate 200, a semiconductor chip 24 disposed on the first adhesive 40 and bonded to the conductor base plate 200, On the conductor base plate 200, the second adhesive 20 is disposed on the outer periphery of the joint surface between the semiconductor chip 24 and the conductor base plate 200 and covers the first adhesive 40. Here, the 1st adhesive agent 40 contains a conductive metal component, and the 2nd adhesive agent 20 does not contain a conductive metal component.

  Moreover, the 1st adhesive agent 40 and the 2nd adhesive agent 20 may be comprised from the same epoxy resin component.

  The second adhesive 20 further covers the outer periphery of the side surface of the semiconductor chip 24.

  The second adhesive 20 may further cover the outer periphery of the side surface of the semiconductor chip 24 and the outer peripheral portion of the edge of the upper surface of the semiconductor chip 24.

  More specifically, the semiconductor device according to the embodiment includes a conductor base plate 200, a semiconductor chip 24 (MMIC substrate) that has an input terminal 24a and an output terminal 24b and is joined to the conductor base plate 200, and a conductor base plate. 200, the ceramic frame 180 surrounding the semiconductor chip 24, the RF input terminal 21a and the RF output terminal 21b disposed on the ceramic frame 180, and the connection between the RF input terminal 21a and the input terminal 24a. A bonding wire 12 that connects the output terminal 24b and the RF output terminal 21b.

  The semiconductor chip 24 is bonded onto the conductor base plate 200 by the first adhesive 40. The first adhesive 40 is an adhesive for joining the joining surfaces of the semiconductor chip 24 and the conductor base plate 200. For example, conductive metal particles such as Ag are used as an electrically conductive filler on an organic material such as an epoxy resin. The contained adhesive can be applied. In addition to Ag, the conductive filler can be appropriately selected from conductive metal particles such as Au, Cu, Pt, Pd, and Ni, or may be selected from functional fillers such as Cu-Ag. On the other hand, the second adhesive 20 is an adhesive formed (applied) on the outer periphery of the bonding surface so as to cover the first adhesive 40 formed on the bonding surface between the semiconductor chip 24 and the conductor base plate 200. An adhesive that does not contain a conductive metal component can be applied.

  Since the first adhesive 40 contains a conductive filler such as Ag, it is used for joining the conductor base plate 200 and the semiconductor chip 24. However, conductive metal components such as Ag used for the conductive filler tend to cause elution and easily cause ion migration.

  Here, ion migration means that when a DC voltage is applied to an electrode under high humidity, a conductive metal component such as silver powder contained in the conductive adhesive is ionized and deposited, and the non-metallic component is deposited on the non-metallic component. It is a phenomenon that grows.

  For example, when a DC voltage is applied to the electrode under high humidity, a conductive metal component such as silver powder contained in the conductive adhesive is ionized and deposited, and as illustrated in FIG. Grows up in the direction of arrow A. The grown metal component causes dielectric breakdown between the electrodes, for example. Further, the grown conductive metal component causes a failure due to a short circuit or the like.

  Therefore, the second adhesive 20 containing no conductive metal component is formed on the outer periphery of the joint surface so as to cover the first adhesive 40 formed on the joint surface of the semiconductor chip 24 and the conductor base plate 200 ( By applying), the second adhesive 20 seals the first adhesive 40. Thereby, it is possible to prevent the conductive metal component contained in the first adhesive 40 from being eluted.

  Since it is not necessary to add a contaminant other than the conductive filler of Ag to the first adhesive 40, there is no problem that the thermal conductivity inherent to the conductive adhesive is impaired. Further, since the second adhesive 20 is only formed so as to cover the first adhesive 40 formed on the joint surface between the semiconductor chip 24 and the conductor base plate 200, the entire surface of the semiconductor chip 24 is coated. There is no problem that the dielectric constant of the surface of the operation region of the semiconductor device is increased and the dielectric constant of the surface of the wire or line is increased.

  Further, by adopting a moisture-proof epoxy adhesive as the second adhesive 20, the conductive metal contained in the first adhesive 40 applied to the bonding surface between the semiconductor chip 24 and the conductor base plate 200. Ingredients can be protected from moisture.

  Furthermore, the first adhesive 40 and the second adhesive 20 are cured and cured by adopting the same epoxy-based solvent as the solvent for the first adhesive 40 and the second adhesive 20, respectively. It is not necessary to perform the process of making it separate, and the curing process of the 1st adhesive agent 40 and the 2nd adhesive agent 20 is realizable by one process.

(Production method)
As shown in FIGS. 4 to 6, the method of manufacturing a semiconductor device according to the embodiment includes a step of forming a first adhesive 40 on the conductor base plate 200, and a conductor base plate 200 on the first adhesive 40. The step of disposing the semiconductor chip 24 to be bonded, and the step of forming the second adhesive 20 covering the first adhesive 40 on the outer periphery of the joint surface between the semiconductor chip 24 and the conductor base plate 200 on the conductor base plate 200. And a step of curing and curing the first adhesive 40 and the second adhesive 20. Here, the 1st adhesive agent 40 contains a conductive metal component, and the 2nd adhesive agent 20 does not contain a conductive metal component.

  In the method for manufacturing a semiconductor device according to the embodiment, the first adhesive 40 and the second adhesive 20 may contain the same epoxy resin component.

  In the method of manufacturing a semiconductor device according to the embodiment, the second adhesive 20 may be formed so as to further cover the outer periphery of the side surface of the semiconductor chip 24 as shown in FIGS.

  In the method of manufacturing a semiconductor device according to the embodiment, the second adhesive 20 further covers the outer periphery of the side surface of the semiconductor chip 24 and the outer peripheral portion of the edge of the upper surface of the semiconductor chip 24 as shown in FIG. It may be formed so as to.

  Hereinafter, a method for manufacturing a semiconductor device according to the embodiment will be described in detail with reference to FIGS.

(A) First, as shown in FIG. 4, the ceramic frame 180 surrounding the semiconductor chip 24 is disposed on the conductor base plate 200, and the RF input terminal 21 a and the RF output terminal 21 b are disposed on the ceramic frame 180. Then, the first adhesive 40 is applied to the joint surface between the conductor base plate 200 and the semiconductor chip 24 on the conductor base plate 200. Although the thickness which apply | coats the 1st adhesive agent 40 depends on the kind of adhesive agent which comprises the 1st adhesive agent 40, it is about 60 micrometers-about 180 micrometers, for example.

(B) Next, as shown in FIG. 5, the semiconductor chip 24 having the input terminal 24 a and the output terminal 24 b is disposed on the first adhesive 40 applied to the bonding surface on the conductor base plate 200. The conductor base plate 200 and the semiconductor chip 24 are joined by the first adhesive 40 formed on the joining surface. The thickness of the first adhesive 40 after the semiconductor chip 24 is disposed on the bonding surface hardly changes compared to the thickness before the semiconductor chip 24 is disposed, and is, for example, about 50 μm to about 150 μm.

(C) Next, as shown in FIG. 6, it coats and forms on the outer periphery of a joining surface so that the 1st adhesive agent 40 formed in the joining surface of the semiconductor chip 24 and the conductor baseplate 200 may be coat | covered. The thickness to which the second adhesive 20 is applied depends on the type of adhesive constituting the second adhesive 20, but is, for example, about 60 μm to about 180 μm. Moreover, as a method of apply | coating the 2nd adhesive agent 20, it can pour into the outer periphery whole area of a joining surface and the 1st adhesive agent 40, for example using the dispenser, syringe, etc. for adhesive agents.

(D) Next, the first adhesive 40 and the second adhesive 20 are cured (heat treated) and cured. The thicknesses of the first adhesive 40 and the second adhesive 20 that have been cooled to room temperature after the curing process are both about 20 μm to about 60 μm, for example.

  In the example shown in FIG. 7, the second adhesive 20 a that has been cured and cured is covered (sealed) so as to cover the first adhesive 40 formed on the joint surface between the semiconductor chip 24 and the conductor base plate 200. And so on) and is formed so as to cover the outer periphery of the side surface of the semiconductor chip 24.

(E) Next, as shown in FIG. 8, the bonding wire 12 connects the RF input terminal 21a and the input terminal 24a, and the bonding wire 16 connects the output terminal 24b and the RF output terminal 21b. .

  FIG. 9 shows another example of forming the second adhesive 20b cured and cured. The second adhesive 20b after the curing process is formed on the outer periphery of the joint surface so as to cover (seal) the first adhesive 40 formed on the joint surface between the semiconductor chip 24 and the conductor base plate 200. Further, it is formed so as to cover the outer periphery of the side surface of the semiconductor chip 24 and the outer peripheral portion of the edge of the upper surface of the semiconductor chip 24.

(Semiconductor element structure)
An enlarged view of a schematic planar pattern configuration of the FET 140 of the semiconductor chip 24 mounted on the semiconductor device according to the embodiment is represented as shown in FIG. 10A, and is an enlarged view of a portion J in FIG. Is expressed as shown in FIG. 11 is a configuration example of the FET 140 of the semiconductor chip 24 mounted on the semiconductor device according to the embodiment, and a schematic cross-sectional configuration example taken along the line II-II in FIG. expressed.

  In the semiconductor chip 24 mounted on the semiconductor device according to the embodiment, the plurality of FET cells FET1 to FET10 include the semi-insulating substrate 110 and the first of the semi-insulating substrate 110 as shown in FIGS. A gate finger electrode 124, a source finger electrode 120, and a drain finger electrode 122, each having a plurality of fingers, disposed on the surface, and disposed on a first surface of the semi-insulating substrate 110, the gate finger electrode 124, the source finger electrode 120, and A plurality of gate terminal electrodes G1, G2,..., G10 formed by bundling a plurality of fingers for each drain finger electrode 122, a plurality of source terminal electrodes S11, S12, S21, S22,. D1, D2, ..., D10 and the source end VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 disposed under the electrodes S11, S12, S21, S22,..., S101, S102, and the first surface of the semi-insulating substrate 110 on the opposite side. Ground electrodes (disposed on the second surface and connected to the source terminal electrodes S11, S12, S21, S22,..., S101, S102 via the VIA holes SC11, SC12, SC21, SC22,. (Not shown).

  The gate terminal electrodes G1, G2,..., G10 are connected with bonding wires, the drain terminal electrodes D1, D2,..., D10 are connected with bonding wires, and the source terminal electrodes S11, S12, S21, S22,. , S101, S102, VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 are formed, and barriers formed on the inner walls of the VIA holes SC11, SC12, SC21, SC22,. The source terminal electrodes S11, S12, S21, S22,..., S101, and S102 are ground electrodes through a metal layer (not shown) formed on the metal layer (not shown) and the barrier metal layer and filling the VIA hole. (Not shown).

  The semi-insulating substrate 110 is a GaAs substrate, SiC substrate, GaN substrate, substrate having a GaN epitaxial layer formed on the SiC substrate, substrate having a heterojunction epitaxial layer made of GaN / AlGaN on the SiC substrate, sapphire substrate, or One of the diamond substrates.

(Structure example of FET cell)
The configuration example of the FET cell of the semiconductor chip 24 mounted on the semiconductor device according to the embodiment includes a semi-insulating substrate 110 and a nitride compound disposed on the semi-insulating substrate 110 as shown in FIG. Semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride compound semiconductor layer 112, and aluminum gallium nitride layer (Al _x Ga) _1-x N) (0.1 ≦ x ≦ 1) 118, a source finger electrode (S) 120, a gate finger electrode (G) 124, and a drain finger electrode (D) 122. A two-dimensional electron gas (2DEG) layer is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. 116 is formed. In the configuration example shown in FIG. 11, a high electron mobility transistor (HEMT) is shown.

  In the above configuration example, the nitride compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region. Here, the active region refers to the 2DEG layer 116 immediately below the source finger electrode 120, the gate finger electrode 124, and the drain finger electrode 122, between the source finger electrode 120 and the gate finger electrode 124, and between the drain finger electrode 122 and the gate finger electrode 124. 2 DEG layer 116.

  The source finger electrode 120 and the drain finger electrode 122 are made of, for example, Ti / Al. The gate finger electrode 124 can be formed of, for example, Ni / Au.

  In the FET 140, the pattern length in the longitudinal direction of the gate finger electrode 124, the source finger electrode 120, and the drain finger electrode 122 is set shorter as the operating frequency increases. For example, in the millimeter wave band, the pattern length is about 25 μm to about 50 μm.

  Further, the width of the source finger electrode 120 is, for example, about 40 μm, and the width of the source terminal electrodes S11, S12, S21, S22,..., S101, S102 is, for example, about 100 μm. The formation width of the VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 is, for example, about 10 μm to about 40 μm.

  According to the embodiment described above, the first adhesive 40 containing the conductive filler such as Ag is used for joining the conductor base plate 200 and the semiconductor chip 24 and does not contain the conductive filler. The conductive material contained in the first adhesive 40 is formed by forming the two adhesives 20 on the outer periphery of the joint surface so as to cover the first adhesive 40 formed on the joint surface between the semiconductor chip 24 and the conductor base plate 200. It is possible to prevent the metallic metal component from elution.

  Further, by adopting a moisture-proof epoxy adhesive as the second adhesive 20, the conductive metal contained in the first adhesive 40 applied to the bonding surface between the semiconductor chip 24 and the conductor base plate 200. Ingredients can be protected from moisture.

  Furthermore, the first adhesive 40 and the second adhesive 20 are cured and cured by adopting the same epoxy-based solvent as the solvent for the first adhesive 40 and the second adhesive 20, respectively. It is not necessary to perform the process of making it separate, and the curing process of the 1st adhesive agent 40 and the 2nd adhesive agent 20 is realizable by one process.

  According to the embodiment described above, it is possible to provide a semiconductor device excellent in ion migration resistance and a manufacturing method thereof.

[Other embodiments]
Although the semiconductor device according to the embodiment has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  The semiconductor device according to the embodiment is not limited to the FET, and a high electron mobility transistor (HEMT) may be applied, or an LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor). Needless to say, an amplifying element such as a heterojunction bipolar transistor (HBT) can also be applied.

  As described above, various embodiments that are not described herein are included.

  The semiconductor device according to the embodiment can be applied to a wide range of fields such as an internal matching power amplifying element, a power MMIC (Monolithic Microwave Integrated Circuit), a microwave power amplifier, a millimeter wave power amplifier, and a high-frequency MEMS element.

DESCRIPTION OF SYMBOLS 12, 16 ... Bonding wire 21a ... RF input terminal 21b ... RF output terminal 24a ... Input terminal 24b ... Output terminal 24 ... Semiconductor chip (MMIC board)
40 ... first adhesive 20 (20a, 20b) ... second adhesive 110 ... semi-insulating substrate 112 ... nitride compound semiconductor layer (GaN epitaxial growth layer)
116: Two-dimensional electron gas (2DEG) layer 118: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
120 ... Source finger electrode 122 ... Drain finger electrode 124 ... Gate finger electrode 126 ... Source region 128 ... Drain region 140FET
180 ... ceramic frame 200 ... conductor base plates D, D1, D2, ..., D10 ... drain terminal electrodes G, G1, G2, ..., G10 ... gate terminal electrodes S, S11, S12, ..., S101, S102 ... source terminal electrodes SC11, SC12, ..., SC102 ... VIA Hall

Claims (8)

A conductor base plate;
A first adhesive disposed on the conductor base plate;
A semiconductor chip disposed on the first adhesive and bonded to the conductor base plate;
On the conductor base plate, the second adhesive is disposed on the outer periphery of the joint surface between the semiconductor chip and the conductor base plate, and covers the first adhesive.
The first adhesive contains a conductive metal component, and the second adhesive does not contain a conductive metal component.   The semiconductor device according to claim 1, wherein the first adhesive and the second adhesive contain the same epoxy resin component.   The semiconductor device according to claim 1, wherein the second adhesive further covers a side surface outer periphery of the semiconductor chip.   2. The semiconductor device according to claim 1, wherein the second adhesive further covers the outer periphery of the side surface of the semiconductor chip and the outer peripheral portion of the edge of the upper surface of the semiconductor chip. Forming a first adhesive on the conductor base plate;
Disposing a semiconductor chip to be bonded to the conductor base plate on the first adhesive;
On the conductor base plate, a step of forming a second adhesive covering the first adhesive on the outer periphery of the joint surface between the semiconductor chip and the conductor base plate;
Curing and curing the first adhesive and the second adhesive,
The method of manufacturing a semiconductor device, wherein the first adhesive contains a conductive metal component, and the second adhesive does not contain a conductive metal component.   The method of manufacturing a semiconductor device according to claim 5, wherein the first adhesive and the second adhesive contain the same epoxy resin component.   The method for manufacturing a semiconductor device according to claim 5, wherein the second adhesive is formed so as to further cover a side surface outer periphery of the semiconductor chip.   The semiconductor device according to claim 5, wherein the second adhesive is further formed so as to cover an outer periphery of a side surface of the semiconductor chip and an outer peripheral portion of an edge of the upper surface of the semiconductor chip. Method.