JP2013196725A - Nonvolatile semiconductor memory device - Google Patents

Abstract

A nonvolatile semiconductor memory device with high controllability is provided.
A non-volatile semiconductor memory device includes a plurality of NAND cell units each including a plurality of memory cells connected in series in a first direction in a second direction orthogonal to the first direction. However, a memory cell array having a semiconductor layer, a gate insulating layer, a floating gate, and a control gate and a plurality of memory cells arranged in the second direction are used as pages, and data is written to the memory cells in units of pages. And a control circuit that responds to write data to the selected memory cell and write data to the memory cell adjacent to the selected memory cell in the second direction during a write operation to the plurality of memory cells in page units. To adjust the write verify level of the selected memory cell.
[Selection] Figure 9

Description

  The technology described in this specification relates to a nonvolatile semiconductor memory device.

  A NAND flash memory is known as a nonvolatile semiconductor memory device that can be electrically rewritten and can be highly integrated. A memory transistor of a conventional NAND flash memory has a stack gate structure in which a charge storage layer (floating gate) and a control gate are stacked via an insulating film. A plurality of memory transistors are connected in series in the column direction so that adjacent ones share a source or drain, and select gate transistors are arranged at both ends to constitute a NAND cell unit. One end of the NAND cell unit is connected to the bit line, and the other end is connected to the source line. A memory cell array is configured by arranging NAND cell units in a matrix. A NAND cell unit arranged in the row direction is called a NAND cell block. The gates of the select gate transistors arranged in the same row are connected to the same select gate line, and the control gates of the memory transistors arranged in the same row are connected to the same word line. When N memory transistors are connected in series in the NAND cell unit, the number of word lines included in one NAND cell block is N.

  In such a NAND flash memory, as the distance between memory cells decreases with miniaturization, the proximity effect due to the increase in inter-cell capacity of the memory cells increases, and the threshold distribution of the memory cells becomes wider. It becomes difficult to secure various disturbances and retention margins.

JP 2009-295232 A JP 2009-123256 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device with high controllability.

  A nonvolatile semiconductor memory device according to an embodiment includes a plurality of memory cells connected in series in a first direction, a source line side select gate transistor connected between the plurality of memory cells and the source line, and a plurality of memory cells A plurality of NAND cell units each including a bit line side select gate transistor connected between the first and second bit lines are arranged in a second direction orthogonal to the first direction, and the memory cell includes a semiconductor layer, a semiconductor layer, A memory cell array having a gate insulating layer formed thereon, a floating gate formed on the gate insulating layer, and a control gate facing the floating gate via the inter-gate insulating layer and extending in the second direction A control circuit for writing data to the memory cells in units of pages using a plurality of memory cells arranged in the second direction as pages. In write operation to the number of memory cells, to adjust the write verify level of the selected memory cell in accordance with the write data and write data and a selected memory cell to the selected memory cell to the memory cells adjacent in the second direction.

1 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device according to a first embodiment. It is a figure which shows the memory cell array structure of the non-volatile semiconductor memory device. It is an equivalent circuit diagram of the same memory cell array. It is a perspective view of the memory cell array. It is sectional drawing of the memory cell array. It is sectional drawing of the memory cell array. It is a schematic diagram for demonstrating the write-in operation of a comparative example. It is a schematic diagram for demonstrating the influence of the proximity effect of the non-volatile semiconductor memory device which concerns on a comparative example. FIG. 6 is a schematic diagram for explaining a write operation of the nonvolatile semiconductor memory device according to the first embodiment. 4 is a flowchart showing an example of a write operation characteristic of an operation of the nonvolatile semiconductor memory device. It is a figure which shows the example of the weighting method of the same non-volatile semiconductor memory device.

  Embodiments will be described below with reference to the accompanying drawings.

[First Embodiment]
[overall structure]
FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to the first embodiment of the present invention.

  This nonvolatile semiconductor memory device includes a memory cell array 1 including a plurality of NAND strings in which a plurality of memory cells MC are NAND-connected.

  Column control for controlling the bit line BL of the memory cell array 1 at a position adjacent to the bit line BL direction of the memory cell array 1 to perform data erasure of the memory cell, data writing to the memory cell, and data reading from the memory cell. A circuit 2 is provided.

  In addition, the word line WL of the memory cell array 1 is selected at a position adjacent to the word line WL direction of the memory cell array 1 and is necessary for erasing data in the memory cell, writing data to the memory cell, and reading data from the memory cell. A row control circuit 3 is provided for applying an appropriate voltage.

  The data input / output buffer 4 is connected to an external host 9 via an I / O line, and receives write data, receives an erase command, outputs read data, and receives address data and command data. The data input / output buffer 4 sends the received write data to the column control circuit 2, receives the data read from the column control circuit 2, and outputs it to the outside. An address supplied from the outside to the data input / output buffer 4 is sent to the column control circuit 2 and the row control circuit 3 via the address register 5.

  The command supplied from the host 9 to the data input / output buffer 4 is sent to the command interface 6. The command interface 6 receives an external control signal from the host 9, determines whether the data input to the data input / output buffer 4 is write data, a command, or an address, and if it is a command, receives it as a received command signal to the state machine 7. Forward.

  The state machine 7 manages the entire nonvolatile memory. The state machine 7 receives commands from the host 9 via the command interface 6 and performs read, write, erase, data input / output management, and the like.

  The external host 9 can also receive status information managed by the state machine 7 and determine the operation result. This status information is also used for control of writing and erasing.

  The data input / output buffer 4 is connected to a comparator 61 that detects and adds the write data received by the data input / output buffer 4 and transfers it to the state machine 7. As the comparator 61, a logic circuit such as an adder circuit can be used.

  In addition, the voltage generator 60 is controlled by the state machine 7. By this control, the voltage generation circuit 60 can output a pulse having an arbitrary voltage and arbitrary timing. In the write operation, the state machine 7 refers to the information output from the comparator 61 and adjusts the verify voltage.

  Here, the formed pulse can be transferred to an arbitrary wiring selected by the column control circuit 2 and the row control circuit 3. Note that peripheral circuit elements other than the memory cell array 1 can be formed on the Si substrate immediately below the memory array 1 when the memory cell array 1 is formed in a wiring layer. The area of the memory cell array 1 can be made equal.

[Memory cell array]
Next, the configuration of the memory cell array 1 of the nonvolatile semiconductor memory device according to the first embodiment will be described.

  In this embodiment, a cell structure that secures coupling between the floating gate and the control gate is not a stack gate structure, but the control gate is embedded on both sides of the floating gate so that the floating gate and the control gate on both sides thereof are connected. A gate structure to be coupled is included.

  FIG. 2 is a diagram showing the structure of the memory cell array 1 according to the present embodiment, and FIG. 3 is a circuit diagram of the memory cell array 1.

The memory cell array 1 includes a NAND string in which _M non-volatile memory cells MC _{0 to} MC _M−1 that can be electrically rewritten are connected in series, and select gate transistors S1 and S2 connected to both ends of the NAND string. A plurality of NAND cell units NU are arranged. One end (selection gate transistor S1 side) of the NAND cell unit NU is connected to the bit line BL, and the other end (selection gate transistor S2 side) is connected to the common source line CELSRC. The gate electrodes of the select gate transistors S1 and S2 are connected to select gate lines SGD and SGS. Control gate electrodes arranged on both sides of the memory cells MC _{0 to} MC _M-1 are connected to word lines WL _{0 to} WL _M , respectively. The bit lines BL are connected to the sense amplifier circuit 2a included in the column control circuit 2, word line _WL 0 to WL _M and the select gate lines SGD, SGS is connected to a row decoder circuit 3a included in the row control circuit 3 ing.

  In the p-type well 51 formed on the substrate, an n-type diffusion layer 52 that functions as a source and drain of a MOSFET constituting the memory cell MC is formed. A floating gate (FG) 54 is formed on the well 51 via a gate insulating film 53 functioning as a tunnel insulating film, and both sides of the floating gate 54 are interposed via an inter-gate insulating layer (IPD) 55. A control gate (CG) 56 is formed. The control gate 56 constitutes a word line WL. Further, the selection gate transistors S 1 and S 2 have a selection gate 57 on the well 51 through a gate insulating layer 53. The selection gate 57 constitutes selection gate lines SGS and SGD. Memory cell MC and select gate transistors S1, S2 are NAND-connected in such a manner that adjacent ones share a drain and a source.

[Memory cell]
In the case of 1 bit / cell in which 1 bit of data is stored in one memory cell MC, 1 page of data is stored in the memory cell MC formed along the word line WL intersecting the NAND cell unit NU. In the case of 2 bits / cell in which 2-bit data is stored in one memory cell MC, two pages (upper page UPPER, lower page LOWER) of data are stored in the memory cell MC formed along the word line WL. Is memorized. Similarly, in the case of 4 bits / cell storing 4 pages of data, the present invention is also applicable to a configuration in which 4 pages of data are stored in the memory cells MC formed along the word line WL. In this embodiment, the 2-bit / cell system is adopted, but a 1-bit / cell system, a 3-bit / cell system, or a 4-bit / cell system may be used.

[Memory block]
One block BLK includes a plurality of NAND cell units NU sharing the word line WL. One block BLK forms one unit of data erasing operation. In one memory cell array 1, the number of word lines WL in one block BLK is M + 1, and the number of pages in one block is 2 bits / cell, which is effective per NAND cell unit in one block. When the number of memory cells (number of memory cells excluding dummy cells) M = 64, M × 2 = 128 pages.

[Memory Cell Array Structure of First Embodiment]
Next, the memory cell array structure according to the first embodiment will be described.
4 is a perspective view of the memory cell array structure according to the first embodiment, FIG. 5 is a cross-sectional view as viewed from the GC (gate) direction of FIG. 4, and FIG. 6 is AA ′, BB ′ of FIG. 5 is a cross-sectional view taken along line AA (active area) in FIG. In order to make the internal structure visible, a part of the structure is omitted.

  In this memory cell array structure, the memory cell array structure shown in FIG. 2 is turned upside down and stacked, and the upper and lower memory cell array layers share a control gate.

  That is, as shown in FIGS. 4 and 5, the first semiconductor layer 11 and the second semiconductor layer 21, which form the body forming the channel, are arranged on the top and bottom of the insulator base 30, and the first semiconductor layer 11 and the second semiconductor layer 21 are interposed therebetween. The first floating gate 13 facing the upper surface of the first semiconductor layer 11 via the gate insulating layer 12 and the second floating electrode facing the lower surface of the second semiconductor layer 21 via the second gate insulating layer 22. The floating gates 23 are stacked one above the other through the first insulating layer 31. These semiconductor layers 11, 21, gate insulating layers 12, 22 and floating gates 13, 23 are layers extending in the AA direction (first direction), as is clear from the AA ′ cross section of FIG. The insulating layers 15 and 25 are insulated from each other in the GC direction (second direction).

  A plurality of stacked structures of floating gates 13 and 23 are formed at predetermined intervals in the AA direction along the semiconductor layers 11 and 21 so as to form a NAND array. Control gates 33 extending in the GC direction are formed on both sides of the stack of floating gates 13 and 23 in the AA direction via an inter-gate insulating layer (IPD: interpoly insulating layer) 32. The control gate 33 is provided in common to the floating gates 13 and 23 so as to be coupled to the upper and lower floating gates 13 and 23 from the side surface. A mask material 33 m is provided between the control gate 33 and the second gate insulating layer 22. The lower first semiconductor layer 11, the first gate insulating layer 12, the first floating gate 13, the inter-gate insulating layer 32, and the control gate 33 are included in the configuration of the lower first memory cell MC1. included. The upper second semiconductor layer 21, the second gate insulating layer 22, the second floating gate 23, the intergate insulating layer 32, and the control gate 33 are included in the configuration of the upper second memory cell MC2. .

  The first selection gate 16 and the second selection gate forming the selection gate transistors S11, S12, S21, and S22 are positioned adjacent to the control gates 33 at both ends in the arrangement direction of the stacked structure of the floating gates 13 and 23. 26 is arranged. The select gates 16 and 26 are stacked one above the other through the first insulating layer 31 and face the semiconductor layers 11 and 21 through the gate insulating layers 12 and 22, respectively. A first selection gate line 17 extending in the GC direction is embedded in the first selection gate 16, and a second selection gate line 27 extending in the GC direction and a mask material 27m are embedded in the second selection gate 26. ing. These select gate lines 17 and 27 are insulated from each other through an interlayer insulating layer 34.

  The lower first NAND cell unit NU1 includes a lower NAND-connected memory cell MC1 and select gate transistors S11 and S21. The first memory cell array layer 10 includes a first element isolation insulating layer 15. Through a plurality of NAND cell units NU1 arranged in the GC direction. The upper second NAND cell unit NU2 includes an upper NAND-connected memory cell MC2 and select gate transistors S12 and S22, and the second memory cell array layer 20 includes a plurality of NANDs arranged in the GC direction. Cell unit NU2 is included.

  In the semiconductor layers 11 and 21 at one end of the NAND cell units NU1 and NU2, a bit line contact 35 extending in common up and down to the bit line BL (not shown) is formed. Further, in the semiconductor layers 11 and 21 at the other ends of the NAND cell units NU1 and NU2, a source line contact 36 is formed which extends vertically in common to these and connects to a source line (not shown). Further, a word line contact 37 is formed at the end of the control gate 33, and a select gate line contact 38 is connected to the ends of the select gate lines 17 and 27.

  The bit line contact 35 includes a lower contact 35a and an upper contact 35b. Similarly, the source line contact 36 includes a lower contact 36a and an upper contact 36b. The lower contacts 35 a and 36 a are connected to the first semiconductor layer 11 through a first groove 81 provided in the first gate insulating layer 12. The lower contacts 35a and 36a in the present embodiment are formed simultaneously with the first floating gate 13 and the first select gate 16 as described later. Accordingly, the widths of the lower contacts 35a, 36a and the first semiconductor layer 11 in the GC direction are substantially the same. The lower contacts 35a and 36a are made of the same material as that of the first floating gate 13, and are formed in the same straight line at the same interval as the first semiconductor layer via the first element isolation insulating layer 15. Has been. The upper contacts 35b and 36b are formed so as to penetrate the second semiconductor layer 21, the second gate insulating layer 22, and the first insulating layer 31 and to be connected to the upper portions of the lower contacts 35a and 36a. . The upper contacts 35a and 36a are also made of the same material as that of the first floating gate 13.

  According to the above configuration, the floating gates 13 and 23 of the memory cells MC1 and MC2 corresponding to the upper and lower sides of the upper and lower NAND cell units NU1 and NU2 are simultaneously driven by the coupling with the word lines WL on both sides, and the common bit Connected to line BL. On the other hand, the selection gate transistors S11 to S22 are provided independently for the upper and lower bit lines BL, and either one is selectively activated to selectively activate the NAND cell units NU1 and NU2. Can be.

  In addition, since the control gates 33 common to both the upper and lower floating gates 13 and 23 are disposed on the both sides, they are hardly affected by the proximity effect in the AA direction and the diagonal direction due to the shielding effect. On the other hand, although affected by the proximity effect in the GC direction, that is, the direction in which the control gate 33 extends, this is reduced by the operation described below.

[Operation method]
Next, an operation method of the nonvolatile semiconductor memory device according to this embodiment is described.

[Write operation of comparative example]
Prior to the description of the write operation according to the present embodiment, the write operation of the comparative example will be described. As shown in FIG. 7, among the memory cells MCn−1, MCn, MCn + 1 connected to the bit lines BLn−1, BLn, BLn + 1 and constituting the same page, the memory cell MCn is the memory cell of interest, and the word line WL The adjacent memory cells MCn−1 and MCn + 1 in the direction are defined as adjacent memory cells MCn−1 and MCn + 1. When writing write data to the target memory cell MCn, the voltage of the control gate 56 constituting the word lines WL _k , WL _{k + 1} on both sides of the floating gate 54 of the memory cell MCn is raised to a predetermined write voltage. At this time, for example, the potential VDD (power supply voltage) is applied to the bit line connected to the non-selected memory cell in the same page to make the non-selected memory cell non-selected, and the bit line connected to the selected memory cell has the potential 0 V, for example. Is applied to set the selected memory cell to a selected state, thereby selectively writing. For the control gates other than the control gate 56, by applying a potential 0V or Vpass which is an intermediate potential between the write voltage and 0V to reduce the voltage, erroneous writing occurs in the memory cells other than the page to be written. To prevent.

  In a configuration like the memory cell array 1 according to the present embodiment, word lines WL are arranged on both side surfaces of the floating gate 54 in the bit line direction, and these word lines WL operate as shield lines. As a result, the proximity effect to the memory cells MC adjacent in the bit line direction during the write operation is suppressed. Therefore, in the memory cell array 1 having the above configuration, it is possible to effectively improve the controllability by reducing the proximity effect to the memory cells MC adjacent in the word line direction.

  The proximity effect to the memory cells MC adjacent in the word line direction will be described with reference to FIG. FIG. 8 is a histogram for explaining the influence of the proximity effect on the threshold distribution when performing two-step writing of coarse (Foggy) writing and fine (Fine) writing. Hereinafter, the threshold value corresponding to the write data for the memory cell MC will be described as data E, A, B, and C in order from the lowest.

  FIG. 8A shows the threshold distribution of the plurality of memory cells MC when the erase operation is performed prior to the write operation. FIG. 8 (2) shows the threshold distribution when the first writing (coarse writing) is performed after the erasing operation, and FIG. 8 (3) shows the second writing (precise writing) after the first writing. Each of the threshold distributions is shown. As shown in the drawing, when the write data for the selected memory cell MCn is greater than or equal to the write data for the adjacent memory cells MCn−1 and MCn + 1, the proximity effect from the adjacent memory cells MCn−1 and MCn + 1 to the selected memory cell MCn almost occurs. Absent. However, when the write data for the selected memory cell MCn is smaller than the write data for the adjacent memory cells MCn−1 and MCn + 1, a proximity effect corresponding to the difference of the write data occurs, and the threshold distribution is widened. The proximity effect becomes more prominent as the write data to the selected memory cell MCn is lower and the write data to the adjacent memory cells MCn−1 and MCn + 1 is higher.

[Write Operation of Nonvolatile Semiconductor Memory Device According to First Embodiment]
In order to solve the above-described problem of threshold variation due to the proximity effect, in the present embodiment, the write condition of the selected memory cell MC that receives many proximity effects from the adjacent memory cells MCn−1 and MCn + 1, more specifically, the write verify. Set the level lower than normal. FIG. 9 is a histogram for explaining the write operation according to the present embodiment. FIG. 9A shows the threshold distribution of the plurality of memory cells MC when the erase operation is performed prior to the write operation.

  FIG. 9B shows a write verify level set in the first write (coarse write) after the erase operation and the threshold distribution of the selected memory cell MCn obtained as a result. In the write operation according to the present embodiment, the write verify level of the selected memory cell MCn is set based on the write data for the selected memory cell MCn and the write data for the adjacent memory cells MCn−1 and MCn + 1. That is, the higher the write level of the adjacent memory cells MCn−1, MCn + 1, the smaller the write verify level of the selected memory cell MCn. For example, when data A is written to the selected memory cell MCn, data C is written to the adjacent memory cells MCn−1 and MCm + 1 than the write verify level VA1 when data E is written to the adjacent memory cell MCn + 1. The write verify level VAC1 is set smaller.

  FIG. 9 (3) shows the write verify level set in the second write after the first write, which is more precise than the first write, and the threshold distribution of the selected memory cell MCn obtained thereby. Yes. Also in the second writing, the threshold voltage for the selected memory cell MCn is adjusted by the same method as in the first writing.

  According to such adjustment of the write verify level, even if the threshold level varies due to the proximity effect from the adjacent memory cells MCn−1 and MCn + 1, the threshold distribution varies in the direction of convergence. It is possible to prevent the value distribution from spreading.

  In the present embodiment, attention is paid only to the influence of the adjacent memory cells MCn−1 and MCn + 1. However, as the memory cell array 1 is miniaturized, the memory cell MCn− further adjacent to the adjacent memory cells MCn−1 and MCn + 1. It may be necessary to consider the effects of 2 and MCn + 2. The above adjustment of the write condition is naturally applicable to such a case.

  Next, the write operation will be described with a more specific example. FIG. 10 is a flowchart showing an example of the write operation according to the present embodiment.

  In the write operation according to the present embodiment, first, an erase operation is collectively performed on a plurality of memory cells MC included in a predetermined erase unit (step S1), and then, with respect to a verify voltage for a selected memory cell MCn, Weighting is performed according to the write data for the adjacent memory cells MCn−1 and MCn + 1 (step S2).

  The threshold voltage is weighted by processing the write data for one page held in the data input / output buffer 4 in the comparator 11 and outputting it as weight data to the state machine 7. In the present embodiment, the arithmetic processing performed by the comparator 11 is a combination of simple addition processing and the like. That is, for each memory cell MCn, the write verify level of the selected memory cell MCn is determined based on the write data for the adjacent memory cells MCn−1 and MCn + 1.

  The state machine 7 obtains weight data for one page in step S2 in accordance with the write data for one page held in the data input / output buffer 4, and sets the write verify level using this. In this embodiment, since the 2-bit / cell system (four values) is adopted, there are 4 × 4 = 16 combinations of adjacent memory cells MCn−1 and MCn + 1. Accordingly, although it is conceivable to set the weights to 16 levels, in this embodiment, as shown in FIG. 11, 7 levels of weighting are performed according to the write data for the adjacent memory cells MCn−1 and MCn + 1.

  The influence of the proximity effect on the selected memory cell MCn due to the write operation to the adjacent memory cells MCn−1 and MCn + 1 becomes more significant as the write data to the selected memory cell MCn is smaller. Therefore, even with the same weighting, different weighting is possible depending on the write data for the selected memory cell MCn. That is, when the write data for the selected memory cell MCn is low (for example, data E), the weight is strongly reflected, and when the write data is high (for example, data C), it is compared with the case where the write data is low. It is possible to reflect it weakly.

Next, first writing is performed (steps S3 to S5). In the first write, a write pulse is applied to the selected word lines WL _k and WL _{k + 1} (step S3), and verification is performed using the weighted write data in step S2 (step S4), and the verification is completed. If not, the voltage of the write pulse is raised and the application and verification of the write pulse are repeated again (step S5).

  In this embodiment, there are four types of write data (data E, A, B, and C), and seven weights are provided for each. Therefore, seven pulse voltages are applied in one verification at each level. The read operation is performed for each. Therefore, although the accuracy of the write operation is improved as the number of weights is increased, the time required for verification is increased accordingly. Therefore, it is conceivable to adjust the number of weights in consideration of this point. The verification for the write data E can be omitted.

  Next, second writing is performed (steps S6 to S8). The second writing is performed in substantially the same manner as the first writing. However, since the verify voltage differs between the first writing and the second writing (see FIG. 4), it is necessary to change the verify voltage.

According to the write operation as described above, it is possible to reduce the adjacent effect generated during the write operation and to provide a highly controllable nonvolatile semiconductor memory device. In addition, since the write operation according to the present embodiment reduces the proximity effect by processing the write data in the same page, there is no need for a cache or the like for reading the next page data. Since it can be configured by a relatively simple logic circuit, the circuit configuration does not increase substantially. Furthermore, it is not necessary to read / write the next page data into the cache.
[Second Embodiment]
Next, a nonvolatile semiconductor memory device according to a second embodiment will be described. The nonvolatile semiconductor memory device according to this embodiment is basically the same as the nonvolatile semiconductor memory device according to the first embodiment. However, in the nonvolatile semiconductor memory device according to this embodiment, the second Verification using weighting is performed only during writing. In the write operation according to the present embodiment, it is possible to shorten the verify time in the first write while maintaining the accuracy of the second write, and to increase the operation speed.

It is also possible to perform verification using weighting only during the first writing.
[Other Embodiments]
As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Column control circuit, 3 ... Row control circuit, 4 ... Data input / output buffer, 5 ... Address register, 6 ... Command I / F, 7 ... State machine, 10 ... Voltage generation circuit, 11 ... Comparator .

Claims (5)

A plurality of memory cells connected in series in a first direction, a source line side select gate transistor connected between the plurality of memory cells and a source line, and connected between the plurality of memory cells and a bit line. A plurality of NAND cell units each including a bit line side select gate transistor are arranged in a second direction orthogonal to the first direction, and the memory cell is formed on the semiconductor layer and the semiconductor layer. A gate insulating layer; a floating gate formed on the gate insulating layer; and a control gate extending in the second direction opposite to both ends of the floating gate in the first direction via an inter-gate insulating layer A memory cell array having:
A plurality of the memory cells arranged in the second direction as a page, and a control circuit for writing data to the memory cell in page units,
The control circuit further includes a comparator that detects write data of a plurality of the selected memory cells constituting a page to which the data is written,
In the write operation to the plurality of memory cells in page units, the first stage write, the first verify after the first stage write, the second write after the first verify, and the second write Later we ’ll do a second verify,
In the write operation to the plurality of memory cells in the page unit, the second verify is performed according to the write data to the selected memory cell and the write data to the memory cell adjacent to the selected memory cell in the second direction. Adjusting the write verify level of the selected memory cell;
The write verify level of the selected memory cell in the second verify is decreased as the threshold level of the write data to the memory cell adjacent to the selected memory cell in the second direction increases.
The nonvolatile semiconductor memory device, wherein the write verify level in the second verify is adjusted according to the output of the comparator. A plurality of memory cells connected in series in a first direction, a source line side select gate transistor connected between the plurality of memory cells and a source line, and connected between the plurality of memory cells and a bit line. A plurality of NAND cell units each including a bit line side select gate transistor are arranged in a second direction orthogonal to the first direction, and the memory cell is formed on the semiconductor layer and the semiconductor layer. A memory cell array having a gate insulating layer, a floating gate formed on the gate insulating layer, and a control gate facing the floating gate via an inter-gate insulating layer and extending in the second direction;
A plurality of the memory cells arranged in the second direction as a page, and a control circuit for writing data to the memory cell in page units,
The control circuit includes:
In the write operation to the plurality of memory cells in page units, the selected memory cell is written according to the write data to the selected memory cell and the write data to the memory cell adjacent to the selected memory cell in the second direction. A nonvolatile semiconductor memory device characterized by adjusting a verify level.   3. The nonvolatile semiconductor memory device according to claim 2, wherein the control gate is disposed on both sides of the floating gate in the first direction with the intergate insulating layer interposed therebetween. The control circuit includes:
4. The write verify level of the selected memory cell is decreased as the threshold level of the write data to the memory cell adjacent to the selected memory cell in the second direction is larger. Nonvolatile semiconductor memory device. The control circuit further includes a comparator that detects write data of a plurality of the selected memory cells constituting a page to which the data is written,
The nonvolatile semiconductor memory device according to claim 2, wherein the write verify level is adjusted according to an output of the comparator.

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