JP2013197358A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can use a terminal as both a terminal subject to high voltage application and a terminal used to input a signal varying in a lower voltage range than that, without increasing the size of a circuit added.SOLUTION: An external input terminal 1 is designed as a common input terminal for a low voltage circuit section 2 and a high voltage circuit section 3. Between the external input terminal 1 and the signal input terminal of the low voltage circuit section 2 is connected an N-channel MOSFET 4, to the gate of which a potential equal to or higher than a maximum value 3 V for the input voltage of the low voltage circuit section 2 and lower than a maximum permissible input voltage VLset for the low voltage circuit section 2 plus a threshold voltage Vth of the N-channel MOSFET 4 is applied to keep the N-channel MOSFET 4 turned on. In this way, when a nonvolatile memory rewrite voltage of 9 V is applied to the external input terminal 1, the source potential of the N-channel MOSFET 4 is made to be equal to or less than the maximum permissible input voltage VLset for the low voltage circuit section 2.

Description

  The present invention relates to a semiconductor integrated circuit including a low voltage circuit section and a high voltage circuit section.

  Some semiconductor integrated circuits (ICs) have a built-in rewritable nonvolatile memory such as an EPROM, an EEPROM, or a flash memory for holding adjustment data of a program memory, a data memory, or an analog circuit, for example. In such an IC, when data is written in the nonvolatile memory, it is necessary to apply a voltage higher than a high level of a general input signal to the input terminal, and therefore a terminal for that purpose is provided separately. However, when the number of input / output terminals of the IC is increased, the chip size or package size that is constantly required is reduced, and there is a situation that the number of terminals used for special purposes is to be reduced as much as possible.

  For example, in Patent Document 1, a terminal for applying a high voltage at the time of writing to a nonvolatile memory and a mode switching terminal for switching between an actual operation mode and a test mode of a microcomputer are shared and input to a mode switching circuit. A configuration in which a level shift circuit formed by connecting two inverter circuits (inversion gates) in series is inserted in the path is disclosed.

Japanese Patent Laid-Open No. 9-44467

However, the configuration of Patent Document 1 still has a problem from the viewpoint of miniaturization because the configuration of the level shift circuit is relatively large. In addition, there is a problem that terminals that can be used also as terminals for high voltage are limited to digital input terminals.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a terminal to which a high voltage is applied and a digital or analog signal changing in a lower voltage range without increasing the size of a circuit to be added. An object of the present invention is to provide a semiconductor integrated circuit that can also serve as a terminal for inputting.

According to the semiconductor integrated circuit of the first aspect, the external input terminal is used as a common input terminal for the low voltage circuit unit and the high voltage circuit unit. Then, an N-channel MOSFET is connected between the external input terminal and the input terminal of the low voltage circuit section, and the gate is connected to the low voltage circuit section which is equal to or higher than the maximum input voltage VL of the low voltage circuit section. A potential lower than the potential obtained by adding the threshold voltage Vth of the N-channel MOSFET to the maximum allowable input voltage VL _MAX set for the unit is applied. Accordingly, when a voltage exceeding the voltage VL is applied to the external input terminal, the potential of the input terminal of the low voltage circuit unit is set to be equal to or lower than the maximum allowable input voltage VL _MAX set for the low voltage circuit unit. .

With this configuration, even when the voltage VH is applied to the external input terminal, the source potential of the N-channel MOSFET becomes lower than the gate potential of the N-channel MOSFET. The allowable input voltage VL _MAX or less can be set. Therefore, even if the external input terminal is shared with the input terminal of the high voltage circuit unit, it is possible to prevent an excessive voltage from being applied to the input terminal of the low voltage circuit unit with a very simple configuration. In addition, the input terminal of the low voltage circuit unit can be used as the input terminal of the high voltage circuit unit regardless of whether an analog signal or a digital signal is input.

The figure which is 1st Example and shows the structure of the input part of a semiconductor integrated circuit Functional block diagram showing the overall configuration when the configuration shown in FIG. 1 is applied to a microcomputer FIG. 1 equivalent view showing the second embodiment FIG. 1 equivalent view showing the third embodiment FIG. 1 equivalent view showing the fourth embodiment FIG. 2 equivalent view showing the fifth embodiment

(First embodiment)
In FIG. 1, an external input terminal 1 of a semiconductor integrated circuit applies a voltage to a terminal for inputting a signal to an internal low voltage circuit unit 2 and a high voltage circuit unit 3 from the outside of the semiconductor integrated circuit. Also serves as a terminal. The low-voltage circuit unit 2 is a 3V circuit in which the voltage range of the input signal is set to 0 V to 3 V (maximum value VL), for example. The high voltage circuit unit 3 is a rewritable nonvolatile memory such as a flash memory, for example, and applies a write voltage of, for example, 9 V (maximum value VH) when data is rewritten via a bus (not shown). There is a need.

  The external input terminal 1 is directly connected to the above-described write voltage application terminal of the high voltage circuit unit 3, and the signal input terminal of the low voltage circuit unit 2 is connected to the drain and source of the N-channel MOSFET 4. Connected. For example, a gate voltage of 5 V is supplied to the gate of the N-channel MOSFET 4. The threshold voltage Vth of the N-channel MOSFET 4 is set to about 1V, for example. The signal input to the low voltage circuit unit 2 via the external input terminal 1 is an analog signal whose voltage changes in the range of 0V to 3V, for example.

  Next, the operation of this embodiment will be described. The gate potential of the N-channel MOSFET 4 is 5 V, and is set to a voltage higher than the voltage obtained by adding the threshold voltage Vth of the N-channel MOSFET 4 to the maximum value 3 V (VL) of the input signal voltage of the low-voltage circuit unit 2. . Therefore, the N-channel MOSFET 4 is always on when the semiconductor integrated circuit is activated. When the signal voltage applied to the external input terminal 1 changes in the range of 0V to 3V, the voltage at the source of the N-channel MOSFET 4, that is, the signal input terminal of the low voltage circuit unit 2 is also in the range of 0V to 3V. It changes in analog. Note that even if a voltage in the above range is applied to the external input terminal 1, it does not affect the high voltage circuit section 3 side.

When the write voltage 9V of the high voltage circuit unit 3 is applied to the external input terminal 1, the source potential of the N-channel MOSFET 4 is about 4V, which is lower than the gate potential of 5V by the threshold voltage Vth. A voltage exceeding the maximum value VL is applied to the signal input terminal of the low voltage circuit unit 2, and this voltage is equal to or lower than the maximum allowable voltage VL _MAX of the low voltage circuit unit 2. (That is, the gate potential of 5 V is lower than the potential obtained by adding the threshold voltage Vth to the maximum allowable voltage VL _MAX ). However, the low-voltage circuit unit 2 ignores the signal input during this period without setting it as a processing target.

  In FIG. 2, a microcomputer 11 (semiconductor integrated circuit) includes an analog circuit section 2A corresponding to the low voltage circuit section 2, a flash memory 3M corresponding to the high voltage circuit section 3, and a digital circuit section 12 such as a CPU. And. The analog circuit unit 2A, the flash memory 3M, and the digital circuit unit 12 are connected to each other via a bus. These may be a common bus. The analog circuit unit 2A includes an A / D converter.

  With this configuration, even when a voltage of 9 V is applied to the external input terminal 1 in order to erase or rewrite the flash memory 3M, the voltage of the signal input terminal of the analog circuit portion 2A can be reduced to a maximum allowable voltage or less. For the input terminal of the analog circuit portion 2A, if the analog signal level applied to the external input terminal 1 changes in the range of 0V to 3V, the signal of 0V to 3V is the same as in the case where the N-channel MOSFET 4 is not provided. Can communicate changes. Needless to say, with respect to the N-channel MOSFET 4, an element having a withstand voltage that covers the potential difference between the gate and the source when 9V is applied to the drain is used.

As described above, according to this embodiment, the external input terminal 1 is used as a common input terminal for the low voltage circuit unit 2 and the high voltage circuit unit 3. Then, an N-channel MOSFET 4 is connected between the external input terminal 1 and the signal input terminal of the low voltage circuit unit 2, and the gate has a maximum input voltage value of 3 V or more of the low voltage circuit unit 2, and A potential lower than the potential obtained by adding the threshold voltage Vth of the N-channel MOSFET 4 to the maximum allowable input voltage VL _MAX set for the low-voltage circuit unit 2 is applied to maintain the N-channel MOSFET 4 in the ON state. As a result, when 9 V, which is a rewrite voltage of the nonvolatile memory, is applied to the external input terminal 1, the source potential of the N-channel MOSFET 4 is set to be equal to or lower than the maximum allowable input voltage VL _MAX set for the low voltage circuit unit 2. To do.

  Therefore, even if the external input terminal 1 is shared with the input terminal of the high voltage circuit unit 3, it is possible to prevent an excessive voltage from being applied to the signal input terminal of the low voltage circuit unit 2 with a very simple configuration. . Specifically, since the gate potential of the N-channel MOSFET 4 is set to 5 V, which is higher than the voltage obtained by adding 1 V, which is the threshold voltage Vth, to the maximum value 3 V of the input voltage of the low voltage circuit unit 2, the external input terminal 1 Can be changed in conjunction with the above change, when the signal level at 1 changes in an analog manner within the range of 0V to 3V.

(Second embodiment)
Only the parts different from the first embodiment will be described below. In the second embodiment, the source of the N-channel MOSFET 4 is pulled up to the 3V power source via the resistance element 5. This pull-up is arranged for the purpose of protecting the input of the low voltage circuit section 2. For this reason, when 9 V is applied to the external input terminal 1, current tends to flow backward from the source of the N-channel MOSFET 4 to the pull-up power supply side. However, if the resistance value of the resistance element 5 is set to about several tens kΩ, for example. The current value can be suppressed to a negligible level.
According to the second embodiment configured as described above, the same effect as that of the first embodiment can be obtained with respect to the configuration of pulling up the input terminal of the low-voltage circuit section 2.

(Third embodiment)
Unlike the low-voltage circuit unit 2, the low-voltage circuit unit 6 of the third embodiment handles binary signals of low level (0V) and high level (3V), that is, digital signals. In this case, the gate potential of the N-channel MOSFET 4 is set to 3 V, which is the same as the high level. When the external input terminal 1 becomes low level, the N-channel MOSFET 4 is turned on by the potential difference between the drain and gate, so that the source potential becomes 0V.

  When the external input terminal 1 becomes high level, the N-channel MOSFET 4 is turned off, but the source potential becomes 3V by pull-up. Therefore, the signal input terminal of the low-voltage circuit unit 6 changes according to the binary level change of the external input terminal 1. Also, when 9V is applied to the external input terminal 1, the N-channel MOSFET 4 is turned off, so that the source potential is 3V.

  As described above, according to the third embodiment, since the gate potential of the N-channel MOSFET 4 is set to the same voltage as the high level 3V of the binary signal input to the low voltage circuit unit 6, the low voltage circuit unit 6 can handle the case of handling digital signals.

(Fourth embodiment)
In the fourth embodiment, a Zener diode 7 is added to the configuration of the second embodiment. The Zener diode 7 has a cathode connected to the external input terminal 1 and an anode connected to the ground. The Zener diode 7 is arranged for ESD (Electro-Static Discharge) countermeasures, and the Zener voltage is set to a voltage higher than VH = 9V. In the case of the fourth embodiment configured as described above, the same effect as that of the second embodiment can be obtained.

(5th Example)
Although the fifth embodiment shows a case where the present invention is applied to the microcomputer 21 as in the first embodiment, the external input terminal 1 is a reset terminal RESN (low active) of the microcomputer 21. In this case, the source of the N-channel MOSFET 4 is connected to the reset signal input terminal of the digital circuit 12 (low voltage circuit unit) via the Schmitt trigger buffer 22 (low voltage circuit unit). Further, the microcomputer 21 includes a peripheral circuit unit 23 including an analog circuit and the like.

  Here, since the reset signal applied to the external input terminal 1 is a digital signal that changes at the high and low binary levels as in the third embodiment, the gate potential of the N-channel MOSFET 4 is 3 V as in the third embodiment. It may be set to. However, the reason why the voltage is set to 5 V, as in the first embodiment, is to prevent the signal input response to the digital circuit unit 12 from being delayed through the Schmitt trigger buffer 22 from being delayed. The reset signal is always inactive while the microcomputer 21 is in operation; since it is at a high level, even if 9 V is applied to the external input terminal 1 in order to rewrite the flash memory 3M or the like, there is no influence. Absent.

  As described above, according to the fifth embodiment, the external input terminal 1 is used as a terminal for supplying a reset signal to the digital circuit unit 12 of the microcomputer 21 and a terminal for applying the rewriting voltage 9 V of the flash memory 3M. Can also be used.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The specific numerical value of each voltage may be appropriately changed according to the individual design without departing from the scope of the invention. For example, the gate potential of the N-channel MOSFET 4 may be set in a range that is lower than the potential obtained by adding the threshold voltage Vth to the maximum allowable input voltage VL _MAX .
The high-voltage circuit unit is not limited to a rewritable nonvolatile memory.
Further, the semiconductor integrated circuit is not limited to that constituting a microcomputer.

  In the drawings, 1 is an external input terminal, 2 is a low voltage circuit section, 3 is a high voltage circuit section, 4 is an N-channel MOSFET, 5 is a resistance element, and 11 is a microcomputer (semiconductor integrated circuit).

Claims (5)

A low voltage circuit portion (2, 2A, 6, 12, 22) in which the maximum value of the input voltage is set to VL;
A high voltage circuit section (3, 3M) in which the maximum value of the input voltage is set to VH (>VL);
The source is connected to the input terminal of the low voltage circuit section (2, 2A, 6, 12, 22), the drain is connected to the external input terminal (1), and the high voltage circuit section (3, 3M) N-channel MOSFET (4) connected to the input terminal of
At the gate of the N-channel MOSFET (4), an N-channel MOSFET is applied to the maximum allowable input voltage VL _MAX that is equal to or higher than the voltage VL and set for the low-voltage circuit section (2, 2A, 6, 12, 22). When a voltage exceeding the voltage VL is applied to the external input terminal (1) by applying a potential lower than the potential obtained by adding the threshold voltage Vth of the low voltage circuit portion (2, 2A, 6, 12, 22) input terminal potential is made to be equal to or lower than the maximum allowable input voltage VL _MAX set for the low voltage circuit section (2, 2 A, 6, 12, 22). Integrated circuit.   2. The semiconductor integrated circuit according to claim 1, wherein the gate potential of the N-channel MOSFET is set to (VL + Vth) or more.   3. The semiconductor integrated circuit according to claim 1, wherein the source of the N-channel MOSFET (4) is pulled up to the voltage VL via a resistance element (5).   4. The semiconductor integrated circuit according to claim 3, wherein the input terminal of the low voltage circuit section (12) is a reset signal terminal. The high-voltage circuit section is (3), a rewritable nonvolatile memory (3M),
5. The semiconductor integrated circuit according to claim 1, wherein a rewriting voltage of the nonvolatile memory (3M) is applied to an input terminal of the high voltage circuit section (3).

Images