JP2013120947A - Class d amplifier - Google Patents

Abstract

An object of the present invention is to reduce current flowing in a body diode of a transistor of an output circuit even when the temperature is increased, to reduce an increase in current consumption, and to reduce output voltage distortion and unnecessary radiation.
A high-side output circuit 50A, a low-side output circuit 50B, a high-side drive circuit 30A that drives the high-side output circuit 50A when a signal at the input terminal IN becomes H level, and a signal at the input terminal IN that is at L level. Then, the low-side drive circuit 30B for driving the low-side output circuit 50B and the high-side output circuit 50A are weakly inverted and driven from a timing earlier by a period corresponding to the temperature immediately before the high-side output circuit 50A is driven by the high-side drive circuit 30A. A high-side weak inversion driving circuit 40A, and a low-side weak inversion driving circuit 40B that weakly inverts the low-side output circuit 50B from a timing that is earlier by a period corresponding to the temperature immediately before the low-side output circuit 50B is driven by the low-side driving circuit 30B. Is provided.
[Selection] Figure 1

Description

  The present invention relates to a class D amplifier in which the reverse recovery time of a body diode of a transistor of an output circuit is shortened.

  The class D amplifier amplifies power by amplifying the PWM signal obtained by modulating the input analog signal to a large amplitude PWM signal that reaches the power supply voltage, and smoothes the large amplitude PWM signal by, for example, an LC type low-pass filter. It is output as an analog signal. In the class D amplifier, since the transistor of the output circuit that is a power amplification stage is a drain output type, loss in the transistor is small, and high efficiency and high output are possible.

  FIG. 5 shows a conventional class D amplifier (for example, see Non-Patent Document 1). In this class D amplifier, the PWM signal input to the input terminal IN passes through the inverters INV21 and INV22, and from the NMOS transistor MN21 via the NAND circuit NAND21 and the high-side dead time generation circuit 60A including the inverters INV23 to INV26. To the high-side output circuit 70A. Further, the signal is input to the low side output circuit 70B including the NMOS transistor MN22 via the inverter INV21 and the low side dead time generating circuit 60B including the NAND circuit NAND22 and the inverters INV27 to INV30.

  The dead time generation circuit 60A also inputs a drive signal for the output circuit 70B so that the output circuits 70A and 70B do not conduct simultaneously when the input signal changes, and the dead time generation circuit 60B also outputs the output circuit 70A. The drive signal is also input.

  In this class D amplifier, an inductive load L is often attached to the output terminal OUT. The inductance load L behaves so that the same current flows when the voltage at the output terminal OUT changes. During the dead time period, the current flowing through the load L is charged or discharged to the parasitic capacitance C of the output terminal OUT, and eventually deviates from the range between the high potential power supply voltage VH and the low potential power supply voltage VL. As a result, the body diodes D21 and D22 of the transistors MN21 and MN22 in the output circuits 70A and 70B become conductive.

  For example, when the output circuit 70A is cut off from conduction, the body diode D21 is turned on. In this state, the dead time period is ended, and when the output circuit 70B is turned off from conduction, the body diode D21 and the output circuit 70B are passed through. When a large current flows and the reverse recovery time of the body diode D21 passes, the body diode D21 is cut off and no current flows there. The current flowing during this time is larger than the load current, which may cause destruction of the output circuits 70A and 70B.

  The conventional class D amplifier of FIG. 6 has an output circuit 70A ′ in which the high side output circuit 70A of the class D amplifier of FIG. 5 is replaced by an NMOS transistor MN21 with a PMOS transistor MP21, and a dead time generation circuit 60A is input. This is a dead time generation circuit 60A ′ in which the NAND circuit NAND21 on the side is replaced with a NOR circuit NOR21. Here, by replacing the transistor of the output circuit 70A ′ with the PMOS transistor MP21, the output dynamic range can be increased and higher output power can be output, but the problem described in FIG. 5 remains as it is. ing.

  The conventional class D amplifier of FIG. 7 includes, in the class D amplifier of FIG. 5, diodes D23 and D24 having lower threshold voltages and shorter reverse recovery times than the body diodes D21 and D22 of the output circuits 70A and 70B, respectively. 70A and 70B are connected in parallel, the period during which current flows through the body diodes D21 and D22 is shortened as much as possible, element destruction is prevented, and more load current can be supplied (for example, non-patent) Reference 2).

  However, as in the case of the class D amplifier in FIG. 7, a problem in increasing the output is unnecessary radiation when switching the switching elements of the output circuit. That is, when a switching element is switched, if a current flows to a parasitic diode inside the switching element, a reverse recovery time is required until the body diode is cut off. During this time, a rush current flows and unnecessary radiation is generated. Therefore, to improve this, at the time of switching, the output circuit that is next conducted is made slightly conductive early, that is, the output circuit is driven by weak inversion to provide a period for removing the charge in the body diode. There is a proposal to reduce rush current and reduce noise of voltage and current during switching (see, for example, Patent Document 1).

  Also, in Patent Document 2, when the output current increases, it takes time to remove the charge accumulated in the body diode. There is a proposal to reduce the charge and current noise at the time of switching by shortening the reverse recovery time of the body diode.

US Pat. No. 7,782,135 US Pat. No. 5,828,232

NEIL H.E.WESTE, KAMRAN ESHRAGHIAN "PRINCIPLE OF CMOS VLSI" A Systems Prespective SECONDE EDITION, P.349 1993. M61571BPF data sheet, 16-19 pages, 2005, Renesas Technology Corporation

  With the increase in the output of the class D amplifier, as shown in FIG. 5 and FIG. 7 as a solution to the problem of the class D amplifier of FIG. 5 and FIG. Class amplifiers have been proposed. As a solution to the problem associated with the high output of the circuit of FIG. 7, a technique for performing weak inversion driving as disclosed in Patent Documents 1 and 2 has been proposed.

  However, if the body diode of the transistor of the output circuit rises in temperature, its threshold voltage decreases, the internal resistance increases, it becomes difficult for the charge to escape, and the reverse recovery time becomes longer, so it is necessary to lengthen the weak inversion drive time However, these are not considered at all in Patent Documents 1 and 2.

  An object of the present invention is to provide a class D amplifier in which the current flowing through the body diode of the transistor of the output circuit is reduced and the reverse recovery time is shortened even when the temperature becomes high.

To achieve the above object, a class D amplifier according to a first aspect of the present invention includes a high-side output circuit connected between an output terminal and a high-potential power supply terminal, and the output terminal and the low-potential power supply terminal. A low-side output circuit connected in between, a high-side drive circuit that drives the high-side output circuit in response to a signal at the input terminal becoming a first logic, and a signal at the input terminal being the first logic The low-side drive circuit that drives the low-side output circuit in accordance with the second logic obtained by inverting the signal, and the temperature detection means than the timing at which the high-side output circuit starts to be driven by the high-side drive circuit. A high-side weak inversion driving circuit that weakly inverts the high-side output circuit and a low-side output circuit are connected to the low-side output circuit from a timing that is earlier than a period corresponding to the detected temperature. A low-side weak inversion driving circuit that weakly inverts and drives the low-side output circuit from a timing earlier than a timing at which driving is started by the side driving circuit by a period corresponding to the temperature detected by the temperature detecting unit. It is characterized by.
According to a second aspect of the present invention, in the class D amplifier according to the first aspect, the temperature detecting means is a delay circuit that delays the signal at the input terminal by a first time proportional to the temperature, The side output circuit is weakly inverted by the high-side weak inversion driving circuit when the signal at the input terminal becomes the first logic, and then driven by the high-side driving circuit after the first time has elapsed, The low-side output circuit is weakly inverted by the low-side weak inversion driving circuit when the signal at the input terminal becomes the second logic, and then driven by the low-side driving circuit after the first time has elapsed. It is characterized by that.
According to a third aspect of the present invention, in the class D amplifier according to the first or second aspect, the high side output circuit is completely driven by the high side drive circuit after the high side output circuit starts weak inversion drive by the high side weak inversion drive circuit. The period of the first time until driving is started, and the time from when the low-side output circuit starts weak inversion driving by the low-side weak inversion driving circuit until full driving is started by the low-side driving circuit. During the first time period, the driving of the high-side output circuit and the low-side output circuit is stopped.
According to a fourth aspect of the present invention, in the class D amplifier according to any one of the first to third aspects, the high-side weak inversion driving circuit has a first current source and a signal at the input terminal is the first. High-side switch means for applying a bias voltage corresponding to the current of the first current source to the high-side output circuit at the time of the logic, the low-side weak inversion driving circuit includes a second current source, And low-side switch means for applying a bias voltage corresponding to the current of the second current source to the low-side output circuit when the signal at the input terminal is of the second logic.
According to a fifth aspect of the present invention, in the class D amplifier according to the fourth aspect, the current of the first and second current sources is a current corresponding to a low-pass signal of a signal input to the input terminal. It is characterized by that.
According to a sixth aspect of the present invention, in the class D amplifier according to any one of the first to fifth aspects, the high-side weak inversion driving circuit and the low-side weak inversion driving circuit have a common enable signal disabled. The weak inversion driving is stopped.
According to a seventh aspect of the present invention, in the class D amplifier according to any one of the first to fifth aspects, the high-side weak inversion driving circuit and the low-side weak inversion driving circuit have the common enable signal valid. In this case, if the individual enable signals for the high side and the low side are invalidated, the high side weak inversion driving circuit or the low side weak inversion driving circuit corresponding to the invalid individual enable signal is stopped. It is characterized by that.

  According to the present invention, the higher the temperature, the longer the time during which the transistor of the output circuit is driven to be weakly inverted, so that when the output signal is inverted, the regenerative current that flows from the inductive load to the body diode of the transistor of the opposite output circuit Can be shunted to the output circuit driven by weak inversion, and the reverse recovery time of the body diode of the transistor of the opposite output circuit can be shortened. Therefore, in addition to eliminating the need for an external diode, it is possible to achieve good power conversion efficiency, suppress sudden fluctuations in the power supply voltage and reduce output voltage distortion and unwanted radiation. Low harmonic distortion can be realized.

1 is a circuit diagram of a class D amplifier according to a first embodiment of the present invention. It is an operation | movement waveform diagram of the class D amplifier of 1st Example. FIG. 3 is a circuit diagram of a class D amplifier according to a second embodiment of the present invention. It is a circuit diagram of the class D amplifier of the 3rd example of the present invention. It is a circuit diagram of the conventional class D amplifier. It is a circuit diagram of the conventional class D amplifier. It is a circuit diagram of the conventional class D amplifier.

<First embodiment>
FIG. 1 shows a class D amplifier according to a first embodiment of the present invention. An inverter INV1 is connected to the input terminal IN, and an inverter INV2 and INV3 are connected to an output node N1 of the inverter INV1, and a delay circuit DL1 that has a longer delay time T1 as the temperature is higher is connected.

  Reference numeral 10A denotes a high side bias voltage generation circuit connected to the node N1, and is composed of inverters INV4 to INV6. Reference numeral 20A denotes a high-side dead time generation circuit, which includes a NOR circuit NOR1 and inverters INV7 and INV8. Reference numeral 30A denotes a high-side drive circuit, which includes a cascade connection circuit of a PMOS transistor MP1 and NMOS transistors MN1 and MN2, and is connected to an output node N3 of the bias voltage generation circuit 10A and an output node N4 of the dead time generation circuit 20A. Reference numeral 40A denotes a high-side weak inversion drive circuit, which includes PMOS transistors MP2 to MP4, an NMOS transistor MN3, and a current source I1. The voltage of the output node N3 of the bias voltage generation circuit 10A is set to the output node N5 of the drive circuit 30A. The voltage is controlled. The transistor MN3 constitutes the high side switch means described in the claims. Reference numeral 50A denotes a high side output circuit comprising a PMOS transistor MP8 whose conduction / cutoff is controlled by the voltage of the node N5. D1 is a body diode of the transistor MP8.

  Reference numeral 10B denotes a low-side bias voltage generation circuit connected to the node N1, and includes inverters INV11 to INV13. Reference numeral 20B denotes a low-side dead time generation circuit, which includes a NAND circuit NAND1 and inverters INV9 and INV10. Reference numeral 30B denotes a low-side drive circuit, which includes a cascade connection circuit of PMOS transistors MP5 and MP6 and an NMOS transistor MN4, and is connected to an output node N6 of the bias voltage generation circuit 10B and an output node N7 of the dead time generation circuit 20B. Reference numeral 40B denotes a low-side weak inversion driving circuit, which includes a PMOS transistor MP7, NMOS transistors MN5 to MN7, and a current source I2. The voltage of the output node N8 of the driving circuit 30B is determined by the voltage of the output node N6 of the bias voltage generating circuit 10B. Is to control. The transistor MP7 constitutes the low-side switch means described in the claims. Reference numeral 50B denotes a low-side output circuit composed of an NMOS transistor MN8 whose conduction / cutoff is controlled by the voltage of the node N8. D2 is a body diode of the transistor MN8.

  The dead time generation circuit 20A receives the voltage at the output node N2 of the delay circuit DL1 and the voltage at the output node N8 of the drive circuit 30B. When both voltages are at the L level, the node N4 is set to the H level. The output circuit 50A is driven via 30A. The dead time generation circuit 20B receives the voltage at the output node N2 of the delay circuit DL1 and the voltage at the output node N5 of the drive circuit 30A. When both voltages are at the H level, the node N7 is set to the L level, and the drive circuit The output circuit 50B is driven via 30B.

  Now, at time t1 in FIG. 2, the input terminal IN is at the H level, the output circuit 50A is in the complete conduction state, the output circuit 50B is in the complete cutoff state, and the output terminal OUT is at the high potential. VH, and no current flows between the output circuits 50A and 50B. At time t2, when the input terminal IN transitions from the H level to the L level, the node N1 becomes the H level and the nodes N3 and N6 become the L level. For this reason, the node N5 becomes H level, and the transistor MP8 of the drive circuit 30A is cut off. Further, the transistor MP7 of the weak inversion driving circuit 40B becomes conductive, and the current source I2 flows through the node N8, and the node N8 is slightly lifted. Therefore, the transistor MN8 of the output circuit 50B is driven to be weakly inverted and becomes slightly conductive. The conduction resistance at this time is relatively large (for example, 8Ω). In this way, when the output circuit 50A is shut off, the output circuit 50B to be conducted next time is weakly inverted. When time T1 elapses and time t3 is reached, the output node N2 of the delay circuit DL1 changes to the H level, whereby the node N7 changes to the L level, the node N8 is raised to the H level, and the output circuit The transistor MN8 of 50B is completely conducted from the weak conducting state. Further, the node N4 changes to L level, and the transistor MN2 is cut off. Thus, the weak inversion driving period T1 coincides with the dead time period.

  When an inductive load is connected to the class D amplifier, the regenerative current at the time of output inversion increases as the load current increases and the temperature increases. An increase in the regenerative current prolongs the reverse recovery time of the body diode. This reverse recovery time lengthens the switching time of the output circuits 50A and 50B, and causes a problem in both efficiency and waveform distortion.

  With respect to this point, in this embodiment, the output circuit 50B is brought into the original complete conduction state after a lapse of time T1 after being slightly turned on by the weak inversion drive as described above. Since it becomes longer as the temperature becomes higher, the regenerative current flowing through the inductance load that increases as the temperature rises can be shunted and discharged to the output circuit 50B. For this reason, the reverse recovery time of the body diode D1 of the transistor MP8 of the output circuit 50A Can be shortened. The greater the regenerative current, the longer the time required to discharge the accumulated charge, but this can be accommodated.

  Next, at time t4 in FIG. 2, the input terminal IN becomes H level, the node N1 becomes L level, and the nodes N3 and N6 become H level. For this reason, the node N8 becomes L level, and the drive circuit 30B transistor MN8 is cut off. In addition, the transistor MN3 of the weak inversion driving circuit 40A becomes conductive, and the current source I1 flows from the node N5 toward the power source VL, and the node N5 is slightly lowered. For this reason, the transistor MP8 of the output circuit 50A is driven reversely and becomes slightly conductive. Further, the transistor MN1 of the drive circuit 30A is turned on. Then, when time T1 elapses and time t5 is reached, the output node N2 of the delay circuit DL1 changes to L level, whereby the node N4 becomes H level, so that the transistor MN2 becomes conductive and the node N5 becomes L level. Level, and the transistor MP8 becomes fully conductive.

  Also in this case, as described above, the transistor MN8 of the output circuit 50B is cut off and the transistor MP8 of the output circuit 50A is slightly turned on by the weak inversion drive. Fully conductive state. Since the weak inversion driving time T1 becomes longer as the temperature increases, the regenerative current flowing in the output circuit 50B, which increases with temperature, can be shunted to the output circuit 50A and discharged, and the body diode D2 of the transistor MN8 of the output circuit 50B can be discharged. The reverse recovery time can be shortened.

<Second embodiment>
FIG. 3 shows a circuit of the class D amplifier of the second embodiment. In the first embodiment described with reference to FIG. 1, since the weak inversion driving circuits 40A and 40B operate during the time T1 after the logic of the signal at the input terminal IN is inverted, a little current flows.

  Therefore, in this embodiment, when the common enable terminal EN is provided and the common enable terminal EN is at the H level, the OR circuit OR1 and the AND circuit AND1 open the gate to pass the output signal of the inverter INV1, and the NMOS transistor MN9. When the PMOS transistor MP9 becomes conductive, the weak inversion driving circuits 40A and 40B operate. When the enable terminal EN is at the L level, the AND circuit AND1, the OR circuit OR1 closes the gate, and the NMOS transistor MN9, When the PMOS transistor MP9 is cut off, the weak inversion driving circuits 40A and 40B are prevented from operating.

  As a result, if the common enable terminal EN is set to L level during standby, the weak inversion driving circuits 40A and 40B will not operate regardless of the inversion of the signal at the input terminal IN. Battery life can be extended. Further, defective products such as junction leaks of the weak inversion driving circuits 40A and 40B can be effectively selected in a test at the time of shipment of the IC.

<Third embodiment>
FIG. 4 shows a circuit of a class D amplifier according to the third embodiment. In this embodiment, in addition to the common enable terminal EN, individual enable terminals EN_H and EH_L are provided, and the weak inversion drive circuits 40A and 40B that can operate when the common enable terminal EN is at the H level are connected to the individual enable terminals EN_H, By setting EH_L to L level, each can be stopped independently. Accordingly, the weak inversion driving circuits 40A and 40B can be individually and directly controlled from the CPU when the output circuits 50A and 50B are in an emergency stop.

<Other examples>
The current of the current sources I1 and I2 of the weak inversion driving circuits 40A and 40B is a low-pass signal of the signal input to the input terminal IN (that is, the analog signal component finally obtained by the class D amplifier). ) Can be used. According to this, the currents of the current sources I1 and I2 can be minimized, and the current flowing during the weak inversion driving can be dynamically minimized.

10A: High side bias voltage generation circuit, 10B: Low side bias voltage generation circuit, 20A: High side time generation circuit, 20B: Low side time generation circuit, 30A: High side drive circuit, 30B: Low side drive circuit, 40A: Low high side Inversion drive circuit, 40B: Low side weak inversion drive circuit 50A: High side output circuit, 50B: Low side output circuit IN: Input terminal OUT: Output terminal EN: Common enable terminal EN_H, EN_L: Individual enable terminal

Claims (7)

A high-side output circuit connected between the output terminal and the high-potential power supply terminal;
A low-side output circuit connected between the output terminal and the low-potential power supply terminal;
A high-side drive circuit that drives the high-side output circuit in response to the signal at the input terminal becoming the first logic;
A low-side drive circuit that drives the low-side output circuit in response to a signal at the input terminal becoming a second logic obtained by inverting the first logic;
A high side that weakly inverts and drives the high side output circuit from a timing that is earlier than the timing at which the high side output circuit starts to be driven by the high side drive circuit by a period corresponding to the temperature detected by the temperature detection means. A weak inversion drive circuit;
Low-side weak inversion driving that weakly inverts the low-side output circuit from a timing earlier than the timing at which the low-side output circuit starts to be driven by the low-side drive circuit by a period corresponding to the temperature detected by the temperature detection unit. Circuit,
A class-D amplifier comprising: The class D amplifier according to claim 1,
The temperature detection means is a delay circuit that delays the signal at the input terminal by a first time proportional to the temperature,
The high-side output circuit is weakly inverted by the high-side weak inversion driving circuit when the signal at the input terminal becomes the first logic, and then driven by the high-side driving circuit after the first time has elapsed. And
The low-side output circuit is weakly inverted by the low-side weak inversion driving circuit when the signal at the input terminal becomes the second logic, and then driven by the low-side driving circuit after the first time has elapsed.
Class D amplifier characterized by the above. The class D amplifier according to claim 1 or 2,
A period of the first time from when the high-side output circuit starts weak inversion driving by the high-side weak inversion driving circuit until full driving is started by the high-side driving circuit; and the low-side output circuit The high-side output circuit and the low-side output circuit are driven during the first time period from when the low-side weak inversion driving circuit starts weak inversion driving to when the low-side driving circuit starts full driving. A class D amplifier characterized by being stopped. The class D amplifier according to any one of claims 1 to 3,
The high side weak inversion driving circuit applies a bias voltage corresponding to the current of the first current source to the high side output circuit when the signal of the first current source and the input terminal is the first logic. High-side switch means to
The low-side weak inversion driving circuit applies a bias voltage corresponding to the current of the second current source to the low-side output circuit when a signal of the second current source and the input terminal is a second logic. Side switch means,
Class D amplifier characterized by the above. The class D amplifier according to claim 4,
A class-D amplifier characterized in that the currents of the first and second current sources are currents corresponding to a low-pass signal of a signal input to the input terminal. The class D amplifier according to any one of claims 1 to 5,
The class D amplifier, wherein the high-side weak inversion driving circuit and the low-side weak inversion driving circuit stop the weak inversion driving when a common enable signal becomes invalid. The class D amplifier according to any one of claims 1 to 5,
The high-side weak inversion driving circuit and the low-side weak inversion driving circuit are disabled when individual enable signals for the high side and the low side become invalid when the common enable signal is valid. A class D amplifier characterized in that the operation of the high-side weak inversion driving circuit or the low-side weak inversion driving circuit corresponding to a signal is stopped.

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