JP2014049973A - Serial data receiving circuit and receiving method, audio signal processing circuit, electronic equipment, and audio system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To receive serial data stably.SOLUTION: A multiplication circuit 30 multiplies a bit clock BCK by N (N is a natural number) to generate a system clock PLLCK. A first counter 12 counts the system clock PLLCK and resets a count value CNT1 thereof to an initial value each time the count value reaches a set value D. A counter clear circuit 16 asserts a counter clear signal CNT_CLR each time the count value CNT1 of the first counter 12 reaches a prescribed value. A second counter 56 counts the system clock PLLCK and resets a count value to an initial value each time the counter clear signal CNT_CLR is asserted. An Lch latch 52 latches parallel data from a shift register 14 synchronously with the counter clear signal CNT_CLR. A cycle setting unit 70 dynamically sets the set value Dof the first counter CNT1.

Description

  The present invention relates to a receiving circuit that receives serial data.

In order to transmit information between integrated circuits, a 2-wire or 3-wire serial interface is used. The I ² C (Inter Integrated Circuit) bus standard is proposed as a 2-wire serial interface, and the I ² S (Inter Integrated circuit Sound) bus standard for transmitting digital audio signals is proposed and used as a 3-wire serial interface. It has become.

FIG. 1 is a diagram illustrating an I ² S signal format. The serial data DATA includes 64 bits for each sampling period Ts. Of the 64 bits, 32 bits are assigned to the L channel and 32 bits are assigned to the R channel. The data for each L channel and R channel is called one word.
The bit clock BCK has a positive edge for each bit of the serial data DATA. That is, the frequency of the bit clock BCK is 64 times the sampling frequency fs (= 1 / Ts).

In the I ² S transmission, in addition to these, a word clock LRCK having a positive edge and a negative edge is input for each word (32 bits). When the word clock LRCK is at a low level, L channel data is transmitted, and when the word clock LRCK is at a high level, R channel data is transmitted.

In I ² S communication, a maximum of 24 bits are assigned to audio data out of 32 bits per word. This bit length K is variable according to the sound quality. In the case of left-justified, the upper K bits of the 32 bits are data indicating audio signals (referred to as audio data), and in the case of right-justified, the lower K bits are audio data. The L channel audio data is referred to as Lch data, and the R channel audio data is referred to as Rch data.

The above is the outline of the format of the I ² S communication.

FIG. 2 is a block diagram showing a configuration of a receiving circuit 100r having an I ² S communication interface studied by the present inventors. It should be noted that the configuration and operation of the receiving circuit 100r in FIG. The receiving circuit 100r includes a serial interface circuit 10, a multiplying circuit 30, and an input stage 50 of a DSP (Digital Signal Processor).

  The serial interface circuit 10 receives the word clock LRCK, the bit clock BCK, and the data DATA, performs parallel-serial conversion, and outputs the L channel data D_Lch and the R channel data D_Rch to the input stage 50 of the subsequent DSP.

  The multiplier circuit 30 includes, for example, a PLL circuit, and generates a system clock PLLCK that is 1024 times the sampling frequency fs by multiplying the bit clock BCK by 16. The DSP that is the data receiving destination processes the audio data D_Lch and D_Rch in synchronization with the system clock PLLCK.

  The serial interface circuit 10 includes a serial / parallel converter 11, a first counter 12, and a counter clear circuit 16.

  The serial / parallel converter 11 extracts L channel data D_Lch and R channel data D_Rch included in the serial data DATA in synchronization with the bit clock BCK and the word clock LRCK.

The serial / parallel converter 11 includes a shift register 14, an Lch buffer BUF_L, an Rch buffer BUF_R, and a timing control unit 15.
The serial data DATA includes 32-bit L channel data and 32-bit R channel data, of which the effective audio data has a maximum length of 24 bits. Therefore, the shift register 14 is composed of 24 bits and shifts the serial data DATA bit by bit in synchronization with the bit clock BCK. The shift register 14 outputs 24-bit parallel data Dp.

The timing controller 15 asserts the first timing signal after counting 24 bit clocks BCK from the negative edge of the word clock LRCK. When the first timing signal is asserted, the Lch buffer BUF_L latches the parallel data Dp stored in the shift register 14 as L channel data D_Lch.
The timing controller 15 asserts the second timing signal when (32 + 24) bit clocks BCK are counted from the negative edge of the word clock LRCK or 24 bit clocks BCK are counted from the positive edge of the word clock LRCK. . When the second timing signal is asserted, the Rch buffer BUF_R latches the parallel data Dp stored in the shift register 14 as R channel data D_Rch.

  When the clear command is issued, the first counter 12 is cleared to zero at the timing of the negative edge of the next word clock LRCK. Thereafter, the first counter 12 performs a count operation in synchronization with the bit clock BCK, and returns to 0 every time the count value CNT1 reaches a predetermined value (for example, 1023), and repeats the operation of counting up again.

  The counter clear circuit 16 receives the count value CNT1 of the first counter 12, and asserts the counter clear signal CNT_CLR every time the count value CNT1 reaches a predetermined value (for example, 800).

  The DSP input stage 50 includes an Lch latch 52, an Rch latch 54, a second counter (DSP sequence counter) 56, and a strobe signal generator 58.

  The second counter 56 is cleared to zero each time the count clear signal CNT_CLR is asserted, and repeats the operation of counting up. The strobe signal generator 58 asserts the first strobe signal STRB1 every time the count value CNT2 of the second counter 56 becomes a first predetermined value (for example, 0), in other words, every time the count clear signal CNT_CLR is asserted, The second strobe signal STRB2 is asserted every time the count value CNT2 becomes a second predetermined value (for example, 512).

  The Lch latch 52 latches the L channel data D_Lch stored in the Lch buffer BUF_L in synchronization with the first strobe signal STRB1. Similarly, the Rch latch 54 latches the R channel data D_Rch stored in the Rch buffer BUF_R in synchronization with the second strobe signal STRB2.

JP 2000-078027 A JP-A-6-224873

The inventor has studied the circuit operation of the receiving circuit 100r in FIG. 2 and has recognized the following problems. FIGS. 3A and 3B are waveform diagrams showing the operation of the receiving circuit 100r in FIG.
FIG. 3A shows an operation when the frequency of the system clock PLLCK is maintained at 1024 × fs. In this case, the counter clear signal CNT_CLR is to be asserted in the vicinity of the center of the L-channel data _{L n,} stably data is captured.

In an actual circuit, the frequency of the system clock PLLCK fluctuates due to the influence of noise or the like and deviates from 1024 × fs. In this case, the clearing timing of the first counter 12 deviates from the negative edge of the word clock LRCK. As a result, the Lch latch 52 of the input stage 50, or _{L n} is _taken, or _{L n + 1} is taken, the operation becomes unstable.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and one of exemplary purposes of an embodiment thereof is to provide a receiving circuit capable of stably receiving serial data regardless of fluctuations in the frequency of the system clock. is there.

  In one aspect of the present invention, serial data including K bits to be received, M bit (M is a natural number), a bit clock having an edge for each bit of the serial data, and an edge for each M bit. The present invention relates to a receiving circuit that receives a word clock. The receiving circuit multiplies the bit clock by N (N is a natural number) to generate a system clock, and synchronizes the bit clock and the word clock with K bits to be received included in the serial data as parallel data. A serial / parallel converter for conversion, a first counter that counts the system clock, and repeats the operation of resetting the count value to the initial value every time the count value reaches the set value, and the system clock is counted. A second counter that repeats the operation of resetting the count value to the initial value every time the set value is reached, a latch circuit that latches K-bit data output from the serial / parallel converter, and the set value of the first counter are dynamically set A cycle setting unit that is set to

  According to this aspect, serial data can be stably received by dynamically setting the setting values of the first counter and the second counter, that is, the period, according to the fluctuation of the system clock.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  The receiving circuit according to the present invention can stably receive serial data.

It is a diagram illustrating a signal format of the I 2 ^S. Is a block diagram showing the configuration of a receiving circuit comprising I ^{2 S} communication interface studied by the present inventor. FIGS. 3A and 3B are waveform diagrams showing the operation of the receiving circuit of FIG. It is a block diagram which shows the structure of the receiving circuit which concerns on embodiment. FIG. 5A is a state transition diagram of the state machine of the cycle setting unit, and FIG. 5B is a diagram illustrating a count value and a count cycle at the negative edge of the word clock LRCK. 6A to 6C are waveform diagrams illustrating the operation of the receiving circuit. It is a block diagram which shows the structure of the audio system using the audio signal processing circuit provided with a receiving circuit. 8A to 8C are external views of electronic devices or audio component devices.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

FIG. 4 is a block diagram illustrating a configuration of the receiving circuit 100 according to the embodiment. The receiving circuit 100 is a source-synchronous three-wire serial interface circuit, and receives a bit clock BCK, a word clock LRCK, and serial data DATA from a transmitting circuit (not shown). The bit clock BCK has an edge for each bit of the serial data DATA. In the following, a system that receives digital audio data compliant with the I ² S bus standard will be described as an example.

  The audio signal is sampled at the sampling frequency fs. The serial data DATA includes 64 bits for each sampling period Ts (= 1 / fs). Of the 64 bits, 32 bits are assigned to the L channel and 32 bits are assigned to the R channel. The 32 bits for each L channel and R channel are referred to as one word. That is, the serial data DATA is transmitted in units of 2 words and M (= 64 bits).

  The bit clock BCK has a positive edge for each bit of the serial data DATA. That is, the frequency of the bit clock BCK is 64 times the sampling frequency fs (= 1 / Ts).

In the I ² S transmission, in addition to these, a word clock LRCK having a positive edge and a negative edge at the boundary of one word (32 bits) is transmitted. When the word clock LRCK is at a low level, L channel data is transmitted, and when the word clock LRCK is at a high level, R channel data is transmitted.

In I ² S communication, a maximum of K (= 24) bits are assigned to audio data out of one word and 32 bits. In I ² S communication, K bits (= 24) out of 32 bits per word are valid bits to be received, and in the case of left-justified, the upper 24 bits of 32 bits are used for audio signals. Assigned to the audio data shown. The L channel audio data (24 bits) is referred to as Lch data D_Lch, and the R channel audio data is referred to as Rch data D_Rch.

  The receiving circuit 100 includes a serial interface circuit 10, a multiplier circuit 30, an input stage 50, and a cycle setting unit 70, and is integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the circuit as one IC, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

  The serial interface circuit 10 receives the word clock LRCK, the bit clock BCK, and the data DATA, performs parallel-serial conversion, and outputs the L channel data D_Lch and the R channel data D_Rch to the input stage 50 of the subsequent DSP.

  The multiplication circuit 30 multiplies the bit clock BCK by N (N is an integer of 2 or more, and N = 16 in the present embodiment), thereby multiplying the sampling frequency fs by M × N (= 1024). A clock PLLCK is generated. For example, the multiplier circuit 30 is configured by a PLL circuit.

  A DSP (Digital Signal Processor) 50 which is a data receiving destination processes the audio data D_Lch and D_Rch in synchronization with the system clock PLLCK.

  The serial interface circuit 10 includes a serial / parallel converter 11 and a first counter 12.

  The serial / parallel converter 11 converts the L channel data D_Lch and the R channel data D_Rch included in the serial data DATA into parallel data in synchronization with the bit clock BCK and the word clock LRCK.

The serial / parallel converter 11 includes a shift register 14, an Lch buffer BUF_L, an Rch buffer BUF_R, and a timing control unit 15.
The serial data DATA includes 32-bit L channel data and 32-bit R channel data, of which the effective audio data has a maximum length of 24 bits. Therefore, the shift register 14 is composed of 24 bits and shifts the serial data DATA bit by bit in synchronization with the bit clock BCK. The shift register 14 outputs 24-bit parallel data Dp.

The timing controller 15 asserts the first timing signal after counting 24 bit clocks BCK from the negative edge of the word clock LRCK. When the first timing signal is asserted, the Lch buffer BUF_L latches the parallel data Dp stored in the shift register 14 as L channel data D_Lch.
The timing controller 15 asserts the second timing signal when (32 + 24) bit clocks BCK are counted from the negative edge of the word clock LRCK or 24 bit clocks BCK are counted from the positive edge of the word clock LRCK. . When the second timing signal is asserted, the Rch buffer BUF_R latches the parallel data Dp stored in the shift register 14 as R channel data D_Rch. The timing at which the first and second timing signals are asserted may be set according to the arrangement of data to be received (left justified, right justified) and the number of bits K of data to be received.

When the clear command is issued, the first counter 12 is cleared to zero at the timing of the negative edge of the next word clock LRCK. Thereafter, the first counter 12 counts the system clock PLLCK, and returns to the initial value α (for example, 0) every time the count value CNT1 reaches a set value D _SET given from the cycle setting unit 70 described later, and counts again. Repeat the action to up. That is, the count cycle of the first counter 12 is dynamically controlled by the cycle setting unit 70.

  The input stage 50 includes an Lch latch 52, an Rch latch 54, a second counter 56, and a strobe signal generator 58.

When the clear command is issued, the second counter (DSP internal counter) 56 is cleared to zero at the timing of the negative edge of the next word clock LRCK. Thereafter, the second counter 56 counts the system clock PLLCK, and returns to the initial value β (for example, 0) every time the count value CNT2 reaches a set value D _SET given from the cycle setting unit 70 described later, and counts up again. Repeat the operation.

  The strobe signal generator 58 asserts the first strobe signal STRB1 every time the count value CNT2 of the second counter 56 becomes a first predetermined value (eg, 0), and the count value CNT2 becomes the second predetermined value (eg, 512). Each time the second strobe signal STRB2 is asserted.

  The Lch latch 52 latches the L channel data D_Lch stored in the Lch buffer BUF_L in synchronization with the first strobe signal STRB1. Similarly, the Rch latch 54 latches the R channel data D_Rch stored in the Rch buffer BUF_R in synchronization with the second strobe signal STRB2.

The cycle setting unit 70 dynamically sets the set value D _SET based on the count value CNT1 of the first counter 12 at the negative edge timing of the word clock LRCK.

Period setting unit 70 transitions between first state φ1 to third state φ3.
The initial value of the first counter 12 and alpha, when x, the y and predetermined number, the first state .phi.1, set value _{D SET} is α + M × N-1, in the second state .phi.2, set value _{D SET} Is α + M × N-1-x, and in the third state φ3, the set value D _SET is α + M × N-1 + y. When α = 0 and x = y = 1, in the first state φ1, the count cycle is 1024, the count value CNT1 repeats from 0 to 1023, and in the second state φ2, the count cycle is 1023, and the count value CNT2 repeats 0 to 1022, and in the third state φ3, the count cycle is 1025, and the count value CNT3 repeats 0 to 1024.

  FIG. 5A is a state transition diagram of the state machine of the cycle setting unit 70, and FIG. 5B is a diagram illustrating the count value and the count cycle at the negative edge of the word clock LRCK. As shown in FIG. 5A, the state machine makes a state transition based on the count value CNT1 of the first counter 12 at the edge timing of the word clock LRCK. In the state transition, hysteresis is set for the count value CNT1. Here, the hysteresis width is shown for 16 clocks. Hysteresis control can suppress frequent state transitions and stabilize the system.

The above is the configuration of the receiving circuit 100. Next, the operation will be described.
6A to 6C are waveform diagrams showing the operation of the receiving circuit 100. FIG. As shown in FIG. 6A, when the system clock PLLCK maintains M × N × fs, the count value CNT1 of the first counter 12 at the negative edge of the word clock LRCK is close to zero. At this time, the cycle setting unit 70 is in the first state φ1, and the count cycle of the first counter 12 is M × N.

  If the system clock PLLCK continues to exceed M × N × fs (= 1024 × fs), the count value CNT1 of the first counter 12 at the negative edge of the word clock LRCK increases as shown in FIG. 6B. To do. When the count value CNT1 of the first counter 12 at the negative edge of the word clock LRCK eventually exceeds the threshold value 16, the state transits to the third state φ3, and the count cycle of the first counter 12 becomes M × N + x (= 1025). .

  When the system clock PLLCK continues to be lower than M × N × fs (= 1024 × fs), the count value CNT1 of the first counter 12 at the negative edge of the word clock LRCK decreases as shown in FIG. 6C. To do. Eventually, when the count value CNT1 of the first counter 12 at the negative edge of the word clock LRCK becomes 1008 or less, the state transits to the second state φ2, and the count cycle of the first counter 12 becomes M × N−y (= 1022).

The above is the operation of the receiving circuit 100. According to the receiving circuit 100, when the frequency of the system clock PLLCK varies, the count cycles of the first counter 12 and the second counter 56 are changed accordingly to M × N−x, M × N + y with M × N as a reference. Increase or decrease by the two values.
In this method, a shift in clock frequency of x or y can be absorbed every sampling period Ts = 1 / fs. For example, when a shift of 100 clocks occurs in the system clock PLLCK due to the influence of noise, the neutral state can be restored thereafter with 100 / x sampling periods or 100 / y sampling periods.

Next, the use of the receiving circuit 100 will be described.
FIG. 7 is a block diagram illustrating a configuration of an audio system 500 using the audio signal processing circuit 200 including the receiving circuit 100.

  The audio system 500 includes a sound source 2, an audio signal processing circuit 200, amplifiers 8L and 8R, and speakers 9L and 9R.

  The audio signal processing circuit 200 is connected to the sound source 2 such as a CD player via a 3-wire serial interface and receives a digital audio signal. The audio signal processing circuit 200 includes a plurality of processing units 203 and a D / A converter 204 in addition to the receiving circuit 100 described above. The input stage 50 and the plurality of processing units 203 are collectively referred to as a DSP 202.

  The input stage 50 receives the digital audio signal from the sound source 2 and generates L channel data D_Lch and R channel data D_Rch. The data D_Lch and D_Rch output from the input stage 50 are input to the subsequent processing unit 203. The processing unit 203 is a digital volume circuit, a multiband equalizer, a loudness circuit, a crossover filter, a bass boost circuit, and the like, and performs predetermined signal processing on the data D_Lch and D_Rch.

  The signal processing of the processing unit 203 is synchronized with the count value CNT2 of the second counter (DSP sequence counter) 56 of the input stage 50. That is, when the count value CNT2 is in the first range, the first processing unit 203 performs signal processing, and when the count value CNT2 is in the second range, the second processing unit 203 performs signal processing.

  The D / A converters 204L and 204R convert the audio data D_Lch and D_Rch that have passed through the processing unit 203 from digital to analog, and generate analog audio signals S_Lch and S_Rch, respectively.

  The amplifiers 8L and 8R amplify the analog audio signals S_Lch and S_Rch and output them to the speakers 9L and 9R.

  The audio signal processing circuit 200 of FIG. 7 can also be used for an in-vehicle audio device and a home audio component device. Alternatively, the audio signal processing circuit 200 can be mounted on an electronic device such as a television, a desktop PC, a notebook PC, a tablet PC, a mobile phone terminal, a digital camera, or a portable audio player.

  8A to 8C are external views of electronic devices or audio component devices. FIG. 8A illustrates a display device 600 that is an example of an electronic device. The display device 600 includes a housing 602 and a speaker 9. The audio signal processing circuit 200 is built in the casing and drives the speaker 9.

  FIG. 7B shows an audio component 700. The audio component 700 includes a housing 702 and a speaker 9. The audio signal processing circuit 200 is built in the housing 702 and drives the speaker 9.

  FIG. 7C illustrates a small information terminal 800 which is an example of an electronic device. The small information terminal 800 is a mobile phone, PHS (Personal Handy-phone System), PDA (Personal Digital Assistant), tablet PC (Personal Computer), audio player, or the like. The small information terminal 800 includes a housing 802, a speaker 9, and a display 804. The audio signal processing circuit 200 is built in the housing 802 and drives the speaker 9.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

In the embodiment, the serial data of the I ² S bus standard has been described as an example. However, the present invention is not limited thereto, and may be used for transmission of serial data compliant with other standards such as the I ² C bus standard. it can. In this case, the values of the natural numbers M, K, x, and y that are parameters may be changed as appropriate. Further, there may be a plurality of lines for transmitting serial data.

  In the embodiment, the case has been described in which the cycle setting unit 70 transitions between three states and the cycle of the first counter 12 is switched between three values. However, the present invention is not limited to this, and the cycle is binary or It may be switched by four or more values.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

BCK ... bit clock, DATA ... serial data, LRCK ... word clock, PLLCK ... system clock, 100 ... receiving circuit, 10 ... serial interface circuit, 12 ... first counter, 14 ... shift register, 16 ... counter clear circuit, 30 ... Multiplier circuit 50 ... Input stage 52 ... Lch latch 54 ... Rch latch 56 ... Second counter 58 ... Strobe signal generation unit 70 ... Period setting unit 200 ... Audio signal processing circuit 202 ... DSP 203 ... Processing unit, 204 ... D / A converter, 500 ... audio system, 2 ... sound source, 8 ... amplifier, 9 ... speaker.

Claims (17)

Serial data that is transmitted in units of M bits (M is a natural number) and includes K bits (K is a natural number) to be received, a bit clock having an edge for each bit of the serial data, and an edge for each M bit A receiving circuit for receiving a word clock comprising:
A multiplier for generating a system clock by multiplying the bit clock by N (N is a natural number);
A serial-parallel converter that converts K bits to be received included in the serial data into parallel data in synchronization with the bit clock and the word clock;
A first counter that repeats an operation of counting the system clock and resetting the count value to an initial value every time the count value reaches a set value;
A second counter that repeats an operation of counting the system clock and resetting the count value to an initial value every time the count value reaches a set value;
A latch circuit for latching K-bit parallel data output from the serial-parallel converter;
A period setting unit for dynamically setting set values of the first counter and the second counter;
A receiving circuit comprising:   The receiving circuit according to claim 1, wherein the period setting unit dynamically sets the setting value based on a count value of the first counter at a predetermined timing.   The receiving circuit according to claim 2, wherein the predetermined timing is a timing of an edge of the word clock.   When the initial value of the first counter is α, and the predetermined constants are x and y, the cycle setting unit is configured such that the set value is α + M × N−1, and α + M × N−1−. The receiving circuit according to claim 2, further comprising a state machine that transitions between a second state that is x and a third state that is α + M × N−1 + y.   5. The receiving circuit according to claim 4, wherein the state machine makes a state transition based on a count value of the first counter at an edge timing of the word clock.   The receiving circuit according to claim 5, wherein a hysteresis is set for the count value in the state transition.   7. The receiving circuit according to claim 1, wherein the serial data includes K-bit L channel data and K-bit R channel data. A strobe signal generator for generating first and second strobe signals that are asserted each time the count value of the second counter reaches a first predetermined value and a second predetermined value;
8. The reception according to claim 7, wherein the latch circuit latches the L channel data in synchronization with the first strobe signal, and latches the R channel data in synchronization with the second strobe signal. circuit.   The receiving circuit according to claim 1, wherein the serial data includes audio data.   The receiving circuit according to claim 1, wherein the receiving circuit is integrated on a single semiconductor substrate. A receiving circuit according to any one of claims 1 to 10,
A processing unit for signal processing the data received by the receiving circuit;
An audio signal processing circuit comprising:   An electronic apparatus comprising the audio signal processing circuit according to claim 11.   An audio system comprising the audio signal processing circuit according to claim 11. Serial data that is transmitted in units of M bits (M is a natural number) and includes K bits (K is a natural number) to be received, a bit clock having an edge for each bit of the serial data, and an edge for each M bit Having a word clock comprising:
Generating a system clock by multiplying the bit clock by N (N is a natural number);
Synchronizing K bits to be received included in the serial data into parallel data in synchronization with the bit clock and the word clock;
Repeating the operation of counting the system clock by a first counter and resetting the count value to an initial value every time the count value reaches a set value;
Repeating the operation of counting the system clock by a second counter and resetting the count value to an initial value every time the count value reaches a set value;
Latching the K-bit parallel data;
Dynamically setting set values of the first counter and the second counter;
A method comprising the steps of:   The method according to claim 14, wherein the setting value is dynamically set based on a count value of the first counter at a predetermined timing.   The method according to claim 15, wherein the predetermined timing is an edge timing of the word clock.   The first state with the set value of M × N, the second state with M × N−1, and the third state with M × N + 1 are transitioned. The method according to any one.

Images