JP2014081270A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency in an inspection process for classifying semiconductor devices as non-defective or defective on the basis of electric characteristics in a plurality of temperature ranges.SOLUTION: When the temperature of the semiconductor device becomes -40°C in a low-temperature chamber in which the temperature is kept at -50°C, the electric characteristics of the semiconductor device are measured and obtained low-temperature measurement data is temporarily stored. Then, the semiconductor device is heated by bringing a heater into contact with the semiconductor device; the electric characteristics of the semiconductor device are measured when the semiconductor temperature becomes 25°C; and obtained room temperature measurement data is temporarily stored. A difference (the amount of drift) between the low-temperature measurement data and the room temperature measurement data is calculated; determination of whether the semiconductor device is non-defective or defective is performed; and semiconductor devices that are determined to be non-defective are stored so as to be arranged closely together in order from an end in an IC storage tray.

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and can be suitably used for, for example, an inspection process for selecting non-defective / defective products of a semiconductor device.

  The electrical characteristics of the semiconductor device are measured in a temperature range of low temperature (for example, −55 ° C. to 0 ° C.), normal temperature (for example, 25 ° C.), and high temperature (for example, 50 ° C. to 135 ° C.). Sorts non-defective and defective equipment.

  For example, Japanese Patent Laid-Open No. 5-34405 (Patent Document 1) discloses an IC that can be accurately controlled so that an IC (Integrated Circuit) device is in a predetermined temperature state in all temperature ranges from high temperature to low temperature. A temperature control system for a handler is disclosed.

  Japanese Patent Application Laid-Open No. 2008-224455 (Patent Document 2) discloses that a test is continuously performed by switching a heating unit, a cooling unit, and a room temperature air supply unit at a predetermined timing by an atmosphere switching unit. A semiconductor device test chamber is disclosed.

JP-A-5-34405 JP 2008-224455 A

  For example, in the inspection process of an in-vehicle semiconductor device, the electrical characteristics of the semiconductor device in each temperature range of low temperature (for example, −55 ° C. to 0 ° C.), normal temperature (for example, 25 ° C.), and high temperature (for example, 50 ° C. to 135 ° C.). The characteristics are being measured. However, the processing of the data obtained in each temperature region is complicated, or it is necessary to refill only the semiconductor devices determined to be non-defective products based on the data into shipping trays. It took a lot of time.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, first, electrical characteristics of a semiconductor device are measured when the temperature of the semiconductor device reaches −40 ° C. in a low temperature chamber maintained at −50 ° C., and the obtained low temperature measurement is performed. Temporarily save data. Subsequently, the semiconductor device is heated by bringing the heater into contact with the semiconductor device, and when the temperature of the semiconductor device reaches 25 ° C., the electrical characteristics of the semiconductor device are measured, and the obtained room temperature measurement data is temporarily stored. To do. Then, the difference (drift amount) between the low-temperature measurement data and the normal-temperature measurement data is calculated to determine whether the semiconductor device is non-defective or defective, and the semiconductor devices determined to be non-defective are packed in the IC storage tray in order from the end. Store.

  According to one embodiment, it is possible to improve efficiency in an inspection process for selecting non-defective / defective products of a semiconductor device based on electrical characteristics in a plurality of temperature regions.

It is process drawing of the manufacturing method of the semiconductor device by embodiment. It is a principal part top view which shows an example of the external shape of the lead frame by embodiment. (A) And (b) is the principal part top view and principal part sectional drawing explaining the product state in the die-bonding process by embodiment, respectively. (A) And (b) is the principal part top view and principal part sectional drawing explaining the product state in the wire bonding process by embodiment, respectively. (A) And (b) is the principal part top view and principal part sectional drawing explaining the product state in the molding process by embodiment, respectively. (A) And (b) is the principal part top view and principal part sectional drawing explaining the product state in the plating process by embodiment, respectively. (A) And (b) is the principal part top view and principal part sectional drawing explaining the product state in the lead cutting process by embodiment, respectively. (A) And (b) is the principal part top view and principal part sectional drawing explaining the product state in the shaping | molding process by embodiment, respectively. It is the figure on which the example of the test content by embodiment was put together. It is a graph which shows an example of the relationship between the measured value of the specific item of the electrical property of the semiconductor device by embodiment, and measured temperature. It is the schematic which shows an example of the structure of the test handler by embodiment. It is a top view of IC storage tray by an embodiment. It is process drawing explaining the procedure of the test method of the semiconductor device in the 1st test process by embodiment. It is the schematic explaining the aspect of the semiconductor device and heater in the low temperature test of the 1st test process by embodiment. It is the schematic explaining the aspect of the semiconductor device and heater in the low temperature test of the 1st test process by embodiment. It is a graph which shows the relationship between the test temperature and test time of a semiconductor device in the 1st test process by embodiment. It is the schematic explaining the aspect of the semiconductor device and heater in the normal temperature test of the 1st test process by embodiment. It is process drawing explaining the procedure of the test method of the semiconductor device in the 2nd test process by embodiment. It is the schematic explaining the aspect of the semiconductor device and the air cooling mechanism in the high temperature test of the 2nd test process by embodiment. It is the schematic explaining the aspect of the semiconductor device and the air cooling mechanism in the high temperature test of the 2nd test process by embodiment. It is the schematic explaining the aspect of the semiconductor device and the air cooling mechanism in the normal temperature test of the 2nd test process by embodiment.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments will be described in detail with reference to the drawings.

(Details of the issue)
For example, in a test process for an in-vehicle semiconductor device, a handler is used in each temperature range of low temperature (for example, −55 ° C. to 0 ° C.), normal temperature (for example, 25 ° C.), and high temperature (for example, 50 ° C. to 135 ° C.). The electrical characteristics of the semiconductor device are measured, and non-defective / defective products of the semiconductor device are selected based on the measurement result.

  Below, the 1st test method and 2nd test method which are performed in the inspection process of the semiconductor device which the present inventors examined so far, and these subjects are explained.

1. First Test Method First, a normal temperature test is sequentially performed on a plurality of semiconductor devices, and semiconductor devices determined to be non-defective products by the normal temperature test are stored in a first non-defective product storage tray sequentially from the end, and determined as defective products. The semiconductor devices are packed in the first defective product storage tray from the end and stored.

  Subsequently, a high temperature test is sequentially performed on the plurality of semiconductor devices stored in the first non-defective product storage tray in the normal temperature test, and the semiconductor devices determined to be non-defective by the high temperature test are placed in the second non-defective product storage tray. The semiconductor devices determined to be defective from the end are stored in the second defective product storage tray in order from the end.

  Subsequently, a low temperature test is sequentially performed on a plurality of semiconductor devices stored in the second non-defective product storage tray in the high temperature test, and the semiconductor devices determined to be non-defective by the low temperature test are placed in the third non-defective product storage tray. The semiconductor devices determined to be defective products are packed and stored in order from the end, and stored in the third defective product storage tray in order from the end. Then, the plurality of semiconductor devices stored in the third non-defective product storage tray are finally shipped.

  However, each time the normal temperature test, the high temperature test, and the low temperature test are performed, the semiconductor devices determined to be non-defective are rearranged in the first good quality storage tray, the second good quality storage tray, and the third good quality storage tray. It is difficult to compare the data collected in the test, the high temperature test, and the low temperature test with the semiconductor device, and the data processing becomes very complicated.

2. Second Test Method First, a normal temperature test is performed on a plurality of semiconductor devices in order, and a semiconductor device determined to be a non-defective product by the normal temperature test is stored in a first non-defective product storage tray. 1. Store in a defective product storage tray. At this time, the semiconductor device stored in the first non-defective product storage tray is stored at the same position as the storage tray stored before the normal temperature test. Accordingly, the first non-defective product storage tray has an empty space in which the semiconductor device determined to be defective is not stored, and a plurality of semiconductor devices are stored in the first non-defective product storage tray in a so-called tooth missing state. .

  Subsequently, a plurality of semiconductor devices determined to be non-defective in the normal temperature test are sequentially subjected to a high temperature test, and the semiconductor device determined to be non-defective by the high temperature test is stored in the second non-defective storage tray and determined to be defective. The semiconductor device is stored in the second defective product storage tray. Here, as in the normal temperature test, the semiconductor device stored in the second non-defective product storage tray is stored in the same position as the storage tray (first non-defective product storage tray) stored before the high temperature test. Therefore, a plurality of semiconductor devices are stored in the second non-defective product storage tray in a state of missing teeth.

  Subsequently, a plurality of semiconductor devices determined to be non-defective in the high-temperature test are sequentially subjected to a low-temperature test, and the semiconductor devices determined to be non-defective by the low-temperature test are stored in the third non-defective storage tray and determined to be defective. The semiconductor device is stored in a third defective product storage tray. Here, similarly to the normal temperature test, the semiconductor device stored in the third non-defective product storage tray is stored in the same position as the storage tray (first or second non-defective product storage tray) stored before the low temperature test. . Accordingly, a plurality of semiconductor devices are stored in the third non-defective product storage tray in a state of missing teeth.

  Subsequently, the plurality of semiconductor devices stored in the third non-defective product storage tray in a state of missing teeth are refilled with a shipping tray, and finally shipped in a state of being sequentially packed from the end of the shipping tray.

  With the second test method, it becomes easy to compare the data collected in the normal temperature test, the high temperature test, and the low temperature test with the semiconductor device. However, it is necessary to modify the handler used in the test process. In addition, it is necessary to refill a plurality of semiconductor devices stored in the third non-defective product storage tray into a shipping tray in the state of missing teeth. At this time, the semiconductor devices are electrically or mechanically destroyed or refilled. Problems such as taking a lot of time.

(Embodiment)
A method of manufacturing a semiconductor device according to an embodiment will be described in the order of steps with reference to FIGS. FIG. 1 is a process diagram of a method for manufacturing a semiconductor device. FIG. 2 is a plan view of an essential part showing an example of the outer shape of the lead frame. 3A and 3B are a top view and a cross-sectional view of relevant parts for explaining a product state in the die bonding process, respectively. FIGS. 4A and 4B are a top view and a cross-sectional view of relevant parts for explaining a product state in the wire bonding process, respectively. FIGS. 5A and 5B are a top view and a cross-sectional view of relevant parts for explaining a product state in the molding process, respectively. FIGS. 6A and 6B are a top view and a cross-sectional view of relevant parts for explaining a product state in the plating process, respectively. FIGS. 7A and 7B are a top view and a cross-sectional view of relevant parts for explaining the product state in the lead cutting process, respectively. FIGS. 8A and 8B are a top view and a cross-sectional view of relevant parts for explaining the product state in the molding process, respectively. 9 to 21 are diagrams for explaining a test method in the inspection process.

  In the present embodiment, a test method in a semiconductor device inspection process is a main feature, and details and effects thereof will be clarified in the following description.

≪Semiconductor chip preparation process≫
An integrated circuit is formed on the circuit formation surface of the semiconductor wafer. An integrated circuit is formed on a semiconductor wafer in units of chips according to a predetermined manufacturing process in a manufacturing process called a pre-process or a diffusion process. Subsequently, after determining whether each semiconductor chip formed on the semiconductor wafer is good or defective, the semiconductor wafer is diced into individual semiconductor chips.

≪Lead frame preparation process≫
A lead frame (wiring) that has a first surface (front surface, upper surface) and a second surface (back surface, lower surface) opposite to the first surface, and is a metal frame made mainly of copper (Cu), for example. Member, wiring board, substrate).

  FIG. 2 shows an example of the lead frame. The lead frame LF has, for example, four unit frames SF corresponding to one semiconductor product, where the longitudinal direction (x-axis direction) of the lead frame LF is a column and the direction orthogonal to the column (y-axis direction) is a row. The arrangement is arranged in two rows, a so-called matrix. A die pad (tab, chip mounting portion) DP for mounting a semiconductor chip is provided at the center of each unit frame SF existing on the first surface of the lead frame LF so as to be separated from the die pad DP and surround the die pad DP. A plurality of leads (external terminals) LE are provided. A plurality of holes LH for positioning the lead frame LF are provided around the lead frame LF.

  3 to 6 used for explaining an example of the semiconductor device manufacturing method, only the region corresponding to one unit frame SF is shown.

≪Die bonding process≫
Next, as shown in FIGS. 3A and 3B, the semiconductor chip SC determined to be good is mounted on the upper surface of the die pad DP of each unit frame SF (the first surface of the lead frame LF). At this time, the upper surface of the die pad DP and the back surface of the semiconductor chip SC are joined using a die bond material, for example, a paste-like adhesive (for example, silver (Ag) paste). Note that the bonding between the die pad DP and the semiconductor chip SC is not limited to a paste-like adhesive, and for example, bonding using a gold-tin (Au—Sn) eutectic may be used.

≪Wire bonding process≫
Next, as shown in FIGS. 4A and 4B, the main surface (surface) of the semiconductor chip SC is formed by, for example, a nail head bonding (ball bonding) method in which ultrasonic vibration is used in combination with thermocompression bonding. A plurality of electrode pads (not shown) and a plurality of leads LE are electrically connected to each other via a plurality of conductive wires CW. Specifically, the tip of the conductive wire CW is melted by arc discharge to form a ball with surface tension, and this is applied to the upper surface (surface) of the electrode pad and the lead LE by a capillary (cylindrical connecting jig). For example, thermocompression bonding is performed while applying ultrasonic vibration of 120 kHz.

  Examples of the material of the conductive wire CW include metal materials such as gold (Au), copper (Cu), and aluminum (Al). In the case of gold (Au), for example, a gold wire of 15 μmφ to 20 μmφ is often used.

  In addition, the forward bonding method (method of connecting the lead LE and the other part of the conductive wire CW after connecting a part of the electrode pad of the semiconductor chip SC and the conductive wire CW) is mainly used, but the reverse bonding method ( A method of connecting the electrode pad of the semiconductor chip SC and the other part of the conductive wire CW after connecting the lead LE and a part of the conductive wire CW may be used.

≪Mold process≫
Next, as shown in FIGS. 5A and 5B, each semiconductor chip SC mounted on the lead frame LF is sealed with a resin sealing body (sealing body, package) MO.

  First, a lead frame LF on which a plurality of semiconductor chips SC are mounted is set in a mold molding machine. Subsequently, the resin liquefied by raising the temperature is pumped and poured into a mold molding machine, and the first surface side and the second surface side on which the semiconductor chip SC of the lead frame LF is mounted are sealed with resin. One resin sealing body MO is formed. The resin sealing body MO is made of an epoxy-based thermosetting insulating resin to which, for example, a phenol-based curing agent, silicone rubber, and a large number of fillers (for example, silica) are added in order to reduce stress.

≪Post-mold baking process≫
Next, the resin sealing body MO in which a part of the semiconductor chip SC and the lead frame LF is resin-sealed is used to further accelerate the curing of the resin sealing body MO and improve the adhesion to the lead frame LF. Annealing treatment (baking treatment) is performed on the substrate. The annealing treatment is performed for about 7 hours at a temperature of about 160 ° C. to 190 ° C., for example. Thereby, the semiconductor chip SC, the die pad DP, a part of each of the plurality of leads LE, and the plurality of conductive wires CW are sealed by the resin sealing body MO.

≪Plating process≫
Next, as shown in FIGS. 6A and 6B, the lead frame LF is plated. Thus, for example, tin (Sn) or tin-silver (Sn-Ag) having a thickness of 10 μm or less on the upper surface (front surface), the lower surface (rear surface), and the side surfaces of the leads LE protruding from the resin sealing body MO. ) -Based alloy, tin-copper (Sn-Cu) -based alloy, tin-bismuth (Sn-Bi) -based alloy, or tin-lead (Sn-Pb) -based alloy is formed.

≪Lead cutting process≫
Next, as shown in FIGS. 7A and 7B, the leads LE are cut using a cutting device, and are divided into individual semiconductor devices (semiconductor products) SD. At this time, for example, the cutting punch (provided in the cutting device) from the second surface side to the first surface side of the lead frame LE with respect to the lead frame LE placed on the die (mold receiving base) provided in the cutting device. Each semiconductor device SD is separated from the main body of the lead frame LE by advancing the cutting teeth.

≪Molding process≫
Next, as shown in FIGS. 8A and 8B, a plurality of leads LE exposed from the resin sealing body MO are molded into a predetermined shape by a molding die.

  In the above description, the semiconductor device SD is manufactured in the order of the plating step, the lead cutting step, and the molding step. However, the plating step and the molding step may be sequentially performed after the lead cutting step.

≪Inspection process≫
Next, the semiconductor device SD is sorted into a non-defective product and a defective product through an inspection process. In the inspection process, various inspections such as an electrical inspection and an appearance inspection according to product standards are performed on each semiconductor device SD. Here, a test method will be described in which specific items of electrical characteristics of the semiconductor device SD in a predetermined temperature region are measured out of various inspections, and non-defective / defective products of the semiconductor device SD are selected based on the measurement results. .

  Hereinafter, a method for testing a semiconductor device according to an embodiment will be described in detail with reference to FIGS. FIG. 9 is a table summarizing examples of test contents. FIG. 10 is a graph showing an example of the relationship between the measured value of the specific item of the electrical characteristics of the semiconductor device and the measured temperature. FIG. 11 is a schematic diagram showing an example of the structure of the test handler. FIG. 12 is a plan view of the IC storage tray. 13 to 17 are diagrams for explaining a test method of the semiconductor device in the first test process. 18 to 21 are diagrams for explaining a test method of the semiconductor device in the second test process.

  As shown in FIG. 9, in the test method according to the embodiment, a first test process and a second test process are performed. In the first test process, a low temperature test (for example, −40 ° C.) of a specific item of electrical characteristics of the semiconductor device is performed using a low temperature handler, followed by a normal temperature test (for example, 25 ° C.). The measurement results of specific items are compared to determine whether the semiconductor device is good or bad. In the second test process, a high-temperature test (for example, 125 ° C.) for a specific item of the electrical characteristics of the semiconductor device determined as a non-defective product in the first test process is performed using an ordinary high-temperature handler, followed by a room-temperature test (for example, 25 ) And compare the measurement results of specific items of each electrical characteristic to determine whether the semiconductor device is good or bad.

  An example of determining whether the semiconductor device is good or bad will be described with reference to FIG. The specific item of the electrical characteristics used for determining whether the semiconductor device is good or defective is, for example, the diode characteristics of the semiconductor chip.

  Ideally, the electrical characteristics of the semiconductor device do not change with temperature, but actually, the electrical characteristics of the semiconductor device change with temperature. Therefore, in the first test process, the data obtained in the low temperature test and the data obtained in the normal temperature test are compared, and if the difference (drift amount) between the two data is less than the target value (for example, ± 20 mV), If it is larger than the target value, it is determined as a defective product. Similarly, in the second test process, the data obtained in the high temperature test is compared with the data obtained in the normal temperature test, and if the difference (drift amount) between the two data is less than the target value (eg, ± 20 mV), the product is non-defective. If it is larger than the target value, it is determined as a defective product.

  FIG. 11 shows a schematic diagram of the structure of the test handler used in the first test process and the second test process. An arrow indicated by a dotted line in FIG. 11 indicates a flow of the semiconductor device. The basic structure of the low temperature handler used in the first test process and the normal high temperature handler used in the second test process is the same.

  A test handler is a type of device that tests a semiconductor device. The test device is placed outside the test chamber by bringing the semiconductor device into electrical contact with a test head (contact pin) in a test chamber that provides a test space. The test apparatus main body performs a test, and after the test, the semiconductor device is unloaded from the test chamber, and is classified into a non-defective product and a defective product based on the test result.

  As shown in FIG. 11, in the test handler HD, unmeasured IC storage (first storage) ST1 for storing a plurality of unmeasured semiconductor devices, specific items of electrical characteristics of the semiconductor devices are measured, Non-defective IC storage (second storage) ST2 for storing a plurality of determined semiconductor devices, measurement of specific items of electrical characteristics of the semiconductor device, and a defective IC for storing a plurality of semiconductor devices determined to be defective A storage (third storage) ST3 is provided. Further, the test handler HD includes a measurement unit MP that measures a specific item of the electrical characteristics of the semiconductor device using the test device.

  In the unmeasured IC storage ST1, for example, a plurality of semiconductor devices are stored in the IC storage tray TR shown in FIG. One semiconductor device is taken out from the unmeasured IC storage ST1 and transported to the measurement unit MP. The measurement unit MP is provided with a low temperature chamber (first test tank) or an ordinary high temperature chamber (second test tank), and the electrical characteristics of the semiconductor device are determined in accordance with a first test process or a second test process described later. Specific items are measured, data is processed, and non-defective / defective products are determined. Thereafter, the semiconductor device determined to be non-defective is transported to the non-defective IC storage ST2, and is packed and stored from the end in, for example, the non-defective IC storage tray TR shown in FIG. Further, the semiconductor device determined to be defective is transported to the defective product IC storage ST3, and is packed and stored in the IC storage tray TR for defective products shown in FIG.

<First test process>
Next, the first test process will be described with reference to FIGS. FIG. 13 is a process diagram illustrating the procedure of the semiconductor device test method in the first test process. 14 and 15 are schematic views for explaining aspects of the semiconductor device and the heater in the low temperature test. FIG. 16 is a graph showing the relationship between the test temperature and test time of the semiconductor device. FIG. 17 is a schematic diagram illustrating aspects of the semiconductor device and the heater in the room temperature test.

(1). Step P101 in FIG.
In the first test process, a low temperature test handler (hereinafter referred to as a low temperature handler) is used. The structure is the same as the structure of the test handler HD shown in FIG.

  First, the temperature of the atmosphere in the low temperature chamber (first test tank) CHL provided in the low temperature handler is set to the test tank temperature (first environmental temperature) and held. The test chamber internal temperature is, for example, −50 ° C.

(2). Step P102 in FIG.
Next, the semiconductor device is transferred from the unmeasured IC storage ST1 of the low temperature handler into the low temperature chamber CHL maintained at the test chamber temperature (−50 ° C.) (see FIG. 11 described above). By putting the semiconductor device into the low temperature chamber CHL, the temperature of the semiconductor device is lowered to a temperature close to the test chamber temperature (−50 ° C.), for example, about −45 ° C.

(3). Step P103 of FIG.
Next, as shown in FIG. 14, the semiconductor device SD is inserted into the socket SK1 in the low temperature chamber CHL. The socket SK1 includes a pedestal PL and a plurality of contact pins (electrodes) CP. The resin sealing body MO of the semiconductor device SD is placed on the pedestal PL, and the semiconductor device is placed on one end of the plurality of contact pins CP. Place a plurality of SD LE leads. The other ends of the plurality of contact pins CP are connected to a test apparatus installed outside the low temperature chamber CHL, and a specific item of electrical characteristics of the semiconductor device SD, for example, by the test apparatus via the plurality of contact pins CP, for example The diode characteristics of the semiconductor chip are measured.

  When the semiconductor device SD is inserted into the socket SK1 in the low temperature chamber CHL, the contact block CB1, the lead presser LB1, the heater block (heater HB, heater plate HP, and cartridge heater CH), etc. are on standby above the socket SK1. doing.

  Next, as shown in FIG. 15, the contact block CB1, the lead presser LB1, the heater block (the heater HB, the heater plate HP, and the cartridge heater CH) and the like that have been waiting above the socket SK1 are lowered integrally. Then, the plurality of leads LE of the semiconductor device SD are pressed by the lead presser LB1. Thereby, the plurality of leads LE of the semiconductor device SD are sandwiched between the lead presser LB1 and the plurality of contact pins CP, and a good electrical connection between the leads LE and the contact pins CP is obtained.

  The heater block (heater HB, heater plate HP, and cartridge heater CH) is on standby with a gap from the semiconductor device SD so as not to contact the semiconductor device SD.

(4). Step P104 in FIG.
Next, as shown in FIG. 16, when the temperature of the semiconductor device SD reaches the first test temperature, the specific item (first electrical property) of the electrical property of the semiconductor device SD is measured (low temperature measurement). The first test temperature is, for example, −40 ° C. The obtained low-temperature measurement data is temporarily stored. The temperature of the semiconductor device SD can be monitored by, for example, an internal circuit formed on the semiconductor chip.

  The heater block (heater HB, heater plate HP, and cartridge heater CH) is on standby with a gap from the semiconductor device SD so as not to contact the semiconductor device SD.

(5). Step P105 of FIG.
Next, as shown in FIG. 17, the heater block (the heater HB, the heater plate HP, and the cartridge heater CH) is lowered by the descending pressurizing unit, and the heater HB is brought into contact with the resin sealing body MO of the semiconductor device SD. . The temperature of the heater HB is controlled by the cartridge heater CH mounted on the heater plate HP, and is set to a heater temperature (second environmental temperature) higher than the test chamber internal temperature (−50 ° C.).

  By bringing the heater HB into contact with the resin sealing body MO of the semiconductor device SD, the temperature of the semiconductor device SD rises. At this time, the temperature of the atmosphere in the low temperature chamber CHL is maintained at the temperature in the test tank (−50 ° C.).

(6). Step P106 in FIG.
Next, the temperature of the semiconductor device SD is raised to the second test temperature. The second test temperature is 25 ° C., for example.

(7). Step P107 in FIG.
Next, as shown in FIG. 16 described above, when the temperature of the semiconductor device SD reaches the second test temperature, a specific item (second electrical property) of the electrical characteristics of the semiconductor device SD is measured (normal temperature measurement). ). The second test temperature is 25 ° C., for example. The obtained room temperature measurement data is temporarily stored. The temperature of the semiconductor device SD can be monitored by, for example, an internal circuit formed on the semiconductor chip.

(8). Step P108 in FIG.
The difference (drift amount) between the low-temperature measurement data obtained in the process P104 and the room-temperature measurement data obtained in the process P107 is calculated, and the difference is compared with a standard value. Selection (semiconductor device SD quality determination).

  The first test process is sequentially performed on the individual semiconductor devices SD, and the semiconductor devices SD determined to be non-defective are transported to the non-defective IC storage ST2 (see FIG. 11 described above), and sequentially from the end to the IC storage tray. Packed and stored. Since the characteristics of the individual semiconductor devices SD are clear even if the IC storage tray is packed, data is stored corresponding to the storage positions of the individual semiconductor devices SD. Therefore, data processing is not complicated.

  The semiconductor device SD determined to be defective is transferred to the defective IC storage ST3 (see FIG. 11 described above), stored in the IC storage tray, and eliminated.

<Second test process>
Next, the second test process will be described with reference to FIGS. FIG. 18 is a process diagram illustrating the procedure of the semiconductor device test method in the second test process. 19 and 20 are schematic diagrams for explaining aspects of the semiconductor device and the air cooling mechanism in the high-temperature test. FIG. 21 is a schematic diagram for explaining aspects of a semiconductor device and an air cooling mechanism in a room temperature test.

  In the second test process, specific items of electrical characteristics of the semiconductor devices determined as non-defective products in the first test process are measured.

(1). Step P201 in FIG.
In the second test process, a test handler for normal temperature (hereinafter referred to as normal temperature handler) is used. The structure is the same as the structure of the test handler HD shown in FIG. 11 described above, but the structure of the measurement unit MP is different from that of the low temperature handler.

  First, the temperature of the atmosphere in the normal temperature chamber (second test tank) CHR provided in the normal temperature handler is set to the test tank temperature (third environment temperature) and held. The test chamber internal temperature is, for example, 125 ° C.

(2). Step P202 in FIG.
Next, the semiconductor device is transferred from the unmeasured IC storage ST1 of the normal high temperature handler into the normal high temperature chamber CHR maintained at the test chamber temperature (125 ° C.) (see FIG. 11 described above). The unmeasured IC storage ST1 stores an IC storage tray in which semiconductor devices determined to be non-defective products in the first test process are stored. By putting the semiconductor device into the ordinary high temperature chamber CHR, the temperature of the semiconductor device rises to the test chamber temperature (125 ° C.).

(3). Step P203 in FIG.
Next, as shown in FIG. 19, the semiconductor device SD is inserted into the socket SK2 in the normal high temperature chamber CHR. The socket SK2 includes a pedestal PL and a plurality of contact pins (electrodes) CP. The resin sealing body MO of the semiconductor device SD is placed on the pedestal PL, and the semiconductor device is placed on one end of the plurality of contact pins CP. Place a plurality of SD LE leads. The other end portion of the plurality of contact pins CP is connected to a test apparatus installed outside the normal high temperature chamber CHR, and a specific item of electrical characteristics of the semiconductor device SD by the test apparatus via the plurality of contact pins CP, For example, the diode characteristics of a semiconductor chip are measured.

  Near the socket SK2, there is provided a nozzle NO capable of injecting gas, for example, dry air (dry air) to the semiconductor device SD by opening and closing the electromagnetic valve CV.

  Next, as shown in FIG. 20, the contact block CB2 and the lead presser LB2 that have been waiting above the socket SK2 are lowered, and the leads LE of the semiconductor device SD are pressed by the lead presser LB2. Thereby, the plurality of leads LE of the semiconductor device SD are sandwiched between the lead presser LB2 and the plurality of contact pins CP, and a good electrical connection between the leads LE and the contact pins CP is obtained.

(4). Step P204 in FIG.
Next, when the temperature of the semiconductor device SD reaches the third test temperature, a specific item (third electrical property) of the electrical property of the semiconductor device SD is measured (high temperature measurement). The third test temperature is, for example, 125 ° C. The obtained high temperature measurement data is temporarily stored. The temperature of the semiconductor device SD can be monitored by, for example, an internal circuit formed on the semiconductor chip.

(5). Step P205 in FIG.
Next, as shown in FIG. 21, gas is injected from the nozzle NO toward the semiconductor device SD to lower the temperature of the semiconductor device SD. The gas is injected by opening a solenoid valve CV installed outside the high-temperature chamber CHR by program control. The temperature of the gas is set to a temperature (fourth environmental temperature) lower than the temperature in the test chamber (125 ° C.).

  By injecting the gas onto the semiconductor device SD, the temperature of the semiconductor device SD is lowered. At this time, the temperature of the atmosphere in the normal high temperature chamber CHR is maintained at the above-mentioned test chamber temperature (125 ° C.).

(6). Step P206 in FIG.
Next, the temperature of the semiconductor device SD is lowered to the fourth test temperature. The fourth test temperature is, for example, 25 ° C.

(7). Step P207 in FIG.
Next, when the temperature of the semiconductor device SD reaches the fourth test temperature, a specific item (fourth electrical property) of the electrical property of the semiconductor device SD is measured (normal temperature measurement). The fourth test temperature is, for example, 25 ° C. The obtained room temperature measurement data is temporarily stored. The temperature of the semiconductor device SD can be monitored by, for example, an internal circuit formed on the semiconductor chip.

(8). Step P208 in FIG.
The difference (drift amount) between the high-temperature measurement data obtained in the process P204 and the room temperature measurement data obtained in the process P207 is calculated, and the difference is compared with a standard value to determine whether or not the semiconductor device SD is good or defective. Selection (semiconductor device SD quality determination).

  The second test process is sequentially performed on each semiconductor device SD in the same manner as the first test process described above, and the semiconductor device SD determined to be non-defective is stored in the non-defective IC storage ST2 (see FIG. 11 described above). It is transported and stored in the IC storage tray in order from the end. Since the characteristics of the individual semiconductor devices SD are clear even if the IC storage tray is packed, data is stored corresponding to the storage positions of the individual semiconductor devices SD. Therefore, data processing is not complicated.

  The semiconductor device SD determined to be defective is transferred to the defective IC storage ST3 (see FIG. 11 described above), stored in the IC storage tray, and eliminated.

  As described above, the plurality of semiconductor devices SD that are determined to be non-defective after the first test process and the second test process are stored in the end-filled state in the IC storage tray, so that they are not rearranged. Can be shipped in the state. In addition, since the characteristics of the individual semiconductor devices SD are obvious, the data can be shipped with the individual semiconductor devices SD.

  By the way, since the plurality of leads LE of the semiconductor device SD are sandwiched between the lead retainers LB1 and LB2 and the plurality of contact pins CP, the plating layer formed on the lower surface of the lead LE by the contact between the lower surface of the lead LE and the contact pin CP. PF may peel off. The peeling of the plating layer PF becomes a conductive foreign matter and causes a short circuit between the leads LE, or adheres to the surface of the contact pin CP and causes a contact failure between the lead LE and the contact pin CP. Problems occur in the measurement of specific items of the electrical characteristics of SD.

  However, in the first test process, a low temperature test and a normal temperature test are performed by one contact between the lead LE and the contact pin CP, and in a second test process, the contact between the lead LE and the contact pin CP is performed once. A high temperature test and a normal temperature test are conducted. Therefore, in the test method according to the embodiment, the number of contact between the lead LE and the contact pin CP is two, and the lead LE and the contact pin are more than in the first or second test method studied by the present inventors. The number of contact with CP can be reduced by one. Thereby, since peeling of the plating layer PF formed on the lower surface of the lead LE can be reduced, it is possible to reduce occurrence of problems in measurement of specific items of the electrical characteristics of the semiconductor device SD.

≪Shipping process≫
Next, the semiconductor device SD determined to be non-defective is shipped in a state of being stored in the IC storage tray in the second test process.

  In the above-described embodiment, after the first test process having the test flow of the low temperature test using the low temperature handler → the normal temperature test, the second test process having the test flow of the high temperature test using the normal temperature handler → the normal temperature test is performed. Although the test method to be performed has been described, the present invention is not limited to this, and the first test process may be performed after the second test process. Alternatively, only the first test process or only the second test process may be performed.

  In the above-described embodiment, a first test process having a test flow of a low temperature test using a low temperature handler → normal temperature test and a second test process having a test flow of high temperature test using a normal temperature handler → normal temperature test. However, a test process having other test flows is also conceivable. For example, a test flow of normal temperature test → low temperature test, normal temperature test → high temperature test, or low temperature test → high temperature test test flow can be considered.

  However, as a result of examination by the present inventors, in the test flow from the normal temperature test to the low temperature test, a considerable amount of cool air is required to bring the temperature of the semiconductor device to −40 ° C., and frost and condensation occur. There is. Further, in the test flow of normal temperature test → high temperature test and low temperature test → high temperature test, the temperature cannot be rapidly increased to a high temperature, and therefore, it takes a lot of time for measurement.

  As described above, according to the embodiment, in the inspection process of the semiconductor device SD, the plurality of semiconductor devices SD that are determined as non-defective products after the first test process and the second test process are packed in the IC storage tray. Paid in state. Therefore, it is possible to ship with the IC storage tray unloaded from the test handler HD without performing the work of refilling the shipping tray or the work of rearranging in the IC storage tray. As a result, the work efficiency is improved, and it is not necessary to perform refilling work or rearrangement work of the semiconductor devices SD, so that destruction of the semiconductor device SD in these work can be avoided.

  In addition, since the characteristics of the individual semiconductor devices SD stored in the IC storage tray are clear, the correspondence between the semiconductor devices SD and the data can be easily obtained, and complicated data processing is not required.

  In addition, the low temperature test and the normal temperature test are performed in one test process (first test process), and the normal temperature test and the high temperature test are performed in one test process (second test process), whereby the lead LE of the semiconductor device SD is performed. And the contact pin CP can be contacted twice. Thereby, in the embodiment, the number of contact between the lead LE of the semiconductor device SD and the contact pin CP can be reduced by one as compared with the case where the test of three times of the low temperature test, the normal temperature test, and the high temperature test is performed. Accordingly, it is possible to reduce the peeling of the plating layer PF formed on the lower surfaces of the plurality of leads LE of the semiconductor device SD. Therefore, it is possible to reduce the occurrence of problems in the measurement of specific items of the electrical characteristics of the semiconductor device SD. it can.

  Although the invention made by the present inventors has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

CB1, CB2 Contact block CH Cartridge heater CHL Low temperature chamber (first test tank)
CHR normal temperature chamber (second test tank)
CP contact pin (electrode)
CV Solenoid valve CW Conductive wire DP Die pad (Tab, chip mounting part)
HB Heater HD Test Handler HP Heater plate LB1, LB2 Lead retainer LE Lead (external terminal)
LF Lead frame (wiring member, wiring board, substrate)
LH hole MO resin sealing body (sealing body, package)
MP measuring unit NO nozzle PF plating layer (plating film)
PL pedestal SC semiconductor chip SD semiconductor device (semiconductor product)
SF Unit frame SK1, SK2 Socket ST1 Unmeasured IC storage (first storage)
ST2 Non-defective IC storage (second storage)
ST3 Defective product IC storage (third storage)
TR IC storage tray

Claims (17)

A semiconductor device manufacturing method including the following steps:
(A) preparing a wiring member having a first surface and a second surface opposite to the first surface;
(B) mounting a semiconductor chip on the first surface of the wiring member;
(C) electrically connecting electrode pads formed on the main surface of the semiconductor chip and external terminals of the wiring member;
(D) sealing the semiconductor chip with a sealing resin to form a sealing body;
(E) a first test step for measuring electrical characteristics of the semiconductor device completed from the step (a) to the step (d);
Further, the step (e) includes the following steps:
(E1) In the first test tank, the first electrical characteristic of the semiconductor device is measured while maintaining the temperature in the first test tank at the first environmental temperature and setting the semiconductor device to the first test temperature. The step of:
(E2) After the step (e1), the semiconductor device is heated in a state where the temperature in the first test tank is maintained at the first environmental temperature, and a second temperature higher than the first test temperature is set. Measuring a second electrical characteristic of the semiconductor device in a state set to a test temperature;
(E3) A step of comparing the first electrical characteristic and the second electrical characteristic after the step (e2) to determine whether the semiconductor device is good or bad. In the manufacturing method of the semiconductor device according to claim 1,
In the step (e2), the semiconductor device is set to the second test temperature by bringing a heater set to a second environmental temperature higher than the first environmental temperature into contact with the semiconductor device. The method of manufacturing a semiconductor device according to claim 2.
In the step (e1), the heater stands by above the semiconductor device so as not to contact the semiconductor device. The method of manufacturing a semiconductor device according to claim 2.
In the step (e2), the heater contacts the sealing body of the semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
The first ambient temperature is lower than the first test temperature. The method of manufacturing a semiconductor device according to claim 2.
The second environmental temperature is higher than the second test temperature. In the manufacturing method of the semiconductor device according to claim 1,
The first electrical characteristic is a diode characteristic of the semiconductor chip when the semiconductor device is at the first test temperature,
The second electrical characteristic is a diode characteristic of the semiconductor chip when the semiconductor device is at the second test temperature. In the manufacturing method of the semiconductor device according to claim 1,
Furthermore, the following steps are included before the step (e) or after the step (e):
(F) a second test step for measuring electrical characteristics of the semiconductor device;
Further, the step (f) includes the following steps:
(F1) In a second test tank different from the first test tank, the temperature in the second test tank is maintained at a third environmental temperature, and the semiconductor device is set at the third test temperature. Measuring a third electrical characteristic of the device;
(F2) After the step (f1), the semiconductor device is cooled in a state where the temperature in the second test tank is maintained at the third environmental temperature, and a fourth temperature lower than the third test temperature is set. Measuring a fourth electrical characteristic of the semiconductor device in a state set to a test temperature;
(F3) A step of comparing the third electrical characteristic and the fourth electrical characteristic after the step (f2) to determine pass / fail of the semiconductor device. The method of manufacturing a semiconductor device according to claim 8.
In the step (f2), the semiconductor device is set to the fourth test temperature by injecting a gas set to a fourth environmental temperature lower than the third environmental temperature to the semiconductor device. In the manufacturing method of the semiconductor device according to claim 9,
A nozzle for injecting the gas is provided in the second test tank, and the gas is not injected from the nozzle in the step (f1). In the manufacturing method of the semiconductor device according to claim 9,
A nozzle for injecting the gas is provided in the second test tank, and in the step (f2), the gas is injected from the nozzle to the sealing body of the semiconductor device. In the manufacturing method of the semiconductor device according to claim 9,
The gas is dry air. The method of manufacturing a semiconductor device according to claim 8.
When the step (f) is performed before the step (e), the step (e) is performed on the semiconductor device determined to be a non-defective product in the step (f3).
When the step (f) is performed after the step (e), the step (f) is performed on the semiconductor device determined to be a non-defective product in the step (e3). The method of manufacturing a semiconductor device according to claim 8.
The second test temperature and the fourth test temperature are the same. The method of manufacturing a semiconductor device according to claim 8.
The third electrical characteristic is a diode characteristic of the semiconductor chip when the semiconductor device is at the third test temperature,
The fourth electrical characteristic is a diode characteristic of the semiconductor chip when the semiconductor device is at the fourth test temperature. In the manufacturing method of the semiconductor device according to claim 1,
The wiring member is a lead frame. A semiconductor device manufacturing method including the following steps:
(A) preparing a wiring member having a first surface and a second surface opposite to the first surface;
(B) mounting a semiconductor chip on the first surface of the wiring member;
(C) electrically connecting electrode pads formed on the main surface of the semiconductor chip and external terminals of the wiring member;
(D) sealing the semiconductor chip with a sealing resin to form a sealing body;
(E) a test process for measuring electrical characteristics of the semiconductor device completed from the process (a) through the process (d);
Further, the step (e) includes the following steps:
(E1) In the second test tank, the temperature in the second test tank is maintained at the third environmental temperature, and the third electrical characteristic of the semiconductor device is measured with the semiconductor device set at the third test temperature. The step of:
(E2) After the step (e1), the semiconductor device is cooled in a state where the temperature in the second test tank is maintained at the third environmental temperature, and a fourth temperature lower than the third test temperature is set. Measuring a fourth electrical characteristic of the semiconductor device in a state set to a test temperature;
(E3) A step of comparing the third electrical characteristic with the fourth electrical characteristic after the step (e2) to determine whether the semiconductor device is good or bad.

Images