JP2014182812A - Data storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data storage device having a hybrid storage architecture.SOLUTION: A device and a method achieve a changing pass-through storage architecture. The device includes a control circuit configured so as to allocate data at least between a first memory hierarchy and a second memory hierarchy. The first memory hierarchy can include a solid-state memory. The second memory hierarchy can include a non-volatile memory. In one embodiment, a pass-through storage device can be achieved. The device in the embodiment can further include the control circuit, and one or more interfaces configured so as to permit communication between one or more memories, devices and systems, and any combination thereof.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a pending US application entitled “Extended Capacity SSD Using Pass Through Tiered Storage Design” filed March 15, 2013. This application claims priority to provisional patent application 61 / 790,978, which is hereby incorporated by reference in its entirety.

  The present disclosure relates to data storage devices having a hybrid storage architecture with at least two different types of data storage media.

US Provisional Patent Application No. 61 / 790,978

  Embodiments disclosed herein generally provide apparatus and methods for pass-through storage devices. Some embodiments of the apparatus may include a control circuit configured to allocate data between at least the first memory hierarchy and the second memory hierarchy. The first memory hierarchy may include non-volatile solid state memory and the second memory hierarchy may include another non-volatile memory. The apparatus can include a host interface and a data storage device interface. The host interface may be configured to communicate between the control circuit and the host device. The data storage device interface may be configured to communicate between a control circuit and a data storage device that includes a second memory hierarchy. The data storage device interface may mimic or duplicate the host interface to interface with the device as if the data storage device were directly interfaced with the host device. The control circuit may be further configured to manage the transfer of data to the host device, the first memory hierarchy, and the second memory hierarchy.

  Some embodiments provide an apparatus that includes a control circuit, an initiator interface, and a target interface. The control circuit may be configured to allocate data between at least the first memory hierarchy and the second memory hierarchy, wherein the first memory hierarchy includes a non-volatile solid state memory, and the second memory hierarchy Includes another non-volatile memory. The initiator interface can be configured to communicate between the control circuit and the initiator device. The target interface may be configured to communicate between the control circuit and the target device. At least one of the initiator interface and the target interface is configured to cause the host controller to interface with the device as if the data storage device including the non-volatile memory of the second memory hierarchy interface is interfaced with the host device. Can be imitated.

  Certain embodiments provide an apparatus that includes a control circuit configured to receive a request to write selected data from a host system. The control circuit may be further configured to cache selected data to the first non-volatile solid state memory. The control circuit may further store at least a subset of the selected data in the second non-volatile memory based on the trigger event. The apparatus may further include a host interface and a data storage interface. The host interface may be configured to communicate between the control circuit and the host system. The data storage interface may be configured to communicate between the control circuit and the second non-volatile memory. The data storage interface may mimic the host interface so that the data storage device interfaces with the device as if it were directly interfaced with the host system.

1 is a diagram of an embodiment of a pass-through storage device. FIG. 1 is a functional block diagram of an embodiment of a pass-through storage device. FIG. 1 is a functional block diagram of an embodiment of a pass-through storage device. FIG. 2 is a flowchart of an embodiment of a method for a pass-through storage device. 2 is a flowchart of an embodiment of a method for a pass-through storage device.

  In the following detailed description of the embodiments, reference is made to the accompanying drawings that form a part hereof, and which are shown by way of illustration of specific embodiments in the specification. It should be understood that features of the various embodiments described may be combined, other embodiments may be utilized, and structures may be changed without departing from the scope of the present disclosure.

  FIG. 1 is a diagram of a system 100 that includes an extended solid state device (XSSD) module 104, according to some embodiments of the present invention. The system 100 includes a host 102 and a data storage device (DSD) having a data storage medium (DSM) 106 (hereinafter referred to as DSM 106) that can be connected to the XSSD module 104. It may further include.

  Host 102 may also be referred to as a host system or host computer. The host 102 may be a desk computer, laptop computer, server, personal digital assistant (PDA), telephone, music player, another electronic device, or any combination thereof. The DSM 106 can be any of the devices listed for the host 102 or any other device that can be used to store or retrieve data, such as a hard disk drive (HDD).

  In some embodiments, the XSSD module 104 can be integrated into a bridge adapter that is configured to connect to and interface with the host 102 and the DSM 106. Alternatively or in addition to this, the XSSD module 104 can be integrated into the host 102 or DSM 106.

  The XSSD module 104 can communicate with the host 102 and the DSM 106 via one or more interfaces 108, 110 that may include connectors that allow the XSSD module 104 to be physically removed from the host 102, the DSM 106, or both. It is. Interface 108 may include hardware circuitry, logic, firmware, or any combination thereof. In some embodiments, interface 108 comprises an interface that conforms to one or more of the following standards: universal serial bus (USB), IEEE 1394, serial advanced technology attachment: SATA), external SATA (eSATA), parallel advanced technology attachment (PATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnect express (peripheral component interconnect express (PCIe), and fiber channel (FC). However, any other interface suitable to allow the XSSD module 104 to communicate with the host 102, the DSM 106, or both can be used. The XSSD module 104, the DSM 106, or both may be located inside or outside the housing of the host 102.

  Referring to FIG. 2, a functional block diagram of an exemplary embodiment of a system 200 that includes an extended solid state module device (XSSD) module 104 is shown. The XSSD module 104 may include multiple ports to allow various devices, such as one or more types of non-volatile data storage media, to be connected thereto.

  The XSSD module 104 may include an initiator interface 202 and a target interface 204. Initiator interface 202 can be configured to allow XSSD module 104 to interface with initiator 206, and target interface 204 can be configured to allow XSSD module 104 to communicate with target 208. It is possible. In some embodiments, initiator 206 may be a host device, such as a device of the type described above in connection with host 102 of FIG. Target 208 may be a data storage device such as the type described above in connection with DSM 106 of FIG. In other embodiments, the data storage device may be considered the initiator 206 and the host device may be considered the target 208.

  The XSSD module 104 can include a control circuit 210 having one or more associated processors 212. The control circuit 210 may be configured to control and execute a hybrid file system that tracks and determines the allocation of data received from or requested by the initiator 206, the target 208, or both.

  In some embodiments, the XSSD module 104 may include a solid state memory (SSM) 214 that is to be used at least in part as a cache for data that meets one or more cache criteria. SSM 214 is volatile solid state memory (VSSM) such as static random access memory (SRAM) or dynamic random access memory (DRAM), or SSM 214 is non-volatile solid state memory (NVSSM) such as flash memory. Or The following description primarily refers to NVSSM, ie flash memory 214, but it should be understood that any other type or combination of SSM 214 or NVSSM may be used.

  The XSSD module 104 may include a buffer manager 216 that can allocate data to / from one or more memory units used as the buffer memory 218. For example, the XSSD module 104 may temporarily transmit data transmitted during read and write operations to / from the initiator 206, to / from the target 208, to / from the NVSSM, or any combination thereof. There may be one or more SRAM or DRAM units 218 used for storage. The buffer memory 218 may include a command queue (not shown) that can temporarily store access operations in an execution wait state. Although the SRAM / DRAM unit 218 is shown in FIG. 2 as resident in the XSSD module 104, these may be in addition to or instead of, for example, the DRAM unit 312 shown in FIG. It should be understood that the external XSSD module 104 may be located externally.

  The XSSD module 104 communicatively couples the flash memory 214 to a first-in-first-out (FIFO) memory unit 220 and a buffer manager 216 communicatively coupled to the control circuit 210. It is further possible to include a flash protocol processor 222. The FIFO memory unit 220 may receive data from the buffer manager 216 and store this data until it is sent to the flash protocol processor 222 in a first-in first-out manner. The FIFO memory unit 220 performs a check on the data received by the FIFO memory unit 220 and corrects any error bits so that the integrity of this data is maintained. : ECC).

  The flash protocol processor 222 extracts / processes / receives data received from the FIFO memory unit 220 according to one or more communication protocols so that the flash protocol processor 222 transmits the data in a format suitable for storage in the flash memory 214. It can be a specialized processor dedicated to configuration.

  Alternatively or in addition to this, the XSSD module 104 may be configured to allow installation of one or more external flash (or any other type of NVSSM) memory unit 214. FIG. 2 illustrates the functionality of flash memory 214 that is communicatively coupled to flash protocol processor 222 via one or more flash input / output (I / O) ports 224. Although one external flash memory 214 is shown, it should be understood that multiple external flash memory units 214 can be attached to the XSSD module 104.

  The XSSD module 104 may further include a general purpose input / output (GPIO) controller 226 that can control the operation of GPIO pins (not shown) to the XSSD module 104. Moreover, the XSSD module 104 may further include one or more additional ports suitable for connecting devices used in combination with the XSSD module 104. For example, the XSSD module 104 may include one or more serial ports 228 compliant with the RS-232 standard for interfacing with a modem or similar communication device. As another example, the XSSD module 104 may include one or more diagnostic ports 230, for example, to interface with a test device that can be used to diagnose problems with the XSSD module 104.

  FIG. 3 shows a functional block diagram of another exemplary embodiment of a system 300 that includes an extended solid state device (XSSD) module 104. The XSSD module 104 may include a controller 302, which in some embodiments is an example of the control circuit 210 described above with reference to FIG.

  Controller 302 may communicate with host system 102 via an interface that includes host controller 304. The controller 302 can also communicate with a data storage device (DSD) 106 via an interface 110 that includes a controller 306 that mimics a host interface. The host interface mimic controller 306 is said to mimic that it interfaces with the XSSD module 104 as if the DSD 106 interfaces directly with the host system 102, ie, the DSD 106 interfaces with the XSSD module 104. This is because the host controller 304 can be configured to be replicated so that there can be no difference between the interface and the host system 102.

  The controller 302 may further communicate with one or more non-volatile solid state memory (NVSSM) units 308 via one or more NVSSM controllers 310. In some embodiments, the NVSSM unit 308 is a NAND flash memory unit and the NVSSM controller 310 is a NAND controller. The XSSD module 104 may further use the NVSSM unit 308 as a non-volatile cache and the DSD 106 as a permanent storage device. Thus, the XSSD module 104 is coupled to and in communication with any type of memory suitable for use as a non-volatile cache and any type of memory suitable for use as a permanent storage device. It should be understood that it can be configured as follows.

  The controller 302 may further communicate with the buffer memory unit 312 via an interface that includes the buffer memory controller 314. In some embodiments, the buffer memory controller 314 may be a component of the buffer manager 316 that is used to allocate data to / from the buffer memory 312. The buffer memory unit 312 temporarily stores data transmitted during read and write operations to / from the initiator 206, to / from the target 208, to / from the NVSSM, or any combination thereof. Can be used to The buffer memory unit 312 may include a command queue (not shown) that can temporarily store access operations in an execution wait state. Although the buffer memory unit 312 is illustrated in FIG. 3 as one DRAM unit external to the XSSD module 104, the controller 302 may include a plurality of buffer memory units 312 (one or more as described above with reference to FIG. 2). It is to be understood that the buffer memory unit 312 can reside in the XSSD module 104 in addition to or instead.

  In some embodiments, the interface between the controller 302 and each of the host system 102, DSD 106, NVSSM unit 308, and buffer memory unit 312 is one or more compliant with one or more of the following standards: Interface: Universal Serial Bus (USB), IEEE 1394, Serial Advanced Technology Attachment (SATA), External SATA (eSATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS) Peripheral Component Interconnect Express (PCIe) and Fiber Channel (FC). However, any other interface suitable to allow the controller 302 to communicate with the host system 102, DSD 106, NVSSM unit 308, buffer memory unit 312 or combinations thereof may be used.

  The controller 302 can include a command CPU 318, a conversion layer CPU 320, a command memory 322, and a data memory 324. Command data transmitted to the controller 302 can be temporarily stored in the command memory 322, while user data transmitted to the controller 302 can be temporarily stored in the data memory 324. Accordingly, the command memory 322 and the data memory 324 are effectively buffer memory units or intermediate buffer memory units (ie, buffer memory units disposed between the buffer memory unit 312 and the CPUs 318, 320) and the command CPU 318. Used to temporarily store data transmitted during read and write operations awaiting execution by conversion layer CPU 320 or both.

  According to some embodiments, the command CPU 318 receives read requests and write requests and passes user data associated with these requests between the host system 102, DSD 106, NVSSM unit 308 and buffer memory unit 312. It can be configured to assign requests. The conversion layer CPU 320 may be configured to process a software layer that manages read and write access to the NVSSM unit 308. The conversion layer CPU 320 or the protocol processor may be a flash translation layer (FTL) CPU that converts data assigned to the NAND flash memory so that the assigned data can be read by the NAND flash memory. To do.

  Some or all of the components shown in FIGS. 2-3 may be built into a single processor or controller chip, and may perform the functions and operations described herein with respect to the XSSD module 104 and the systems 200, 300. In addition, it can be configured through firmware or a circuit.

  FIG. 4 shows a flowchart of an example embodiment of a method 400 for implementing a hierarchical storage architecture. In describing the embodiment of the method 400 illustrated by FIG. 4, reference is also made to FIGS. 1-3 to clarify certain aspects of the method 400.

  At block 402, the XSSD module 104 receives a read request. For example, the host system 102 may send a read request to the XSSD module 104. However, this read request can originate from any device or system to which the XSSD module 104 is communicatively coupled.

  If, at block 404, the XSSD module 104 determines that the read request is a cache hit (ie, the requested data is stored in the cache at the time of the request), the XSSD module 104 stores the requested data in DRAM ( Alternatively, it is determined in block 405 whether the data is cached in SRAM. If the requested data is cached in the DRAM, at block 410, the XSSD module 104 retrieves this data from the DRAM and reads this data from the requestor (ie, the device or system that initiated the read request). To provide. If the requested data is not cached in the DRAM, the XSSD module 104 retrieves this data from the first memory tier non-volatile solid state memory (NVSSM) at block 406 and stores this data in the block. At 410, the read requester is provided.

  However, if at block 404 the XSSD module 104 determines that the read request is not a cache hit, the XSSD module 104 retrieves this data from the second memory tier data storage device / medium at block 408. This data is then provided to the read requester at block 410.

  In this specification, the term “first memory hierarchy” is used to distinguish a memory hierarchy containing NVSSM used as a cache from a “second memory hierarchy” containing non-volatile memory used as permanent storage. Used. However, the terms “first memory hierarchy” and “second memory hierarchy” are neither intended to limit the embodiments of the present disclosure to two memory hierarchies, and the first It is not intended to exclude one or more memory hierarchies before, during or after the memory hierarchy and the second memory hierarchy. The flash memories 214, 308 of FIGS. 2-3 illustrate NVSSMs that are included in the first memory hierarchy of some embodiments. The data storage device / medium (DSD / DSM) 106 of FIG. 3 illustrates non-volatile memory included in the second memory hierarchy of some embodiments.

  In some embodiments, the XSSD module 104 determines whether the requested data meets one or both of the cache criteria and the persistent storage criteria, respectively. If the XSSD module 104 determines that the data meets its cache criteria, the data is written to the NVSSM of the first memory hierarchy if it is not already stored there. If the XSSD module 104 determines that the data meets its permanent storage criteria, the data is written to the DSD / DSM that includes the non-volatile memory of the second memory hierarchy, if not already stored there. In some embodiments, the cache criteria, permanent storage criteria, or both are predetermined based on one or more parameters. However, in some embodiments, the cache criteria, parameters for permanent storage criteria, or both can be determined by the XSSD module 104 or updated on the fly. Parameters that may be the basis for cache criteria, permanent storage criteria, or both include, but are not limited to, age (timing), capacity (percentage of the whole), power events (eg, shutdown), detected idle time, etc. Or a combination of these are possible.

  FIG. 5 is a flowchart of another exemplary embodiment of a method 500 for implementing a hierarchical storage architecture. In describing the embodiment of the method 500 illustrated in FIG. 5, reference is also made to FIGS. 1-3 to clarify certain aspects of the method 500.

  At block 502, the XSSD module 104 receives a write request. For example, the host system 102 may send a write request to the XSSD module 104. However, this write request can originate from any device or system to which the XSSD module 104 is communicatively coupled. In some embodiments, the write request may include command data and user data buffered in volatile memory.

  In an embodiment of the method 500, at block 504, the XSSD module 104 transfers the selected data (ie, data that is to be written as a result of a received write request) to a non-volatile in the first memory hierarchy. It is possible to write to a solid state memory (NVSSM). Thus, all selected data can be cached in the first memory hierarchy NVSSM before pushing any of the selected data somewhere else.

  In some embodiments, all data passing through the XSSD module 104 may be stored in the NVSSM. For example, all write content can be provided to the NVSSM after a threshold time in the cache buffer, which can be a volatile random access memory. After this threshold time (or based on another trigger), flushing the cache to the NVSSM may require a minimum amount of write data, such as one equal to one page of flash memory. Further, the read content received by the XSSD module 104 may be stored in the NVSSM. In some embodiments, when data from a read command is stored in the XSSD module 104, at least items may be stored in the NVSSM. First, the actual data requested by the host is stored, and second, further read lookahead data can be stored in the NVSSM. For example, if the host 102 requests data from a logical block address (LBA) 100 and it is not already in the NVSSM, the XSSD module 104 retrieves this data from the DSD 106 and returns this data Is returned from the LBA 100 to the host 102. The XSSD module 104 also stores data from the LBA 100 in the NVSSM for future reads, and further read look-ahead from the LBA 101 in case a subsequent request from the host 102 is directed to the LBA 101. Store the data. Either the XSSD module 104 or the DSD 106 can initiate a read for read lookahead data, which can then be stored in the NVSSM of the XSSD module 104.

  At block 506, the XSSD module 104 determines whether a permanent storage trigger event has occurred for any or all of the selected data, or whether one or more permanent storage criteria are met, or The combination of these is determined. If yes, the XSSD module 104 moves at least a subset of the selected data to non-volatile memory in the second memory hierarchy at block 508. Permanent storage trigger events, permanent storage criteria or combinations thereof include age (timing), capacity (percentage of total), power events (eg, shutdown), detected idle time, other parameters, or combinations thereof, etc. Can be determined based on one or more of the parameters.

  FIG. 5 illustrates that the method 500 caches all selected data to the NVSSM in the first memory hierarchy before pushing any of the selected data somewhere else. Although illustrated, in certain embodiments, only data that satisfies a predetermined or on-the-fly cache criterion, such as the cache criterion described above with reference to FIG. 4, may be cached.

  In some embodiments with such examples of apparatus and methods described above with reference to FIGS. 1-5, the hybrid data storage system includes a host system or data storage device (eg, a hard disk drive (HDD)). It can be implemented with little or no modification. Further, the XSSD module 104 may selectively allocate storage space among multiple devices used as non-volatile caches or as addressable storage space. In some examples, a non-volatile solid state memory (NVSSM) is used as a non-volatile cache for data that is input or output or data that is pinned to the cache so that the read access time is faster than the HDD. On the other hand, the HDD can be used as a permanent storage device. In one embodiment, the total storage capacity reported to the host system may be the HDD capacity plus the NVSSM capacity. Further, in some embodiments, multiple storage devices / media may function as backups to each other, for example, an HDD may be a backup to NVSSM and vice versa.

  The XSSD module 104 may be at least partially integrated into the host system so that data can be transmitted between the host system, the first memory hierarchy and the second memory hierarchy. In addition or alternatively, the XSSD module 104 can transmit data between the host system, the first memory tier, and the second memory tier so that data can be transmitted between the second memory tier and the second memory tier. It may be at least partially integrated into a data storage device including non-volatile memory. In addition or alternatively, the XSSD module 104 may allow the host to send data between the host system, the first memory hierarchy, and the second memory hierarchy. It may be at least partially integrated into a bridge adapter configured to allow coupling to the system and a data storage device that includes a non-volatile memory of the second memory hierarchy.

  According to various embodiments, the methods described herein may be implemented as one or more software programs running on a controller, such as a computer processor or controller 206. According to another embodiment, the methods described herein may be implemented as one or more software programs running on a computing device such as a personal computer using a disk drive. Dedicated hardware implementations, including but not limited to application specific integrated circuits, programmable logic arrays, and other hardware devices are similarly implemented to implement the methods described herein. Can be built. Further, the methods described herein may be implemented as a computer readable medium containing instructions that, when executed, cause a processor to perform the method.

  The examples of embodiments described herein are intended to give a general understanding of the structure of the various embodiments. The examples are not intended to serve as a complete description of all of the elements and features of apparatus and systems that utilize the structures or methods described herein. Many other embodiments will be apparent to those of skill in the art upon reviewing the disclosure. Other embodiments may be utilized and derived from the disclosure so that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. Moreover, while specific embodiments have been illustrated and described herein, any subsequent arrangement designed to achieve the same or similar purpose can be substituted for the specific embodiments shown. Should be understood.

  This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the description. Further, the examples are merely representative and may not be drawn to scale. Certain parts within the scope of the examples may be exaggerated while other parts may be reduced. Accordingly, the disclosure and drawings are to be regarded as illustrative rather than restrictive.

  100 systems, 102 hosts, 104 XSSD modules, 106 data storage media, 108, 110 interfaces.

Claims (20)

A device,
And a control circuit configured to allocate data between at least a first memory hierarchy and a second memory hierarchy, wherein the first memory hierarchy includes a non-volatile solid state memory, and the second memory The hierarchy includes another non-volatile memory,
The device is
A host interface configured to communicate between the control circuit and a host device;
The data storage device is configured to communicate between the control circuit and a data storage device including the second memory hierarchy, wherein the data storage device is directly interfaced with the host device. A data storage device interface that mimics the host interface to interface with the device;
The apparatus, wherein the control circuit is further configured to manage transfer of data to the host device, the first memory hierarchy, and the second memory hierarchy.   The control circuit of claim 1, wherein the control circuit is integrated with the host device so as to be able to transmit data between the host device, the first memory hierarchy, and the second memory hierarchy. The device described.   The control circuit includes the non-volatile memory of the second memory hierarchy so that data can be transmitted between the host device, the first memory hierarchy, and the second memory hierarchy. The apparatus of claim 1, wherein the apparatus is integrated with the data storage device.   The apparatus of claim 1, comprising an individually removable hardware device that can be disconnected from the host interface and the data storage device, comprising a non-volatile solid state memory configured as a buffer.   Implementing a protocol conversion layer for converting the allocated data so that when the data is allocated to the non-volatile solid state memory, the allocated data is in a format readable by the non-volatile solid state memory. 5. The apparatus of claim 4, further comprising a non-volatile solid state memory protocol processor configured in A buffer manager configured to communicate with the control circuit and allocate data to one or more volatile memory units configured as buffers;
6. The apparatus of claim 5, further comprising a first in first out (FIFO) memory unit configured to store data received from the buffer manager and send the received data to the non-volatile solid state memory protocol processor. . The non-volatile solid state memory is a flash memory, and the non-volatile memory is a magnetic data storage medium;
The apparatus of claim 5, further comprising a buffer manager configured to communicate with the control circuit and allocate data to one or more volatile memory units configured as buffers. The first memory hierarchy;
An output from the non-volatile solid state memory protocol processor;
The apparatus of claim 5, wherein the output is configured to couple the non-volatile solid state memory protocol processor to the non-volatile solid state memory. A non-volatile solid state memory interface configured to communicate between the non-volatile solid state memory protocol processor and the non-volatile solid state memory;
6. The apparatus of claim 5, wherein the first memory hierarchy is integrated into one or more individually removable hardware devices that can be disconnected from the apparatus. The control circuit includes:
Caching data that satisfies one or more cache criteria to the non-volatile solid state memory of the first memory hierarchy, and at least data that satisfies one or more storage criteria for the second memory hierarchy The apparatus of claim 1, further configured to store partly in the non-volatile memory of the second tier as storage space.   11. The one or more cache criteria and the one or more storage criteria are determined based on one or more parameters selected from the group consisting of timing, capacity, power event, and idle time. The device described. A device,
And a control circuit configured to allocate data between at least a first memory hierarchy and a second memory hierarchy, wherein the first memory hierarchy includes a non-volatile solid state memory, and the second memory The hierarchy includes another non-volatile memory,
The device is
An initiator interface configured to communicate between the control circuit and an initiator device;
A target interface configured to communicate between the control circuit and a target device;
At least one of the initiator interface and the target interface is configured to interface with the apparatus as if a data storage device including the non-volatile memory of the second memory hierarchy is interfaced with the host device. Duplicate the interface
The apparatus, wherein the control circuit is further configured to manage transfer of data to the host device, the first memory hierarchy, and the second memory hierarchy.   The apparatus of claim 12, wherein the initiator interface and the target interface each conform to an interface standard.   The control circuit is configured to cache the data in the nonvolatile solid state memory of the first memory hierarchy before storing all the data in the nonvolatile memory of the second memory hierarchy. The apparatus according to claim 12.   The apparatus of claim 14, further comprising a buffer manager configured to communicate with the control circuit and to allocate data to one or more volatile memory units configured as buffers.   Implementing a protocol conversion layer for converting the allocated data so that when the data is allocated to the non-volatile solid state memory, the allocated data is in a format readable by the non-volatile solid state memory. 16. The apparatus of claim 15, further comprising a non-volatile solid state memory protocol processor configured in A non-volatile solid state memory interface configured to communicate between the non-volatile solid state memory protocol processor and the non-volatile solid state memory;
The apparatus of claim 16, further comprising: the buffer manager and a volatile memory interface configured to communicate between one or more volatile memory units configured as a buffer. A device,
Equipped with a control circuit,
The control circuit includes:
Receives a request from the host system to write the selected data,
Caching the selected data into a first non-volatile solid state memory;
Configured to store at least a subset of the selected data to a second non-volatile memory based on a trigger event;
The device is
A host interface configured to communicate between the control circuit and the host system;
The data storage device is configured to communicate between the control circuit and the second non-volatile memory, and the data storage device interfaces with the apparatus as if the data storage device is directly interfaced with the host system. And a data storage interface that mimics the host interface.   The selected data is transmitted to a protocol processor before being cached in the first non-volatile solid state memory such that the selected data is in a format readable by the first non-volatile solid state memory. The apparatus of claim 18, converted by   The apparatus of claim 19, further comprising a non-volatile solid state memory interface configured to communicate between the protocol processor and the first non-volatile solid state memory.