JP2014239424A - Semiconductor device - Google Patents

Abstract

To prevent a malfunction of a power device. Or suppress the increase in manufacturing cost. In a semiconductor device for driving a power device for power supply, a buffer circuit and a level shift circuit are configured by transistors having the same polarity. Further, a capacitive element is provided in the level shift circuit, and a signal for boosting is supplied to the capacitive element, and a signal is boosted using capacitive coupling in the capacitive element. Therefore, a transistor included in the semiconductor device can be formed using a unipolar transistor. Further, a capacitor can be provided between a wiring for supplying a potential for boosting a signal for driving the power transistor by the level shift circuit and a wiring for supplying a low power supply potential, thereby boosting the signal. . [Selection] Figure 1

Description

The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device that functions as a drive circuit for driving a power device for supplying power.

A power device is an element used to drive a load such as a motor. The power device can be controlled to intermittently supply a large current to the load by a switching operation.

An example of a power device is a power transistor such as an IGBT (Insulated Gate Bipolar Transistor). The power transistor has a larger gate capacitance than other transistors.

The power transistor is driven by PWM (Pulse Width Modulation) control. The PWM control is performed by a PWM signal output from a microcomputer or the like. The PWM signal has a small voltage for directly driving a power transistor having a large gate capacity. Therefore, the PWM signal needs to be converted into a high voltage signal and given to the power transistor.

A drive circuit for converting a PWM signal into a high voltage signal is composed of a transistor using silicon. For example, Patent Document 1 discloses a configuration of a semiconductor device in which an n-channel transistor and a p-channel transistor are provided over a silicon substrate to control on / off of the IGBT.

JP 2004-328329 A

As described above, the semiconductor device described in Patent Document 1 includes an n-channel transistor and a p-channel transistor that are formed using silicon transistors as a drive circuit for converting a PWM signal into a high-voltage signal. In this configuration, a transistor is used.

In the case where a driver circuit is formed using complementary transistors, the number of photomasks for separately forming n-channel transistors and p-channel transistors increases. Therefore, the manufacturing cost increases. In order to suppress the increase in the manufacturing cost, there can be a configuration in which the complementary transistors constituting the drive circuit are configured with unipolar transistors.

When a driving circuit that converts a PWM signal into a high voltage signal with a unipolar transistor is used, a high voltage is used for signal conversion, which may cause dielectric breakdown of the transistor. When the transistor is destroyed, a driving circuit including the transistor malfunctions.

Thus, an object of one embodiment of the present invention is to prevent a malfunction of a power device. Another object of one embodiment of the present invention is to suppress an increase in manufacturing cost.

Note that the description of a plurality of tasks does not disturb each other's existence. One embodiment of the present invention does not have to solve all of these problems. Problems other than those listed will be apparent from the description of the specification, drawings, claims, and the like, and these problems may be a problem of one embodiment of the present invention.

According to one embodiment of the present invention, in a semiconductor device which is a driver circuit for driving a power device for supplying power, the buffer circuit and the level shift circuit are formed using transistors having the same polarity. Further, according to one embodiment of the present invention, a capacitor is provided in the level shift circuit, a signal for boosting is supplied to the capacitor, and a signal is boosted using capacitive coupling in the capacitor.

In the structure according to one embodiment of the present invention, the transistor provided in the driver circuit for driving the power device for supplying power can be a unipolar transistor. Further, according to the structure of one embodiment of the present invention, a capacitor is provided between a wiring for applying a potential for boosting a signal for driving a power transistor by a level shift circuit and a wiring for supplying a low power supply potential, thereby boosting the signal. It can be set as the structure which performs.

According to one embodiment of the present invention, a first buffer circuit that converts a first signal into a second signal, a level shift circuit that converts a second signal into a third signal, and a third signal as a fourth signal A level shift circuit, and a first buffer, and a second buffer circuit that converts the first potential to the first signal and a third buffer circuit that outputs the first potential or the second potential according to the fourth signal. The transistors included in the circuit to the third buffer circuit are transistors having the same polarity, and the second signal is supplied to the capacitor included in the level shift circuit and converted into a third signal using capacitive coupling. It is a semiconductor device.

In one embodiment of the present invention, the first buffer circuit converts the first signal into a second signal having a higher potential than the potential of the first signal. A semiconductor device that converts the above signal into a fourth signal having a higher potential than the potential of the third signal is preferable.

In one embodiment of the present invention, the level shift circuit is preferably a semiconductor device that converts a second signal into a third signal having a higher potential than the potential of the second signal.

In one embodiment of the present invention, the semiconductor layer included in the transistor is preferably a semiconductor device including an oxide semiconductor.

In one embodiment of the present invention, a semiconductor device in which the wiring that supplies a low power supply potential to the first buffer circuit is different from the wiring that supplies the low power supply potential to the second buffer circuit and the third buffer circuit is preferable. .

In one embodiment of the present invention, the level shift circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor, and the first terminal of the first transistor and the first transistor A first terminal of the second transistor is electrically connected to a wiring for applying a second potential, and one electrode of the first capacitor is connected to the second terminal of the first transistor, the gate of the second transistor, and The second buffer circuit is electrically connected, and one electrode of the second capacitor is electrically connected to the second terminal of the second transistor, the gate of the first transistor, and the second buffer circuit. A semiconductor device in which the second signal is supplied to the other electrode of the first capacitor and the inverted signal of the second signal is supplied to the other electrode of the second capacitor is preferable.

One embodiment of the present invention has a structure in which a signal is supplied to a capacitor in a level shift circuit using capacitive coupling. With this configuration, a high voltage is not directly applied between the source and drain of the transistor in the level shift circuit, and the dielectric breakdown of the transistor can be eliminated. Therefore, the drive circuit for driving the power device can be operated in a normal state, and malfunction can be prevented. Further, the through current flowing in the level shift circuit can be eliminated, and the power consumption can be reduced.

Further, according to one embodiment of the present invention, the transistor included in the buffer circuit and the level shift circuit is configured as a unipolar transistor. With this structure, a transistor provided in a driver circuit for driving a power device for power supply can be formed using a semiconductor material such as an oxide semiconductor that has excellent electrical characteristics at high temperatures. Therefore, malfunction of the power device can be prevented. Moreover, the increase in manufacturing cost can be suppressed.

FIG. 11 is a block diagram illustrating a structure of a semiconductor device. FIG. 6 is a circuit diagram illustrating a configuration of a semiconductor device. FIG. 6 is a circuit diagram illustrating a configuration of a semiconductor device. FIG. 6 is a timing chart for explaining the operation of the semiconductor device. 6A and 6B are a circuit diagram and a block diagram illustrating a structure of a semiconductor device. FIG. 6 is a circuit diagram illustrating a configuration of a semiconductor device. FIG. 14 is a cross-sectional view of a transistor. FIG. 14 is a cross-sectional view of a transistor. FIG. 14 is a cross-sectional view of a transistor. 10A and 10B are a flowchart and a perspective schematic view illustrating a manufacturing process of a semiconductor device. Electronic equipment using semiconductor devices.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments. Note that in the structures of the invention described below, the same portions are denoted by the same reference numerals in different drawings.

In the drawings, the size, the thickness of layers, or regions are exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. It is something that can be done.

Here, since the source and the drain vary depending on the structure or operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, a portion functioning as a source and a portion functioning as a drain are not referred to as a source or a drain, one of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. There is a case.

Note that the ordinal numbers “first”, “second”, and “third” used in this specification are added to avoid confusion between components, and are not limited in number. To do.

Note that in this specification, A and B are connected to each other, including A and B being directly connected, as well as those being electrically connected. Here, A and B are electrically connected. When there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. It says that.

Note that in this specification, terms such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

Note that the layout of each circuit block in the drawing specifies the positional relationship for the sake of explanation. Even if the drawing shows that different functions are realized in different circuit blocks, the same circuit or region is not used in an actual circuit or region. In some cases, different functions are provided in the same area. In addition, the function of each circuit block in the drawing is to specify the function for explanation. Even if the function is shown as one circuit block, in an actual circuit or region, processing performed by one circuit block is performed by a plurality of circuit blocks. In some cases, it is provided.

Note that in this specification, the voltage often indicates a potential difference between a certain potential and a reference potential (eg, a ground potential). Thus, voltage, potential, and potential difference can be referred to as potential, voltage, and voltage difference, respectively. The voltage refers to a potential difference between two points, and the potential refers to electrostatic energy (electric potential energy) possessed by a unit charge in an electrostatic field at a certain point.

In this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

(Embodiment 1)
In this embodiment, a circuit configuration and operation of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS.

Note that a semiconductor device refers to a circuit including a semiconductor element (a transistor, a diode, or the like) and a device including the circuit. In addition, it refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including the integrated circuit, a display device, a light-emitting device, a lighting device, an electronic device, and the like are all semiconductor devices.

FIG. 1 is a block diagram of a semiconductor device. A semiconductor device 100 illustrated in FIG. 1 includes a buffer circuit 101 (also referred to as a first buffer circuit, expressed as 1st Buffer in the diagram), a level shift circuit 102 (expressed as HV Level Shift in the diagram), and a buffer circuit 103 (first buffer circuit). 2, which is also referred to as 2nd Buffer in the drawing), and a buffer circuit 104 (also referred to as third buffer circuit, which is referred to as 3rd Buffer in the drawing).

In the semiconductor device 100 described in this embodiment, the buffer circuit 101, the buffer circuit 103, the buffer circuit 104, and the level shift circuit 102 are formed using transistors having the same polarity. Therefore, in the semiconductor device 100, a transistor provided in the semiconductor device 100 can be formed using a unipolar transistor.

Further, the semiconductor device 100 has a configuration in which a capacitive element is provided in the level shift circuit 102, a signal for boosting is given to the capacitive element, and a signal is boosted using capacitive coupling in the capacitive element. In this configuration, the voltage applied between the source and drain of the transistor in the level shift circuit 102 can be made smaller than the voltage applied to the capacitor in the level shift circuit 102, so that the breakdown of the transistor can be suppressed.

Next, each circuit included in the semiconductor device 100 will be described.

The buffer circuit 101 is a circuit having a function of converting a PWM signal output from a microcomputer or the like into a signal capable of operating the level shift circuit 102 into a signal having a boosting and / or charge supply capability and outputting the signal. A signal input to the buffer circuit 101 is a PWM signal output from a microcomputer or the like via the terminal IN_H and the terminal IN_L. A signal output from the buffer circuit 101 is a signal input to the level shift circuit 102.

In FIG. 1, a PWM signal output from a microcomputer or the like is a first signal (denoted as 1st Signal in the figure). In FIG. 1, a signal output from the buffer circuit 101 and input to the level shift circuit 102 is a second signal (denoted as 2nd Signal in the figure). Note that the PWM signal is boosted by the buffer circuit 101, the level shift circuit 102, and the buffer circuit 103, and is a signal for alternately turning on the transistor 121 and the transistor 122 included in the buffer circuit 104.

In FIG. 1, two signals input from the terminal IN_H and the terminal IN_L are shown as an example of the PWM signal, but the present invention is not limited to this. For example, three or more PWM signals may be input to the buffer circuit 101. Note that the two signals input from the terminal IN_H and the terminal IN_L are preferably signals inverted from each other.

The level shift circuit 102 includes a transistor 111, a transistor 112, a capacitor 113, and a capacitor 114. The transistors 111 and 112 are connected to a wiring to which a voltage V2 for driving the power transistor is applied.

The level shift circuit 102 outputs a voltage obtained by boosting the voltage of the PWM signal output from the microcomputer or the like to the voltage for driving the power transistor based on the second signal output from the buffer circuit 101. It is a circuit which has. A signal input to the level shift circuit 102 is a signal output from the buffer circuit 101 and supplied to the capacitor 113 and the capacitor 114. A signal output from the buffer circuit 101 is a signal input to the level shift circuit 102.

The second signal is supplied to the level shift circuit 102 by capacitive coupling between the capacitor 113 and the capacitor 114. The second signal given to the level shift circuit 102 by capacitive coupling is further boosted by the voltage V 2 for driving the power transistor, and is output to the buffer circuit 103. In FIG. 1, the signal output from the level shift circuit 102 and input to the buffer circuit 103 is a third signal (denoted as 3rd Signal in the figure). Note that the second signal and the third signal are signals originally supplied to the terminal IN_H and the terminal IN_L, and two signals are supplied to the two wirings in FIG.

The transistors 111 and 112 are transistors that function as switches. Further, the transistor 111 and the transistor 112 are transistors having the same polarity. As an example, in FIG. 1, the transistors 111 and 112 are illustrated as n-channel transistors.

The transistor 111 and the transistor 112 are operated at a timing when one of the second signals input to the capacitor 113 and the capacitor 114 becomes the H level, and the transistor whose gate is connected to the capacitor having the H level is turned on. State. On the other hand, at the timing when the other of the second signals input to the capacitor 113 and the capacitor 114 becomes the L level, the transistor whose gate is connected to the capacitor having the L level is turned off. For example, when the second signal input to the capacitor 113 is set to H level, the transistor 112 is turned on, and when the second signal input to the capacitor 114 is set to L level, the transistor 111 is turned off. Further, when the second signal input to the capacitor 113 is set to L level, the transistor 112 is turned off, and when the second signal input to the capacitor 114 is set to H level, the transistor 111 is turned on.

In the period in which the transistor 111 is in a conductive state, the voltage V2 is applied to a node where the capacitor 113 connected to one of the source and the drain of the transistor 111 and the gate of the transistor 112 in a non-conductive state are connected to each other. A current flows from the connected wiring, and the node is charged (first operation).

On the other hand, the transistor 112 operates in reverse to the transistor 111. That is, during the period in which the transistor 112 is in a conductive state, the voltage V2 is applied to a node where the capacitor 114 connected to one of the source and the drain of the transistor 112 and the gate of the transistor 111 in a non-conductive state are connected to each other. Current flows from the given wiring, and the node is charged (first operation).

Next, in a period in which the transistor 111 is off, a node where the capacitor 113 connected to one of the source and the drain of the transistor 111 and the gate of the transistor 112 are connected to each other is electrically floating (floating). Become. At this time, an H level is given to the capacitor 113. Then, the potential of the node in an electrically floating state is further increased by capacitive coupling. The signal boosted by this capacitive coupling is output to the buffer circuit 103 as a third signal (second operation).

On the other hand, in a period in which the transistor 112 is off, the node where the capacitor 114 connected to one of the source and the drain of the transistor 112 and the gate of the transistor 111 are connected to each other is electrically floating (floating). Become. At this time, an H level is applied to the capacitor 114. Then, the potential of the node in an electrically floating state is further increased by capacitive coupling. The signal boosted by this capacitive coupling is output to the buffer circuit 103 as a third signal (second operation).

By repeating the first operation and the second operation described above, the level shift circuit 102 can output a third signal obtained by boosting the second signal.

Note that the capacitor 113 and the capacitor 114 are desirably elements that do not break down due to a high voltage. The capacitances of the capacitor 113 and the capacitor 114 are preferably 10 times or more larger than the gate capacitance of the buffer circuit 103. Note that in the case where the capacitances of the capacitor 113 and the capacitor 114 are increased, the second signal is preferably a signal whose charge supply capability is increased by the buffer circuit 101.

Note that the capacitor 113 and the capacitor 114 may be provided over a substrate different from the substrate over which the transistor included in the semiconductor device is formed in order to increase capacitance.

The capacitances of the capacitive element 113 and the capacitive element 114 may be the same or different.

The structure of the level shift circuit 102 shown in FIG. 1 has a structure in which the second signal is supplied to the capacitor 113 and the capacitor 114 using capacitive coupling. With this structure, a high voltage is not directly applied between the source and the drain of the transistor 111 and the transistor 112, and dielectric breakdown of the transistor can be eliminated. Therefore, the drive circuit for driving the power transistor can be operated in a normal state, and malfunction can be prevented. Further, the through current flowing in the level shift circuit 102 can be eliminated, and the power consumption can be reduced.

The buffer circuit 103 has a function of converting the third signal output from the level shift circuit 102 into a signal capable of operating the fourth buffer circuit 104 into a signal having a boosted and / or charge supply capability and outputting the signal. It is a circuit having. A signal input to the buffer circuit 103 is a signal supplied to the gate of a transistor included in the buffer circuit 103. A signal output from the buffer circuit 103 is a signal input to the buffer circuit 104.

In FIG. 1, the signal given to the gate of the transistor included in the buffer circuit 103 is a third signal. In FIG. 1, a signal output from the buffer circuit 103 and input to the buffer circuit 104 is a fourth signal (denoted as 4th Signal in the figure). Note that the fourth signal is originally a signal given to the terminal IN_H and the terminal IN_L, and two signals are given to two wirings in FIG.

In FIG. 1, the buffer circuit 103 is provided between the level shift circuit 102 and the buffer circuit 104, but a buffer circuit may be further added. Alternatively, a delay circuit such as a flip-flop may be added.

The buffer circuit 104 includes a transistor 121 and a transistor 122. The transistor 121 is connected to a wiring to which a voltage V1 for driving the power transistor is applied. The transistor 122 is connected to a wiring to which a voltage V2 for driving the power transistor is applied. A signal output from the buffer circuit 104 is supplied to an external power transistor (not shown) through a terminal OUT.

The voltage V1 is a voltage for switching the power transistor connected to the terminal OUT to a conductive state. The voltage V2 is a voltage for switching the power transistor connected to the terminal OUT to a non-conductive state. The buffer circuit 104 switches the voltage output from the terminal OUT to the voltage V1 or the voltage V2 and outputs the voltage to control switching of the power transistor connected to the terminal OUT. Note that the voltage V1 is sometimes referred to as a first voltage. Further, the voltage V2 may be referred to as a second voltage. Note that the voltage V1 and the voltage V2 are preferably voltages generated by boosting using a bootstrap circuit based on the high power supply potential VDD. Further, the voltage V1 and the voltage V2 may be voltages generated by stepping down the high power supply potential VDD when the high power supply potential VDD is a higher voltage. Note that the voltage V1 and the voltage V2 may be directly applied from the outside. The voltage V1 is higher than the voltage V2.

The buffer circuit 104 is a circuit having a function of outputting the voltage V1 or the voltage V2 for driving the power transistor based on the fourth signal output from the buffer circuit 103. A signal input to the buffer circuit 104 is a signal supplied to the gate of the transistor 121 or the transistor 122 included in the buffer circuit 104. The signal output from the buffer circuit 104 is a signal for driving an externally provided power transistor output via the terminal OUT. Note that the fourth signal given to the gates of the transistor 121 and the transistor 122 is originally a signal given to the terminal IN_H and the terminal IN_L, as described above. The fourth signal turns on the transistors 121 and 122 alternately. For this reason, the signal output from the terminal OUT is a signal output by switching between the voltage V1 and the voltage V2.

The semiconductor device 100 described above has a configuration in which a signal is supplied to the capacitive element 113 and the capacitive element 114 in the level shift circuit 102 using capacitive coupling. With this structure, a high voltage is not directly applied between the source and the drain of the transistor 111 and the transistor 112, and dielectric breakdown of the transistor can be eliminated. Therefore, the drive circuit for driving the power device can be operated in a normal state, and malfunction can be prevented. Further, the through current flowing in the level shift circuit 102 can be eliminated, and the power consumption can be reduced.

Next, a specific circuit configuration and operation of the semiconductor device 100 illustrated in FIG. 1 will be described with reference to FIGS.

FIG. 2 is a diagram illustrating a specific example of a circuit configuration of the block diagram of the semiconductor device illustrated in FIG.

The buffer circuit 101 illustrated in FIG. 2 includes an inverter circuit 131 and an inverter circuit 132 that serve as buffers for PWM signals supplied to the terminal IN_H and the terminal IN_L. The inverter circuit 131 and the inverter circuit 132 are supplied with a power supply voltage by a wiring to which the voltage V3 is applied and a wiring to which the ground potential GND is applied. The inverter circuit 131 and the inverter circuit 132 include transistors having the same polarity as the transistors 111 and 112 included in the level shift circuit 102.

Here, FIG. 3A illustrates an example of a circuit configuration of the inverter circuit 131 and the inverter circuit 132 each including an n-channel transistor as a transistor having the same polarity.

The inverter circuit 131 (or the inverter circuit 132) illustrated in FIG. 3A includes a transistor 151, a transistor 152, a transistor 153, a transistor 154, and a capacitor 155. The transistor 151, the transistor 152, the transistor 153, and the transistor 154 are illustrated as n-channel transistors similarly to the transistors 111 and 112 in FIGS.

Note that the voltage V3 is a voltage for boosting the level shift circuit 102 by charge and discharge of charge in the capacitor 113 and the capacitor 114. Note that the wiring for applying the voltage V3 preferably has high charge supply capability so that charge and discharge of the capacitor 113 and the capacitor 114 can be performed at high speed. The voltage V3 is sometimes referred to as a third voltage. Note that the voltage V3 is preferably a voltage generated by boosting using a bootstrap circuit based on the high power supply potential VDD. Further, the voltage V3 may be a voltage generated by stepping down the high power supply potential VDD when the high power supply potential VDD is a higher voltage. The voltage V3 may be a voltage directly applied from the outside. The voltage V3 is smaller than the voltage V1 and the voltage V2.

In the transistor 151 and the transistor 152, one of a source terminal and a drain terminal is connected to a wiring to which the voltage V3 is applied. In the transistors 153 and 154, one of a source terminal and a drain terminal is connected to a wiring to which a ground potential GND is supplied. The capacitor 155 is provided between the gate of the transistor 152 and the other terminal of the source and the drain. The inverter circuit 131 (or the inverter circuit 132) illustrated in FIG. 3A is a circuit that can output a signal obtained by inverting the logic of the first signal as the second signal.

Note that the inverter circuit 131 (or the inverter circuit 132) illustrated in FIG. 3A is electrically arranged in series as illustrated in FIG. 3B, and the logic of the first signal is inverted again to the original logic. It may be a circuit that can output the second signal.

Further, the level shift circuit 102 shown in FIG. 2 has the same configuration as the level shift circuit 102 described in FIG. In FIG. 2, as in FIG. 1, the transistor 111 and the transistor 112 included in the level shift circuit 102 are illustrated as n-channel transistors.

In addition, the buffer circuit 103 illustrated in FIG. 2 includes a transistor 141, a transistor 142, a transistor 143, and a transistor 144. The buffer circuit 103 is connected to a wiring to which the voltage V4 is applied and a wiring to which the voltage V2 is applied. The buffer circuit 103 outputs a signal applied to the gates of the transistor 121 and the transistor 122 of the buffer circuit 104 as a fourth signal that is switched between the voltage V4 and the voltage V2 based on the third signal. Note that the transistor 141, the transistor 142, the transistor 143, and the transistor 144 are illustrated as n-channel transistors similarly to the transistors 111 and 112 in FIGS.

Note that the voltage V4 is a voltage for further boosting the third signal in order to surely turn on the transistor 121 and the transistor 122. For example, when the third signal output through the transistor 111 and the transistor 112 is a signal having a voltage that is reduced by the threshold voltage of the transistor, this boosting can be performed without reliably turning on the transistor 121 and the transistor 122. It is for prevention. The voltage V4 is sometimes referred to as a fourth voltage. The voltage V4 is preferably a voltage generated by boosting using a bootstrap circuit based on the high power supply potential VDD. Further, the voltage V4 may be a voltage generated by stepping down the high power supply potential VDD when the high power supply potential VDD is a higher voltage. Voltage V4 may be a voltage directly applied from the outside. The voltage V4 is the same as the voltage V1 or higher than the voltage V1.

Assuming that the PWM signal applied to the terminal IN_H shown in FIG. 2 is the PWM signal S_H and the PWM signal applied to the terminal IN_L is the PWM signal S_L, the output signal applied to the terminal OUT is the output signal S_OUT. The PWM signal S_H, the PWM signal S_L, and the output signal S_OUT can be expressed as shown in the timing chart of FIG. Note that the PWM signal S_H, the PWM signal S_L, and the output signal S_OUT show the same amplitude voltage, but the amplitude voltage of the output signal S_OUT is actually smaller than the amplitude voltage of the PWM signal S_H and the PWM signal S_L. Note that the potential at which the PWM signal S_H and the PWM signal S_L are amplified is boosted by the buffer circuit 101, the level shift circuit 102, and the buffer circuit 103, and the conduction state or non-conduction state of the transistor 121 and the transistor 122 included in the buffer circuit 104 is determined. The voltage to be controlled. The semiconductor device 100 can output an output signal S_OUT that outputs either the voltage V1 or the voltage V2 in accordance with the boosted PWM signal S_H and PWM signal S_L.

In the structure of the semiconductor device 100 illustrated in FIG. 2, the voltage of the wiring that supplies the low power supply potential of the buffer circuit 101 and the voltage of the wiring that supplies the low power supply potential of the buffer circuit 103 and the buffer circuit 104 are different voltages. can do. Specifically, the voltage of the wiring that supplies the low power supply potential of the buffer circuit 101 can be the ground potential GND, and the voltage of the wiring that supplies the low power supply potential of the buffer circuit 103 and the buffer circuit 104 can be the voltage V2. Therefore, when a current due to a reactance component accumulated in the wiring flows in the semiconductor device 100, malfunction caused by flowing to the terminals IN_H and IN_L to which the PWM signal is supplied can be reduced.

The transistors 111 and 112, the transistors 121 and 122, the transistors 141 to 144, and the transistors 151 to 154 described with reference to FIGS. 2 and 3 are all n-channel transistors. That is, the buffer circuit 101, the buffer circuit 103, the buffer circuit 104, and the level shift circuit 102 included in the semiconductor device can be formed using unipolar transistors.

By configuring a semiconductor device with unipolar transistors, the number of photomasks for separately creating n-channel transistors and p-channel transistors is reduced compared to the case where a driver circuit is configured with complementary transistors. can do. Therefore, the manufacturing cost can be reduced by adopting the configuration of the present invention.

By simply replacing a transistor constituting a semiconductor device with a unipolar transistor, when a drive circuit for converting a PWM signal into a high voltage signal is used, a high voltage is used for signal conversion. There is a risk of destruction. On the other hand, the semiconductor device having the structure of this embodiment has a structure in which a signal is supplied to the capacitor 113 and the capacitor 114 in the level shift circuit 102 using capacitive coupling. With this structure, a high voltage is not directly applied between the source and the drain of the transistor 111 and the transistor 112, and dielectric breakdown of the transistor can be eliminated. Therefore, the drive circuit for driving the power device can be operated in a normal state, and malfunction can be prevented.

Further, in the semiconductor device having the structure of this embodiment, a semiconductor device can be formed using a semiconductor material other than silicon for the semiconductor layer by forming the semiconductor device using a unipolar transistor. As an example, a transistor can be formed using an oxide semiconductor for a semiconductor layer.

An oxide semiconductor has an energy gap of 3.0 eV to 3.5 eV. This energy gap is larger than silicon. Thus, in an oxide semiconductor, generation of carriers due to thermal excitation can be extremely reduced. Therefore, a transistor in which an oxide semiconductor is used for a semiconductor layer does not cause deterioration in characteristics even in a high-temperature environment and can keep electric characteristics from changing to a low level.

In addition, an oxide semiconductor is a highly purified oxide semiconductor (purified OS) in which impurities such as moisture or hydrogen which are electron donors (donors) are reduced and oxygen vacancies are reduced. Is preferred. A highly purified oxide semiconductor is almost i-type (intrinsic semiconductor) or i-type. Therefore, a transistor including a channel formation region in a highly purified oxide semiconductor layer has extremely low off-state current and high reliability in a high-temperature environment. A transistor including an oxide semiconductor having such characteristics is preferable as a transistor used in the semiconductor device of this embodiment.

The semiconductor device 100 described above constitutes a circuit with unipolar transistors. With this structure, the transistor included in the semiconductor device 100 can be formed using a transistor including an oxide semiconductor. With this structure, the transistor included in the semiconductor device 100 can be a transistor with extremely low off-state current and high reliability in a high temperature environment. For this reason, it is possible to prevent the transistors included in the semiconductor device 100 from malfunctioning due to a temperature change. Further, the semiconductor device 100 can eliminate restrictions on arrangement such as providing the power transistor and the semiconductor device separately in advance and providing a cooling means so as not to reach a high temperature state.

Note that in the structure of the semiconductor device 100 illustrated in FIGS. 2A and 2B, the output terminal OUT can be divided into an output terminal OUT_H and an output terminal OUT_L as illustrated in FIG. As shown in FIG. 5A, by separating the output terminal into two of the output terminal OUT_H and the output terminal OUT_L, the through current flowing between the power supply lines can be reduced.

Further, when the semiconductor device 100 illustrated in FIG. 5A is simplified and illustrated in a block diagram, it can be represented as illustrated in FIG. Note that the terminals illustrated in FIG. 5B are terminals of the circuit illustrated in FIG. 5A, and the terminals VH and VL are terminals to which the voltage V3 and the ground potential GND are applied.

A terminal VpH and a terminal VpL illustrated in FIG. 5B are terminals for applying the voltage V1 and the voltage V2. The voltage V4 may be boosted using a bootstrap circuit based on the voltage V1.

Next, an application example of a semiconductor device for driving a power transistor is illustrated in FIG. 6 with reference to the block diagram of FIG.

In the structure of the low-side driver using the semiconductor device 100 in FIG. 5A illustrated in FIG. 6, the semiconductor device 201A and the semiconductor device 201B are provided. Further, in FIG. 6, as other configurations, a control circuit 211 (indicated as Controller), a photocoupler 212 and a photocoupler 213, reference voltage generation circuits 214 to 216, diodes Di1 to Di3, capacitive elements Cap1 to Cap4, power A transistor 221 and a power transistor 222 are shown. Note that in the circuit diagram illustrated in FIG. 6, a resistance element provided over the wiring is an element provided to convert a flowing current into a voltage. In the circuit diagram shown in FIG. 6, the voltage PHV and the voltage PGND are voltages applied to a load (not shown) connected to the power transistor 221 and the power transistor 222.

The PWM signal output from the control circuit 211 is supplied to the semiconductor device 201A and the semiconductor device 201B via the photocoupler 212 and the photocoupler 213 or wiring. The semiconductor devices 201A and 201B are supplied with the reference voltages VDD1 to VDD3 from the reference voltage generation circuits 214 to 216 as the voltages V1 to V3. For the semiconductor devices 201A and 201B, the reference voltages VDD1 to VDD3 output from the reference voltage generation circuits 214 to 216 are used as the reference voltages VDD1 to VDD3, the diodes Di1 and Di2, and the capacitative elements Cap1 and Cap2. The boosted voltage is given.

In the configuration of the low-side driver shown in FIG. 6, the diode Di3 is provided between the terminal VL and the terminal VpL of the semiconductor device 201A so that the current direction is bidirectional. This diode Di3 is an element provided for short-circuiting so as not to cause a large potential difference between the terminals so that a malfunction does not occur when the difference between the voltages applied to the terminals VL and VpL changes greatly. Should be provided.

In the semiconductor device described in this embodiment, the buffer circuit and the level shift circuit are formed using transistors having the same polarity. Therefore, a transistor provided in the semiconductor device can be a unipolar transistor.

Further, in the semiconductor device, a capacitor is provided in the level shift circuit, and a signal for boosting is supplied to the capacitor, and the signal is boosted using capacitive coupling in the capacitor. In this configuration, the voltage applied between the source and drain of the transistor in the level shift circuit can be made smaller than the voltage applied to the capacitive element in the level shift circuit, and the dielectric breakdown of the transistor can be suppressed.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 2)
In this embodiment, an oxide semiconductor layer used for the semiconductor layer of the unipolar transistor described in the above embodiment will be described.

An oxide semiconductor used for a channel formation region in the semiconductor layer of the transistor preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain In and Zn. In addition to these, it is preferable to have a stabilizer that strongly binds oxygen. The stabilizer may include at least one of gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), and aluminum (Al).

As other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb) , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

Examples of the oxide semiconductor used as the semiconductor layer of the transistor include indium oxide, tin oxide, zinc oxide, In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, and Zn—Mg oxide. Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also referred to as IGZO), In-Al-Zn oxide, In-Sn -Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-Zr-Zn oxide In-Ti-Zn-based oxide, In-Sc-Zn-based oxide, In-Y-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr- Zn-based oxide, In-Nd-Zn-based oxide, In-Sm Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf -Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide There are things.

  For example, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 3: 1: 2, or In: Ga: Zn = 2: 1: 3 atomic ratio In—Ga—Zn-based oxidation An oxide in the vicinity of the product or its composition may be used.

  When a large amount of hydrogen is contained in the oxide semiconductor film included in the semiconductor layer, a part of the hydrogen serves as a donor and an electron serving as a carrier is generated by bonding with the oxide semiconductor. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, after the oxide semiconductor film is formed, it is preferable that heat treatment for dehydration be performed to remove hydrogen or moisture from the oxide semiconductor film so that impurities are not included as much as possible.

  Note that oxygen may be reduced from the oxide semiconductor film due to dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. Therefore, it is preferable to perform treatment in which oxygen is added to the oxide semiconductor film in order to fill oxygen vacancies increased by dehydration treatment (dehydrogenation treatment). In this specification and the like, the case where oxygen is supplied to the oxide semiconductor film may be referred to as oxygenation treatment, or the case where oxygen contained in the oxide semiconductor film is larger than the stoichiometric composition is excessive. Sometimes referred to as oxygenation treatment.

As described above, the oxide semiconductor film is made i-type (intrinsic) or i-type by removing hydrogen or moisture by dehydration treatment (dehydrogenation treatment) and filling oxygen vacancies by oxygenation treatment. An oxide semiconductor film that is substantially i-type (intrinsic) can be obtained. Note that substantially intrinsic means that the number of carriers derived from a donor in the oxide semiconductor film is extremely small (near zero), and the carrier density is 1 × 10 ¹⁷ / cm ³ or less, 1 × 10 ¹⁶ / cm ³ or less, It means 1 × 10 ¹⁵ / cm ³ or less, 1 × 10 ¹⁴ / cm ³ or less, and 1 × 10 ¹³ / cm ³ or less.

In this manner, a transistor including an i-type or substantially i-type oxide semiconductor film can achieve extremely excellent off-state current characteristics. For example, the drain current when the transistor including an oxide semiconductor film is off is 1 × 10 ⁻¹⁸ A or less, preferably 1 × 10 ⁻²¹ A or less, more preferably 1 at room temperature (about 25 ° C.). × 10 ⁻²⁴ A or less, or 1 × 10 ⁻¹⁵ A or less, preferably 1 × 10 ⁻¹⁸ A or less, more preferably 1 × 10 ⁻²¹ A or less at 85 ° C. Note that an off state of a transistor means a state where a gate voltage is sufficiently lower than a threshold voltage in the case of an n-channel transistor. Specifically, when the gate voltage is 1 V or higher, 2 V or higher, or 3 V or lower than the threshold voltage, the transistor is turned off.

Next, the structure of the oxide semiconductor is described.

An oxide semiconductor film is classified roughly into a single crystal oxide semiconductor film and a non-single crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film, or the like.

An amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal component. An oxide semiconductor film which has no crystal part even in a minute region and has a completely amorphous structure as a whole is typical.

The microcrystalline oxide semiconductor film includes a microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Therefore, the microcrystalline oxide semiconductor film has higher regularity of atomic arrangement than the amorphous oxide semiconductor film. Therefore, a microcrystalline oxide semiconductor film has a feature that the density of defect states is lower than that of an amorphous oxide semiconductor film.

The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts are large enough to fit in a cube whose one side is less than 100 nm. Therefore, the case where a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm is included. The CAAC-OS film is characterized by having a lower density of defect states than a microcrystalline oxide semiconductor film. Hereinafter, the CAAC-OS film is described in detail.

When the CAAC-OS film is observed with a transmission electron microscope (TEM), a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

When the CAAC-OS film is observed by TEM (cross-sectional TEM observation) from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

On the other hand, when the CAAC-OS film is observed by TEM (planar TEM observation) from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

From the cross-sectional TEM observation and the planar TEM observation, it is found that the crystal part of the CAAC-OS film has orientation.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS film crystal has c-axis orientation, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Six peaks attributed to the crystal plane equivalent to the (110) plane are observed. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56 °.

From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the c-axis is aligned, and the c-axis is a normal line of the formation surface or the top surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of metal atoms arranged in a layer shape confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

Note that the crystal part is formed when a CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film.

Further, the crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, the region near the top surface can have a higher degree of crystallinity than the region near the formation surface. is there. In addition, in the case where an impurity is added to the CAAC-OS film, the crystallinity of a region to which the impurity is added changes, and a region having a different degree of crystallinity may be formed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 3)
In this embodiment, a cross-sectional structure of a transistor included in a semiconductor device according to one embodiment of the disclosed invention will be described with reference to drawings.

7 to 9 illustrate part of a cross-sectional structure of a transistor included in a semiconductor device according to one embodiment of the present invention as an example. Note that this embodiment exemplifies the case where a transistor including an oxide semiconductor as a semiconductor layer is formed over a substrate as a transistor.

Note that in the case of a transistor using an oxide semiconductor, change in electrical characteristics due to temperature can be reduced as compared to a transistor using silicon. Therefore, even if the semiconductor device is provided in the vicinity of the IGBT that becomes high temperature by the switching operation, a change in electrical characteristics can be suppressed, so that malfunction of the semiconductor device can be reduced.

In FIG. 7A, an n-channel transistor 800 is formed over a substrate 820. FIG. 7A illustrates a coplanar transistor structure as an example.

The transistor 800 includes a semiconductor film 830 including an oxide semiconductor over a substrate 820, a conductive film 832 and a conductive film 833 that function as a source electrode or a drain electrode over the semiconductor film 830, a semiconductor film 830, a conductive film 832, and A gate insulating film 831 over the conductive film 833 and a conductive film 834 which is located over the gate insulating film 831 and functions as a gate electrode overlapping with the semiconductor film 830 between the conductive film 832 and the conductive film 833 are provided.

As the substrate 820, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Alternatively, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be used.

The conductive films 832 and 833 and the conductive film 834 are formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium or an alloy material containing any of these materials as its main component. Can do. The conductive film 832, the conductive film 833, and the conductive film 834 may have a single-layer structure or a stacked structure.

The gate insulating film 831 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating film containing one or more of them can be used. The gate insulating film 831 may be a stacked layer of the above materials.

Note that although a coplanar transistor structure is illustrated in FIG. 7A, a staggered transistor structure such as a transistor 801 illustrated in FIG. 7B may be employed.

The transistor 801 includes a conductive film 832 and a conductive film 833 that function as a source electrode and a drain electrode over a substrate 820, a semiconductor film 830 including an oxide semiconductor over the conductive film 832 and the conductive film 833, a semiconductor film 830, A conductive film 832 and a gate insulating film 831 over the conductive film 833; a conductive film 834 which is located over the gate insulating film 831 and functions as a gate electrode overlapping with the semiconductor film 830 between the conductive films 832 and 833; Have.

Further, the semiconductor film 830 is not necessarily formed of a single oxide semiconductor, and may be formed of a plurality of stacked oxide semiconductors. For example, FIGS. 8A and 8B illustrate a structure example of the transistor 800 in the case where the semiconductor film 830 is stacked to have three layers.

A transistor 802 illustrated in FIG. 8A includes a semiconductor film 830 provided over a substrate 820 and the like, a conductive film 832 and a conductive film 833 which are electrically connected to the semiconductor film 830, and a gate insulating film 831. And a conductive film 834 functioning as a gate electrode provided to overlap with the semiconductor film 830 over the gate insulating film 831.

In the transistor 802, as the semiconductor film 830, oxide semiconductor layers 830a to 830c are stacked in this order from the substrate 820 side.

The oxide semiconductor layer 830a and the oxide semiconductor layer 830c each include at least one of metal elements included in the oxide semiconductor layer 830b in its constituent elements, and the energy at the lower end of the conduction band is higher than that of the oxide semiconductor layer 830b. The oxide film has a vacuum level of 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Further, the oxide semiconductor layer 830b preferably contains at least indium because carrier mobility is increased.

Note that as in the transistor 803 illustrated in FIG. 8B, the oxide semiconductor layer 830c may be provided over the conductive films 832 and 833 so as to overlap with the gate insulating film 831.

Further, the structure of the transistor provided over the substrate 820 is not limited to the top gate structure illustrated in FIGS. 7A and 7B, and a bottom gate transistor can be used. FIG. 9A illustrates an inverted coplanar transistor structure as an example.

The transistor 804 includes a conductive film 834 functioning as a gate electrode, a gate insulating film 831 over the conductive film 834, a conductive film 832 functioning as a source electrode or a drain electrode over the substrate 820, and a conductive film. A film 833, a conductive film 832, and a semiconductor film 830 over the conductive film 833 are included.

Note that although an inverse coplanar transistor structure is shown in FIG. 9A, an inverted staggered transistor structure such as a transistor 805 shown in FIG. 9B can also be used.

The transistor 805 includes a conductive film 834 functioning as a gate electrode, a gate insulating film 831 over the conductive film 834, a semiconductor film 830 over the gate insulating film 831, and a source electrode over the semiconductor film 830 over the substrate 820. Alternatively, the conductive film 832 and the conductive film 833 function as a drain electrode.

7 to 9, the transistors 800 to 805 may have at least one conductive film 834 functioning as a gate electrode on one side of the semiconductor film 830; however, a pair of the transistors 800 to 805 exist with the semiconductor film 830 interposed therebetween. The gate electrode may be provided.

In the case where the transistors 800 to 805 have a pair of gate electrodes that are sandwiched between the semiconductor films 830, a signal for controlling on or off is given to one gate electrode, and the other gate electrode May be in a state where a potential is applied from another. In the latter case, the same potential may be applied to the pair of electrodes, or a fixed potential such as a ground potential may be applied only to the other gate electrode. By controlling the potential applied to the other gate electrode, the threshold voltage of the transistors 800 to 805 can be controlled.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 4)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to an electronic component and an example in which the semiconductor device is applied to an electronic device including the electronic component will be described with reference to FIGS.

FIG. 10A illustrates an example in which the semiconductor device described in the above embodiment is applied to an electronic component. Note that the electronic component is also referred to as a semiconductor package or an IC package. This electronic component has a plurality of standards and names depending on the terminal take-out direction and the shape of the terminal. Therefore, in this embodiment, an example will be described.

A semiconductor device including a transistor as shown in FIGS. 7 to 9 in the third embodiment is completed by assembling a plurality of detachable components on a printed circuit board through an assembly process (post-process).

The post-process can be completed through each process shown in FIG. Specifically, after the element substrate obtained in the previous process is completed (step S1), the back surface of the substrate is ground (step S2). This is because by reducing the thickness of the substrate at this stage, it is possible to reduce the warpage of the substrate in the previous process and to reduce the size of the component.

A dicing process is performed in which the back surface of the substrate is ground to separate the substrate into a plurality of chips. Then, a die bonding process is performed in which the separated chips are individually picked up and mounted on the lead frame and bonded (step S3). For the bonding between the chip and the lead frame in this die bonding process, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. The die bonding step may be mounted on the interposer and bonded.

Next, wire bonding is performed in which the lead of the lead frame and the electrode on the chip are electrically connected by a thin metal wire (wire) (step S4). A silver wire or a gold wire can be used as the metal thin wire. For wire bonding, ball bonding or wedge bonding can be used.

The wire-bonded chip is subjected to a molding process that is sealed with an epoxy resin or the like (step S5). By performing the molding process, the inside of the electronic component is filled with resin, the built-in circuit part and wire can be protected by mechanical external force, and the deterioration of characteristics due to moisture and dust can be reduced. .

Next, the lead of the lead frame is plated. Then, the lead is cut and molded (step S6). By this plating treatment, rusting of the lead can be prevented, and soldering when mounting on a printed circuit board can be performed more reliably.

Next, a printing process (marking) is performed on the surface of the package (step S7). An electronic component is completed through a final inspection process (step S8) (step S9).

The electronic component described above can include the semiconductor device described in the above embodiment. Therefore, it is possible to realize an electronic component having a semiconductor device in which malfunctions in a high temperature environment are reduced and manufacturing costs are reduced. Since the electronic component includes a semiconductor device in which malfunction under a high temperature environment is reduced and manufacturing cost is reduced, the restriction on the use environment is relaxed and the electronic component is reduced in size.

A perspective schematic view of the completed electronic component is shown in FIG. FIG. 10B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 700 illustrated in FIG. 10B illustrates a lead 701 and a semiconductor device 703. An electronic component 700 illustrated in FIG. 10B is mounted on a printed circuit board 702, for example. A plurality of such electronic components 700 are combined and each is electrically connected on the printed circuit board 702 to complete a substrate (mounting substrate 704) on which the electronic components are mounted. The completed mounting board 704 is provided inside an electronic device or the like.

Next, an application example in which the above-described electronic component is applied to a drive circuit that drives an inverter, a motor, or the like provided in a vehicle (such as a bicycle) that is driven by electric power of a fixed power source will be described with reference to FIG.

FIG. 11A illustrates an electric bicycle 1010 as an application example. The electric bicycle 1010 obtains power by passing a current through the motor unit 1011. The electric bicycle 1010 includes a battery 1012 for supplying a current to be supplied to the motor unit 1011 and a drive circuit 1013 for driving the motor unit 1011. Note that although the pedal is illustrated in FIG.

A mounting substrate provided with an electronic component including the semiconductor device described in any of the above embodiments is mounted on the driver circuit 1013. Therefore, restrictions on the use environment are relaxed, and an electric bicycle including an electronic component with a reduced size is realized.

FIG. 11B illustrates an electric vehicle 1020 as another application example. The electric vehicle 1020 obtains power by passing a current through the motor unit 1021. The electric vehicle 1020 includes a battery 1022 for supplying a current to be supplied to the motor unit 1021 and a drive circuit 1023 for driving the motor unit 1021.

A mounting substrate provided with an electronic component including the semiconductor device described in any of the above embodiments is mounted on the driver circuit 1023. Therefore, the restriction of the use environment is relaxed, and an electric vehicle including an electronic component with a reduced size is realized.

As described above, the electronic device described in this embodiment includes a mounting board provided with an electronic component including the semiconductor device according to any of the above embodiments. For this reason, the restriction of the use environment is relaxed, and an electronic device including an electronic component that is reduced in size is realized.

100 Semiconductor Device 101 Buffer Circuit 102 Level Shift Circuit 103 Buffer Circuit 104 Buffer Circuit 111 Transistor 112 Transistor 113 Capacitor Element 114 Capacitor Element 121 Transistor 122 Transistor 131 Inverter Circuit 132 Inverter Circuit 141 Transistor 142 Transistor 143 Transistor 144 Transistor 151 Transistor 152 Transistor 153 Transistor 154 Transistor 155 Capacitance element 201A Semiconductor device 201B Semiconductor device 211 Control circuit 212 Photocoupler 213 Photocoupler 214 Reference voltage generation circuit 215 Reference voltage generation circuit 216 Reference voltage generation circuit Cap1 Capacitance element Cap2 Capacitance element Cap3 Capacitance element Cap4 Capacitance element Di1 Diode Di2 Diode Di Diode 221 Power transistor 222 Power transistor 700 Electronic component 701 Lead 702 Printed circuit board 703 Semiconductor device 704 Mounting substrate 800 Transistor 801 Transistor 802 Transistor 803 Transistor 804 Transistor 805 Transistor 820 Substrate 830 Semiconductor film 830a Oxide semiconductor layer 830b Oxide semiconductor layer 830c Oxide Physical semiconductor layer 831 gate insulating film 832 conductive film 833 conductive film 834 conductive film 1010 electric bicycle 1011 motor unit 1012 battery 1013 drive circuit 1020 electric vehicle 1021 motor unit 1022 battery 1023 drive circuit 1311 inverter circuit

Claims (6)

A first buffer circuit for converting a first signal into a second signal;
A level shift circuit for converting the second signal into a third signal;
A second buffer circuit for converting the third signal into a fourth signal;
A third buffer circuit for outputting a first potential or a second potential in accordance with the fourth signal;
Have
The transistors included in the level shift circuit and the first to third buffer circuits are transistors having the same polarity.
The semiconductor device, wherein the second signal is supplied to a capacitive element included in the level shift circuit and converted into the third signal using capacitive coupling. In claim 1,
The first buffer circuit converts the first signal into the second signal having a higher potential than the potential of the first signal;
The semiconductor device, wherein the second buffer circuit converts the third signal into the fourth signal having a higher potential than the potential of the third signal. In claim 1 or 2,
The level shift circuit converts the second signal into the third signal having a higher potential than the potential of the second signal. In any one of Claims 1 thru | or 3,
The semiconductor device of the transistor includes an oxide semiconductor. In any one of Claims 1 thru | or 4,
The semiconductor device is characterized in that the wiring that applies a low power supply potential to the first buffer circuit is different from the wiring that applies the low power supply potential to the second buffer circuit and the third buffer circuit. In any one of Claims 1 thru | or 5,
The level shift circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor,
A first terminal of the first transistor and a first terminal of the second transistor are electrically connected to a wiring for applying the second potential;
One electrode of the first capacitor is electrically connected to a second terminal of the first transistor, a gate of the second transistor, and the second buffer circuit;
One electrode of the second capacitor is electrically connected to a second terminal of the second transistor, a gate of the first transistor, and the second buffer circuit;
The semiconductor device, wherein the second signal is applied to the other electrode of the first capacitor, and a signal obtained by inverting the second signal is applied to the other electrode of the second capacitor. .

Images