JP2015095541A - Surge protector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a surge protector capable of ensuring high surge resistance without increasing chip area by preventing a current from flowing even when a negative voltage is continuously applied to an I/O terminal.SOLUTION: A surge protector 10 includes: an N-channel type low-voltage MOS transistor 11 which is connected to a first diffusion region, a gate and a back gate and an input/output terminal 104; and a first high breakdown voltage diode 12 with its cathode connected to a second diffusion region of the low-voltage MOS transistor 11 and its anode connected to a negative power terminal 103.

Description

 The present disclosure relates to a surge protection device that can prevent a current from continuing to flow even when a negative voltage is continuously applied to an input / output terminal, and can ensure a high surge resistance without increasing the chip area.

  In an electrical component used for in-vehicle use, for example, a semiconductor device or a semiconductor integrated circuit (hereinafter also referred to as “IC (Integrated Circuit)”), the power supply terminal is a high-voltage (for example, about 12 V) in-vehicle battery. Connected. On the other hand, generally, since the inside of the IC is composed of semiconductor elements, a single voltage (for example, about 5 V) suitable for a TTL (Transistor-Transistor Logic) level, a CMOS (Complementary MOS) level, or the like is also used. The In such an internal circuit of an IC used for in-vehicle use, a voltage obtained by stepping down the above-mentioned in-vehicle battery voltage to a single voltage is used as a power supply voltage for the internal circuit of the IC.

  As described above, an IC used for in-vehicle use includes a semiconductor element used for a voltage supplied from an external in-vehicle battery (hereinafter also referred to as “high voltage semiconductor element”) and an internal circuit at a TTL level. For example, the semiconductor device is used for the above-described single voltage (hereinafter also referred to as “low-voltage semiconductor device”). Examples of the high voltage semiconductor element include a high voltage MOS transistor and a high voltage diode. In addition, examples of the low breakdown voltage semiconductor element include a low breakdown voltage MOS transistor.

  A circuit shown in FIG. 7 is known as a conventional IC surge protection device used for in-vehicle components and the like (see Patent Document 1).

  In FIG. 7, the IC 60 includes a positive power supply terminal 602, a negative power supply terminal 603, and at least one input / output terminal 604. The positive power supply terminal 602 is connected to the positive terminal of the DC power supply 601, and the negative power supply terminal 603 is connected to the negative terminal of the DC power supply 601. A first high voltage diode 62 is connected between the input / output terminal 604 and the negative power supply terminal 603. A second high voltage diode 63 is connected between the positive power supply terminal 602 and the input / output terminal 604. As the first and second high voltage diodes 62 and 63, a parasitic diode of a transistor (not shown) in the internal circuit 606 may be used.

  On the other hand, an Nch (N channel) type high voltage MOS transistor 64 is connected between the positive power supply terminal 602 and the negative power supply terminal 603. Note that the input / output terminal 604 is a terminal to which an input signal to the internal circuit 606 is applied, or a terminal to which a signal from the internal circuit 606 is output. Reference numeral 64B denotes a parasitic diode of the high voltage MOS transistor 64.

  Next, the operation of the surge protection circuit of FIG. 7 will be described.

  When the input voltage applied to the input / output terminal 604 is within the range of the power supply voltage, the first high breakdown voltage diode 62 and the second high breakdown voltage diode 63 are in a cut-off state. Both diodes have high impedance. For this reason, the surge protection circuit does not operate, and the input voltage applied to the input / output terminal 604 is supplied to the internal circuit 606 as it is, and normal signal processing is performed.

  On the other hand, when a negative voltage exceeding the range of the power supply voltage is applied to the input / output terminal 604 for some reason, the first high-breakdown-voltage diode 62 becomes conductive, and the forward diode voltage ( The voltage at the input / output terminal 604 is clamped to a low value (approximately 0.7V).

  Further, when a positive high voltage exceeding the range of the power supply voltage is applied to the input / output terminal 604, the second high voltage diode 63 becomes conductive, and the voltage of the positive power supply terminal 602 is increased. When the voltage of the positive power supply terminal 602 reaches the threshold voltage of the high voltage MOS transistor 64, the high voltage MOS transistor 64 establishes a discharge path between the positive power supply terminal 602 and the negative power supply terminal 603. Then, the voltage of the input / output terminal 604 is clamped by the parasitic diode 64B of the high voltage MOS transistor 64. Thereby, destruction of the internal circuit 606 can be prevented.

JP-A-3-27566

  However, in the conventional surge protection circuit, when a negative voltage is applied to the input / output terminal 604 for a long time, the first high voltage diode 62 is biased in the forward direction and the current continues to flow. There has been a problem that the breakdown voltage diode 62 and the wiring around the diode 62 generate excessive heat and the IC is destroyed.

  Here, the time during which a pulse of surge voltage (or current) due to disturbance is applied (the time inputted to the IC) ranges from a short time of about several psec to a long time of about 1 msec. In particular, when a negative surge voltage is applied for a long time, it breaks beyond the breakdown voltage of the first high-breakdown-voltage diode 62, and the path for discharging the surge is cut off so that the internal circuit cannot be protected. was there.

  In general, a high-breakdown-voltage semiconductor element used for a voltage supplied from an in-vehicle battery has a larger element area than a low-breakdown-voltage semiconductor element such as a TTL level in order to withstand the voltage. There is a problem that the area of the semiconductor chip increases. In addition, when the power supply wiring becomes longer due to an increase in the chip area, the power supply wiring impedance becomes larger. As a result, for example, if a surge protection circuit composed of a high-breakdown-voltage semiconductor element is arranged at one location, While there is a sufficient protection effect against a surge from a pad with a short distance, there is a problem that the surge protection effect is reduced for a surge from a pad at a distance from the surge protection circuit.

  Furthermore, in the case of an in-vehicle IC, for example, the maximum rating of the input / output terminal of the IC is required to be −10 V or higher, and therefore there is a problem that the conventional technology shown in FIG. 7 cannot be used at a DC voltage of about −0.7 V or higher. It was.

  Therefore, the present disclosure solves such a conventional problem and can prevent excessive heat generation caused by current flow even when a negative voltage is applied to the input / output terminals for a long time, which increases the chip area. The purpose of the present invention is to provide a surge protection device capable of ensuring a high surge resistance without failing and to ensure the rating required for in-vehicle components.

  In one aspect of the present disclosure, a surge connected to an input / output terminal of an internal circuit connected between a first power supply terminal and a second power supply terminal receiving a power supply voltage lower than the first power supply terminal. In the protection device, a first diffusion region, a gate, and a back gate are connected to the input / output terminal, an N-channel first transistor, and a cathode is connected to the second diffusion region of the first transistor. And a first diode having an anode connected to the second power supply terminal.

  According to this aspect, the first transistor and the first diode are connected in series between the input / output terminal and the second power supply terminal. During normal operation, the first transistor has no voltage drop between the first diffusion region and the second diffusion region, and functions as an OFF transistor. On the other hand, when a negative surge voltage is applied to the input / output terminal, that is, when a voltage higher than the threshold voltage is applied between the drain and source of the first transistor, the first transistor is turned on. Accordingly, it is possible to prevent a high voltage from being applied to the input / output terminals, and thus it is possible to prevent the internal circuit from excessively generating heat due to the high voltage. When a negative voltage is applied to the input / output terminal, that is, when a negative voltage lower than the threshold voltage is applied between the drain and source of the first transistor, the first transistor is in the OFF state. In other words, even when a negative voltage is applied to the input / output terminal for a long time, it is possible to prevent excessive heat generation of the semiconductor device that occurs due to current flow.

  According to the surge protection device of the present disclosure as described above, excessive heat generation of the semiconductor device can be prevented even when a negative voltage is applied to the input / output terminal for a long time without increasing the chip area of the semiconductor device. it can.

It is a surge protection device of the 1st example. It is sectional drawing of a surge protection circuit. It is a surge protection device of the 2nd example. It is a surge protection device of the 3rd example. It is a surge protection device of the 4th example. It is a conceptual diagram of the layout of a surge protection device. It is a conventional surge protection device.

An embodiment according to the present disclosure will be described in detail with reference to the drawings.
[Example 1]
FIG. 1 shows a first embodiment of a surge protection device according to the present disclosure.

  The internal circuit 106 is connected to the positive power supply terminal 102 as the first power supply terminal connected to the positive terminal (the power supply voltage is VDD) of the DC power supply 101 and the negative terminal (the ground voltage is VSS) of the DC power supply 101. Further, it is provided between the negative power supply terminal 103 as the second power supply terminal, and is configured by a semiconductor element, a passive element, or the like. The internal circuit 106 is connected to at least one input / output terminal. In the present disclosure, an input / output terminal is a terminal to which an input signal to the internal circuit 106 is applied, or a terminal to which a signal from the internal circuit 106 is output. Alternatively, the input / output terminal is a terminal for selectively applying an input signal to the internal circuit 106 and outputting a signal from the internal circuit 106. In FIG. 1, the input / output terminal 104 is representatively shown as the input / output terminal.

  The surge protection device 10 includes a second high breakdown voltage diode 13 as a second diode provided between the positive power supply terminal 102 and the input / output terminal 104, and the input / output terminal 104 and the negative power supply terminal 103. A surge protection circuit 105 provided between the positive power supply terminal 102 and the negative power supply terminal 103, and a surge protection circuit 107 for protection between VDD and VSS provided between the positive power supply terminal 102 and the negative power supply terminal 103. .

  The surge protection circuit 105 includes an Nch type low breakdown voltage MOS transistor 11 as a first transistor and a first high breakdown voltage diode 12 as a first diode. In the low breakdown voltage MOS transistor 11, the source, gate, and back gate as the first diffusion region are connected to the input / output terminal 104, and the drain as the second diffusion region is connected to the cathode of the first high breakdown voltage diode 12. ing. The anode of the first high voltage diode 12 is connected to the negative power supply terminal 103. Reference numeral 11B denotes a parasitic diode of the low breakdown voltage MOS transistor 11.

  The surge protection circuit 107 includes an Nch type high voltage MOS transistor 14 as a second transistor. In the high voltage MOS transistor 14, the source, gate, and back gate as the first diffusion region are connected to the negative power supply terminal 103, and the drain as the second diffusion region is connected to the positive power supply terminal 102. Reference numeral 14B denotes a parasitic diode of the high voltage MOS transistor 14.

  In the present disclosure, a high breakdown voltage semiconductor element (for example, a high breakdown voltage diode, a high breakdown voltage MOS transistor, etc.) refers to an element used for a high power supply voltage (for example, about 12 V). Moreover, a low breakdown voltage semiconductor element (for example, a low breakdown voltage diode, a low breakdown voltage MOS transistor, etc.) refers to an element used for a single power supply voltage (for example, about 5 V) stepped down from the high power supply voltage. Shall.

  When a positive voltage (hereinafter also simply referred to as a positive voltage) within the range of the power supply voltage (below the power supply voltage VDD and above the ground voltage VSS) is applied to the input / output terminal 104, that is, a surge protection device during normal operation The operation of 10 will be described in detail.

  When a positive voltage is applied to the input / output terminal 104, the first high-breakdown-voltage diode 12 is in a reverse bias state, and the current is cut off. The voltage between the drain and source of the low breakdown voltage MOS transistor 11 is clamped to a forward diode voltage (eg, 0.7 V) by the parasitic diode 11B. Therefore, the voltage drop between the input / output terminal 104 and the first high voltage diode 12 is a value that can be almost ignored. Therefore, the surge protection circuit 105 does not affect the operation of the internal circuit 106 regardless of the presence or absence of the low voltage MOS transistor 11.

  1 will be described in detail when a negative surge voltage is applied to the input / output terminal 104 for a long time.

  When the voltage between the drain and source of the low voltage MOS transistor 11 reaches the threshold voltage due to a negative surge from the outside, the low voltage MOS transistor 11 forms a discharge path. As a result, the impedance between the input / output terminal 104 and the cathode of the first high voltage diode 12 becomes low. In this state, since the first high-voltage diode 12 conducts, the voltage at the input / output terminal 104 is clamped to a value lower than the voltage at the negative power supply terminal 103 (VSS) by the forward diode voltage (about 0.7V). Is done. That is, it is possible to prevent a negative high voltage from being applied to the input / output terminal 104. Thereby, it is possible to prevent the internal circuit 106 from excessively generating heat due to a negative high voltage.

  Next, the operation when a positive surge voltage is applied to the input / output terminal 104 for a long time in the configuration of FIG. 1 will be described in detail.

  When a positive high voltage exceeding the range of the power supply voltage VDD is applied due to a positive surge from the outside, the second high voltage diode 13 is turned on, and the voltage of the positive power supply terminal 102 is increased. When the voltage of the positive power supply terminal 102 reaches the threshold voltage of the high voltage MOS transistor 14, a discharge path is formed between the positive power supply terminal 102 and the negative power supply terminal 103 by the high voltage MOS transistor 14. The impedance between the positive power supply terminal 102 and the negative power supply terminal 103 is low. That is, it is possible to prevent a positive high voltage from being applied between the positive power supply terminal 102 and the negative power supply terminal 103. Thereby, excessive heat generation of the internal circuit 106 due to a positive high voltage applied to the input / output terminal 104 is prevented.

  Next, the low breakdown voltage MOS transistor 11 when a negative voltage (hereinafter also simply referred to as a negative voltage) is applied to the input / output terminal 104 so that the drain-source voltage of the low breakdown voltage MOS transistor 11 is less than the breakdown voltage. Will be described in detail. At this time, since there is no path in which the diode is connected in the forward direction between the input / output terminal 104 and the power supply voltage VDD and between the input / output terminal 104 and the ground potential VSS, a current flows through the low breakdown voltage MOS transistor 11. There is no. The breakdown voltage between the drain and source of the low breakdown voltage MOS transistor 11 can be arbitrarily set. That is, even if a voltage of 10 V or more required for the in-vehicle component is input, the first high voltage diode 12 does not break down and the maximum rating can be ensured.

  In this embodiment, one example of the low voltage MOS transistor 11 is shown, but a plurality of low voltage MOS transistors may be connected in series and / or in parallel.

  FIG. 2 shows a cross-sectional view of the surge protection circuit 105 (low voltage MOS transistor 11 and first high voltage diode 12). An N-type diffusion layer 206 is provided on a P-type semiconductor substrate 214, and a first P-type semiconductor region 205A and a second P-type semiconductor region 205B are formed thereon. Under the low breakdown voltage MOS transistor 11 and the first high breakdown voltage diode 12 between the P type semiconductor substrate 214 and the N type diffusion layer 206, high concentration N type diffusion regions 207 are respectively formed. The low breakdown voltage MOS transistor 11 is formed in the first P-type semiconductor region 205A, and the first high breakdown voltage diode 12 is formed in the second P-type semiconductor region 205B.

  The low breakdown voltage MOS transistor 11 includes an N-type diffusion region 201 as a first diffusion region and an N-type diffusion region 202 as a second diffusion region. A gate 210 is formed across the N-type diffusion region 201 and the N-type diffusion region 202. As a result, the first P-type semiconductor region 205A, the N-type diffusion region 201, and the gate 210 are connected. Here, the N-type diffusion region 201 functions as a source, and the N-type diffusion region 202 functions as a drain. A source electrode 209 is formed in the N-type diffusion region 201, and a drain electrode 211 is formed in the N-type diffusion region 202. The input / output terminal 104 is connected to the gate 210, the back gate electrode 208, and the source electrode 209 of the low voltage MOS transistor 11.

  The second P-type semiconductor region 205B includes an N-type diffusion region 204 and a high-concentration N-type cathode region 203 formed in the N-type diffusion region 204. Further, the second P-type semiconductor region 205B includes a high-concentration P-type anode region 215 at a position away from the N-type diffusion region 204. Then, the cathode electrode 212 of the first high voltage diode 12 is formed in the N-type cathode region 203, and the anode electrode 213 of the first high voltage diode 12 is formed in the P-type anode region 215. The cathode electrode 212 of the first high voltage diode 12 is connected to the drain electrode 211 of the low voltage MOS transistor 11, and the anode electrode 213 of the first high voltage diode 12 is connected to the negative power supply terminal 103.

As described above, the low breakdown voltage MOS transistor 11 does not have a voltage drop between the drain and the source during normal operation and functions as an OFF transistor. . Therefore, the threshold voltage of the low breakdown voltage MOS transistor 11 may be a low voltage, and there is no need to provide a diffusion region for increasing the breakdown voltage between the drain and source. Therefore, the surge resistance can be maintained without a large increase in the chip area.
[Example 2]
FIG. 3 shows a second embodiment of the surge protection device according to the present disclosure.

  In this embodiment, the surge protection device 10 includes a surge protection circuit 108 between the positive power supply terminal 102 and the negative power supply terminal 103.

  The surge protection circuit 108 includes a Pch (P channel) type high voltage MOS transistor 15 as a second transistor. In the high voltage MOS transistor 15, the drain as the second diffusion region is connected to the negative power supply terminal 103, and the source, gate and back gate as the first diffusion region are connected to the positive power supply terminal 102. Reference numeral 15B denotes a parasitic diode of the high voltage MOS transistor 15.

With this configuration, even when a positive high voltage exceeding the range of the power supply voltage VDD is applied due to a positive surge from the outside, when the threshold voltage of the high voltage MOS transistor 15 is reached, A discharge path is formed between the negative power supply terminal 102 and the negative power supply terminal 103, and the impedance between the positive power supply terminal 102 and the negative power supply terminal 103 is low. That is, a surge protection circuit between VDD and VSS (between the positive power supply terminal 102 and the negative power supply terminal 103) that clamps the voltage of the input / output terminal 104 can be formed. The operation when a negative surge voltage is applied to the input / output terminal 104 for a long time is the same as or similar to that of the first embodiment.
[Example 3]
FIG. 4 shows a third embodiment of the surge protection device according to the present disclosure.

  In the present embodiment, the surge protection device 10 includes a surge protection circuit 109 between the positive power supply terminal 102 and the negative power supply terminal 103.

  The surge protection circuit 109 includes an Nch type high voltage MOS transistor 14 and a resistance element 16 provided between the gate and source of the high voltage MOS transistor 14. The high voltage MOS transistor 14 has a drain connected to the positive power supply terminal 102 and a source and back gate connected to the negative power supply terminal 103.

With this configuration, when the drain-source voltage of the high voltage MOS transistor 14 becomes equal to or higher than the threshold voltage, the gate-source voltage can be increased as compared with the configuration of FIG. Therefore, the surge protection circuit 109 can realize surge protection between VDD and VSS (between the positive power supply terminal 102 and the negative power supply terminal 103) through which a larger current flows than in the configuration of FIG.
[Example 4]
FIG. 5 shows a fourth embodiment of the surge protection device according to the present disclosure.

  In this embodiment, the surge protection device 10 includes a surge protection circuit 110 between the positive power supply terminal 102 and the negative power supply terminal 103.

  The surge protection circuit 110 includes a Pch type high voltage MOS transistor 15 and a resistance element 17 provided between the gate and source of the high voltage MOS transistor 15. The high voltage MOS transistor 15 has a drain connected to the negative power supply terminal 103 and a source and a back gate connected to the positive power supply terminal 102.

  With this configuration, when the voltage between the drain and source of the high voltage MOS transistor 15 becomes equal to or higher than the threshold voltage, the gate-source voltage can be increased as compared with the configuration of FIG. Therefore, the surge protection circuit 110 can realize surge protection between VDD and VSS (between the positive power supply terminal 102 and the negative power supply terminal 103) through which a larger current flows than in the configuration of FIG.

In each of the above-described embodiments, a low breakdown voltage MOS transistor is provided between the input / output terminal 104 and the cathode of the first high breakdown voltage diode 12 according to the magnitude of the DC negative voltage applied to the input / output terminal 104. By connecting two or more 11 in series, the drain-source breakdown voltage may be increased more than twice.
[Example 5]
FIG. 6 shows a fifth embodiment of the surge protection device in the first to fourth embodiments.

  This embodiment is an example of a layout of a semiconductor device (for example, IC) having a surge protection device, a pad, and an internal circuit.

  The semiconductor device includes a pad PAD1 connected to the positive power supply terminal 102, a pad PAD2 connected to the input / output terminal 104, and a pad PAD3 connected to the negative power supply terminal 103. In the vicinity of the input / output terminal 104, a second high voltage diode 13 and a surge protection circuit 105 to which a negative voltage countermeasure is applied are laid out. An internal circuit 106 is laid out inside the IC. Between the positive power supply terminal 102 and the negative power supply terminal 103, a plurality of surge protection circuits 107 (three in FIG. 6) for VDD-VSS protection are provided.

  Here, the wiring connecting the respective surge protection circuits 107 arranged on the semiconductor device and the respective pads PAD1 to PAD3 is wired so that the impedance thereof is minimized. Thereby, when a surge is input from each pad PAD1 to PAD3, the impedance between each pad PAD1 to PAD3 and the gate terminal of each surge protection circuit 107 is minimized. As a result, the voltage drop due to the wiring is minimized, a voltage sufficient to operate the gate terminal of the surge protection circuit 107 is applied, and the protection effect can be exhibited more effectively.

  In FIG. 6, only three pads PAD1 to PAD3 are shown as representatives. However, normally, a semiconductor device (IC) includes more pads and circuits (internal circuits and the like). In FIG. 6, the same or similar effect can be obtained by using surge protection circuits 108, 109, and 110 instead of the surge protection circuit 107.

(Other examples)
The embodiment has been described above as an example of the technique disclosed in the present application. However, the technology in the present disclosure is not limited to this, and can be applied to embodiments in which changes, replacements, additions, omissions, and the like are appropriately made. Hereinafter, other examples are illustrated.

  For example, in FIG. 1, the surge protection circuit 107 for protecting between VDD and VSS may be omitted. However, when there is a purpose of protecting between VDD and VSS, it is preferable that the surge protection circuit 107 is provided.

  Similarly, in FIG. 3 to FIG. 5, the surge protection circuits 108, 109, and 110 for protecting between VDD and VSS may be omitted. However, when the purpose is to protect between VDD and VSS, it is preferable to have the surge protection circuits 108, 109, and 110.

  In FIG. 1, the second high voltage diode 13 and the surge protection circuit 107 may be omitted. However, when the purpose is to protect the positive surge voltage, it is preferable to have the second high voltage diode 13 and the surge protection circuit 107.

  In FIG. 1, a low breakdown voltage MOS transistor may be used in place of the high breakdown voltage MOS transistor 14 of the surge protection circuit 107. However, in order to ensure the surge protection capability between VDD and VSS, it is preferable to use a high voltage MOS transistor for the surge protection circuit 107.

  Even if a negative voltage is applied to the input / output terminals for a long time, it is possible to provide a surge protection circuit that can prevent excessive heat generation and ensure high surge resistance without increasing the chip area of the semiconductor device. It is useful for a semiconductor device or the like that is used by being connected to a high-voltage battery or the like such as an electrical component for use.

10 Surge protection device 11 Low voltage MOS transistor (first transistor)
12 1st high voltage | pressure-resistant diode (1st diode)
13 Second high voltage diode (second diode)
14 High voltage MOS transistor (second transistor)
15 High voltage MOS transistor (second transistor)
16 resistance element 17 resistance element 102 positive power supply terminal (first power supply terminal)
103 Negative power supply terminal (second power supply terminal)
104 I / O terminal 106 Internal circuit

Claims (9)

A surge protection device connected to an input / output terminal of an internal circuit connected between a first power supply terminal and a second power supply terminal receiving a power supply voltage lower than the first power supply terminal;
An N-channel first transistor having a first diffusion region, a gate, and a back gate connected to the input / output terminal;
A surge protection device comprising: a first diode having a cathode connected to a second diffusion region of the first transistor and an anode connected to the second power supply terminal. The surge protection device according to claim 1,
A surge protection device comprising: a second diode having a cathode connected to the first power supply terminal and an anode connected to the input / output terminal. The surge protection device according to claim 2,
A first diffusion region, a gate and a back gate are connected to the second power supply terminal, and a second diffusion region is provided with an N-channel type second transistor connected to the first power supply terminal. A surge protection device characterized by comprising: The surge protection device according to claim 2,
A P-channel type second transistor having a second diffusion region connected to the second power supply terminal and a first diffusion region, a gate, and a back gate connected to the first power supply terminal; A surge protection device characterized by comprising: The surge protection device according to claim 3,
The surge protection device further comprising a resistance element connected between the gate of the second transistor and the first diffusion region. The surge protection device according to claim 4,
The surge protection device further comprising a resistance element connected between the gate of the second transistor and the first diffusion region. In the surge protection device according to claim 3 or 5,
The threshold voltage between the second diffusion region and the first diffusion region in the first transistor is a threshold voltage between the second diffusion region and the first diffusion region in the second transistor. Surge protector characterized by being lower than the threshold voltage between. The surge protection device according to claim 4 or 6,
The threshold voltage between the second diffusion region and the first diffusion region in the first transistor is a threshold voltage between the second diffusion region and the first diffusion region in the second transistor. Surge protector characterized by being lower than the threshold voltage between. The surge protection device according to claim 1,
The surge protection device according to claim 1, wherein the first diffusion region is a source and the second diffusion region is a drain.

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