JP2015159145A - Nonvolatile memory element and nonvolatile memory device - Google Patents

Abstract

A non-volatile memory element and a non-volatile memory device capable of suppressing drain disturbance are provided.
A first conductivity type first impurity diffusion layer formed on a silicon substrate and a first conductivity type second impurity formed on a region of the silicon substrate away from the first impurity diffusion layer. Formed on the impurity diffusion layer 20, the tunnel gate insulating film 30 formed on the channel region between the first impurity diffusion layer 10 and the second impurity diffusion layer 20 in the silicon substrate 1, and the tunnel gate insulating film 30. The floating gate electrode 40, the gate insulating film 50 formed on the floating gate electrode 40, and the second gate electrode 60 formed on the gate insulating film 50 are included. The shape of the first impurity diffusion layer 10 in plan view includes a first extension region 11 extending in the −X direction from the channel region and a second extension extending in the −Y direction from the first extension region 11. It is a shape having the installation area 12.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile memory element and a nonvolatile memory device.

  Conventionally, an EEPROM (Electrically Erasable Programmable Read-Only Memory) is known as a nonvolatile storage device that can electrically write and erase data (see, for example, Patent Document 1). The EEPROM has a plurality of memory cells arranged in a matrix in plan view, and data can be written (erased) or erased (erase) for each memory cell.

Japanese Patent No. 2807304

  In the EEPROM, when data is written to or erased from a memory cell, charges are injected into the floating gate electrode. For example, when data is written in the memory cell, electrons are injected into the floating gate electrode, and when data is erased, holes are injected into the floating gate electrode. Then, by injecting charges into the floating gate electrode, the threshold voltage Vth of the memory cell is set to Vth in the written state or Vth in the erased state.

  However, in a conventional EEPROM, when an arbitrary memory cell is selected from a plurality of memory cells and charge is injected into the floating gate electrode of the selected memory cell (hereinafter referred to as a selected memory), memory cells other than the selected memory ( Hereinafter, in the non-selected memory cell), electric charges are unintentionally injected into the floating gate electrode, and there is a possibility that Vth of the non-selected memory fluctuates (that is, data becomes garbled).

  For example, when the selected memory is changed from the written state to the erased state, as shown in FIG. 12, the voltage VM or VH is applied to the drain layer 515 of the selected memory via the bit line 610 (| VM | <| VH |). . Further, the control gate electrode 560 of the selected memory is fixed at 0V. As a result, holes are injected from the drain layer 515 of the selected memory into the floating gate electrode 540, and the selected memory is rewritten from the written state to the erased state.

  Here, the bit line 610 connected to the drain layer 515 of the selected memory is also connected to the drain layer 515 of the unselected memory, and VM or VH is also applied to the drain layer 515 of the unselected memory. As a result, in some non-selected memories, electrons may be unintentionally injected from the drain layer 515 to the floating gate electrode 540, and data may be garbled. Hereinafter, this phenomenon is referred to as drain disturb.

  Accordingly, the present invention has been made in view of such circumstances, and an object thereof is to provide a nonvolatile memory element and a nonvolatile memory device that can suppress drain disturbance.

  In order to solve the above problems, a nonvolatile memory element according to one embodiment of the present invention includes a first impurity diffusion layer of a first conductivity type formed in a semiconductor substrate, and the first impurity diffusion layer of the semiconductor substrate. A second impurity diffusion layer of a first conductivity type formed in a region away from the first region and a channel region formed on a channel region between the first impurity diffusion layer and the second impurity diffusion layer of the semiconductor substrate. A first gate insulating film; a first gate electrode formed on the first gate insulating film; a second gate insulating film formed on the first gate electrode; and a second gate insulating film formed on the second gate insulating film. The first impurity diffusion layer extending in the first direction from the channel region in plan view, and the first extension region from the first extension region. A second extending area extending in a second direction intersecting the first direction; With the door. Here, the “channel region” refers to a region where a channel (that is, a current path) is formed by applying or not applying a voltage to the second gate electrode.

  A non-volatile memory element according to another aspect of the present invention is formed in a first conductivity type first impurity diffusion layer formed in a semiconductor substrate, and in a region of the semiconductor substrate away from the first impurity diffusion layer. A first conductivity type second impurity diffusion layer; a first gate insulating film formed on a channel region of the semiconductor substrate between the first impurity diffusion layer and the second impurity diffusion layer; A first gate electrode formed on the first gate insulating film; a second gate insulating film formed on the first gate electrode; a second gate electrode formed on the second gate insulating film; The shape of the first impurity diffusion layer in plan view has an L shape.

  A nonvolatile memory device according to one embodiment of the present invention includes a plurality of the nonvolatile memory elements described above.

  ADVANTAGE OF THE INVENTION According to this invention, the non-volatile memory element and non-volatile memory device which enabled it to suppress drain disturbance can be provided.

It is a figure which shows typically the structural example of the non-volatile memory element 100 which concerns on embodiment. It is a figure which shows typically the 1st structural example of the non-volatile memory device 200 which concerns on embodiment. 3 is a diagram schematically illustrating a second configuration example of a nonvolatile memory device 200. FIG. 3 is a diagram schematically illustrating a third configuration example of the nonvolatile memory device 200. FIG. FIG. 10 is a diagram showing a bias state at the time of erasing operation on a selected memory in the nonvolatile memory device 200 FIG. 6 is a diagram schematically showing a modification of the nonvolatile memory device 200. 6 is a diagram schematically showing a first modification of the nonvolatile memory element 100. FIG. 6 is a diagram schematically showing a second modification of the nonvolatile memory element 100. FIG. It is a figure which shows typically the structural example of the non-volatile memory element 500 which concerns on a comparative example. It is a figure which shows the suppression effect of the drain disturbance by embodiment. It is a figure which shows the reduction effect of the junction leak by embodiment. It is a figure for demonstrating a subject.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof is omitted.

(Nonvolatile memory element)
First, a configuration example of the nonvolatile memory element according to the embodiment of the present invention will be described.
FIG. 1 is a diagram schematically illustrating a configuration example of a nonvolatile memory element 100 according to an embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a nonvolatile memory of FIG. FIG. 4 is a cross-sectional view of the memory element 100 taken along the line A1-A′1. In FIG. 1A and FIG. 1B, the scale of the nonvolatile memory element 100 is changed. Further, the X axis and the Y axis are orthogonal to each other in plan view, for example, the X axis is a direction parallel to the channel length direction of the nonvolatile memory element 100, and the Y axis is in the channel width direction of the nonvolatile memory element 100. Parallel direction. The nonvolatile memory element 100 is, for example, one memory cell among a plurality of memory cells included in the EEPROM.

  As shown in FIGS. 1A and 1B, the nonvolatile memory element 100 is formed in, for example, an N-type well diffusion layer 3 formed in a silicon substrate 1 and the well diffusion layer 3. A P-type first impurity diffusion layer (drain-side impurity diffusion layer) 10 and a P-type second impurity diffusion layer (source-side impurity diffusion layer) formed in a region of the well diffusion layer 3 away from the first impurity diffusion layer. Impurity diffusion layer) 20 and a tunnel formed on part of channel region 6 (N-type region 5 described later) between first impurity diffusion layer 10 and second impurity diffusion layer 20 in well diffusion layer 3. Gate insulating film 30, floating gate electrode 40 formed on tunnel gate insulating film 30, gate insulating film 50 formed on floating gate electrode 40, and control gate electrode 60 formed on gate insulating film 50 And formed in the well diffusion layer 3 Having an STI layer 7, an impurity diffusion layer of the N type formed in the well diffusion layer 3 and the (N + layer) 9, a.

  The channel region 6 includes, for example, N-type threshold adjustment layers (N− layers) 17 and 27 having a higher N-type impurity concentration than the well diffusion layer 3, and N sandwiched between the threshold adjustment layers 17 and 27. And a mold region (region near the surface of the well diffusion layer 3) 5. The threshold adjustment layers 17 and 27 are impurity diffusion layers for adjusting the threshold of the programmed state. The threshold adjustment layers 17 and 27 have, for example, the same N-type impurity concentration.

  As shown in FIG. 1A, the first impurity diffusion layer 10 includes a first extension region 11 extending from the channel region 6 in the first direction and a first extension region 11 in a plan view. And a second extending region 12 extending in a second direction intersecting the first direction. That is, the shape of the first impurity diffusion layer 10 in plan view (hereinafter referred to as a planar shape) is a shape having the first extending region 11 and the second extending region 12.

  For example, the first direction is the minus (−) direction of the X axis, and the second direction is the minus (−) direction of the Y axis that is orthogonal to the X axis in plan view. In the following description, the minus (−) direction of the X axis is referred to as the −X direction, and the plus (+) direction of the X axis is referred to as the + X direction. Further, the minus (−) direction of the Y axis is referred to as the −Y direction, and the plus (+) direction of the Y axis is referred to as the + Y direction. In FIG. 1A, the second extension region 12 extends in the −Y direction from the −X direction end of the first extension region 11, and the planar shape of the first impurity diffusion layer 10 is L. The case where it is the shape of a character (henceforth L shape) is shown.

  As shown in FIG. 1B, the first impurity diffusion layer 10 includes a drain layer (P + layer) 15 and a PDD layer (P drift diffusion: P layer) 16 having a P-type impurity concentration lower than that of the drain layer 15. And have. The positional relationship between each layer constituting the first impurity diffusion layer 10 and the threshold adjustment layer 17 will be described. The drain layer 15 is located at the end of the second extending region 12 in the −Y direction. The PDD layer 16 is located between the drain layer 15 and the end portion in the + X direction of the first extension region 11 (that is, the end portion on the channel region 6 side). The PDD layer 16 is in contact with the drain layer 15 and the threshold adjustment layer 17. The threshold adjustment layer 17 is covered with the control gate electrode 60.

As shown in FIG. 1B, the PDD layer 16 may be continuously formed from between the drain layer 15 and the threshold adjustment layer 17 to below the drain layer 15. A drain contact electrode 19 is formed on the drain layer 15. That is, the first impurity diffusion layer 10 has a drain contact at the end of the second extending region.
As shown in FIG. 1A, the planar shape of the second impurity diffusion layer 20 includes a third extension region 21 extending from the channel region 6 in the third direction and a third extension region 21 to a second extension region 21. 3 is a shape having a fourth extending region 22 extending in a fourth direction intersecting with the direction 3. For example, the third direction is the + X direction, and the fourth direction is the + Y direction. In FIG. 1A, the fourth extending region 12 extends in the + Y direction from the end of the third extending region 11 in the + X direction, and the planar shape of the second impurity diffusion layer 20 is L-shaped. The case is shown.

As shown in FIG. 1B, the second impurity diffusion layer 20 includes a source layer (P + layer) 25 and a PDD layer (P layer) 26 having a P-type impurity concentration lower than that of the source layer 25. For example, the source layer 25 has the same P-type impurity concentration as the drain layer 15, and the PDD layer 26 has the same P-type impurity concentration as the PDD layer 16.
The positional relationship between each layer constituting the second impurity diffusion layer 20 and the threshold adjustment layer 27 will be described. The source layer 25 is located at the end of the fourth extending region 22 in the + Y direction. Further, the PDD layer 26 is located at the −X direction end of the source layer 25 and the third extension region 21 (that is, the end on the channel region 6 side). The PDD layer 26 is in contact with the source layer 25 and the threshold adjustment layer 27, respectively. The threshold adjustment layer 27 is covered with the control gate electrode 60.

As shown in FIG. 1B, the PDD layer 26 may be continuously formed from between the source layer 25 and the threshold adjustment layer 27 to below the source layer 25. A source contact electrode 29 is formed on the source layer 25. That is, the second impurity diffusion layer 20 has a source contact at the end of the fourth extension region.
In FIG. 1A, the first impurity diffusion layer 10 and the second impurity diffusion layer 20 have the same shape and the same size in a plan view, and are point-symmetric with respect to the center of the channel region 6. The case where it is arranged is shown.

The tunnel gate insulating film 30 is made of, for example, a silicon oxide film (SiO ₂ film). The floating gate electrode 40 is made of, for example, a polysilicon film (Poly-Si film). As shown in FIG. 1B, sidewalls 41 made of, for example, a silicon oxide film are formed on both side surfaces of the floating gate electrode 40.
The gate insulating film 50 is made of, for example, a silicon oxide film. For example, the gate insulating film 50 includes, for example, a thermal oxide film (SiO ₂ film) 51 formed by thermally oxidizing a polysilicon film, and an LPCVD film formed on the thermal oxide film 51 by the LPCVD method. (SiN film) 52 and a three-layer structure of HLD film (SiO ₂ film) 53 formed on LPCVD film 52 by the HLD method.

  The control gate electrode 60 is made of, for example, a polysilicon film. On the side surfaces on both sides of the control gate electrode 60, sidewalls 61 made of, for example, a silicon oxide film are formed. An insulating film 70 is disposed between the control gate electrode 60 and the side wall 61 and the silicon substrate 1. The insulating film 70 is, for example, a thermal oxide film 71 (formed by RTA) formed by thermally oxidizing the surface of the silicon substrate 1 and a thermal oxide film 72 (formed by a furnace body) formed on the thermal oxide film 71. And a three-layer structure of an HLD film 73 formed on the thermal oxide film 72.

The STI layer 7 is an insulating layer. The STI layer 7 is disposed between the second impurity diffusion layer 20 and the P-type impurity diffusion layer 9, and the lower portion of the well diffusion layer 3 exists under the STI layer 7. A body contact electrode 80 is disposed on the P-type impurity diffusion layer 9. Thereby, the potential of the well diffusion layer 3 (that is, the body potential) can be controlled via the body contact electrode 80 and the impurity diffusion layer 9.
In FIG. 1A, illustration of the sidewalls 41 and 61, the insulating film 70, and the body contact electrode 80 shown in FIG. 1B is omitted in order to avoid complication of the drawing. The same applies to FIGS. 2 to 4 and FIGS. 6 to 8 described later.

(Non-volatile storage device)
Next, a configuration example of the nonvolatile memory device according to the embodiment of the present invention will be described.
FIG. 2 is a plan view schematically showing a first configuration example of the nonvolatile memory device 200 according to the embodiment of the present invention. The nonvolatile storage device 200 is, for example, an EEPROM.
As shown in FIG. 2, the nonvolatile memory device 200 includes a silicon substrate 1, a plurality of nonvolatile memory elements (memory cells) 100 formed on the silicon substrate 1, a first bit line 110, and a second bit line. 120, a word line 130, and a body bias line (not shown).

  The first bit line 110 is a wiring that electrically connects the drain layers 15 of the nonvolatile memory elements 100 arranged in the row direction among the plurality of nonvolatile memory elements 100. The second bit line 120 is a wiring that electrically connects the source layers 25 of the nonvolatile memory elements 100 arranged in the row direction among the plurality of nonvolatile memory elements 100. The word line 130 is a wiring that electrically connects the control gate electrodes 60 of the nonvolatile memory elements 100 arranged in the column direction among the plurality of nonvolatile memory elements 100. The body bias line is a wiring for controlling the body potential.

  The first bit line 110, the second bit line 120, the word line 130, and the body bias line are disposed above the silicon substrate 1 via an interlayer insulating film (not shown). The nonvolatile memory element 100 may include other elements formed on the silicon substrate 1, other circuits, and the like. In FIG. 2 and FIGS. 3, 4, and 6 to be described later, the body bias lines are not shown in order to avoid complication of the drawings (in FIG. 1B and FIG. 5, the body bias lines are omitted). Line 140 is shown.)

FIG. 3 is a plan view schematically showing a second configuration example of the nonvolatile memory device 200. As shown in FIG. 3, each of the plurality of nonvolatile memory elements 100 included in the nonvolatile memory device 200 includes another adjacent nonvolatile memory device 200, the second extended region 12, and the fourth extended region 22. At least one of them may be shared.
That is, at least two adjacent nonvolatile memory elements 100 share the first impurity diffusion layer 10 with other adjacent nonvolatile memory elements 100, and the shared first impurity diffusion layer 10 is (L It may have a T-shape (part of the characters overlap each other). Similarly, at least two adjacent nonvolatile memory elements 100 share the second impurity diffusion layer 20 with other adjacent nonvolatile memory elements 100, and the shared second impurity diffusion layer 20 is viewed in plan view ( It may have a T-shape in which L-shaped portions overlap each other. Thereby, the nonvolatile memory device 200 can be reduced (shrink) as compared with the first configuration example shown in FIG.

  FIG. 4 is a plan view schematically showing a third configuration example of the nonvolatile memory device 200. As shown in FIG. 4, in the nonvolatile memory device 200, a plurality of nonvolatile memory elements 100 may be arranged in the row direction and in the column direction orthogonal to the row direction in plan view (that is, in a matrix form). May be arranged). The row direction is a direction parallel to one of the X axis and the Y axis, and the column direction is a direction parallel to the other of the X axis and the Y axis.

  In the third configuration example shown in FIG. 4, the plurality of nonvolatile memory elements 100 are connected to the other nonvolatile memory elements 100 adjacent in the row direction, and the second extension region of the first impurity diffusion layer 10. 12 or the fourth extended region 22 of the second impurity diffusion layer 20 is arranged so as to share each other. That is, the shared first impurity diffusion layer 10 and the shared second impurity diffusion layer 20 each have a T shape. As a result, the nonvolatile memory device 200 is reduced in size.

In addition, the first bit line 110 and the second bit line 120 are extended in the row direction above the nonvolatile memory element 100 via an interlayer insulating film (not shown).
The first bit line 110 is connected to the drain contact electrodes 19 of the plurality of nonvolatile memory elements 100 arranged in the row direction, and the second bit line 120 is connected to the plurality of nonvolatile memory elements 100 arranged in the row direction. The source contact electrodes 29 are respectively connected. As a result, the first bit line 110 causes the first impurity diffusion layers 10 of the plurality of nonvolatile memory elements 100 arranged in the row direction to conduct with each other, and the second bit line 120 has a plurality of nonvolatile elements arranged in the row direction. The second impurity diffusion layers 20 of the memory element 100 are made conductive.

  Further, in the third configuration example shown in FIG. 4, the control gate electrodes 60 of the plurality of nonvolatile memory elements 100 arranged in the row direction are continuously formed along the column direction. A control gate contact electrode 150 is formed on one end of the control gate electrode 60 in the column direction. The word line 130 extends in the column direction above the nonvolatile memory element 100 via an interlayer insulating film (not shown), and is connected to the control gate contact electrode 150.

  In this embodiment, the silicon substrate 1 corresponds to the “semiconductor substrate” of the present invention, and the tunnel gate insulating film 30 corresponds to the “first gate insulating film” of the present invention. The floating gate electrode 40 corresponds to the “first gate electrode” of the present invention, and the gate insulating film 50 corresponds to the “second gate insulating film” of the present invention. Further, the control gate electrode 60 corresponds to the “second gate electrode” of the present invention. The PDD layer 16 corresponds to the “drift layer” of the present invention, and the well diffusion layer 3 corresponds to the “third impurity diffusion layer” of the present invention. Further, the first bit line 110 corresponds to the “first wiring” of the present invention, and the second bit line 120 corresponds to the “second wiring” of the present invention.

(Effect of embodiment)
The embodiment of the present invention has the following effects.
(1) When the plurality of nonvolatile memory elements 100 are arranged in, for example, a matrix, the second extending region 12 may be arranged in an empty space between one and the other of the adjacent nonvolatile memory elements 100. it can. Thereby, without increasing the arrangement interval of the nonvolatile memory elements 100 (that is, without impairing the arrangement density of the nonvolatile memory elements 100), from the end of the first impurity diffusion layer 10 on the channel region 6 side, The distance to the opposite end of the channel region 6 can be increased. Therefore, it is possible to increase the distance (i.e., the drain drift length) L _D from the end of the channel region 6 side of the PDD layer 16 to the edge of the drain layer 15 side. Thereby, in the non-selected memory, unintentional injection of charges from the drain layer 15 to the floating gate electrode 40 (ie, drain disturb) can be suppressed.

This effect will be described more specifically by taking the case where the selected memory is changed from the write state to the erase state as an example.
FIG. 5 is a conceptual diagram showing a bias state at the time of erasing operation on the selected memory in the nonvolatile memory device 200. As shown in FIG. 5, the voltage VM or VH is applied to the drain layer 15 of the selected memory via the first bit line 110 (| VM | <| VH |). Further, the control gate electrode 560 of the selected memory is fixed at 0V. Further, the impurity diffusion layer 9 of the selected memory is fixed to VH via the body bias line 140. As a result, holes are injected from the drain layer 15 of the selected memory into the floating gate electrode 40, and the selected memory is rewritten from the written state to the erased state.

Here, the first bit line 110 connected to the drain layer 15 of the selected memory is also connected to the drain layer 15 of the non-selected memory, and VM or VH is also applied to the drain layer 15 of the non-selected memory. However, for example, as illustrated in FIG. 1 (a), the planar shape of the first impurity diffusion layer 10 having a drain layer 15 is, for example, L-shaped, it is possible to increase the drain drift length L _D, a drain The electric field between the layer 15 and the floating gate electrode 40 can be weakened. Thereby, drain disturbance can be suppressed. The VM can be set to 5.5V, for example, and the VH can be set to 13V, for example.
(2) Further, since it is possible to increase the drain drift length L _D, it is possible to reduce the drain of the nonvolatile memory element, a junction leakage between the body.

(Modification)
(1) In the above embodiment, as shown in FIG. 4, the first bit line 110 and the second bit line 120 are extended in the row direction, and the word line 130 is extended in the column direction. Explained the case. However, the embodiment of the present invention is not limited to this.
FIG. 6 is a plan view schematically showing a modification of the nonvolatile memory device 200. As shown in FIG. 6, the first bit line 110 and the second bit line 120 may extend in the column direction instead of the row direction. Even in such a configuration, it is possible to increase the drain drift length L _D, the same effect as the effect of Embodiment (1) (2).
(2) In the above embodiment, as shown in FIG. 1A, the second extension region 12 of the first impurity diffusion layer 10 extends from the first extension region 11 in the −Y direction. Explained the case. However, the present embodiment is not limited to this.

FIG. 7 is a plan view schematically showing a first modification of the nonvolatile memory element 100. As shown in FIG. 7, the second extension region 12 may extend from the first extension region 11 in the + Y direction. That is, the second direction and the fourth direction of the present invention may be the same direction. In FIG. 7, the first impurity diffusion layer 10 and the second impurity diffusion layer 20 have the same shape and the same size in plan view, and the channel along the direction parallel to the channel width (that is, the Y axis). The case where it arrange | positions axisymmetrically with respect to the line which passes along the center of the area | region 6 is shown. Even in such a configuration, it is possible to increase the drain drift length L _D, the same effect as the effect of Embodiment (1) (2).

(3) In the above embodiment, as shown in FIG. 1A, the planar shape of the second impurity diffusion layer 20 is the third extended region 21 extending in the + X direction from the channel region 6. In addition, a case has been described in which the shape has the fourth extending region 22 extended in the + Y direction from the third extending region 21. However, the present embodiment is not limited to this.
FIG. 8 is a plan view schematically showing a second modification of the nonvolatile memory element 100. The planar shape of the second impurity diffusion layer 20 may be a shape having only the third extended region 21. That is, the planar shape of the second impurity diffusion layer 20 may be a straight belt shape instead of the L shape. Even in such a configuration, it is possible to increase the drain drift length L _D, the same effect as the effect of Embodiment (1) (2).

(4) In the above embodiment, the case where the shape of the first impurity diffusion layer 10 in a plan view is one L-shape has been described. However, the present invention is not limited to this. The shape of the first impurity diffusion layer 10 in plan view may have an L shape, that is, a multi-stage L shape in which a plurality of L shapes are connected, or a shape in which other shapes are connected to the L shape. . Similarly, the shape of the second impurity diffusion layer 20 in plan view may be a multi-stage L shape in which a plurality of L shapes are connected, or a shape in which another shape is connected to the L shape. Even with such a configuration, the same effects as the effects (1) and (2) of the embodiment can be obtained.

(5) In the above embodiment, the case where the first conductivity type of the present invention is P type and the second conductivity type is N type has been described, but the present invention is not limited to this. The first conductivity type may be N-type and the second conductivity type may be P-type. Even in such a case, the same effects as the effects (1) and (2) of the embodiment can be obtained.

(Verification)
The inventor has verified the effects of the embodiment as follows.
(1) Comparative Example FIG. 9 is a plan view schematically showing a configuration example of a nonvolatile memory element 500 according to a comparative example of the present invention. The nonvolatile memory element 500 is one memory cell among a plurality of memory cells included in the EEPROM.

  As shown in FIG. 9, the nonvolatile memory element 500 includes a first impurity diffusion layer 410 formed on the silicon substrate and a second impurity diffusion layer formed in a region away from the first impurity diffusion layer 410 of the silicon substrate. 420, a floating gate electrode 440 formed through a tunnel gate insulating film on a channel region between the first impurity diffusion layer 410 and the second impurity diffusion layer 420 of the silicon substrate, and a gate on the floating gate electrode 440 And a control gate electrode 460 formed with an insulating film interposed therebetween. The first impurity diffusion layer 410 includes a P-type drain layer (P + layer) 415 and a PDD layer (P layer) 416. The second impurity diffusion layer 420 includes a P-type source layer (P + layer) 425 and a PDD layer (P layer) 426. A drain contact electrode 419 is formed on the drain layer 415, and a source contact electrode 429 is formed on the source layer 425.

(2) Effect of suppressing drain disturbance The nonvolatile memory element 100 shown in FIGS. 1A and 1B and the nonvolatile memory element 500 shown in FIG. 9 were prepared. The nonvolatile memory elements 100 and 500 prepared here have a gate length Lsg of 0.260 μm. In these nonvolatile memory elements 100 and 500, the drain potential VD is set to 5.5 (V) and the body potential VB is set to 13 (V) (drain voltage = VD−VB = −7.5 (V). Set to.) Next, the nonvolatile memory elements 100 and 500 in which VD and VB were set as described above were placed in an atmosphere of 90 ° C., and the amount of change ΔVth in threshold voltage with respect to the elapsed time (stress time) was measured.

  FIG. 10 is a diagram illustrating the drain disturb suppressing effect according to the embodiment of the present invention. The vertical axis in FIG. 10 indicates the change amount ΔVth of the threshold voltage in logarithm, and the vertical axis indicates the elapsed time (stress time) in logarithm. As shown in FIG. 10, it was confirmed that the nonvolatile memory element 100 had a very small threshold voltage change amount ΔVth with respect to the elapsed time as compared with the nonvolatile memory element 500 and the drain disturbance was sufficiently suppressed.

(3) Effect of reducing junction leak The nonvolatile memory element 100 shown in FIGS. 1A and 1B and the nonvolatile memory element 500 shown in FIG. 9 were prepared. Next, the threshold voltage Vth of the nonvolatile memory elements 100 and 500 is set to −3.2 (V), respectively, and the breakdown voltage BVDSS is set in the Eace state where the control gate electrode and the source layer are set to the ground potential of 0V. Was measured respectively. The drain current difference ΔID was calculated from the measurement result of the breakdown voltage BVDSS.

FIG. 11 is a diagram illustrating the effect of reducing junction leakage according to the embodiment of the present invention. The vertical axis of FIG. 11 represents the drain current difference ΔID. ΔID = │ID ₂₀₀ │-│ID ₁₀₀ │. ID ₂₀₀ is a drain current when the BVDSS of the nonvolatile memory device 200 is measured. ID ₁₀₀ is a drain current when BVDSS of the volatile memory element 100 is measured. Further, the horizontal axis of FIG. 11 indicates the absolute value | VD−VB | of the drain voltage. As shown in FIG. 11, since ΔID is large in the range of | VD−VB | ≈10 to 15 (V), the effect of reducing junction leakage was confirmed.

  Further, in the non-volatile memory element 100 during standby, that is, in the non-selected memory of the non-volatile memory device 200, VD = VM or VH and VB = VH are set. For this reason, in the case of | VM−VH | ≈10 to 15 (V), it has been found that the effect of reducing the junction leak is remarkable in the non-selected memory, and the standby power consumption may be reduced. Moreover, even in the case of | VM-VH | <10 (V), it was confirmed that the junction leak was low equivalent to or higher than that of the comparative example.

<Others>
The present invention is not limited to the embodiments and modifications described above. Based on the knowledge of those skilled in the art, design changes and the like may be added to the embodiments and modifications, and the embodiments and modifications may be arbitrarily combined, and aspects in which such changes are added are also included in the present invention. Included in the range.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Well diffused layer 5 N type area | region 6 Channel area | region 7 STI layer 9 Impurity diffused layer 10 1st impurity diffused layer 11 1st extended area 12 2nd extended area 15 Drain layers 16, 26 PDD layers 17, 27 Threshold adjustment layer 19 Drain contact electrode 20 Second impurity diffusion layer 21 Third extended region 22 Fourth extended region 25 Source layer 29 Source contact electrode 30 Tunnel gate insulating film 40 Floating gate electrodes 41 and 61 Side wall 50 Gate insulating film 51, 71, 72 Thermal oxide film 52 LPCVD film 53, 73 HLD film 60 Control gate electrode 80 Body contact electrode 100 Non-volatile memory element 110 First bit line 120 Second bit line 130 Word line 140 Body bias line 150 Control gate contact Electrode 200 Nonvolatile memory device

Claims (20)

A first conductivity type first impurity diffusion layer formed on the semiconductor substrate;
A first conductivity type second impurity diffusion layer formed in a region of the semiconductor substrate away from the first impurity diffusion layer;
A first gate insulating film formed on a channel region between the first impurity diffusion layer and the second impurity diffusion layer in the semiconductor substrate;
A first gate electrode formed on the first gate insulating film;
A second gate insulating film formed on the first gate electrode;
A second gate electrode formed on the second gate insulating film,
The first impurity diffusion layer is a plan view,
A first extension region extending in a first direction from the channel region;
A non-volatile memory element comprising: a second extending region extending from the first extending region in a second direction intersecting the first direction. The second impurity diffusion layer is a plan view,
A third extending region extending in a third direction from the channel region;
The nonvolatile memory element according to claim 1, further comprising: a fourth extending region extending from the third extending region in a fourth direction intersecting with the third direction.   The nonvolatile memory element according to claim 2, wherein the first impurity diffusion layer and the second impurity diffusion layer have the same shape and the same size in plan view.   The nonvolatile memory element according to claim 3, wherein the first impurity diffusion layer and the second impurity diffusion layer are arranged point-symmetrically with respect to the center of the channel region in plan view. The first impurity diffusion layer has a drain layer in the second extending region,
5. The nonvolatile memory element according to claim 2, wherein the second impurity diffusion layer has a source layer in the fourth extending region. 6. The first impurity diffusion layer has a drain contact at an end of the second extension region,
The nonvolatile memory element according to claim 5, wherein the second impurity diffusion layer has a source contact at an end of the fourth extending region.   The first impurity diffusion layer has a drift layer having an impurity concentration of a first conductivity type lower than that of the drain layer between the drain layer and an end of the first extension region on the channel region side. The non-volatile memory element according to any one of claims 1 to 6. A third impurity diffusion layer of a second conductivity type formed on the semiconductor substrate,
The nonvolatile memory element according to claim 1, wherein the first impurity diffusion layer and the second impurity diffusion layer are formed in the third impurity diffusion layer. A first conductivity type first impurity diffusion layer formed on the semiconductor substrate;
A first conductivity type second impurity diffusion layer formed in a region of the semiconductor substrate away from the first impurity diffusion layer;
A first gate insulating film formed on a channel region between the first impurity diffusion layer and the second impurity diffusion layer in the semiconductor substrate;
A first gate electrode formed on the first gate insulating film;
A second gate insulating film formed on the first gate electrode;
A second gate electrode formed on the second gate insulating film,
The non-volatile memory element in which the shape of the first impurity diffusion layer in a plan view has an L shape.   The nonvolatile memory element according to claim 9, wherein a shape of the second impurity diffusion layer in a plan view has an L shape. The second gate electrode is rectangular in plan view;
The first impurity diffusion layer extends in a first direction intersecting the long side from the center of the long side of the control gate electrode in plan view, and further, a second crossing the first direction. L-shaped extending in the direction,
The second impurity diffusion layer extends in the third direction intersecting the long side from the center of the other long side of the control gate electrode in plan view, and further intersects from the third direction. The nonvolatile memory element according to claim 10, wherein the non-volatile memory element has an L shape extending in a fourth direction opposite to the second direction.   The first impurity diffusion layer includes an L-shaped drift layer and a drain layer having an impurity concentration of the first conductivity type higher than that of the drift layer formed at the L-shaped end away from the channel region. The nonvolatile memory element according to claim 9, further comprising:   A non-volatile memory device comprising a plurality of the non-volatile memory elements according to claim 1.   The non-volatile memory according to claim 13, wherein at least two non-volatile memory elements adjacent to each other among the plurality of non-volatile memory elements share the second extended region with another adjacent non-volatile memory element. apparatus. A plurality of the nonvolatile memory elements according to any one of claims 2 to 6,
Among the plurality of nonvolatile memory elements, at least two adjacent nonvolatile memory elements share the second extended region with other adjacent nonvolatile memory elements,
The non-volatile memory device in which at least two non-volatile memory elements adjacent to each other among the plurality of non-volatile memory elements share the fourth extended region with other adjacent non-volatile memory elements.   A non-volatile memory device comprising a plurality of the non-volatile memory elements according to claim 9.   Among the plurality of nonvolatile memory elements, at least two adjacent nonvolatile memory elements share the first impurity diffusion layer with other adjacent nonvolatile memory elements, and the shared first impurity diffusion layer is The nonvolatile memory device according to claim 16, which has a T shape in a plan view. A plurality of the nonvolatile memory elements according to claim 10 or 11,
Among the plurality of nonvolatile memory elements, at least two adjacent nonvolatile memory elements share the first impurity diffusion layer with other adjacent nonvolatile memory elements, and the shared first impurity diffusion layer is It has a T shape in plan view,
Of the plurality of nonvolatile memory elements, at least two adjacent nonvolatile memory elements share the second impurity diffusion layer with other adjacent nonvolatile memory elements, and the shared second impurity diffusion layer is A non-volatile memory device having a T shape in plan view.   The nonvolatile memory device according to any one of claims 13 to 18, wherein the plurality of nonvolatile memory elements are respectively arranged in a row direction and a column direction orthogonal to the row direction in a plan view. A first wiring for electrically connecting the first impurity diffusion layers of the nonvolatile memory elements arranged in the row direction or the column direction among the plurality of nonvolatile memory elements;
20. The nonvolatile memory according to claim 19, further comprising: a second wiring that electrically connects the second impurity diffusion layers of the nonvolatile memory elements arranged in the row direction or the column direction among the plurality of nonvolatile memory elements. Sex memory device.

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