JP2015198175A - nitride semiconductor device - Google Patents

Abstract

A forward surge withstand capability of a nitride semiconductor device is improved. A substrate 11 and a buffer layer 12, an electron transit layer 13 made of a nitride semiconductor provided in an upper layer of the buffer layer 12, and an electron transit layer 13 provided on an upper layer and more average than the electron transit layer 13. A semiconductor laminate including an electron supply layer 14 made of a nitride semiconductor having a wide band gap, an anode electrode 17A provided on at least a part of the semiconductor layers constituting the semiconductor laminate, and the semiconductor laminate A cathode electrode 17C provided on and separated from the anode electrode 17A on at least a part of the semiconductor layers constituting the semiconductor layer, and a forward voltage is applied between the anode electrode 17A and the cathode electrode 17C. In this state, a forward current flows in a region other than the two-dimensional electron gas generation region generated at the interface between the electron transit layer 13 and the electron supply layer 14. Provision of the order of the current path. [Selection] Figure 1

Description

  The present invention relates to a nitride semiconductor device such as a Schottky barrier diode.

  Wide bandgap semiconductors represented by nitride semiconductors have high dielectric breakdown voltage, good electron transport properties, and good thermal conductivity, so they are very attractive as materials for semiconductor devices for high temperature, high power, or high frequency. Is. Further, for example, a field effect transistor (FET) having an AlGaN / GaN heterojunction structure generates two-dimensional electron gas (2DEG) at the heterojunction interface due to piezo polarization and spontaneous polarization. Yes. This 2DEG has high electron mobility and carrier density, and has attracted much attention. Therefore, a nitride semiconductor device such as a Schottky Barrier Diode (SBD) using such an AlGaN / GaN heterojunction structure has high breakdown voltage, low on-resistance, and fast switching speed, and power switching Very suitable for application.

  Here, in the SBD, the surge withstand characteristics are important. The surge resistance is a specification that guarantees that the semiconductor device is not broken against a surge current. Further, the withstand capability of surge current flowing in the forward direction is referred to as forward surge withstand capability.

  The surge current is a current that flows in an unsteady state such as when the power is turned on and off, and is larger than that during steady operation. Other than when the power is turned on / off, there may be a case where a current caused by a lightning strike or a sudden large current from another device enters the circuit through the power line, or it is generated by absorbing a strong electromagnetic field around it. . When such a surge current adversely affects the operation of the nitride semiconductor device, there is a possibility that the system using the nitride semiconductor device may be adversely affected. For this reason, surge withstand capability is one of important performance indicators of semiconductor devices including power devices used in electric systems.

International Publication WO2011 / 162243

  However, in the conventional SBD as a nitride semiconductor device using a nitride semiconductor such as GaN, the forward surge withstand capability is limited due to the characteristic that the forward current is saturated. There was a problem that the surge resistance was low.

  The present invention has been made in view of the above, and an object thereof is to provide a nitride semiconductor device capable of improving the forward surge resistance.

  In order to solve the above-described problems and achieve the above object, a nitride semiconductor device according to the present invention includes a base, a first semiconductor layer made of a nitride semiconductor provided on an upper layer of the base, and a first semiconductor layer And a semiconductor stacked body including a second semiconductor layer made of a nitride semiconductor having an average band gap wider than that of the first semiconductor layer, and at least a part of the semiconductor layers constituting the semiconductor stacked body An anode electrode provided on the layer, and a cathode electrode provided on and separated from the anode electrode on at least a part of the semiconductor layers constituting the semiconductor laminate, the anode electrode and the cathode electrode With the voltage applied in the forward direction between the anode electrode and the cathode through the region other than the two-dimensional electron gas generation region generated at the interface between the first semiconductor layer and the second semiconductor layer. Characterized in that it has a current path through which a current flows between the electrodes.

The nitride semiconductor device according to the present invention is the Al _x Ga _{1 according to} the above invention, wherein the semiconductor stacked body is selectively provided above the second semiconductor layer and has an average band gap narrower than that of the second semiconductor layer. The semiconductor device further includes a third semiconductor layer made of _-xN .

  In the nitride semiconductor device according to the present invention, in the above invention, the third semiconductor layer is made of an n-type semiconductor containing an n-type impurity, and the portion of the third semiconductor layer constitutes at least a part of the current path. Features.

  The nitride semiconductor device according to the present invention is characterized in that, in the above invention, the thickness of the third semiconductor layer is greater than 20 nm and not greater than 200 nm.

In the nitride semiconductor device according to the present invention, in the above invention, the impurity concentration of the n-type impurity contained in the third semiconductor layer is 3.0 × 10 ¹⁷ cm ⁻³ or more and 3.0 × 10 ¹⁹ cm ⁻³ or less. It is characterized by being.

The nitride semiconductor device according to the present invention is characterized in that, in the above invention, the impurity concentration of the n-type impurity contained in the third semiconductor layer is 6.0 × 10 ¹⁷ cm ⁻³ or more.

The nitride semiconductor device according to the present invention is characterized in that, in the above invention, the impurity concentration of the n-type impurity contained in the third semiconductor layer is 1.0 × 10 ¹⁹ cm ⁻³ or less.

  In the nitride semiconductor device according to the present invention, in the above invention, a fourth semiconductor layer made of a p-type semiconductor containing a p-type impurity selectively is provided above the first semiconductor layer, and the anode electrode and the fourth semiconductor layer Are electrically connected, and the fourth semiconductor layer and the first semiconductor layer constitute at least part of the current path.

  In the nitride semiconductor device according to the present invention, in the above invention, a fifth semiconductor layer made of a p-type semiconductor selectively including a p-type impurity is provided on an upper layer of a layer constituting the semiconductor stacked body, and Between the first semiconductor layer and the first semiconductor layer is a sixth semiconductor layer made of an n-type semiconductor containing an n-type impurity, and a current path is formed from the first semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer. It is characterized by being.

  The nitride semiconductor device according to the present invention is characterized in that, in the above invention, the anode electrode is a Schottky electrode and the cathode electrode is an ohmic electrode.

  The nitride semiconductor device according to the present invention can improve the forward surge withstand capability.

FIG. 1 is a schematic cross-sectional view showing an SBD according to Embodiment 1 of the present invention. FIG. 2 is a graph showing the forward voltage dependency of the forward current when an n-GaN layer is adopted as the field plate layer in the SBD according to the first embodiment of the present invention. FIG. 3 is a graph showing the forward voltage dependence of the forward current when the p-GaN layer is adopted as the field plate layer in the SBD according to the first embodiment of the present invention. FIG. 4 is a graph showing the reverse bias dependence of the depletion layer width for each n-type impurity concentration of the field plate layer in the SBD according to the first embodiment of the present invention. FIG. 5 is a graph showing the field plate length dependency of the breakdown voltage in the SBD according to the first embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing an SBD according to Embodiment 2 of the present invention. FIG. 7 is a schematic cross-sectional view showing an SBD according to Embodiment 3 of the present invention. FIG. 8 is a graph showing the forward voltage dependence of the forward current density in an SBD employing an i-GaN layer or an n-GaN layer as a field plate layer in the SBD according to the third embodiment of the present invention. FIG. 9 is a graph showing the cathode-anode voltage dependence of the depletion layer width when a reverse bias is applied to the SBD according to Embodiment 3 of the present invention. FIG. 10 is a schematic cross-sectional view showing an SBD as an examination target. FIG. 11 is a graph showing the forward characteristics of the SBD as the object of examination.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, this invention is not limited by the following embodiment. In the drawings, the same or corresponding elements are denoted by the same reference numerals as appropriate, and repeated descriptions are omitted as appropriate. Furthermore, it should be noted that the drawings are schematic, and dimensional relationships between elements may differ from actual ones. Even between the drawings, there are cases in which portions having different dimensional relationships and ratios are included. Further, “upper”, “upper” or “upper” and “lower”, “lower” or “lower” used in the description of the following embodiments are perpendicular to the main surface of the substrate of the semiconductor device, respectively. It should also be noted that the direction of moving away and the direction of approaching the main surface of the substrate are shown and do not necessarily coincide with the vertical direction in the mounting state of the semiconductor device.

  First, in describing embodiments of the present invention, in order to facilitate the understanding of the present invention, an intensive study conducted by the present inventor to solve the above-described problems will be described. First, a description will be given of a conventional nitride semiconductor device that has been the subject of intensive studies by the inventors.

  First, a Schottky barrier (SBD) as a conventional nitride semiconductor device that is the subject of study by the present inventor will be described. FIG. 10 is a schematic cross-sectional view showing an SBD as an object to be examined, and FIG. 11 is a graph showing an example of a forward characteristic that is a forward voltage dependency of a forward current in a conventional SBD.

  As shown in FIG. 10, the SBD 100 to be studied has a base body in which a buffer layer 102 is provided on a substrate 101. On the buffer layer 102, an electron transit layer 103 made of undoped gallium nitride (u-GaN) and an electron supply layer 104 made of AlGaN are sequentially stacked. On the electron supply layer 104, a field plate layer 105 made of GaN, an insulating film 106, and an anode electrode 107A and a cathode electrode 107C are selectively provided. The field plate layer 105, the insulating film 106, the anode electrode 107A, and the cathode electrode 107C have a shape extending along the direction perpendicular to the paper surface. Two-dimensional electron gas layers (2DEG layers) A and a are generated at the interface between the electron transit layer 103 and the electron supply layer 104. Since the field plate layer 105 is selectively provided on the electron supply layer 104, the carrier concentration (2DEG concentration) of the lower 2DEG layer a is lower than that of the 2DEG layer A.

  According to the knowledge of the present inventors, the SBD 100 using GaN configured as described above has forward characteristics as shown in FIG. That is, when the forward voltage is increased from 0V, the forward current starts to increase beyond the threshold voltage when the forward voltage is about 1V, and the forward current increases up to about 8V. However, when the forward voltage exceeds about 8V, the forward current stops increasing and becomes saturated. In the forward characteristics shown in FIG. 11, the forward current is a forward current of about 1 mm along the depth of the SBD 100 (the direction perpendicular to the paper surface). When this is the SBD 100 alone, the forward current is saturated at about 43 A, for example. Such forward current saturation limits the forward surge withstand capability.

  In view of this, the present inventor has examined a technique for improving the surge resistance in a conventional Schottky barrier diode (SiC-SBD) using silicon carbide (SiC) in order to improve the forward surge resistance in the SBD 100 described above. Went. In this SiC-SBD, a method of supplying holes from the PN junction to the drift layer when a surge current is generated is employed in order to improve surge resistance. As a result, the resistance of the SiC-SBD drift layer is lowered to change the conductivity, thereby improving the surge resistance. Specifically, first, when a surge current is generated in SiC-SBD, holes are supplied to the drift layer by turning on the PN junction. By supplying the holes, holes are further accumulated in the drift layer and the overall resistance is lowered, and a large forward current can flow between the anode electrode and the cathode electrode.

  However, it has been difficult to apply a surge withstand technology that is effective in SiC-SBD to nitride semiconductor devices such as SBD using GaN. That is, the SBD 100 described above is a lateral nitride semiconductor device that uses 2DEG as a channel. In such a nitride semiconductor device, when a p-type layer is formed in the vicinity of 2DEG serving as a channel in order to form a PN junction, the on-resistance may increase. Further, since it is difficult to control doping of the p-type impurity such as magnesium (Mg) to the GaN layer, there is a problem that it is difficult to obtain a good semiconductor layer.

  In addition, a method for improving the forward surge resistance by doping the field plate layer 105 provided on the electron supply layer 104 with a p-type impurity has been proposed (for example, Patent Document 1). However, when the present inventor examined this method, the details will be described later. However, it has been found that even if the field plate layer 105 is doped with a p-type impurity, it is difficult to improve the forward surge resistance. I came to get.

  In view of this, the present inventor has made various studies again, and in order to improve the forward surge withstand capability, the forward surge current is applied to a region other than the generation region of the 2DEG layers A and a as a channel when the forward surge current flows. It was recalled that it is preferable to newly provide a current path through which a current flows. Specifically, the present inventor firstly provides a current path through which a large current can flow by passing through other than the 2DEG layers A and a while passing through at least a part of the 2DEG layers A and a. I recalled to do. In addition, the inventor secondly recalled a method of providing a current path through which a large current flows along a path different from the 2DEG layers A and a without passing through the 2DEG layers A and a. It has also been recalled that such a current path is preferably configured to be turned on when a current larger than a steady current, such as a forward surge current, flows.

  By these methods, when a forward surge current is generated, the forward surge current flows along a current path provided to portions other than the 2DEG layers A and a. Therefore, compared to a conventional nitride semiconductor device such as the SBD 100 described above, it is possible to improve the resistance to forward surge current and improve the forward surge resistance. The embodiment described below has been devised based on the above-mentioned diligent study.

(Embodiment 1)
First, a Schottky barrier diode (SBD) as a nitride semiconductor device according to the first embodiment of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing an SBD according to the first embodiment.

  As shown in FIG. 1, in the SBD 10 according to the first embodiment, a buffer layer 12, an electron transit layer 13, and an electron supply layer 14 are sequentially stacked on a substrate 11. Further, an anode electrode 17A as a Schottky electrode is selectively provided in the recess portion 13a from which the electron supply layer 14 and the electron transit layer 13 are partially removed. A field plate layer 15 is selectively provided on the anode electrode 17A side on the electron supply layer. In addition, a cathode electrode 17C as an ohmic electrode is selectively provided in the recess portion 13b in which the electron supply layer 14 and the electron transit layer 13 are partially removed in a region separated from the field plate layer 15 and the anode electrode 17A. ing. An insulating film 16 is provided so as to cover at least a part of the electron supply layer 14 and the field plate layer 15 and the anode electrode 17A and the cathode electrode 17C.

The substrate 11 is, for example, a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, a GaN substrate, an AlN substrate, a silicon carbide (SiC) substrate, a carbon (C) substrate, or sapphire (Al ₂ O). ₃ ) It consists of a substrate. The buffer layer 12 is composed of a high resistance layer in which, for example, a plurality of AlGaN layers, GaN layers, AlN layers, or the like are stacked, and the average Al composition ratio is, for example, 0.15 to 0.25. Note that the buffer layer 12 may be semi-insulated by adding impurities such as C, Fe, and Mg to the buffer layer 12. Moreover, you may provide the various layers required for the structure of a nitride semiconductor device as needed. The substrate of the nitride semiconductor device is constituted by the substrate 11, the buffer layer 12, and other layers as necessary.

  The electron transit layer 13 as the first semiconductor layer is made of undoped gallium nitride (u-GaN) having a film thickness of, for example, 700 nm (0.7 μm). Note that a nitride semiconductor material other than GaN may be used as the material constituting the electron transit layer 13, and when AlGaN is used, the Al composition ratio is preferably 5% or less.

The electron supply layer 14 as the second semiconductor layer has a superlattice structure including a superlattice layer in which a plurality of at least two types of group III nitride semiconductors having different Al composition ratios and different band gaps are stacked. Specifically, the electron supply layer 14 in the first embodiment has, for example, a pseudo mixed crystal structure of Al _x Ga _1-x N having an average Al composition ratio X. This Al _x Ga _1-x N pseudo-mixed crystal structure has Al _x Ga _1-x N having an Al composition ratio x of various values of at least two different maximum Al composition ratio x1 or minimum Al composition ratio x2. It is composed of an AlGaN superlattice layer in which a plurality of layers are stacked. For the Al composition ratio x, x2 <X <x1. In addition, the average Al composition ratio X of the electron supply layer 14 is based on the premise that 0 <X <1 and the necessity of obtaining a desired 2DEG concentration in the 2DEG layer A having a high 2DEG concentration at the interface with the electron transit layer 13 is considered. Then, 10% to 40% (0.1 ≦ X ≦ 0.4) is preferable, 15% to 35% (0.15 ≦ X ≦ 0.35) is more preferable, and 20% to 30% ( 0.2 ≦ X ≦ 0.3) is more preferable. Further, from the viewpoint of sheet resistance in the Al _x Ga _1-x N superlattice layer, and also from the viewpoint of lattice relaxation that can be laminated freely against strain, the average Al composition ratio X of the electron supply layer 14 is preferably in the above range. . Here, the band gap of the electron supply layer 14 is an average band gap, specifically, a band gap value weighted (integrated) by the layer thickness ratio of each semiconductor layer constituting the stacked structure. The electron supply layer 14 is configured such that the average band gap is wider than the band gap of the electron transit layer 13.

Of the AlGaN layers constituting the electron supply layer 14, the Al _x1 Ga _1-x1 N layer having the maximum Al composition ratio x1 and the Al _x2 Ga _1-x2 N layer having the minimum Al composition ratio x2 are layered. Specifically, from the viewpoint that it is necessary to exude the electron wave function of the 2DEG layer A with a desired average Al composition ratio X or more, ie, a minimum atomic thickness of 2 atomic layers or more, for example, 0.5 nm or more. The thickness is 0 nm or less, preferably 0.5 nm or more and 3.5 nm or less, more preferably 0.5 nm or more and 3.0 nm or less. In the first embodiment, for example, the thickness is about 1.5 nm. In addition, the thickness of each Al _x Ga _1-x N layer is preferably less than or equal to the critical thickness in order not to cause misfit dislocations. Specifically, the critical film thickness of the Al _x Ga _1-x N layer is about 5 nm when the Al composition ratio x is 0.6 with respect to the lattice constant of the GaN layer, and the Al composition ratio x is 0.1. In some cases, it is about 100 nm. The critical film thickness is not necessarily limited to these film thicknesses because the film thickness differs depending on the adjacent layers in the stacked structure. Based on the above conditions, the film thickness, the number of layers, or the number of layers of each Al _x Ga _1-x N layer are appropriately determined according to the 2DEG concentration set concentration of the 2DEG layer A and the design of the nitride semiconductor device. The optimal value is selected. In the first embodiment, the 2DEG concentration is adjusted to be less than 3 × 10 ¹³ cm ^−2, for example.

The lower limit of the film thickness of the electron supply layer 14, and the Al _x2 Ga _1-x2 N layer of Al _x1 Ga _1-x1 N layer and the minimum Al composition ratio x2 of the electron supply layer 14 a maximum Al composition ratio x1 Considering that it is composed of a set of Al _x1 Ga _1-x1 N / Al _x2 Ga _1-x2 N superlattice layers, 2 nm or more is preferable, and considering increasing the 2DEG concentration of 2DEG layer A, 5 nm or more is preferable and 10 nm or more is more preferable. In addition, the upper limit of the film thickness of the electron supply layer 14 is preferably a critical film thickness or less at which misfit dislocation does not occur. Considering the limit of ohmic contact, 100 nm or less, preferably 50 nm or less, more preferably 30 nm or less. Is preferred. In the first embodiment, the thickness of the electron supply layer 14 is, for example, 20 nm.

A field plate layer 15 as a third semiconductor layer is selectively provided on the electron supply layer 14. Although details will be described later, the field plate layer 15 constitutes a part of a current path for flowing a forward surge current. The field plate layer 15 is a nitride semiconductor whose average band gap is narrower than the average band gap of the electron supply layer 14, more specifically, an In _u Al _v Ga _1-uv N layer (0 ≦ u ≦ 1). , 0 ≦ v ≦ 1, 0 ≦ u + v <1). As a result, the 2DEG concentration of 2DEG generated in the electron transit layer 13 below the field plate layer 15 is changed to at least two levels and reduced. The field plate layer 15 is made of, for example, an n-type semiconductor layer doped with an n-type impurity. Field plate layer 15 in the first embodiment is made of, for example, a GaN layer doped with Si as an n-type impurity.

  The electron transit layer 13, the electron supply layer 14, and the field plate layer 15 described above constitute the semiconductor stacked body in the first embodiment. In the case where an etching sacrificial layer is provided on the upper layer of the electron supply layer 14 due to the configuration of the nitride semiconductor device, the semiconductor stacked body includes the electron transit layer 13, the electron supply layer 14, the etching sacrificial layer, and the field plate layer 15. May be. In addition, the uppermost layer of the electron supply layer 14 can be substituted for the etching sacrificial layer.

  Further, the anode electrode 17A as the first electrode is selectively provided in the recess portion 13a that is recess-etched to the inside of the electron transit layer 13 in the formation region of the anode electrode 17A. The anode electrode 17A has, for example, a Ni / Au laminated structure in which the lower electrode layer is a Ni layer and the upper electrode layer is an Au layer. As a result, the anode electrode 17A makes Schottky contact with the 2DEG layer a generated in the lower layer of the field plate layer 15 from the side surface. The anode electrode 17A can also be provided on the electron supply layer 14. In this case, the anode electrode 17A is in Schottky contact with the 2DEG layer A generated in the electron transit layer 13 via the electron supply layer 14.

  The anode electrode 17A runs on the field plate layer 15 to form at least one step, and extends so as to protrude toward the cathode electrode 17C on the upper layer of the insulating film 16 formed in the step shape. doing. In the first embodiment, the anode electrode 17A is provided in contact with part of the side surface and the upper surface of the field plate layer 15. In the first embodiment, the field plate portion is provided in a shape having multiple steps on the anode electrode 17A, for example, two steps.

  Further, the cathode electrode 17C as the second electrode is selectively provided in the recess portion 13b that is recess-etched up to the electron transit layer 13 in the formation region of the cathode electrode 17C. The cathode electrode 17C has, for example, a Ti / Al laminated structure in which the lower electrode layer is a Ti layer and the upper electrode layer is an Al layer. Accordingly, the cathode electrode 17C is in ohmic contact with the 2DEG layer A generated in the lower layer of the electron supply layer 14 from the side surface. The cathode electrode 17C can also be provided on the electron supply layer 14. In this case, the cathode electrode 17 </ b> C is in ohmic contact with the 2DEG layer A generated in the electron transit layer 13 via the electron supply layer 14.

The insulating film 16 mainly protects the surfaces of the electron supply layer 14, the field plate layer 15, and the cathode electrode 17C. The insulating film 16 is made of, for example, silicon oxide (SiO ₂ ), but may be made of other materials, specifically, silicon nitride (SiN _x ), aluminum oxide (Al ₂ O ₃ : alumina), or the like. A plurality of types of materials may be appropriately combined or sequentially stacked. The SBD 10 according to the first embodiment is configured as described above.

  Next, the field plate layer 15 in the SBD 10 configured as described above will be described. As described above, the field plate layer 15 in the first embodiment is composed of an n-type semiconductor layer doped with an n-type impurity. Here, examples of the n-type impurity include silicon (Si), germanium (Ge), selenium (Se), tellurium (Te), sulfur (S), and oxygen (O).

First, the present inventor derived the electron concentration distribution and the hole concentration distribution in the field plate layer 15 when the forward voltage is 5V. As a result, when the field plate layer 15 is made of i-GaN not doped with impurities, holes are generated in the field plate layer 15 as the forward voltage increases, and these holes are generated in the 2DEG layer. It was found that A and a were injected. When holes are injected into the 2DEG layers A and a, it is considered that the 2DEG concentration Ns in the lower region at the end of the field plate layer 15 decreases, the access resistance increases, and the forward current does not increase significantly. In this case, since the channel resistance also increases, there is a problem that the portion of the anode electrode 17A generates heat. On the other hand, in the field plate layer 15 doped with n-type impurities to a predetermined impurity concentration or higher, holes were not accumulated, and it was also confirmed that the access resistance did not increase. In addition, since the forward current flows through the field plate layer 15 while passing at least part of the 2DEG layers A and a, the saturation current related to the forward current in the conventional SBD can be extremely increased. In addition, when the forward voltage was about 5 V, it was also confirmed that there was almost no difference in the forward current in the range where the n-type impurity concentration was about 10 ¹⁸ cm ⁻³ .

Furthermore, the present inventor has derived the electron concentration distribution and the hole concentration distribution of the field plate layer 15 when the forward voltage is 10V. Then, the inventor doped the n-type impurity at an impurity concentration of 3.0 × 10 ¹⁷ cm ⁻³ when the field plate layer 15 is made of i-GaN, unlike the case where the forward voltage is 5V. It has been confirmed that there is a difference in the hole concentration distribution between the case of the above cases. Specifically, the present inventor has confirmed that when the n-type impurity concentration Nd is set to 3.0 × 10 ¹⁷ cm ⁻³ , holes accumulate in the vicinity of the end of the field plate layer 15 on the cathode electrode 17C side. did.

Based on the above examination, the present inventor conducted various experiments on the field plate layer 15 with n-type impurities as various impurity concentrations Nd. FIG. 2 is a graph showing the forward voltage dependency of the forward current in the SBD 10 when the field plate layer 15 is not doped with impurities and when the n-type impurities are doped. FIG. 3 is a graph showing the forward voltage dependence of the forward current in the SBD 10 when the field plate layer 15 is not doped with impurities and when p-type impurities are doped. In the following drawings, the description of αE + β means α × 10 ^{+ β} .

From FIG. 2, in both cases where the field plate layer 15 is not doped with impurities (solid line in FIG. 2) and when n-type impurities are doped, the SBD 10 increases with an increase in the forward voltage. It can be seen that the forward current flowing in the current increases. Further, when the n-type impurity concentration Nd is 3.0 × 10 ¹⁷ cm ⁻³ (in FIG. 2, a two-dot chain line), the forward current is smaller than that when the n-type impurity is not doped. I understand. That is, when the impurity concentration Nd of the n-type impurity doped in the field plate layer 15 is 3.0 × 10 ¹⁷ cm ⁻³ or less, the forward current that increases with the increase in the forward voltage is doped with the n-type impurity. It becomes smaller than the case where it is not. Further, from FIG. 2, when the n-type impurity concentration Nd is 6.0 × 10 ¹⁷ cm ⁻³ (dotted line in FIG. 2), when the forward voltage becomes 16 V or more, the forward current is doped with the n-type impurity. It turns out that it becomes large compared with the case where it is not.

Similarly, in the case where the n-type impurity concentration Nd is 1.5 × 10 ¹⁸ cm ⁻³ (in FIG. 2, a one-point two-short chain line), when the forward voltage is 11 V or more, the forward current is reduced to the n-type impurity. It turns out that it becomes large compared with the case where it does not dope. Furthermore, in the case where the n-type impurity concentration Nd is 3.0 × 10 ¹⁸ cm ⁻³ (broken line in FIG. 2) and 3.0 × 10 ¹⁹ cm ⁻³ (dotted line in FIG. 2), It can be seen that regardless of the magnitude of the directional voltage, the forward current increases as compared to the case where the n-type impurity is not doped. From the above, the n-type impurity concentration Nd of the field plate layer 15 is larger than 3.0 × 10 ¹⁷ cm ⁻³ , preferably 6.0 × 10 ¹⁷ cm ⁻³ or more, more preferably 1.5 × 10 ^18. By setting it to cm ⁻³ or more, the amount of current when a forward surge current flows in the SBD 10 can be increased. Further, the inventor of the present invention also has a case where the field plate layer 15 is composed of an In _u Al _v Ga _1-uv N layer (0 ≦ u ≦ 1, 0 ≦ v ≦ 1, 0 ≦ u + v <1) other than GaN. It was confirmed that the same tendency as the above-mentioned tendency was exhibited.

That is, the impurity concentration Nd of the n-type impurity doped in the field plate layer 15 needs to be larger than 3.0 × 10 ¹⁷ cm ⁻³ from the viewpoint of the forward characteristics of the SBD 10, and further forward direction Considering that the surge current is large, 6.0 × 10 ¹⁷ cm ⁻³ or more is preferable. On the other hand, the n-type impurity concentration Nd of the field plate layer 15 needs to be 3.0 × 10 ¹⁹ cm ⁻³ or less from the viewpoint of making the crystallinity of the nitride semiconductor constituting the field plate layer 15 a desired crystallinity. Yes, 1.0 × 10 ¹⁹ cm ⁻³ or less is more preferable. That is, it is preferable that the following expression (1) is satisfied at the impurity concentration Nd of the n-type impurity doped in the field plate layer 15.
3.0 × 10 ¹⁷ cm ⁻³ <Nd ≦ 3.0 × 10 ¹⁹ cm ⁻³ (1)

On the other hand, from FIG. 3, when the field plate layer 15 in the SBD 10 is not doped with impurities as in FIG. 2 described above (solid line in FIG. 3), the forward current increases as the forward voltage increases. On the other hand, it can be seen that when the p-type impurity is doped, the forward current is saturated. That is, when the field plate layer 15 is doped with p-type impurities at a high concentration such that the impurity concentration Nd is 3.0 × 10 ¹⁸ cm ⁻³ (broken line in FIG. 3), the forward current Until it reaches about 10V, it increases in the same manner as when impurities are not doped, but when it exceeds about 10V, it decreases. Further, the forward current does not increase as compared with the case where no p-type impurity is doped. Further, when the field plate layer 15 is doped with p-type impurities at an impurity concentration Nd of 3.0 × 10 ¹⁹ cm ⁻³ (indicated by a one-dot chain line in FIG. 3), the forward current is the forward voltage. However, when the voltage exceeds about 7V, the voltage decreases rapidly. From these facts, it can be seen that when the field plate layer 15 is doped with a p-type impurity, the forward current hardly flows when the forward surge current is generated in the SBD 10. According to the study of the present inventor, even if the field plate layer 15 is doped with p-type impurities, the forward current does not increase as the forward voltage increases. This is because the on-resistance increases without changing and does not contribute to an increase in forward current. Thus, it can be seen that the technique for doping the field plate layer with the p-type impurity described in the above-mentioned Patent Document 1 cannot improve the forward surge withstand capability.

Further, the film thickness of the field plate layer 15 shown in FIG. 1 is such that when a forward surge current flows through the SBD 10, in order to efficiently flow the forward surge current through a part of the field plate layer 15, for example, the upper part, It is preferable to be greater than 20 nm and less than or equal to 200 nm. On the other hand, the 2DEG concentration of 2DEG generated in the electron transit layer 13 below the field plate layer 15 decreases as the film thickness of the field plate layer 15 increases. Therefore, in order to set the 2DEG concentration of the 2DEG layer a to 7 × 10 ¹² cm ⁻² or less, for example, the film thickness of the field plate layer 15 is preferably set to be larger than 20 nm and not larger than 200 nm. As a result, the 2DEG concentration in the 2DEG layer a is lower than the 2DEG concentration in the 2DEG layer A. The 2DEG concentration of the 2DEG layer A is preferably higher than 7 × 10 ¹² cm ⁻² . Further, if the film thickness of the field plate layer 15 is 20 nm or less, there is a possibility that leakage cannot be suppressed. On the other hand, if the film thickness of the field plate layer 15 is 300 nm or more, there is a possibility that leakage increases when the impurity concentration is 1 × 10 ¹⁸ cm ⁻³ or more. Furthermore, the film thickness of the field plate layer 15 is more preferably 20 nm or more and 100 nm or less, which makes it easy to control the 2DEG concentration by controlling the film thickness using growth and etching, and is less susceptible to variations in 2DEG concentration due to film thickness variations. More preferably, it is 25 nm or more and 80 nm or less. Here, in the first embodiment, the thickness of the field plate layer 15 is, for example, 30 nm.

  By configuring the field plate layer 15 as described above, when a forward surge current flows through the SBD 10, the forward surge current is applied to the 2DEG layer A of the electron transit layer 13 and, for example, the upper portion of the field plate layer 15. Flowing. That is, when a forward surge current is generated, the current path composed of the 2DEG layer A and the field plate layer 15 is turned on, and the forward surge current flows through this current path. On the other hand, in a steady state in which a normal forward current flows, the forward current flows through the 2DEG layer A and does not saturate, and therefore does not flow through the field plate layer 15. That is, the current path through which the forward surge current flows is turned off.

  In addition, when the reverse bias is applied to the SBD 10, the field plate layer 15 is configured to be fully depleted, so that a decrease in the breakdown voltage of the SBD 10 can also be suppressed. That is, it is desirable that the doping amount (impurity concentration Nd) of the n-type impurity doped in the field plate layer 15 is such that it is fully depleted when a reverse bias is applied to the SBD 10. In other words, the maximum impurity concentration (doping concentration) of the n-type impurity can be determined by the depletion ratio when a reverse bias is applied to the SBD 10. FIG. 4 is a graph showing the dependence of the depletion layer width on the applied voltage (V) when a reverse bias is applied to the SBD 10 when the field plate layer 15 is doped with n-type impurities at various impurity concentrations.

FIG. 4 shows that when a reverse bias is applied to the SBD 10, the depletion layer width of the field plate layer 15 also monotonously increases as the reverse bias increases. Further, from FIG. 4, as the n-type impurity concentration Nd increases, the depletion layer width of the field plate layer 15 decreases, and when the impurity concentration Nd is 3.0 × 10 ¹⁹ cm ⁻³ , the depletion layer It can be seen that the width is the smallest. In this case, even when the n-type impurity concentration Nd is set to 3.0 × 10 ¹⁹ cm ⁻³ , the field plate layer 15 has a thickness of 50 nm or less so that when the reverse bias is applied, the field plate layer 15 15 can be fully depleted. Therefore, it can be seen from FIG. 4 that even when the n-type impurity is doped with an impurity concentration necessary for improving the forward surge withstand capability, a decrease in breakdown voltage in the SBD 10 can be suppressed. Further, according to the study by the present inventor, the impurity concentration Nd of the n-type impurity doped in the field plate layer 15 is set to 1 × 10 ¹⁸ cm ⁻³ or more, preferably 1.5 × 10 ¹⁸ cm ⁻³ or more. Even if it does, degradation of the reverse direction characteristic when a reverse bias is applied with respect to SBD10 can be suppressed. That is, a forward surge current can flow through the field plate layer 15 without causing a decrease in the breakdown voltage of the SBD 10.

The field plate layer 15 is provided apart from the cathode electrode 17C in order to reduce leakage between the anode electrode 17A and the cathode electrode 17C. That is, in the upper layer of the electron supply layer 14, the length L _FP along the interval direction (hereinafter referred to as the horizontal direction) between the anode electrode 17A and the cathode electrode 17C of the field plate layer 15 is equal to the electron supply layer 14 of the anode electrode 17A. a cathode electrode 17C side end portion of the contact portion, the distance between the anode electrode 17A side end portion of the cathode electrode 17C L _AC (hereinafter, cathode - anode distance L _AC) smaller than (L _FP <L _AC).

Here, FIG. 5, the cathode - anode distance L _AC is a graph showing the length (field plate length) L _FP-dependent field plate layer 15 in the withstand voltage of SBD10 of about 14.5 [mu] m. From FIG. 5, the length L _FP of the field plate layer 15 is ½ of the cathode-anode distance L _AC from the viewpoint of securing the breakdown voltage of the SBD 10 to a predetermined breakdown voltage or more, specifically, a breakdown voltage of, for example, 700 V or more. It is understood that the following degree (L _FP ≦ L _AC / 2) is preferable. Specifically cathode - if anode distance L _AC is about 14.5 [mu] m, the length L _FP field plate layer 15 is preferably to be about 7μm or less. Further, from the viewpoint of alleviating electric field concentration in the electron supply layer 14, it is between the cathode electrode 17C side end of the field plate layer 15 shown in FIG. 1 and the cathode electrode 17C side end of the field plate portion of the anode electrode 17A. The interval along the horizontal direction is preferably 1 μm or more. Thereby, the electric field concentration points are dispersed in the electron supply layer 14, the electric field can be relaxed, and the breakdown voltage can be improved.

According to the first embodiment of the present invention described above, in the SBD 10, the field plate layer 15 having a film thickness of greater than 20 nm and less than or equal to 200 nm is provided, and the field plate layer 15 is provided with 3.0 × 10 ¹⁷ cm ^−3. A larger n-type impurity having an impurity concentration Nd of 3.0 × 10 ¹⁹ cm ⁻³ or less is doped. As a result, even if an excessive forward current such as a forward surge current flows through the SBD 10, a current path that allows the excessive forward current to flow so as to be extracted can be defined as the 2DEG layer A and the field plate. Since the area including the layer 15 can be secured, the SBD 10 can improve the resistance against an excessive forward current such as a forward surge resistance. In addition, since the field plate layer 15 can be fully depleted when a reverse bias is applied to the SBD 10, a decrease in breakdown voltage is also suppressed, and a leakage current is also suppressed by separating the field plate layer 15 from the cathode electrode 17C. it can.

(Embodiment 2)
Next, a nitride semiconductor device according to the second embodiment of the present invention will be described. FIG. 6 is a schematic cross-sectional view showing an SBD 20 that is a nitride semiconductor device according to the second embodiment.

  As shown in FIG. 6, in the SBD 20 according to the second embodiment, as in the first embodiment, the buffer layer 12, the electron transit layer 13, and the electron supply layer 14 are sequentially stacked on the substrate 11. A field plate layer 15 made of u-GaN, for example, is selectively provided on the electron supply layer 14. Recess portions 13a and 13b that are recess-etched up to the electron transit layer 13 are formed in the anode formation region and the cathode formation region, respectively. An anode electrode 17A is provided on the recess portion 13a, and a cathode electrode 17C is provided on the recess portion 13b. The anode electrode 17A has a field plate structure in which a part of the anode electrode 17A is mounted on the insulating film 16.

Further, in the SBD 20 according to the second embodiment, unlike the first embodiment, the p-type semiconductor layer selectively doped with p-type impurities on the electron transit layer 13 while being separated from or in contact with the anode electrode 17A. For example, a bonding layer 21 made of a p-GaN layer is provided. In the bonding layer 21 as the fourth semiconductor layer, for example, p-type impurities such as magnesium (Mg) are 1.0 × 10 ¹⁷ cm ⁻³ or more and 3.0 × 10 ¹⁹ cm ⁻³ or less, specifically For example, it is doped with an impurity concentration of 1.0 × 10 ¹⁹ cm ⁻³ . The bonding layer 21 is grounded and electrically connected to the anode electrode 17A. The cathode electrode 17C is connected to the external power source 22 and set to a negative potential. Since other configurations are the same as those of the first embodiment, description thereof is omitted. As described above, the SBD 20 according to the second embodiment is configured.

  In the SBD 20 according to the second embodiment, since the bonding layer 21 is provided on the electron transit layer 13, a PN junction is formed by the junction layer 21 and the electron transit layer 13. Further, since the bonding layer 21 is short-circuited with the anode electrode 17A, holes are injected from the bonding layer 21 into the electron transit layer 13 when a forward surge current is generated. By the injection of holes, the conductivity in the region under the bonding layer 21 of the electron transit layer 13 increases, and the resistance in the region under the bonding layer 21 decreases. Thereby, as indicated by an arrow in FIG. 6, the forward surge current travels through the anode electrode 17 </ b> A through the bonding layer 21 and travels through an electron path that includes a current path including a region where the resistance other than at least the 2 DEG layers A and a is reduced. It passes through the layer 13 and flows into the cathode electrode 17C. Therefore, when the forward surge current is generated, the forward surge current can be passed through the region other than the 2DEG layers A and a in the electron transit layer 13.

  According to the second embodiment described above, the junction layer 21 short-circuited to the anode electrode 17A is selectively provided on the upper layer of the electron transit layer 13, so that an excessive forward current such as a forward surge current is reduced. Only at the time of occurrence, the resistance of the region below the bonding layer 21 in the electron transit layer 13 can be reduced, and the forward current can flow through the regions other than the 2DEG layers A and a in the electron transit layer 13. The same effect as in the first mode can be obtained.

(Embodiment 3)
Next, a nitride semiconductor device according to the third embodiment of the present invention will be described. FIG. 7 is a schematic cross-sectional view showing an SBD 30 that is a nitride semiconductor device according to the third embodiment.

As shown in FIG. 7, in the SBD 30 according to the third embodiment, a buffer layer 12, a drift layer 31, an electron transit layer 32 composed of a u-GaN layer, and an electron supply layer 14 are sequentially stacked on a substrate 11. Yes. In addition, a field plate layer 15 made of a u-GaN layer is selectively provided on the electron supply layer 14. Further, the drift layer 31 as the sixth semiconductor layer has a higher concentration of n-type impurities than the electron transit layer 32 having an impurity concentration of, for example, 1.0 × 10 ¹⁶ cm ⁻³ or less and a film thickness of about 400 nm. It is composed of a doped Al _z Ga _{1 -z} N layer (0 ≦ z <0.05). In addition, the thickness of the drift layer 31 is preferably 500 nm or less because the desired breakdown voltage cannot be maintained in the SBD 30 if the thickness is too large. On the other hand, if the thickness of the drift layer 31 is too small, the resistance of the drift layer 31 increases, and may not function as a part of a current path when a large forward current such as a forward surge current described later is generated. For this reason, the thickness of the drift layer 31 is preferably 100 nm or more. Moreover, in order to reduce the resistance of the drift layer 31, it is possible to increase the doping concentration of the n-type impurity as necessary. In the third embodiment, the drift layer 31 is composed of, for example, a GaN layer having an Al composition ratio z of 0 and a film thickness of about 500 nm.

In the anode formation region of the SBD 30, a recess 32a formed by recess etching up to the electron transit layer 32 is formed. A buried layer 33 made of a p ⁺ -GaN layer doped with a p-type impurity at a high concentration is buried in the recess 32a. Here, the p-type impurity concentration in the bonding layer 33 as the fifth semiconductor layer is 1 × 10 ¹⁸ cm ⁻³ in order to sufficiently inject holes into the electron transit layer 32 below the bonding layer 33. The above is preferable, and in order to suppress deterioration of crystallinity, 3 × 10 ¹⁹ cm ⁻³ or less is preferable. In the third embodiment, the p-type impurity concentration in bonding layer 33 is, for example, 3.0 × 10 ¹⁹ cm ⁻³ . The film thickness of the electron transit layer 32 in the region where the recess 32a is formed, that is, the film thickness of the electron transit layer 32 below the bonding layer 33 is determined based on the diffusion length of holes that are minority carriers. The film thickness of the electron transit layer 32 below the bonding layer 33 in the third embodiment is, for example, 300 nm or less, preferably 150 nm or less. In addition, an anode electrode 35A is provided on the bonding layer 33 embedded in the recess 32a. The anode electrode 35A is in Schottky contact with the 2DEG layer a from the side surface. Similarly to the first embodiment, the anode electrode 35A has a field plate portion that extends toward the cathode electrode 35C and is stepped on the field plate layer 15 and the insulating film 16.

On the other hand, in the cathode formation region of the SBD 30, a recess portion 31a formed by recess etching up to the drift layer 31 below the electron transit layer 32 is formed. A contact layer 34 is formed in the recess 31a. The contact layer 34 is made of a conductive material such as GaN (n ⁺ -GaN) doped with n-type impurities such as Si, S, Se, Te, and O at a high concentration of about 1 × 10 ¹⁹ cm ^−3. The The contact layer 34 can also be formed by selectively doping an n-type impurity into at least a part of the cathode formation region in the electron transit layer 32 and the drift layer 31. A cathode electrode 35 </ b> C is provided on the contact layer 34 in conduction with the contact layer 34. The cathode electrode 35 </ b> C is in ohmic contact with the 2DEG layer A on the side surface and is electrically connected to the drift layer 31 through the contact layer 34. Since other configurations are the same as those in the first and second embodiments, description thereof is omitted.

  In the SBD 30 according to the third embodiment, since the bonding layer 33 is provided between the anode electrode 35 </ b> A and the electron transit layer 32, a PN junction is formed by the junction layer 33 and the electron transit layer 32. When a forward surge current or the like is generated, holes are injected from the bonding layer 33 into the electron transit layer 32. By the injection of holes, the conductivity of the electron transit layer 32 in the region below the bonding layer 33 is increased, and the resistance in this region is selectively reduced. In addition, since holes do not diffuse into the region other than the region below the bonding layer 33, the resistance other than the region does not decrease. Thereby, as indicated by an arrow in FIG. 7, the forward surge current flows from the anode electrode 35 </ b> A to the drift layer 31 through the lower bonding layer 33 and the electron transit layer 32. Then, the forward surge current flows through the drift layer 31 and flows into the cathode electrode 35C through the contact layer 34. That is, the junction layer 33, the electron transit layer 32, the drift layer 31, and the contact layer 34 below the anode electrode 35 </ b> A constitute a current path through which a forward surge current flows. As a result, a forward surge current can be passed through a region other than the 2DEG layers A and a.

In addition, the inventor examined the impurity concentration Nd of the n-type impurity doped in the drift layer 31 in the SBD 30 according to the above-described third embodiment. FIG. 8 is a graph showing the forward voltage dependence of the forward current, that is, the forward characteristic, in the SBD 30 according to the third embodiment. From FIG. 8, when the drift layer 31 is composed of an i-GaN layer that is not doped with n-type impurities, the forward current increases as the forward voltage increases, but when the forward voltage is 10V. The forward current is about 0.13 A / mm. On the other hand, in the drift layer 31 where the impurity concentration of the n-type impurity is 1.0 × 10 ¹⁷ cm ⁻³ , the forward current is about 2.2 times 0.29 A when the forward voltage is 10V. It turns out that it increases to about / mm. Similarly, when the impurity concentration of the n-type impurity of the drift layer 31 is 4.0 × 10 ¹⁷ cm ⁻³ , the forward current increases to about 0.62 A / mm, which is about 4.8 times, In the case of 1.0 × 10 ¹⁸ cm ⁻³ , it can be seen that the forward current increases to about 0.98 A / mm, which is about 7.5 times. In other words, in the drift layer 31, by increasing the impurity concentration of the n-type impurity, that is, the electron concentration, the on-resistance in the drift layer 31 is reduced, so that the forward current can be increased. Note that the electron mobility in the drift layer 31 is, for example, 300 to 400 cm ² / Vs. Thereby, when the forward surge current is generated, the drift layer 31 can be made a part of a current path for extracting the forward surge current.

  In addition, if the impurity concentration of the n-type impurity in the drift layer 31 is too high, the depletion layer does not spread, and the electric field is strengthened in the region of the drift layer 31 or the electron transit layer 32 on the anode electrode 17A side as an equipotential surface. Become. Therefore, the maximum value of the impurity concentration of the n-type impurity in the drift layer 31 is determined from the maximum value at which the drift layer 31 is depleted when a reverse bias is applied to the SBD 30. FIG. 9 is a graph showing the reverse bias dependence of the depletion layer width in the drift layer 31. The depletion layer width of the drift layer 31 in FIG. 9 is a distance that is depleted along the horizontal direction in the SBD 30 in which the distance between the anode and the cathode is, for example, 10 μm or more, for example, about 14.5 μm. In FIG. 9, the arrow position is a voltage (about 300 V) applied to the drift layer 31 when the reverse bias is 600 V.

FIG. 9 shows that when the n-type impurity concentration Nd is 1.0 × 10 ¹⁸ cm ⁻³ , the depletion layer width is about 5000 nm (5 μm). Similarly, when the n-type impurity concentration Nd is 4.0 × 10 ¹⁷ cm ⁻³ , the depletion layer width is about 9000 nm (9 μm) and the n-type impurity concentration Nd is 1.0 × 10 ¹⁷ cm ⁻³ . It can be seen that the width of the depletion layer reaches about 17500 nm (17.5 μm). That is, the reverse bias is applied to the SBD 30 by setting the n-type impurity concentration of the drift layer 31 to be preferably in the range of 1.0 × 10 ¹⁷ cm ^{−3 to} 1.0 × 10 ¹⁸ cm ⁻³ . At this time, the drift layer 31 can be fully depleted, so that a decrease in breakdown voltage in the SBD 30 can be suppressed.

  According to the third embodiment described above, since the junction layer 33 is interposed between the anode electrode 35A and the electron transit layer 32 and the drift layer 31 is provided, when a forward surge current is generated, The resistance of the electron transit layer 32 below the bonding layer 33 can be lowered. Further, the diffusion length of minority carriers in the GaN layer is about 150 to 300 nm. Therefore, the film thickness of the electron transit layer 32 in the region below the bonding layer 33 is set to 300 nm or less. Thus, only when a forward surge current is generated, the PN junction is turned on, and the current path is turned on by connecting the anode electrode 35A, the junction layer 33, the electron transit layer 32, and the drift layer 31. Thus, since the forward surge current can flow through the region other than the 2DEG layers A and a only when the forward surge current is generated, the same effect as in the first and second embodiments can be obtained.

  Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible. For example, the numerical values given in the above embodiment are merely examples, and different numerical values may be used as necessary. Further, the present invention is not limited to the above-described embodiment. What was comprised combining each component mentioned above suitably is also contained in this invention. Further effects and modifications can be easily derived by those skilled in the art.

For example, in the above-described embodiment, the electron supply layer is an AlGaN superlattice layer, but in addition to the AlGaN superlattice layer, a plurality of In _u Al _v Ga _{1 -uv} N layers (0 ≦ u <1, 0 It is also possible to employ an InAlGaN superlattice layer in which <v ≦ 1, 0 <u + v <1) is laminated to form a superlattice layer. In addition to those described in the above embodiment, various pseudo-mixed crystal structures belonging to the scope of the present invention are employed in the electron supply layer 14 in accordance with the structure design based on desired characteristics in the semiconductor device. Is possible.

In the above-described embodiment, SiO ₂ is used as the material of the insulating film 16, but the material is not necessarily limited to this. Specifically, AlN, Al ₂ O ₃ , SiN _x , gallium oxide (Ga ₂ O ₃ ), tantalum oxide (TaO ₃ ), or silicon oxynitride (SiON) can be adopted as the material of the insulating film 16. is there.

  The lower electrode layer of the anode electrode of the diode is an electrode that is in Schottky contact with the 2DEG layer through the electron supply layer. Therefore, besides nickel (Ni) and titanium (Ti) described above, for example, platinum (Pt), palladium (Pd), tungsten (W), gold (Au), silver (Ag), copper (Cu), tantalum ( Ta), a metal film containing at least one of aluminum (Al), or a metal film made of an alloy containing at least one of Ti, Ni, Pt, Pd, W, Au, Ag, Cu, Ta, and Al Of these, various metal materials satisfying the above conditions, such as a metal film containing at least one or a metal film made of a nitride alloy containing at least one of Ti, W, and Ta may be used. good. The upper electrode layer of the anode electrode of the diode is made of a metal having a work function smaller than that of the lower electrode layer, and various materials may be used as long as the metal material satisfies this condition.

  The lower electrode layer of the cathode electrode of the diode is an electrode that is in ohmic contact with the 2DEG layer through the electron supply layer, or an electrode having a sufficiently small contact resistance. However, the present invention is not limited thereto. For example, a metal film containing at least one of Ti, Al, silicon (Si), lead (Pb), chromium (Cr), In, Ta, Ti, Al, Si, Metal film made of an alloy containing at least one of Pb, Cr, In, Ta, or metal film made of a silicide alloy containing at least one of Ti, Al, Si, Ta, or Ti, W, Ta Any metal material satisfying the above conditions, such as a metal film including at least one of metal films made of a nitride alloy including at least one of them, may be used.

  In the above-described embodiment, the electrodes are formed on the recesses of the electron transit layer by etching up to the electron transit layer. However, the present invention is not necessarily limited thereto. Specifically, an electrode is formed on at least one layer of a semiconductor laminate including an electron transit layer, an electron supply layer, an etching sacrificial layer, a semiconductor layer or a field plate layer, and other layers as necessary. Can be provided. That is, an electrode may be provided on another layer constituting the semiconductor stacked body. Specifically, an anode electrode or a cathode electrode can be provided on the surface of the electron supply layer via a nitride semiconductor layer such as an insulating layer or a field plate layer, or a laminated film thereof.

In the above-described embodiment, the etching sacrificial layer is not provided on the electron supply layer 14, but if necessary, the electron supply layer 14 is larger than the average Al composition ratio X of the electron supply layer 14, It is also possible to provide an etching sacrificial layer made of Al _Y Ga _1-Y N with an Al composition ratio Y of preferably 40% or more. In this case, when the Al composition ratio of the semiconductor layer formed on the Al _Y Ga _1-Y N layer, which is the etching sacrificial layer, is 0 or an extremely small material, the etching rate is extremely large, about 25 times or more of the etching sacrificial layer. it can. Further, the thickness of the etching sacrificial layer is preferably not less than 1 nm, more preferably not less than 2 nm, more preferably not less than 12 nm which can be precisely controlled by controlling the etching rate, and preferably not more than 12 nm which can suppress deterioration of crystallinity.

10, 20, 30 Schottky barrier diode (SBD)
DESCRIPTION OF SYMBOLS 11 Board | substrate 12 Buffer layer 13, 32 Electron travel layer 13a, 13b, 31a, 32a Recess part 14 Electron supply layer 15 Field plate layer 16 Insulating film 17A, 35A Anode electrode 17C, 35C Cathode electrode 21, 33 Junction layer 22 External power supply 31 Drift layer 34 Contact layer

Claims (10)

A substrate;
A first semiconductor layer made of a nitride semiconductor provided on the upper layer of the base, and a nitride semiconductor made of a nitride semiconductor provided on the upper layer of the first semiconductor layer and having an average wider band gap than the first semiconductor layer. A semiconductor laminate including two semiconductor layers;
An anode electrode provided on at least a part of the semiconductor layers constituting the semiconductor laminate;
A cathode electrode provided on and separated from the anode electrode on at least a part of the semiconductor layers constituting the semiconductor laminate;
With
Through a region other than the two-dimensional electron gas generation region generated at the interface between the first semiconductor layer and the second semiconductor layer with a voltage applied in a forward direction between the anode electrode and the cathode electrode, A nitride semiconductor device comprising a current path through which a current flows between the anode electrode and the cathode electrode. The semiconductor stacked body further includes a third semiconductor layer made of Al _x Ga _1-x N, which is selectively provided on the second semiconductor layer and has an average band gap narrower than that of the second semiconductor layer. The nitride semiconductor device according to claim 1.   3. The nitride semiconductor according to claim 2, wherein the third semiconductor layer is made of an n-type semiconductor containing an n-type impurity, and a portion of the third semiconductor layer constitutes at least a part of the current path. apparatus.   4. The nitride semiconductor device according to claim 2, wherein the thickness of the third semiconductor layer is greater than 20 nm and equal to or less than 200 nm. 5. The impurity concentration of the n-type impurity contained in the third semiconductor layer is 3.0 × 10 ¹⁷ cm ⁻³ or more and 3.0 × 10 ¹⁹ cm ⁻³ or less. Nitride semiconductor device. 6. The nitride semiconductor device according to claim 3, wherein an impurity concentration of the n-type impurity contained in the third semiconductor layer is 6.0 × 10 ¹⁷ cm ⁻³ or more. The nitride semiconductor device according to claim 3, wherein an impurity concentration of an n-type impurity contained in the third semiconductor layer is 1.0 × 10 ¹⁹ cm ⁻³ or less.   A fourth semiconductor layer made of a p-type semiconductor containing a p-type impurity selectively is provided above the first semiconductor layer, and the anode electrode and the fourth semiconductor layer are electrically connected to form the fourth semiconductor. 3. The nitride semiconductor device according to claim 1, wherein the layer and the portion of the first semiconductor layer constitute at least a part of the current path.   A fifth semiconductor layer made of a p-type semiconductor containing a p-type impurity selectively is provided above the layer constituting the semiconductor stacked body, and an n-type is interposed between the base and the first semiconductor layer. A sixth semiconductor layer made of an n-type semiconductor containing an impurity is provided, and the current path is formed by the first semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer. The nitride semiconductor device according to claim 1 or 2.   The nitride semiconductor device according to claim 1, wherein the anode electrode is a Schottky electrode and the cathode electrode is an ohmic electrode.

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