JP2015216408A - Semiconductor light emitting device - Google Patents

Abstract

A semiconductor light-emitting device capable of improving light extraction efficiency and handleability is provided. According to an embodiment, a semiconductor light emitting device includes a laminate having a first surface provided with irregularities, a second surface opposite to the first surface, a light emitting layer, and the light emitting layer. A p-side electrode provided on the second surface in the region; an n-side electrode provided on the second surface in the region not including the light emitting layer; and a phosphor provided on the first surface. And a contact layer provided along the unevenness of the first surface between the first surface and the phosphor layer, and having an unevenness on the upper surface. [Selection] Figure 21

Description

  Embodiments described herein relate generally to a semiconductor light emitting device.

  In a semiconductor light emitting device having a structure in which an electrode is not provided on the light extraction surface and a p-side electrode and an n-side electrode are provided on the opposite side of the light extraction surface, the structure on the light extraction surface has light extraction efficiency and A structure that does not impair handling is required.

US Patent Application Publication No. 2010/0148198

  Embodiments of the present invention provide a semiconductor light-emitting device that can improve light extraction efficiency and handleability.

  According to the embodiment, the semiconductor light-emitting device includes a stacked body including a first surface provided with unevenness, a second surface opposite to the first surface, a light-emitting layer, and the first surface in a region including the light-emitting layer. A p-side electrode provided on the second surface, an n-side electrode provided on the second surface in a region not including the light emitting layer, a phosphor layer provided on the first surface, An adhesion layer provided along the unevenness of the first surface between the first surface and the phosphor layer, and having an unevenness on the upper surface.

1 is a schematic cross-sectional view of a semiconductor light emitting device according to a first embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram which shows the manufacturing method of the semiconductor light-emitting device of 1st Embodiment. The schematic cross section of the modification of the semiconductor light-emitting device of 1st Embodiment. The schematic diagram of the other modification of the semiconductor light-emitting device of 1st Embodiment. FIG. 17 is a schematic cross-sectional view of the semiconductor light emitting device shown in FIG. 16 mounted on a mounting substrate. The schematic cross section of the semiconductor light-emitting device of 2nd Embodiment. (A) is a schematic cross section of the modification of the semiconductor light-emitting device of 1st Embodiment, (b) is a schematic cross section of the modification of the semiconductor light-emitting device of 2nd Embodiment. The schematic diagram of the further another modification of the semiconductor light-emitting device of 1st Embodiment. FIG. 6 is a schematic cross-sectional view of a semiconductor light emitting device according to a third embodiment. The schematic cross section of the modification of the semiconductor light-emitting device of 3rd Embodiment. The schematic cross section of the other modification of the semiconductor light-emitting device of 3rd Embodiment. The schematic cross section of the further another modification of the semiconductor light-emitting device of 3rd Embodiment. The schematic cross section of the further another modification of the semiconductor light-emitting device of 3rd Embodiment. The schematic cross section of the further another modification of the semiconductor light-emitting device of 3rd Embodiment. The schematic cross section of the further another modification of the semiconductor light-emitting device of 3rd Embodiment. The graph which compared the adhesion strength of the adhesion layer.

  Hereinafter, embodiments will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element in each drawing.

(First embodiment)
FIG. 1 is a schematic cross-sectional view of a semiconductor light emitting device 1 according to the first embodiment.

  The semiconductor light emitting device 1 has a semiconductor layer 15 including a light emitting layer 13. The semiconductor layer 15 has a first surface 15a and a second surface opposite to the first surface 15a. An electrode and a wiring part are provided on the second surface side, and light is mainly emitted from the first surface 15a where the electrode and the wiring part are not provided.

  The semiconductor layer 15 includes a first semiconductor layer 11 and a second semiconductor layer 12. The first semiconductor layer 11 and the second semiconductor layer 12 include, for example, gallium nitride. The first semiconductor layer 11 includes, for example, a base buffer layer, an n-type GaN layer, and the like. The second semiconductor layer 12 includes a p-type GaN layer, a light emitting layer (active layer) 13 and the like. The light emitting layer 13 can be made of a material that emits blue, purple, blue purple, ultraviolet light, or the like.

  The second surface of the semiconductor layer 15 is processed into a concavo-convex shape, and the convex portion includes the light emitting layer 13. A p-side electrode 16 is provided on the surface of the second semiconductor layer 12 that is the surface of the convex portion. That is, the p-side electrode 16 is provided on the second surface in the region having the light emitting layer 13.

  On the second surface of the semiconductor layer 15, a region not including the light emitting layer 13 is provided beside the convex portion, and an n-side electrode 17 is provided on the surface of the first semiconductor layer 11 in the region. That is, the n-side electrode 17 is provided on the second surface in a region not including the light emitting layer 13.

  As shown in FIG. 4B, the area of the second semiconductor layer 12 including the light emitting layer 13 on the second surface of the semiconductor layer 15 is larger than the area of the first semiconductor layer 11 not including the light emitting layer 13. Is also wide.

  Further, as shown in FIG. 5B, in the semiconductor layer 15, the p-side electrode 16 provided in the region including the light emitting layer 13 is n-side electrode 17 provided in the region not including the light emitting layer 13. The area is wider than. Thereby, a wide light emitting region is obtained. The layout of the p-side electrode 16 and the n-side electrode 17 shown in FIG. 5B is an example and is not limited to this.

  A first insulating film (hereinafter simply referred to as an insulating film) 18 is provided on the second surface side of the semiconductor layer 15. The insulating film 18 covers the semiconductor layer 15, the p-side electrode 16, and the n-side electrode 17. The insulating film 18 covers and protects the side surfaces of the light emitting layer 13 and the second semiconductor layer 12.

  Note that another insulating film (for example, a silicon oxide film) may be provided between the insulating film 18 and the semiconductor layer 15. The insulating film 18 is, for example, a resin such as polyimide having excellent patterning characteristics for fine openings. Alternatively, an inorganic film such as a silicon oxide film or a silicon nitride film may be used as the insulating film 18.

  The insulating film 18 is not provided on the first surface 15 a of the semiconductor layer 15. The insulating film 18 covers and protects the side surface 15c continuing from the first surface 15a in the semiconductor layer 15.

  On the surface of the insulating film 18 opposite to the second surface of the semiconductor layer 15, the p-side wiring layer 21 and the n-side wiring layer 22 are provided apart from each other.

  The p-side wiring layer 21 is also provided in the plurality of first openings 18 a that reach the p-side electrode 16 and are formed in the insulating film 18, and is electrically connected to the p-side electrode 16. The n-side wiring layer 22 is also provided in the second opening 18 b that reaches the n-side electrode 17 and is formed in the insulating film 18, and is electrically connected to the n-side electrode 17.

  A p-side metal pillar 23 is provided on the surface opposite to the p-side electrode 16 in the p-side wiring layer 21. The p-side wiring layer 21, the p-side metal pillar 23, and the metal film 19 used as a seed layer to be described later constitute the p-side wiring portion in the present embodiment.

  An n-side metal pillar 24 is provided on the surface opposite to the n-side electrode 17 in the n-side wiring layer 22. The n-side wiring layer 22, the n-side metal pillar 24, and the metal film 19 used as a seed layer to be described later constitute an n-side wiring portion in the present embodiment.

  For example, a resin layer 25 is laminated on the insulating film 18 as a second insulating film. The resin layer 25 covers the periphery of the p-side wiring portion and the periphery of the n-side wiring portion. The resin layer 25 is filled between the p-side metal pillar 23 and the n-side metal pillar 24.

  The side surface of the p-side metal pillar 23 and the side surface of the n-side metal pillar 24 are covered with a resin layer 25. The surface of the p-side metal pillar 23 opposite to the p-side wiring layer 21 is exposed from the resin layer 25 and functions as the p-side external terminal 23a. The surface of the n-side metal pillar 24 opposite to the n-side wiring layer 22 is exposed from the resin layer 25 and functions as the n-side external terminal 24a.

  The p-side external terminal 23a and the n-side external terminal 24a are joined to a pad formed on the mounting substrate via a joining material such as solder, other metal, or a conductive material.

  The distance between the p-side external terminal 23a and the n-side external terminal 24a exposed on the same surface (the lower surface in FIG. 1) of the resin layer 25 is the p-side wiring layer 21 and the n-side wiring layer 22 on the insulating film 18. Greater than the distance between. The p-side external terminal 23a and the n-side external terminal 24a are separated by a distance that is not short-circuited by solder or the like when mounted on the mounting board.

  The p-side wiring layer 21 can be brought close to the n-side wiring layer 22 to the limit of the process, and the area of the p-side wiring layer 21 can be increased. As a result, the contact area between the p-side wiring layer 21 and the p-side electrode 16 can be increased, and the current distribution and heat dissipation can be improved.

  The area where the p-side wiring layer 21 is in contact with the p-side electrode 16 through the plurality of first openings 18a is larger than the area where the n-side wiring layer 22 is in contact with the n-side electrode 17 through the second opening 18b. Therefore, the current distribution to the light emitting layer 13 can be improved, and the heat dissipation of the light emitting layer 13 can be improved.

  The area of the n-side wiring layer 22 extending on the insulating film 18 is larger than the area where the n-side wiring layer 22 is in contact with the n-side electrode 17.

  According to the embodiment, a high light output can be obtained by the light emitting layer 13 formed over a region wider than the n-side electrode 17. In addition, the n-side electrode 17 provided in a region narrower than the region including the light emitting layer 13 is drawn out to the mounting surface side as an n-side wiring layer 22 having a larger area.

  The first semiconductor layer 11 is electrically connected to an n-side metal pillar 24 having an n-side external terminal 24a via an n-side electrode 17, a metal film 19, and an n-side wiring layer 22. The second semiconductor layer 12 including the light emitting layer 13 is electrically connected to the p-side metal pillar 23 having the p-side external terminal 23a through the p-side electrode 16, the metal film 19, and the p-side wiring layer 21. Yes.

  The p-side metal pillar 23 is thicker than the p-side wiring layer 21, and the n-side metal pillar 24 is thicker than the n-side wiring layer 22. Each of the p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 is thicker than the semiconductor layer 15. Here, “thickness” represents the thickness in the vertical direction in FIG.

  In addition, the thickness of each of the p-side metal pillar 23 and the n-side metal pillar 24 is larger than the thickness of the stacked body including the semiconductor layer 15, the p-side electrode 16, the n-side electrode 17, and the insulating film 18. In addition, the aspect ratio (ratio of the thickness to the plane size) of each metal pillar 23 and 24 is not limited to 1 or more, and the ratio may be smaller than 1. That is, the thickness of the metal pillars 23 and 24 may be smaller than the planar size.

  According to the embodiment, the semiconductor layer 15 is stably formed by the p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 even when the substrate 10 described later used to form the semiconductor layer 15 is removed. The mechanical strength of the semiconductor light emitting device 1 can be increased.

  As a material of the p-side wiring layer 21, the n-side wiring layer 22, the p-side metal pillar 23, and the n-side metal pillar 24, copper, gold, nickel, silver, or the like can be used. Among these, when copper is used, good thermal conductivity, high migration resistance, and excellent adhesion with an insulating material can be obtained.

  The resin layer 25 reinforces the p-side metal pillar 23 and the n-side metal pillar 24. It is desirable to use a resin layer 25 having the same or close thermal expansion coefficient as the mounting substrate. As such a resin layer 25, an epoxy resin, a silicone resin, a fluororesin, etc. can be mentioned as an example, for example.

  Further, in a state where the semiconductor light emitting device 1 is mounted on the mounting substrate via the p-side external terminal 23a and the n-side external terminal 24a, stress applied to the semiconductor layer 15 via solder or the like is applied to the p-side metal pillar 23 and n. It can be mitigated by absorption by the side metal pillar 24.

  The p-side wiring portion including the p-side wiring layer 21 and the p-side metal pillar 23 is connected to the p-side electrode 16 through a plurality of vias 21a provided in the plurality of first openings 18a and separated from each other. ing. For this reason, the high stress relaxation effect by a p side wiring part is acquired.

  Alternatively, as shown in FIG. 15B, the p-side wiring layer 21 is connected to the p-side electrode 16 via a post 21c that is provided in one large first opening 18a and has a larger planar size than the via 21a. In this case, the heat dissipation of the light emitting layer 13 can be improved through the p-side electrode 16, the p-side wiring layer 21, and the p-side metal pillar 23, all of which are metals.

  As will be described later, the substrate 10 used for forming the semiconductor layer 15 is removed from the first surface 15a. For this reason, the semiconductor light emitting device 1 can be reduced in height.

  On the first surface 15 a of the semiconductor layer 15, minute irregularities are formed. The first surface 15a is subjected to wet etching (frost treatment) using, for example, an alkaline solution, and irregularities are formed. By providing irregularities on the first surface 15a, which is the main extraction surface for the emitted light of the light emitting layer 13, the outside of the first surface 15a without totally reflecting light incident on the first surface 15a at various angles. Can be taken out.

  A phosphor layer 30 is provided on the first surface 15a. The phosphor layer 30 includes a transparent resin 31 and a plurality of particulate or powder phosphors 32 dispersed in the transparent resin 31.

  The transparent resin 31 has transparency to the light emitted from the light emitting layer 13 and the light emitted from the phosphor 32. For example, a silicone resin, an acrylic resin, a phenyl resin, or the like can be used.

  The phosphor 32 can absorb the emitted light (excitation light) of the light emitting layer 13 and emit wavelength converted light. For this reason, the semiconductor light emitting device 1 can emit mixed light of the light emitted from the light emitting layer 13 and the wavelength converted light from the phosphor 32.

  For example, when the phosphor 32 is a yellow phosphor that emits yellow light, the mixed color of the blue light of the light emitting layer 13 that is a GaN-based material and the yellow light that is the wavelength converted light in the phosphor 32 is white or a light bulb. Color can be obtained. The phosphor layer 30 may include a plurality of types of phosphors (for example, a red phosphor that emits red light and a green phosphor that emits green light).

  A transparent film 35 is provided on the upper surface of the phosphor layer 30. The transparent film 35 is transmissive to the light emitted from the light emitting layer 13 and the light emitted from the phosphor 32. For example, the transparent film 35 is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an acrylic resin film.

  The transparent film 35 has lower adhesiveness (tackiness) than the transparent resin 31 of the phosphor layer 30. Therefore, as will be described later, the force required to peel the cover tape 85 attached to the transparent film 35 shown in FIG. 14A from the transparent film 35 at a constant speed is the transparent resin 31 of the phosphor layer 30. This is smaller than the force required to peel the cover tape 85 affixed to the transparent resin 31 at a constant speed.

  Further, the transparent film 35 is thinner than the phosphor layer 30. For this reason, the light diffusion in the lateral direction in the transparent film 35 can be suppressed, and the directivity of light in the direction perpendicular to the light extraction surface can be enhanced.

  Further, when the thickness of the transparent film 35 is ¼ or less of the wavelength of light in the transparent film 35, the interface between the phosphor layer 30 and the transparent film 35 and the interface between the transparent film 35 and the air layer are used. Therefore, high light extraction efficiency can be obtained.

  Next, with reference to FIG. 2A to FIG. 13B, a method for manufacturing the semiconductor light emitting device 1 of the embodiment will be described. FIG. 2A to FIG. 13B show a partial region in the wafer state.

  2A shows a stacked body in which the first semiconductor layer 11 and the second semiconductor layer 12 are formed on the main surface of the substrate 10 (the lower surface in FIG. 2A). FIG. 2B corresponds to the bottom view in FIG.

  A first semiconductor layer 11 is formed on the main surface of the substrate 10, and a second semiconductor layer 12 including a light emitting layer 13 is formed thereon. The first semiconductor layer 11 and the second semiconductor layer 12 containing gallium nitride can be crystal-grown on a sapphire substrate, for example, by MOCVD (metal organic chemical vapor deposition). Alternatively, a silicon substrate can be used as the substrate 10.

  The surface in contact with the substrate 10 in the first semiconductor layer 11 is the first surface 15 a of the semiconductor layer 15, and the surface of the second semiconductor layer 12 is the second surface 15 b of the semiconductor layer 15.

  Next, by RIE (Reactive Ion Etching) method using a resist (not shown), as shown in FIG. 3A and its bottom view, FIG. A reaching groove 80 is formed. The grooves 80 are formed, for example, in a lattice shape on the substrate 10 in a wafer state, and separate the semiconductor layer 15 into a plurality of chips on the substrate 10.

  The step of separating the semiconductor layer 15 into a plurality may be performed after the selective removal of the second semiconductor layer 12 described later or after the formation of the electrodes.

  Next, a part of the second semiconductor layer 12 is removed by, for example, RIE using a resist (not shown), as shown in FIG. 4A and its bottom view, FIG. A portion of one semiconductor layer 11 is exposed. The region where the first semiconductor layer 11 is exposed does not include the light emitting layer 13.

  Next, as shown in FIG. 5A and a bottom view thereof, FIG. 5B, the p-side electrode 16 and the n-side electrode 17 are formed on the second surface of the semiconductor layer 15. The p-side electrode 16 is formed on the surface of the second semiconductor layer 12. The n-side electrode 17 is formed on the exposed surface of the first semiconductor layer 11.

  The p-side electrode 16 and the n-side electrode 17 are formed by, for example, a sputtering method or a vapor deposition method. Either the p-side electrode 16 or the n-side electrode 17 may be formed first, or may be formed of the same material at the same time.

  The p-side electrode 16 includes, for example, silver, a silver alloy, aluminum, an aluminum alloy or the like that is reflective to the light emitted from the light emitting layer 13. Further, in order to prevent sulfidation and oxidation of the p-side electrode 16, a structure including a metal protective film (barrier metal) may be used.

  Further, for example, a silicon nitride film or a silicon oxide film may be formed as a passivation film between the p-side electrode 16 and the n-side electrode 17 or on the end face (side face) of the light emitting layer 13 by a CVD (chemical vapor deposition) method. Good. In addition, activation annealing or the like for making ohmic contact between each electrode and the semiconductor layer is performed as necessary.

  Next, after all the exposed portions on the main surface of the substrate 10 are covered with the insulating film 18 shown in FIG. 6A, the insulating film 18 is patterned by, for example, wet etching to selectively form the insulating film 18. A first opening 18a and a second opening 18b are formed. A plurality of first openings 18 a are formed, and each first opening 18 a reaches the p-side electrode 16. The second opening 18 b reaches the n-side electrode 17.

  As the insulating film 18, for example, an organic material such as photosensitive polyimide or benzocyclobutene can be used. In this case, the insulating film 18 can be directly exposed and developed without using a resist.

  Alternatively, an inorganic film such as a silicon nitride film or a silicon oxide film may be used as the insulating film 18. When the insulating film 18 is an inorganic film, the first opening 18 a and the second opening 18 b are formed by etching after patterning the resist formed on the insulating film 18.

  Next, as shown in FIG. 6B, a metal film 19 is formed on the surface of the insulating film 18, the inner walls (side walls and bottom) of the first opening 18a, and the inner walls (side walls and bottom) of the second opening 18b. Form. The metal film 19 is used as a seed metal for plating described later.

  The metal film 19 is formed by sputtering, for example. The metal film 19 includes, for example, a laminated film of titanium (Ti) and copper (Cu) laminated in order from the insulating film 18 side. Alternatively, an aluminum film may be used instead of the titanium film.

  Next, as shown in FIG. 6C, a resist 91 is selectively formed on the metal film 19, and Cu electrolytic plating using the metal film 19 as a current path is performed.

  As a result, the p-side wiring layer 21 and the n-side wiring layer 22 are selectively formed on the metal film 19, as shown in FIG. The p-side wiring layer 21 and the n-side wiring layer 22 are made of, for example, a copper material that is simultaneously formed by a plating method.

  The p-side wiring layer 21 is also formed in the first opening 18 a and is electrically connected to the p-side electrode 16 through the metal film 19. The n-side wiring layer 22 is also formed in the second opening 18 b and is electrically connected to the n-side electrode 17 through the metal film 19.

  The resist 91 used for plating the p-side wiring layer 21 and the n-side wiring layer 22 is removed using a solvent or oxygen plasma.

  Next, as shown in FIG. 8A and a bottom view thereof, FIG. 8B, a resist 92 for forming metal pillars is formed. The resist 92 is thicker than the resist 91 described above. Note that the resist 91 may be left without being removed in the previous step, and the resist 92 may be formed over the resist 91. The resist 92 has a first opening 92a and a second opening 92b.

  Then, using the resist 92 as a mask, Cu electrolytic plating is performed using the metal film 19 as a current path. As a result, the p-side metal pillar 23 and the n-side metal pillar 24 are formed as shown in FIG. 9A and the bottom view of FIG. 9B.

  The p-side metal pillar 23 is formed on the surface of the p-side wiring layer 21 in the first opening 92 a formed in the resist 92. The n-side metal pillar 24 is formed on the surface of the n-side wiring layer 22 in the second opening 92 b formed in the resist 92. The p-side metal pillar 23 and the n-side metal pillar 24 are made of, for example, a copper material formed simultaneously by a plating method.

  As shown in FIG. 10A, the resist 92 is removed using, for example, a solvent or oxygen plasma. Thereafter, the exposed portion of the metal film 19 is removed by wet etching using the metal pillar 23, the n-side metal pillar 24, the p-side wiring layer 21 and the n-side wiring layer 22 as a mask. As a result, as shown in FIG. 10B, the electrical connection between the p-side wiring layer 21 and the n-side wiring layer 22 through the metal film 19 is broken.

  Next, as shown in FIG. 11A, a resin layer 25 is laminated on the insulating film 18. The resin layer 25 covers the p-side wiring layer 21, the n-side wiring layer 22, the p-side metal pillar 23, and the n-side metal pillar 24.

  The resin layer 25 has an insulating property. Further, for example, carbon black may be contained in the resin layer 25 so as to provide a light shielding property to the light emitted from the light emitting layer 13.

  Next, as shown in FIG. 11B, the substrate 10 is removed. When the substrate 10 is a sapphire substrate, the substrate 10 can be removed by, for example, a laser lift-off method. Specifically, laser light is irradiated from the back surface side of the substrate 10 toward the first semiconductor layer 11. The laser beam is transmissive to the substrate 10 and has a wavelength that serves as an absorption region for the first semiconductor layer 11.

  When the laser light reaches the interface between the substrate 10 and the first semiconductor layer 11, the first semiconductor layer 11 near the interface absorbs the energy of the laser light and decomposes. The first semiconductor layer 11 is decomposed into gallium (Ga) and nitrogen gas. By this decomposition reaction, a minute gap is formed between the substrate 10 and the first semiconductor layer 11, and the substrate 10 and the first semiconductor layer 11 are separated.

  Laser light irradiation is performed over the entire wafer in multiple times for each set region, and the substrate 10 is removed.

  When the substrate 10 is a silicon substrate, the substrate 10 can be removed by etching.

  Since the above-described laminate formed on the main surface of the substrate 10 is reinforced by the p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 that are thicker than the semiconductor layer 15, even if the substrate 10 disappears. It is possible to keep the wafer state.

  The resin layer 25 and the metal constituting the p-side metal pillar 23 and the n-side metal pillar 24 are also flexible materials compared to the semiconductor layer 15. The semiconductor layer 15 is supported on such a flexible support. Therefore, even if a large internal stress generated when the semiconductor layer 15 is epitaxially grown on the substrate 10 is released at a time when the substrate 10 is peeled off, the semiconductor layer 15 can be prevented from being destroyed.

  The first surface 15a of the semiconductor layer 15 from which the substrate 10 has been removed is cleaned. For example, gallium (Ga) attached to the first surface 15a is removed with dilute hydrofluoric acid or the like.

  Thereafter, the first surface 15a is wet-etched with, for example, a KOH (potassium hydroxide) aqueous solution or TMAH (tetramethylammonium hydroxide). Thereby, unevenness is formed on the first surface 15a as shown in FIG. 12A due to the difference in the etching rate depending on the crystal plane orientation. Alternatively, etching may be performed after patterning with a resist to form irregularities on the first surface 15a. The light extraction efficiency can be improved by forming irregularities on the first surface 15a.

  Next, as shown in FIG. 12B, the phosphor layer 30 is formed on the first surface 15a. The phosphor layer 30 is also formed on the insulating film 18 between the adjacent semiconductor layers 15.

  The liquid transparent resin 31 in which the phosphor 32 is dispersed is supplied onto the first surface 15a by, for example, a method such as printing, potting, molding, compression molding, etc., and then thermally cured.

  Further, a transparent film 35 is formed on the upper surface of the phosphor layer 30. When the transparent film 35 is an inorganic film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, the transparent film 35 can be formed by, for example, a CVD method. When the transparent film 35 is a resin material, the transparent film 35 can be formed by supplying a liquid resin onto the phosphor layer 30 and then curing it. Alternatively, a film-like transparent film 35 may be adhered on the phosphor layer 30.

  Next, the surface of the resin layer 25 (the lower surface in FIG. 12 (b)) is ground, and as shown in FIG. 13 (a) and FIG. The external terminal 24a is exposed.

  Thereafter, the transparent film 35, the phosphor layer 30, the insulating film 18, and the resin layer 25 are cut at the position of the groove 80 described above and separated into a plurality of semiconductor light emitting devices 1. For example, cutting is performed using a dicing blade. Or you may cut | disconnect by laser irradiation.

  At the time of dicing, the substrate 10 has already been removed. Furthermore, since the semiconductor layer 15 does not exist in the groove 80, damage to the semiconductor layer 15 during dicing can be avoided. In addition, a structure in which the end portion (side surface) of the semiconductor layer 15 is covered and protected by the insulating film 18 can be obtained without an additional step after separation.

  The singulated semiconductor light emitting device 1 may have a single chip structure including one semiconductor layer 15 or a multichip structure including a plurality of semiconductor layers 15.

  The above-described processes before dicing are performed all at once in the wafer state, so there is no need to perform wiring and packaging for each individual device, and the production cost can be greatly reduced. It becomes possible. That is, wiring and packaging have already been completed in the state of being separated. For this reason, productivity can be improved and as a result, price reduction becomes easy.

  As shown in FIG. 14A, the semiconductor light emitting device 1 is cut from the resin layer 25 side with the transparent film 35 attached to the cover tape 85.

  Then, the separated semiconductor light emitting device 1 is peeled off from the cover tape 85 and the case 100 with the resin layer 25 and the metal pillars 23 and 24 facing downward as shown in FIG. 14B. Is housed in the recess 101.

  According to the embodiment, the semiconductor light emitting device 1 is attached to the cover tape 85 via the transparent film 35 having lower adhesiveness than the transparent resin 31 of the phosphor layer 30. For this reason, the semiconductor light emitting device 1 can be easily peeled from the cover tape 85 without damaging the phosphor layer 30. That is, according to the embodiment, the handleability of the semiconductor light emitting device 1 after separation can be improved.

  As shown in FIG. 15A, the transparent film 35 may be provided on the side surface of the semiconductor light emitting device (the side surface of the phosphor layer 30, the side surface of the insulating film 18, and the side surface of the resin layer 25).

  Dicing without forming the transparent film 35 on the phosphor layer 30, and forming the transparent film 35 by, for example, a spray coating method on the upper surface and the side surface of each individual semiconductor light emitting device. The structure of 15 (a) can be obtained.

  By providing the low-viscosity transparent film 35 also on the side surface of the semiconductor light emitting device, the semiconductor light emitting device is accommodated in the recess 101 of the case 100 as shown in FIG. Even if the side surface is in contact with the side wall of the recess 101, the side surface of the semiconductor light emitting device can be easily separated from the side wall of the recess 101, and the removal of the semiconductor light emitting device from the case 100 is not prevented.

  Further, on the first surface 15a, a lens 36 may be provided as in the semiconductor light emitting device 2 shown in FIGS. 16 (a) to 16 (c) and FIG. The lens 36 is not limited to a concave shape, and may be a convex shape.

  FIG. 16A is a schematic perspective view of a semiconductor light emitting device 2 according to a modification of the first embodiment. FIG.16 (b) is AA sectional drawing in Fig.16 (a). FIG.16 (c) is BB sectional drawing in Fig.16 (a).

  FIG. 17 is a schematic cross-sectional view of a light emitting module having a configuration in which the semiconductor light emitting device 2 is mounted on the mounting substrate 200.

  As shown in FIGS. 16A and 16C, a part of the side surface of the p-side metal pillar 23 has a third surface 25 b having a plane orientation different from that of the first surface 15 a and the second surface of the semiconductor layer 15. Thus, the resin layer 25 is exposed. The exposed surface functions as a p-side external terminal 23b for mounting on an external mounting substrate.

  The third surface 25b is a surface substantially perpendicular to the first surface 15a and the second surface of the semiconductor layer 15. The resin layer 25 has, for example, four rectangular side surfaces, and one of the side surfaces is a third surface 25b.

  A part of the side surface of the n-side metal pillar 24 is exposed from the resin layer 25 on the same third surface 25b. The exposed surface functions as an n-side external terminal 24b for mounting on an external mounting substrate.

  Further, as shown in FIG. 16A, a part of the side surface 21b of the p-side wiring layer 21 is also exposed from the resin layer 25 on the third surface 25b and functions as a p-side external terminal. Similarly, a part of the side surface 22b of the n-side wiring layer 22 is exposed from the resin layer 25 on the third surface 25b and functions as an n-side external terminal.

  In the p-side metal pillar 23, portions other than the p-side external terminal 23 b exposed at the third surface 25 b are covered with the resin layer 25. Further, in the n-side metal pillar 24, a portion other than the n-side external terminal 24 b exposed at the third surface 25 b is covered with the resin layer 25.

  Further, in the p-side wiring layer 21, portions other than the side surface 21 b exposed at the third surface 25 b are covered with the resin layer 25. Further, in the n-side wiring layer 22, a portion other than the side surface 22 b exposed at the third surface 25 b is covered with the resin layer 25.

  As shown in FIG. 17, the semiconductor light emitting device 2 is mounted in a posture in which the third surface 25 b faces the mounting surface 201 of the mounting substrate 200. The p-side external terminal 23b and the n-side external terminal 24b exposed at the third surface 25b are respectively joined to the pads 202 formed on the mounting surface 201 via the solder 203. A wiring pattern is also formed on the mounting surface 201 of the mounting substrate 200, and the pad 202 is connected to the wiring pattern.

  The third surface 25b is substantially perpendicular to the first surface 15a, which is the main light emission surface. Accordingly, with the third surface 25b facing the lower mounting surface 201, the first surface 15a faces the lateral direction, not the upper surface of the mounting surface 201. That is, the semiconductor light emitting device 2 is a so-called side view type semiconductor light emitting device that emits light in the lateral direction when the mounting surface 201 is a horizontal plane.

  In such a side view type semiconductor light emitting device 2 as well, by providing the low-adhesive transparent film 35 on the phosphor layer 30, the semiconductor light emitting device 2 can be easily peeled from the cover tape 85, Handleability can be improved.

(Second Embodiment)
FIG. 18 is a schematic cross-sectional view of the semiconductor light emitting device 3 of the second embodiment.

  The semiconductor light emitting device 3 of the second embodiment is different from the semiconductor light emitting device 1 of the first embodiment in the configuration on the first surface 15a. Including a semiconductor layer 15, a p-side electrode 16, an n-side electrode 17, an insulating film 18, a p-side wiring layer 21, an n-side wiring layer 22, a p-side metal pillar 23, an n-side metal pillar 24, and a resin layer 25. The configuration on the opposite side of the first surface 15a is the same as in the first embodiment.

  According to the semiconductor light emitting device 3 of the second embodiment, the transparent laminated film 40 is provided on the first surface 15a. The transparent laminated film 40 does not contain a phosphor and is transparent to the light emitted from the light emitting layer 13.

  The semiconductor layer 15 includes gallium nitride. The transparent laminated film 40 has a refractive index between the refractive index of gallium nitride (about 2.4) and the refractive index of air (1.0).

  The transparent laminated film 40 includes an organic film 41 provided in contact with the first surface 15 a and one or more transparent films 42 provided on the organic film 41 and having a refractive index smaller than that of the organic film 41.

  The organic film 41 is a compound containing carbon and has transparency to the light emitted from the light emitting layer 13. The refractive index of the organic film 41 is lower than that of gallium nitride and higher than that of air. For the organic film 41, for example, a thermoplastic resin such as an epoxy resin having a refractive index of 1.50 to 1.65 or a melamine resin having a refractive index of 1.60 to 1.75 can be used. The organic film 41 can also be a hybrid material in which an epoxy resin and a silicone resin are mixed.

  The organic film 41 covers the unevenness of the first surface 15a, and the upper surface of the organic film 41 is flat. The organic film 41 is easier to ensure flatness than the inorganic film, and facilitates optical design, handling, and mountability.

  The transparent film 42 provided on the organic film 41 is also transmissive to the light emitted from the light emitting layer 13. The refractive index of the transparent film 42 is lower than the refractive index of the organic film 41 and higher than the refractive index of air. For the transparent film 42, for example, a silicone resin having a refractive index of 1.45 to 1.60, a polycarbonate resin having a refractive index of 1.40 to 1.60 can be used. Alternatively, the transparent film 42 may be a silicon oxide film or a silicon nitride film that can be formed by a CVD method or a sputtering method.

  In FIG. 18, only one layer of the transparent film 42 is shown, and a plurality of transparent films 42 may be provided. In that case, the plurality of transparent films 42 have a higher refractive index as a film provided on the organic film 41 side and a lower refractive index as a film provided on the air layer side.

  According to the second embodiment, the first surface 15a containing gallium nitride has a refractive index between gallium nitride and air, and the refractive index is higher on the first surface 15a side, and on the air layer side. A transparent laminated film 40 that is a laminated film of a plurality of films having a low refractive index is provided. Thereby, it is possible to prevent the refractive index of the medium from changing greatly in the light extraction direction through the first surface 15a, and to improve the light extraction efficiency.

  In the semiconductor light emitting device 3 of the second embodiment, not only the plurality of vias 21a but also the p side via one post 21c having a larger planar size than the via 21a as shown in FIG. 15B. The wiring layer 21 may be connected to the p-side electrode 16. In this case, the heat dissipation of the light emitting layer 13 is improved through the p-side electrode 16, the p-side wiring layer 21, and the p-side metal pillar 23, all of which are metals. Can be planned.

  Also in the semiconductor light emitting device 3 of the second embodiment, the side surface, not the lower surface, of the p-side metal pillar 23 is exposed to form a p-side external terminal, and the side surface, not the lower surface, of the n-side metal pillar 24 is exposed. A side view type semiconductor light emitting device can be used as the external terminal.

  FIG. 19A is a schematic cross-sectional view illustrating a modification of the semiconductor light emitting device of the first embodiment.

  In the semiconductor light emitting device shown in FIG. 19A, p-side pads 51 that cover the p-side electrode 16 are provided on the surface and side surfaces of the p-side electrode 16. The p-side electrode 16 includes, for example, at least one of nickel (Ni), gold (Au), and rhodium (Rh) that can form an alloy with gallium (Ga) included in the semiconductor layer 15. The p-side pad 51 has a higher reflectance with respect to the emitted light of the light-emitting layer 13 than the p-side electrode 16 and contains, for example, silver (Ag) as a main component. The p-side pad 51 protects the p-side electrode 16 from oxidation and corrosion.

  An n-side pad 52 that covers the n-side electrode 17 is provided on the surface and side surfaces of the n-side electrode 17. The n-side electrode 17 includes, for example, at least one of nickel (Ni), gold (Au), and rhodium (Rh) that can form an alloy with gallium (Ga) included in the semiconductor layer 15. The n-side pad 52 has a higher reflectance with respect to the emitted light of the light-emitting layer 13 than the n-side electrode 17 and contains, for example, silver (Ag) as a main component. The n-side pad 52 protects the n-side electrode 17 from oxidation and corrosion.

  An insulating film 53 such as a silicon oxide film or a silicon nitride film is provided around the p-side electrode 16 and the n-side electrode 17 on the second surface of the semiconductor layer 15. The insulating film 53 is provided between the p-side electrode 16 and the n-side electrode 17 and between the p-side pad 51 and the n-side pad 52.

  On the insulating film 53, the p-side pad 51, and the n-side pad 52, an insulating film 54 such as a silicon oxide film or a silicon nitride film is provided. The insulating film 54 is also provided on the side surface 15c of the semiconductor layer 15 and covers the side surface 15c.

  On the insulating film 54, the p-side wiring layer 21 and the n-side wiring layer 22 are provided. The p-side wiring layer 21 is connected to the p-side pad 51 through the first opening 54 a formed in the insulating film 54. The n-side wiring layer 22 is connected to the n-side pad 52 through the second opening 54 b formed in the insulating film 54.

  Also in this structure, the p-side wiring layer 21 may be connected to the p-side pad 51 through a plurality of vias 21a as shown in the figure, or a single post having a larger planar size than the via 21a. To the p-side pad 51.

  A p-side metal pillar 23 thicker than the p-side wiring layer 21 is provided on the p-side wiring layer 21. An n-side metal pillar 24 thicker than the n-side wiring layer 22 is provided on the n-side wiring layer 22.

  A resin layer 25 is laminated on the insulating film 54. The resin layer 25 covers the p-side wiring part including the p-side wiring layer 21 and the p-side metal pillar 23 and the n-side wiring part including the n-side wiring layer 22 and the n-side metal pillar 24. However, the surface (the lower surface in the figure) opposite to the p-side wiring layer 21 in the p-side metal pillar 23 is exposed from the resin layer 25 and functions as the p-side external terminal 23a. Similarly, the surface (the lower surface in the drawing) opposite to the n-side wiring layer 22 in the n-side metal pillar 24 is exposed from the resin layer 25 and functions as the n-side external terminal 24a.

  Alternatively, the side surface of the p-side metal pillar 23 and the side surface of the n-side metal pillar 24 may be exposed to form a side view type semiconductor light emitting device.

  The resin layer 25 is filled through the insulating film 54 into the groove 80 described above that separates the semiconductor layer 15 into a plurality of parts on the substrate 10. Therefore, the side surface 15 c of the semiconductor layer 15 is covered and protected by the insulating film 54 that is an inorganic film and the resin layer 25.

  In the structure below the first surface 15a shown in FIG. 19A, a transparent laminated film 40 may be provided on the first surface 15a as shown in FIG. 19B. The configuration and function of the transparent multilayer film 40 are the same as those in the second embodiment.

  In the embodiment described above, the p-side wiring layer 21 and the n-side wiring layer 22 may be bonded to the pads of the mounting substrate without providing the p-side metal pillar 23 and the n-side metal pillar 24.

  In addition, the p-side wiring layer 21 and the p-side metal pillar 23 are not limited to separate bodies, and the p-side wiring layer 21 and the p-side metal pillar 23 are integrally provided in the same process to constitute the p-side wiring portion. May be. Similarly, the n-side wiring layer 22 and the n-side metal pillar 24 are not limited to being separate bodies, and the n-side wiring layer 22 and the n-side metal pillar 24 are integrally provided in the same process to form the n-side wiring portion. It may be configured.

  In the semiconductor light emitting device 1 according to the first embodiment, the transparent film 35 is not limited to be formed as a continuous film on the upper surface of the phosphor layer 30, but is island-shaped or partially as shown in FIG. Even if formed, since the low-adhesive transparent film 35 exists on the phosphor layer 30, the semiconductor light-emitting device 1 can be easily peeled off from the cover tape 85, and the handleability can be improved. The transparent film 35 formed on the side surface of the semiconductor light emitting device may also be formed in an island shape or partially as shown in FIG.

(Third embodiment)
FIG. 21A is a schematic cross-sectional view of the semiconductor light emitting device of the third embodiment.

  The semiconductor light emitting device of the third embodiment includes an adhesion layer 37 provided between the first surface 15 a of the semiconductor layer 15 and the phosphor layer 30. The adhesion layer 37 does not include a phosphor and is transparent to the light emitted from the light emitting layer 13.

  The adhesion layer 37 is formed conformally along the unevenness of the first surface 15 a and is thinner than the phosphor layer 30. Concavities and convexities reflecting the concavities and convexities of the first surface 15 a are also formed on the upper surface of the adhesion layer 37. The phosphor layer 30 is provided on the uneven surface of the adhesion layer 37.

The adhesion layer 37 includes, for example, a silicon oxide film (SiO ₂ film), a silicon nitride film (SiN film), a glass film (SOG (spin on glass) film) formed by spin coating, and a silicon oxynitride film (SiON film). ), A silicon carbide film (SiC film), and a carbon-containing silicon oxide film (SiOC film).

  The adhesion layer 37 has higher adhesion to the phosphor layer 30 than the semiconductor layer 15. That is, the force required to peel the phosphor layer 30 adhered to the adhesion layer 37 from the adhesion layer 37 is greater than the force required to peel the phosphor layer 30 adhered to the semiconductor layer 15 from the semiconductor layer 15. large. For this reason, peeling of the phosphor layer 30 from the semiconductor layer 15 can be prevented and reliability can be improved.

  FIG. 28 is a graph comparing the presence or absence of the adhesion layer 37 and the adhesion strength (MPa) of the phosphor layer 30 depending on the material of the adhesion layer 37. The adhesion strength is a value determined by a stud pull method (tensile test).

  “No adhesion layer” represents a structure in which the phosphor layer 30 is provided directly on the first surface 15 a without providing the adhesion layer 37. In this case, the adhesion strength of the phosphor layer 30 to the first surface 15a is about 2.0 (MPa).

When an SOG film is provided as the adhesion layer 37, the adhesion strength of the phosphor layer 30 is about 3.0 (MPa). When the SiO ₂ film is provided as the adhesion layer 37, the adhesion strength of the phosphor layer 30 is about 3.5 (MPa). When a SiN film is provided as the adhesion layer 37, the adhesion strength of the phosphor layer 30 is about 4.7 (MPa).

From the graph of FIG. 28, the structure in which the adhesion layer 37 is provided can increase the adhesion strength of the phosphor layer 30 than the structure in which the adhesion layer 37 is not provided. Further, as the material of the adhesion layer 30, adhesion strength towards the SiO ₂ film than SOG film and the phosphor layer 30 is high, who SiN film than SiO ₂ film adhesion strength between the phosphor layer 30 high.

  An adhesion layer 37 having a refractive index between the refractive index of gallium nitride and the refractive index of air is provided on the first surface 15a containing gallium nitride. For this reason, it is possible to prevent the refractive index of the medium from changing greatly in the light extraction direction through the first surface 15a, and to improve the light extraction efficiency.

  FIG. 23A shows a structure in which an adhesive layer 37 is provided between the first surface 15 a and the phosphor layer 30 in the structure of FIG. 1 in which the above-described transparent film 35 is provided on the upper surface of the phosphor layer 30. Represents.

  The transparent body on the first surface 15a to be improved in adhesion with the semiconductor layer 15 by the adhesion layer 37 is not limited to the phosphor layer 30, and as shown in FIG. The transparent laminated film 40 of the embodiment may be used.

  That is, the adhesion layer 37 is provided between the first surface 15 a and the organic film 41 of the transparent laminated film 40, and has a higher adhesion to the organic film 41 than the semiconductor layer 15. That is, the force required to peel the organic film 41 adhered to the adhesion layer 37 from the adhesion layer 37 is greater than the force required to peel the organic film 41 adhered to the semiconductor layer 15 from the semiconductor layer 15. For this reason, peeling of the organic film 41 with respect to the semiconductor layer 15 and by extension, the transparent laminated film 40 is prevented, and reliability can be improved.

  Further, in the semiconductor light emitting device shown in FIG. 23B, a transparent film 35 is provided on the upper surface of the transparent film 42 of the transparent laminated film 40.

  The transparent film 35 is less sticky (tackiness) than the transparent film 42. Therefore, the force required to peel off the cover tape 85 shown in FIG. 14A attached to the transparent film 35 from the transparent film 35 at a constant speed causes the cover tape 85 attached to the transparent film 42 to be transparent. It is smaller than the force required to peel from 42 at a constant speed.

  That is, the semiconductor light emitting device of FIG. 23B is attached to the cover tape 85 via the transparent film 35 having lower adhesiveness than the transparent film 42. For this reason, the semiconductor light emitting device can be easily peeled off from the cover tape 85 without damaging the transparent laminated film 40, and the handleability of the semiconductor light emitting device after separation can be improved.

  FIG. 24A shows a structure in which an adhesion layer 37 is provided between the first surface 15a and the phosphor layer 30 in the structure of FIG. FIG. 24B shows a structure in which an adhesion layer 37 is provided between the first surface 15a and the phosphor layer 30 in the structure of FIG. In the structure of FIG. 24B, the transparent film 35 on the phosphor layer 30 may be omitted as shown in FIG.

  FIG. 25 shows a structure in which an adhesion layer 37 is provided between the first surface 15 a and the phosphor layer 30 in the side view type structure shown in FIG. 17. 25, the lens 36 shown in FIG. 17 is not provided, but the lens 36 may be provided on the adhesion layer 37. In the structure of FIG. 25, as shown in FIG. 22A, the transparent film 35 on the surface of the phosphor layer 30 opposite to the first surface 15a may not be provided.

  FIG. 26A shows a structure in which an adhesion layer 37 is provided between the first surface 15a and the phosphor layer 30 in the structure shown in FIG. In the structure of FIG. 26A, as shown in FIG. 22B, the transparent film 35 on the phosphor layer 30 may not be provided.

  FIG. 26B shows a structure in which a transparent film 35 is provided on the upper surface of the transparent film 42 of the transparent laminated film 40 in the structure shown in FIG. Further, in the structure of FIG. 26B, a transparent film 35 is provided on the phosphor layer 30.

  FIG. 27A shows a structure in which an adhesion layer 37 is provided between the first surface 15a and the phosphor layer 30 in the structure shown in FIG. FIG. 27B shows a structure in which an adhesion layer 37 is provided between the first surface 15 a and the phosphor layer 30 in the structure shown in FIG.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1-3 ... Semiconductor light-emitting device, 10 ... Board | substrate, 11 ... 1st semiconductor layer, 12 ... 2nd semiconductor layer, 13 ... Light emitting layer, 15 ... Semiconductor layer, 15a ... 1st surface, 16 ... p side electrode 17 ... n-side electrode, 18 ... insulating film, 21 ... p-side wiring layer, 22 ... n-side wiring layer, 23 ... p-side metal pillar, 24 ... n-side metal pillar, 25 ... resin layer, 30 ... phosphor layer 31 ... Transparent resin, 32 ... Phosphor, 35 ... Transparent film, 37 ... Adhesion layer, 40 ... Transparent laminated film, 41 ... Organic film, 42 ... Transparent film, 85 ... Cover tape, 100 ... Case

Claims (13)

A laminate having a first surface provided with irregularities, a second surface opposite to the first surface, and a light emitting layer;
A p-side electrode provided on the second surface in the region including the light emitting layer;
An n-side electrode provided on the second surface in a region not including the light emitting layer;
A phosphor layer provided on the first surface;
An adhesion layer provided between the first surface and the phosphor layer along the unevenness of the first surface, and an upper surface having unevenness;
A semiconductor light emitting device comprising:   The semiconductor light emitting device according to claim 1, wherein the adhesion layer includes at least one of a silicon oxide film, a silicon nitride film, a glass film, a silicon oxynitride film, a silicon carbide film, and a carbon-containing silicon oxide film. Further comprising a light-shielding resin provided around the laminate,
The semiconductor light-emitting device according to claim 1, wherein the phosphor layer is also provided on the resin via the adhesion layer.   4. The semiconductor light emitting device according to claim 3, wherein the upper surface of the adhesion layer on the laminate is provided with unevenness larger than the upper surface of the adhesion layer on the resin.   5. The semiconductor light emitting device according to claim 1, further comprising a transparent film that is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an acrylic resin film provided on the phosphor layer. apparatus. A laminated body having a first surface provided with unevenness, a second surface opposite to the first surface, and a light emitting layer, and including gallium nitride;
A p-side electrode provided on the second surface in the region including the light emitting layer;
An n-side electrode provided on the second surface in a region not including the light emitting layer;
A transparent laminated film that is provided on the first surface and has a refractive index between the refractive index of the gallium nitride and the refractive index of air, and does not include a phosphor;
An adhesion layer provided between the first surface and the transparent laminated film along the irregularities of the first surface, and an upper surface having irregularities;
With
The transparent laminated film is
An organic film provided in contact with the adhesion layer;
One or more transparent films provided on the organic film and having a refractive index lower than that of the organic film, the transparent film having a higher refractive index as the film is provided on the organic film side;
A semiconductor light emitting device.   The semiconductor light emitting device according to claim 6, wherein unevenness is provided on the first surface, and an upper surface of the organic film covering the unevenness is flat.   8. The semiconductor light emitting device according to claim 6, further comprising a second transparent film that is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an acrylic resin film provided on the transparent laminated film. A first insulating film provided on the second surface side and having a first opening communicating with the p-side electrode and a second opening communicating with the n-side electrode;
A p-side wiring portion provided on the first insulating film and electrically connected to the p-side electrode through the first opening;
An n-side wiring portion provided on the first insulating film and electrically connected to the n-side electrode through the second opening;
The semiconductor light-emitting device according to claim 1, further comprising:   The semiconductor light-emitting device according to claim 9, wherein the first insulating film covers a side surface continuing from the first surface of the stacked body.   The semiconductor light emitting device according to claim 9, further comprising a second insulating film provided between the p-side wiring portion and the n-side wiring portion.   The semiconductor light emitting device according to claim 11, wherein the second insulating film covers a periphery of the p-side wiring portion and a periphery of the n-side wiring portion. The p-side wiring portion is
A p-side wiring layer provided in the first opening and on the first insulating film;
A p-side metal pillar provided on the p-side wiring layer and thicker than the p-side wiring layer;
Have
The n-side wiring portion is
An n-side wiring layer provided in the second opening and on the first insulating film;
An n-side metal pillar provided on the n-side wiring layer and thicker than the n-side wiring layer;
The semiconductor light-emitting device according to claim 9, comprising:

Images