JP2015228060A - Arithmetic processing unit and control method for arithmetic processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic processing unit capable of setting cache division information between arithmetic processing units and the control method of the arithmetic processing unit.SOLUTION: The arithmetic processing unit includes: a plurality of cores; and a first cache including a first cache control part and a first cache memory. The first cache control part includes: a first core group for performing cache division control to divide the first cache memory in accordance with a memory access request source; a second core group configured similarly as the first core group; and an inter-core group bus to which a memory access request is transmitted. When the memory access request source of the first core group issues a memory access request to a main memory managed by the second core group by adding second cache division information, a second cache control part of the second core group registers the added second cache division information in response to the memory access request.

Description

  The present invention relates to an arithmetic processing unit and a control method for the arithmetic processing unit.

  An arithmetic processing unit (or CPU (CPU: Central Processing Unit)) includes one or a plurality of CPU cores and a cache memory used by the CPU cores, and the CPU core includes a primary cache memory therein. The cache memory is a secondary cache memory (hereinafter referred to as L2 cache memory) used by the CPU core.

  A large-scale arithmetic processing device generates a plurality of virtual machines (hereinafter referred to as VMs (Virtual Machines)) in a CPU core by virtualization technology, and the plurality of virtual machines share a cache memory. Further, when the CPU core processes a plurality of processes, the plurality of processes share the cache memory. Alternatively, the plurality of CPU cores share the cache memory. As described above, cache memory sharing units include memory access request sources such as a plurality of CPU cores, a plurality of processes, and a plurality of VMs.

  On the other hand, the cache memory has a plurality of way structures and allows a plurality of cache blocks to be registered for a common index, thereby increasing the capacity of the cache memory. As the number of ways increases, the number of cache blocks that can be used for the same index increases and the use efficiency of the cache memory improves.

  In recent arithmetic processing units, it is possible to set the maximum number of ways of a cache memory corresponding to a plurality of request sources (for example, a plurality of CPU cores, a plurality of processes, and a plurality of VMs) issuing memory access requests. Therefore, cache partition control has been proposed in which the cache memory is divided into different sizes and assigned to a plurality of request sources. For example, the following patent documents.

  According to this cache partitioning control, it is possible to set the maximum number of ways that each requester can use. If a cache miss occurs when registering data in the cache memory in response to a memory access request, for example, a load request, a request is made at this time. Compare the number of ways originally assigned to the preset maximum number of ways, and if the number of currently assigned ways has not reached the maximum number of ways, replace the cache block assigned to another request source. Then, the data of the current request source is stored, and if it has reached, the cache block allocated to the current request source is replaced and stored.

  The maximum number of ways that can be used by each request source is set by, for example, a special instruction for setting the maximum number of ways from the CPU core, or by adding the maximum number of ways to the memory access request. When the registration of data to the cache memory occurs after the maximum number of ways has been set, the data is stored in the cache block replaced by the above replacement process, and the size of the cache memory allocated to each request source is maximized. Controlled to maintain less than the number of ways. In this way, the cache size divided by the cache division control is dynamically changed to efficiently use a limited amount of cache memory for a plurality of request sources.

JP 2009-163450 A JP 2011-18196 A JP2012-203729A JP 2002-140234 A JP 2007-299423 A

  A large-scale information processing apparatus is equipped with an arithmetic processing unit system composed of a plurality of arithmetic processing units. Each arithmetic processing unit has a plurality of CPU cores and a cache memory shared by them, and each arithmetic processing unit accesses a main memory managed by each arithmetic processing unit, and registers data in the cache memory of each arithmetic processing unit. Therefore, each arithmetic processing unit performs cache division control by setting the maximum number of ways of each cache memory for each of a plurality of memory access request sources (for example, a plurality of VMs).

  However, the first arithmetic processing unit cannot set the cache division information including the request source and the maximum number of ways necessary for the cache division control in the second arithmetic processing unit. In order to make this possible, it is necessary to newly introduce a special instruction for setting the cache division information and to execute the special instruction by the first arithmetic processing unit. As a result, it is necessary to drastically change the configuration of the arithmetic processing unit so that special instructions can be processed. Further, since a new bus transaction occurs between the processing units by processing special instructions, the latency due to a normal memory access request is deteriorated.

  Therefore, an object of one embodiment is to provide an arithmetic processing device and a control method for the arithmetic processing device that can set cache division information between arithmetic processing devices.

The first aspect of the embodiment includes a first cache including a plurality of cores, a first cache control unit, and a first cache memory, wherein the first cache control unit includes a first cache A first core group for performing cache division control for dividing the first cache memory in response to a memory access request source based on the cache division information of
A second cache including a plurality of cores, a second cache control unit, and a second cache memory, wherein the second cache control unit accesses the memory based on the second cache division information A second core group for performing cache partitioning control for partitioning the second cache memory in response to a request source;
An inter-core group bus provided between the first and second core groups to which a memory access request is transmitted;
When the memory access request source of the first core group issues a memory access request to the main memory managed by the second core group with the second cache partition information added, the second core The second cache control unit of the group is an arithmetic processing unit that registers the added second cache division information in response to the issued memory access request.

  According to the first aspect, cache division information can be set between arithmetic processing devices.

It is a figure which shows the structure of the arithmetic processing unit in this Embodiment. It is a figure which shows the structure of the arithmetic processing unit in this Embodiment. It is a figure which shows the more detailed structure of cache L2_CACHE in this Embodiment. It is a flowchart figure of the replacement process by the replacement control part in the case of carrying out cache registration of data. It is a figure which shows an example of the format of the memory access request | requirement which can set the maximum number of ways in this Embodiment. It is a sequence diagram showing processing of a memory access request with the maximum number of ways in the present embodiment. It is a figure which shows the format of an IO store request with a cache registration instruction. An example in which the maximum number of ways is set in another core group by a memory access request with cache division information according to the present embodiment, and a comparative example in which the maximum number of ways is set in another core group by a dedicated maximum number of ways setting request It is a figure which shows a comparison with.

  FIG. 1 is a diagram showing a configuration of an arithmetic processing device according to the present embodiment. In FIG. 1, the first core group LOCAL_CPU_0 is a CPU that manages the first main memory M_MEM_0. The second core group HOME_CPU_1 is a CPU that manages the second main memory M_MEM_1. The first and second core groups may be different CPU chips, or may be different CPU units provided in a single CPU chip. In the present embodiment, the present invention can be applied to either an arithmetic processing device composed of different CPU chips or an arithmetic processing device composed of a single CPU chip. In the following, the two CPUs will be referred to as first and second core groups, respectively, without distinguishing between different CPU chip embodiments and single CPU chip embodiments.

  The first core group LOCAL_CPU_0 includes a plurality of, for example, four CPU cores CORE-00 to CORE-03, a cache L2_CACHE provided in common to those CPU cores, and an external hard disk connected via the IO bus IO_BUS. It has an IO device IO_DEVICE that controls input / output to / from an HDD, etc., and a remote buffer R_BUF. The first core group LOCAL_CPU_0 manages the main memory M_MEM_0 and controls its memory access. Each of the CPU cores CORE-00 to CORE-03 issues a memory access request to the cache L2_CACHE via the bus BUS_1 in the core group. When the cache L2_CACHE processes the memory access request and a cache miss occurs, the CPU core CORE-00 to CORE-03 Control memory access.

  The second core group LOCAL_CPU_1 also has a configuration similar to that of the first core group LOCAL_CPU_0, and a plurality of, for example, four CPU cores CORE-10 to CORE-13 and a cache L2_CACHE provided in common to those CPU cores. And an IO device IO_DEVICE for controlling input / output with an external hard disk HDD or the like, and a remote buffer R_BUF. The second core group LOCAL_CPU_1 manages the main memory M_MEM_1 and controls its memory access. Each of the CPU cores CORE-10 to CORE-13 issues a memory access request to the cache L2_CACHE via the bus BUS_1 in the core group. When the cache L2_CACHE processes the memory access request and a cache miss occurs, the CPU core CORE-10 to CORE-13 sends the memory access request to the main memory M_MEM_1. Control memory access.

  The first core group LOCAL_CPU_0 and the second core group HOME_CPU_1 are connected by an inter-core group bus BUS_0, and a memory access request to the main memory managed by the other core group issued by the core group is sent to the core. Sent by bus transaction via inter-group bus BUS_0.

  The above-mentioned first core group LOCAL_CPU_0 manages the main memory M_MEM_0 and controls its memory access specifically to the following management and control. A memory access request (load request or store request) for data in the main memory M_MEM_0 is executed by a memory access controller (not shown) in the first core group LOCAL_CPU_0. In addition, when the first core group LOCAL_CPU_0 generates a load request to the main memory M_MEM_0 and the data in the main memory M_MEM_0 is taken out by the second core group HOME_CPU_1, the fact is stored in the main memory or in the cache control. Store in the internal directory. After that, when writing to the data in the main memory M_MEM_0 occurs, the directory is checked, the data in the cache memory of the second core group HOME_CPU_1 that has taken out the data is invalidated, and then writing is performed. Run. As a result, data coherency can be maintained.

  In FIG. 1, the first core group is referred to as a local CPU as a memory access request issuer CPU, and the second core group is referred to as a home CPU as a CPU accessed from the memory access request issuer. In some cases, the first core group and the second core group have an opposite relationship.

  FIG. 2 is a diagram illustrating a configuration of the arithmetic processing device according to the present embodiment. FIG. 2 shows the configuration of the caches L2_CACHE_0 and L2_CACHE_1 in the first and second core groups, and further shows the virtual machine VM generated in each core. However, the bus BUS_1 and IO device in the core group are omitted.

  The cache L2_CACHE_0 in the first core group LOCAL_CPU_0 has a request port group R_PORT that stores various requests such as a memory access request issued by a core or the like. The request port group R_PORT consists of a move import MIP that stores a load request to read data from the memory, a move out port MOP that stores a request to write the data in the cache memory to the main memory M_MEM_0, and the data in the main memory as the cache memory Includes a prefetch port PFP for storing a prefetch request stored in advance, and a remote request port R_RP for storing a request from the second core group HOME_CPU1.

  The cache L2_CAHCE_0 includes a request control unit RC0 that selects a request in the request port group R_PORT with a predetermined priority algorithm and inputs or inputs the request to the cache control unit CC0, and a cache control unit CC0 that processes the input or input request. , A data memory D_RAM and a tag memory TAG constituting a cache memory. The cache control unit CC0 has a pipeline configuration and is also referred to as a cache pipeline. Further, the cache L2_CACHE_0 is connected to the move-in buffer MIB that performs processing when a cache miss occurs, the memory access controller MAC that controls memory access including reading and writing of the main memory M_MEM_0, and the second core group HOME_CPU1. A remote buffer R_BUF is provided for temporarily storing requests to the inter-core group bus B_00.

  In the example of FIG. 2, virtual machines VM are generated in four cores CORE_00 to CORE_03, respectively. As examples of memory access request sources, there are cores, processes, and virtual machines, and it has been explained that cache memory division is controlled according to memory access request sources by cache division control. In the present embodiment, a virtual machine VM will be described as an example of the memory access request source. However, the divided areas of the cache memory by the cache division control are generally distinguished and managed by sector IDs. In this case, the sector ID is associated with the memory access request source.

  According to FIG. 2, a virtual machine VM_00 is created in the core CORE_00, a virtual machine VM_01 is created in the core CORE_01, a virtual machine VM_02 is created in the core CORE_02, and a virtual machine VM_03 is created in the core CORE_03. . Then, it is shown that the maximum way number MAX_W indicating the maximum number of cache blocks is set to 2, 0, 4, 2 as an example for each of the virtual machines VM_00 to VM_03. The maximum way number MAX_W is set by, for example, a software way.

  The cache L2_CACHE_0 includes a replacement control unit RPC0 that performs cache block replacement control in cache partition control as part of the cache control unit CC0. The replacement control unit RPCO has a maximum way number table (maximum number of cache blocks) having the maximum number of ways MAX_W set for each virtual machine VM. In the example of FIG. 2, the maximum way number MAX_W is set to “2” and “2” for the virtual machines VM00 and VM03, and the maximum way number MAX_W is the initial value for the virtual machines VM01 and VM02. It remains “0”. When the initial value is “0”, it is assumed that cache division control is performed with the maximum number of ways set to infinity.

  In FIG. 2, the configuration in the second core group HOME_CPU1 is equivalent to the configuration in the first core group LOCAL_CPU_0. However, in a different configuration, virtual machines VM_10 to VM_13 are generated in the respective cores CORE_10 to CORE_13 in the second core group HOME_CPU1, and the maximum number of ways MAX_W remains “0”. Correspondingly, the maximum way number MAX_W set for each virtual machine in the maximum way number table in the replacement control unit RPC1 is also kept at “0”.

  As described above, the inter-core group bus BUS_0 is provided between the remote buffer R_BUF and the remote request port R_RP, and is also provided between the move-in buffer MIB.

  FIG. 3 is a diagram showing a more detailed configuration of the cache L2_CACHE in the present embodiment. Since the caches L2_CACHE of the first and second core groups have the same configuration as described above, FIG. 3 shows the cache L2_CACHE_0 in the first core group LOCAL_CPU_0.

  In FIG. 3, the tag memory TAG_RAM and the data memory D_RAM constituting the cache memory have a set associative configuration, and a multiple way configuration in which tag values and data of a plurality of cache blocks can be registered with respect to a common index. . Specifically, it is configured with, for example, 32 ways. As shown in the data memory D_RAM in FIG. 3, the cache memory is divided and assigned to four sectors 00 to 03 corresponding to the four virtual machines VM00 to VM03. Although not shown, the tag memory TAG_RAM is also divided into four sectors correspondingly. Therefore, in this example, four sectors 00 to 03 of the cache memory are assigned to four virtual machines VM00 to VM03, respectively.

  In the example of FIG. 3, for example, two ways (way numbers 0 and 1) are assigned to the virtual machine VM00, seven ways (way numbers 2 to 8) are assigned to VM01, and two ways are assigned to VM02. (Way numbers 9, 10) and 21 ways (way numbers 11 to 31) are assigned to VM03.

  On the other hand, the replacement control unit RPC0 that performs cache division control of the cache control unit CC0 includes a maximum way number table MW_TBL for registering the maximum number of ways MAX_W set corresponding to the IDs 00 to 03 of the virtual machine VM, and the way to be replaced. A replacement way selection unit RP_W. The replacement control by the replacement control unit RPCO will be described later.

  In addition to the cache L2_CACHE_0, FIG. 3 shows an intra-core group bus BUS_1 that connects the four cores CORE_00 to CORE_03 and the request port group R_PORT. In this way, the virtual machines VM in the four cores CORE_00 to CORE_03 issue memory access requests, move-out requests, and prefetch requests to the corresponding request ports MIP, MOP, and PFP via the bus BUS_1 in the core group, respectively. To do.

  Next, cache division control by the cache control unit will be described. As a premise, the virtual machine VM generated in the core CORE in the first core group LOCAL_CPU_0 issues a memory access request with the cache partition information added, and the maximum way in the replacement control unit RPC0 of the cache control unit CC0. Set the maximum number of ways in the number table MW_TLB. For example, the virtual machine VM_02 generated in the core CORE_02 issues a load request for the address of the main memory M_MEM_0 as a memory access request. This load request includes the load destination address in the main memory M_MEM_0 and the ID of the requesting virtual machine VM, and also includes information on the maximum number of ways.

  The load request issued by the core CORE_02 is stored in the move import MIP via the bus BUS_1 in the core group, and the request control unit RCO selects the load request entry in the move import MIP and inputs it to the cache control unit CC0. . In response to this load request entry, the cache control unit CC0 performs a cache hit determination, a data response to the core CORE_02 in the case of a cache hit, a read request to the main memory M_MEM_0 in the case of a cache miss hit, etc. Based on the cache partition information including the virtual machine ID and the maximum number of ways added to the load request, the maximum number of ways table MW_TBL in the replacement control unit RPC0 corresponds to the maximum of the virtual machine ID. Set the number of ways.

  With the maximum number of ways set in advance corresponding to the virtual machine ID, the same virtual machine VM_02 issues a load request, for example. When the cache control unit CC0 makes a cache miss determination in response to the load request, the cache miss control unit CC0 registers the entry in the move-in buffer MIB and reads it into the main memory M_MEM_0 via the memory access controller MAC. Make a request and receive a data response. In response to this, the aforementioned entry registered in the move-in buffer MIB is input again to the cache control unit CC0 together with the read data.

  In this case, the cache control unit CC0 registers the data read from the main memory and its tag information in the data memory D_RAM and the tag memory TAG_RAM constituting the cache memory. At the time of data registration in the cache memory, the replacement control unit RP0 selects a replacement way to which data and tag information are registered.

  FIG. 4 is a flowchart of the replacement process performed by the replacement control unit when registering data in the cache. In response to the cache registration entry registered in the move-in buffer MIB as described above (S30), the cache control unit CC0 requests the replacement control unit RPC0 to select a way to be registered in the cache. The replacement way selection unit RP_W in the replacement control unit RPC0 determines whether the current number of ways allocated to the virtual machine VM_02 is equal to the maximum number of ways MAX_WAY set in the maximum number of ways table MW_TBL, that is, the maximum number of ways. It is checked whether or not MAX_WAY has been reached (S32). If the current number of ways is equal to the maximum number of ways MAX_WAY (YES in S34), among the ways assigned to the virtual machine VM_02, for example, the least recently used, that is, the longest since it was used The way storing the data and the tag whose time has passed is selected (S36). On the other hand, if the current number of ways is not equal to the maximum number of ways MAX_WAY (NO in S34), among the ways assigned to virtual machines other than the virtual machine VM_02, the least recently used, for example, by the LRU algorithm, In other words, the way storing the data and tag that have been used for the longest time has been selected (S38).

  Then, the replacement control unit RP0 returns the selected way to the cache control unit CC0. Then, the cache control unit CC0 writes the data of the selected way back to the main memory M_MEM_0, and registers the cache registration target data and tag information in the selected way.

  The virtual machine VM generated in the core CORE in the second core group HOME_CPU_1 issues a memory access request with the cache partition information added thereto, and the maximum way number table MW_TLB in the replacement control unit RPC1 of the cache control unit CC1 The processing for setting the maximum number of ways in the same manner as described above. Further, the process of selecting a way to be registered by the replacement control unit RPC1 at the time of cache registration based on the set maximum number of ways is the same as described above.

  As described above, the virtual machine VM generated in the core CORE in the first core group LOCAL_CPU_0 adds cache partition information (virtual machine ID and maximum number of ways) to the memory access request to the main memory M_MEM_0. By issuing, the maximum number of ways can be set in the replacement control unit RPC0 of the cache L2_CACHE_0 in the first core group LOCAL_CPU_0. Thereby, based on the set maximum number of ways, the replacement control unit RPC0 of the cache control unit CC0 in the cache L2_CACHE_0 selects a way to be registered in the cache. As a result, the cache control unit CC0 in the first core group LOCAL_CPU_0 performs cache partition control for allocating a partition area of the cache memory to the virtual machine VM in the first core group LOCAL_CPU_0.

  Similarly, the virtual machine VM generated in the core CORE in the second core group HOME_CPU_1 issues a cache access information (virtual machine ID and maximum number of ways) to the memory access request to the main memory M_MEM_1. Thus, the maximum number of ways can be set in the replacement control unit RPC1 of the cache control unit CC1 in the cache L2_CACHE_1 in the second core group HOME_CPU_1. Thereby, based on the set maximum number of ways, the replacement control unit RPC1 of the cache L2_CACHE_1 selects a way to be registered in the cache. As a result, the cache control unit CC0 in the second core group HOME_CPU_1 performs cache partition control for allocating a partition area of the cache memory to the virtual machine VM in the second core group HOME_CPU_1.

  As described above, the virtual machines in the first and second core groups issue a memory access request to which cache partition information is added, so that the maximum way is sent to the cache replacement controllers RPC0 and RPC1 in the same core group. After that, the cache control unit performs cache division control when registering the cache. Similarly to the above, it is also possible to set the maximum number of ways by adding cache division information including the maximum number of ways to a store request that is a memory access request.

  On the other hand, a virtual machine in the local CPU that is the first core group LOCAL_CPU_0 may make a memory access request to the main memory M_MEM_1 managed by the home CPU that is the second core group HOME_CPU_1. For example, when the memory access request is a load request, when a virtual machine in the first core group LOCAL_CPU_0 issues a load request to the main memory M_MEM_1, the cache control in the first core group to which the load request is input The section CC0 determines a cache miss and stores the load request in the remote request port R_RP of the second core group HOME_CPU_1 via the remote buffer R_BUF and the inter-core bus BUS_0. In response to this load request, when the cache control unit CC1 of the second core group HOME_CPU_1 determines a cache miss, the memory access controller MAC executes a read request to the main memory M_MEM_1 to acquire data and move it. Data response is made to the move-in buffer MIB in the first core group LOCAL_CPU_0 via the in-buffer MIB and the inter-core group bus BUS_0. The data returned as a response is reintroduced from the move-in buffer MIB to the cache control unit CC0, and the cache control unit CC0 registers the data and tag information in cache.

  When the virtual machine in the first core group makes a load request to the main memory managed by the second core group in the above load request, the load request data is registered in the cache memory in the second core group. There is no. Therefore, there is no need for the virtual machines in the first core group to set the maximum number of ways in the replacement control unit RPC1 of the cache control unit CC1 in the second core group.

  On the other hand, when the memory access request is a store instruction, the second core group manages when the cache block of the data is evicted by writing the store data to the cache memory in the first core group and then cache control. Data is written back to the main memory. In this case as well, there is no need for the virtual machines in the first core group to set the maximum number of ways in the replacement control unit RPC1 of the cache control unit CC1 in the second core group.

  However, in recent years, in response to an IO store request from an IO device IO_DEVICE instead of a request from a virtual machine, the memory access controller MAC performs DMA (Direct Memory Access) processing on data transferred from an external storage device HDD or the like. As a result, data can be registered in the cache memory when writing to the main memory. This is so-called cache injection processing. The advantage of cache injection is that the cache control unit can respond to data in the cache memory in response to a load request issued after an IO store request, and the load request latency can be shortened. .

  In response to the DMA request requested by the virtual machine in the first core group LOCAL_CPU_0, the IO device IO_DEVICE of the second core group HOME_CPU_1 issues an IO store request, and in response, the cache control unit CC1 The cache injection process is also performed when the memory access controller MAC processes an IO store request. That is, by cache injection processing, the cache control unit CC1 in the second core group HOME_CPU_1 registers the data of the IO store request originating from the virtual machine in the first core group LOCAL_CPU_0 in the cache memory.

  In this case, the IO store request data requested by the virtual machine in the first core group is registered in the cache memory in the second core group. Therefore, the cache control unit CC1 needs to set the maximum number of ways for the virtual machines in the first core group in advance. The reason is that the initial value of the maximum number of ways is infinite, so if the maximum number of ways is not set and the cache controller CC1 registers the data downloaded from the outside by cache injection in the cache memory, the cache This is because data is registered in many cache blocks in the memory, and the virtual machine data in the second core group is evicted. As a result, the original cache division control cannot be performed.

  Therefore, in the present embodiment, as described below, the virtual machines in the first core group can set the maximum number of ways in the replacement control unit RPC1 of the cache control unit CC1 in the second core group. It has been improved. According to this embodiment, when the virtual machine VM in the first core group LOCAL_CPU_0 issues a memory access request to the main memory M_MEM_1 managed by the second core group HOME_CPU_1 with the cache division information added, In response to the memory access request, the cache control unit CC1 in the second core group HOME_CPU_1 sets the maximum number of ways in the maximum number of ways table in the replacement control unit RPC1. As described above, the cache division information added to the memory access request has the maximum number of ways and the sector number of the divided area of the cache memory. In the above-described example, this sector number is the ID number of the virtual machine VM that requests cache memory allocation. However, other than the ID number of the virtual machine VM, for example, a process ID requesting allocation of cache memory or a core ID may be used. It depends on how cache partitioning control is performed.

  The virtual machine in the first core group, which is the local CPU, issues a cache access information to the main memory M_MEM_1 managed by the second core group, which is the remote CPU, with cache partition information added, and issues the maximum way Make the number configurable. Thus, by making it possible to set the maximum number of ways in another core group by a memory access request, there is no need to define a special request for setting the maximum number of ways in another core group. In addition, when using a request for setting the maximum number of ways other than the normal memory access request, the traffic volume of the inter-core bus BUS_0 increases, and the latency of the normal memory access request deteriorates. Therefore, according to the present embodiment, it is possible to set the maximum number of ways in the cache control units in different core groups without increasing the traffic volume of the inter-core group bus BUS_0.

  FIG. 5 is a diagram showing an example of a format of a memory access request that can set the maximum number of ways in the present embodiment. Memory access requests for which the maximum number of ways can be set include a load request for reading data from the main memory and a store request for writing data to the main memory. The memory access request for which the maximum number of ways can be set may include a prefetch request and a moveout request.

  The memory access request of FIG. 5 has a 64-bit header HEADER and 16 sets of data blocks DATA # 0-15. In the case of a load request or prefetch request, only the header HEADER is required, and the data block DATA # 0-16 need not be included. In the example of the 64-bit header HEADER shown in FIG. 5, bits 0-6 are unused, the address ADDRESS in bits 7-46, the operand code OP_CODE in bits 47-53, and the virtual machine in bits 54-57. ID (VM_ID), and bits 58-63 include the maximum number of ways MAX_WAY, respectively.

The unused 7 bits correspond to the cache block size 128 bits = 2 ⁷ . Also, the information of bits 7-15 in the address ADDRESS is used as a search index for the cache memory. Further, the information of bit 16 in the address ADDRESS is used as a memory interleave bit. That is, the data having the memory interleave bit “0” is stored in the main memory M_MEM_0 managed by the first core group LOCAL_CPU_0, and the data having the memory interleave bit “1” is managed by the second core group HOME_CPU_1. Stored in the main memory M_MEM_1. Accordingly, the bit number 9 of bits 7-15 of the address ADDRESS is corresponds to the size 2 ⁹ on page region OS where (Operation System) manages. Further, the upper address of bits 17 to 46 in the address ADDRESS is used for tag information registered in the tag memory TAG of the cache memory.

  A load request and a store request are distinguished by the operation code OP_CODE. The virtual machine ID information is included in all requests, but the maximum number of ways MAX_WAY need only be included when setting the maximum number of ways, and is not necessarily included in all requests.

  FIG. 6 is a sequence diagram showing processing of a memory access request with the maximum number of ways in the present embodiment. As an example, the virtual machine VM_02 of the core CORE_2 in the first core group LOCAL_CPU_0, which is a local CPU (memory access request issuing CPU), is loaded to the main memory M_MEM_1 managed as the home CPU by the second core group HOME_CPU_1. Is issued to the Move Import MIP (S1). As described above, the virtual machine ID and the maximum number of ways MAX_WAY are added to this load request.

  Then, the request control unit RO0 inputs the load request to the cache control unit CC0. In response to the load request, the cache control unit CC0 searches the cache tag to determine a cache miss (S3), registers the load request entry in the move-in buffer MIB, and stores the load request in the remote buffer R_BUF ( S5). Further, since the memory interleave bit is “1”, the cache control unit CC0 does not set the maximum number of ways of the load request in the maximum way number table MW_TABLE in the replacement control unit RPC0 (S4). However, the cache control unit CC0 may set the maximum number of ways regardless of the memory interleave bit.

  The load request with the maximum number of ways stored in the remote buffer R_BUF is propagated to the remote request port R_RP in the second core group HOME_CPU_1 as a bus transaction via the inter-core group bus BUS_0 (S11).

  The request control unit RC1 in the second core group outputs the load request in the remote request port R_RP to the cache control unit CC1 (S12). In response to this, since the memory interleave bit of the load request is “1”, the cache control unit CC1 sets the maximum number of ways of the load request in the maximum way number table MW_TABLE in the replacement control unit RPC1 (S14). In response to the load request, the cache control unit CC1 searches the cache memory tag to determine a cache miss (S13), registers an entry in the move-in buffer MIB, and registers the main memory M_MEM_1 in the memory access controller MAC. Read processing is performed and load request data is read (S16).

  The memory access controller MAC responds the read data to the move-in buffer MIB, and the move-in buffer MIB together with the entry in which the read data is registered passes through the inter-core bus BUS_0 to the first core group HOME_CPU_1. A data response is made to the entry of the move-in buffer MIB in (S17). At this time, since it is a load request from the virtual machine VM_02 of the first core group, as described above, the cache control unit CC1 in the second core group HOME_CPU_1 does not perform cache registration of read data. Therefore, cache division control based on the set maximum number of ways is not performed.

  In response to the data response, the move-in buffer MIB in the first core group LOCAL_CPU_1 inputs the registered entry to the cache control unit CC0 (S22), and the cache control unit CC0 stores the tag information in the tag memory TAG_RAM of the cache memory. And the read data is registered in the data memory D_RAM (S23, S25). Then, the cache control unit CC0 returns a data response to the request source virtual machine VM_02 (S26).

  As described above, the virtual machine VM_02 in the first core group LOCAL_CPU_0 issues a load request for the main memory M_MEM_1 with cache division information added thereto, thereby issuing a replacement control of the cache control unit CC1 in the second core group HOME_CPU_1. The maximum number of ways of the virtual machine VM_02 can be set in the unit RPC1. In response to this load request, the cache control unit CC1 in the second core group does not register the cache in the cache memory, and also performs the cache block replacement control by the cache division control based on the set maximum number of ways. Absent.

  In the above example, the maximum number of ways is set in another core group by issuing a load request addressed to the main memory managed by another core group with the maximum number of ways added. However, it is not limited to load requests, and the maximum number of ways can be set for other core groups by issuing the maximum number of ways to store requests addressed to main memory managed by other core groups. Also good.

  In the arithmetic processing unit or the arithmetic processing unit system shown in FIGS. 1 and 2, a device with an IO other than the core CORE is asynchronous with the core CORE, and the virtual machine VM of the core CORE is expected to use data from the outside in the near future. Download and store in main memory and issue IO store request with cache registration to register in cache memory. The IO store request with a cache registration instruction may be a request for registering input data only in the cache memory without storing in the main memory.

  FIG. 7 is a diagram showing a format of an IO store request with a cache registration instruction. Similar to the header HEADER of the load / store request in FIG. 5, the format of the IO store request is that bits 0-6 are not used, the address ADDRESS is in bits 7-26, the operation code is in bits 47-53, and the bit 54- 57 is assigned the ID (VM_ID) of the virtual machine VM of the IO store request source. Bits 58-63 are unused.

  The virtual machine VM_02 in the first core group described in FIG. 6 sets the maximum number of ways in the replacement control unit RPC1 of the cache control unit CC1 in the second core group by a load request, and then performs DMA by the same virtual machine VM_02. The process when the IO device issues an IO store request with a cache registration instruction asynchronously with the virtual machine VM_02 in response to the request will be described. This IO store request includes the address of the main memory of the IO store destination as shown in FIG. In the following example, the main memory M_MEM_1 managed by the second core group HOME_CPU_1 is designated as the main memory of the IO store destination.

  In response to the DMA request issued by the virtual machine VM_02 in the first core group, the IO device in the second core group issues an IO store request with a cache registration instruction. This IO store request is input from the move import MIB in the second core group to the cache control unit CC1, and in response to this, the cache control unit CC1 sends the data input by the IO device to the memory access controller MAC in the main memory M_MEM_1. Process to write to. At the same time, the memory access controller MAC causes the cache control unit CC1 to register the data in the cache so that the input data is substantially prefetched into the cache memory. The memory access controller MAC may cause the cache control unit CC1 to perform cache registration without writing data to the main memory M_MEM_1.

  In the cache registration of data input by the IO device by the cache control unit CC1, the cache control unit CC1 controls the replacement of the cache block of the cache memory, that is, the way, based on the previously set maximum number of ways of the virtual machine VM_02. I do. The replacement control is as described with reference to FIG. Since the maximum number of ways of the virtual machine VM_02 has already been set in the replacement control unit RPC1 of the cache control unit CC1, the replacement control in the cache registration processing by the IO store request with the cache registration instruction is appropriately performed, and a large capacity input Most of the data of the virtual machines in the second core group that has already been cached by data is not evicted from the cache memory.

  Then, after the IO store request with the cache registration instruction is processed, when the virtual machine VM_02 in the first core group issues a load request for the IO stored data, the load request is in the first core group as described above. Is transferred from the cache control unit CC0 to the cache control unit CC1 in the second core group, the cache control unit CC1 detects a cache hit, and moves the prefetched data in the cache memory to the move-in buffer in the first core group. Responds to the MIB. Therefore, the latency of the load request issued by the virtual machine VM_02 is shortened.

  In the present embodiment, the virtual machine VM in the first core group receives a memory access request addressed to the main memory managed by the second core group, and the replacement control unit of the cache control unit CC1 in the second core group. Set the maximum number of ways to RPC1. Therefore, since a special request for setting the maximum number of ways is not issued, an increase in the traffic volume of the inter-core group bus BUS_0 can be suppressed. In addition, it is possible to suppress the deterioration of the busy rate of the cache control unit CC1 due to processing of special requests.

  FIG. 8 shows an example in which the maximum number of ways is set in another core group by a memory access request with cache division information according to the present embodiment and the maximum number of ways in another core group by a dedicated maximum number of ways setting request. It is a figure which shows the comparison with the comparative example to set. In the present embodiment, the cache partition information is updated by a load request with cache partition information, and in the comparative example, the cache partition information is updated by a dedicated maximum way number setting request.

  For example, the performance comparison is performed on the assumption that a transaction for updating the cache partition information occurs at a rate of once every 10 times. Further, as shown in FIG. 8, it is assumed that the load request ratio is 20%, the cache miss rate is 4% (cache hit rate is 96%), the cache hit latency is 20 cycles, and the cache miss latency is 200 cycles. Further, it is assumed that the number of instructions in the program is 100 and execution of instructions other than the load instruction for which a load request is issued is completed in one cycle. Then, when the dedicated maximum way number setting request is adopted, the number of requests competing for the inter-core bus BUS_0 is increased, so that it is assumed that the cache miss latency is deteriorated by, for example, 10% and becomes 220 cycles. When the dedicated maximum way number setting request is not adopted as in the present embodiment, it is assumed that the cache miss latency is 200 cycles as shown in FIG.

  When calculated based on the above assumption, execution of 100 program instructions is performed in an example in which the maximum number of ways is set by a normal load request as in the present embodiment and in a comparative example in which a dedicated maximum number of ways setting request is adopted. The number of cycles required for is as shown in FIG.

First, in the example of the present embodiment, the number of cycles required to execute 100 program instructions is one cycle other than load instructions (100-20), and a cache miss rate of 4% 200 out of 20 load instructions. Since the cycle and cache hit rate of 96% requires 20 cycles, adding these results in the following.
(100-20) × 1 [cycle] + 20 × 4% × 200 [cycle] + 20 × 96% × 20 [cycle] = 624 [cycle]
On the other hand, the number of cycles required to execute 100 program instructions in the comparative example employing a dedicated maximum way number setting request requires 220 cycles in the case of a cache miss. is there.
(100-20) × 1 [cycle] + 20 × 4% × 220 [cycle] + 20 × 96% × 20 [cycle] = 640 [cycle]
Actually, in the case of the comparative example, the busy rate of the pipeline control unit in the second core group which is the home CPU is also deteriorated by 10% similarly to the bus between core groups. Performance is expected to deteriorate beyond the above formula.

  As described above, compared to the comparative example, this embodiment adds cache division information to a load request or a store request to a main memory managed by another core group, and the cache control unit in the other core group Since the maximum number of ways is set, the overall operation efficiency can be increased.

  The above embodiment is summarized as follows.

(Appendix 1)
A first cache including a plurality of cores, a first cache control unit, and a first cache memory, wherein the first cache control unit accesses the memory based on the first cache division information; A first core group performing cache partitioning control for partitioning the first cache memory corresponding to a request source;
A second cache including a plurality of cores, a second cache control unit, and a second cache memory, wherein the second cache control unit accesses the memory based on the second cache division information A second core group for performing cache partitioning control for partitioning the second cache memory in response to a request source;
An inter-core group bus provided between the first and second core groups to which a memory access request is transmitted;
When the memory access request source of the first core group issues a memory access request to the main memory managed by the second core group with the second cache partition information added, the second core An arithmetic processing unit in which a second cache control unit of the group registers the added second cache division information in response to the issued memory access request.

(Appendix 2)
After the second cache control unit of the second core group registers the second cache partition information, the cache partition is performed on the second cache memory based on the registered second cache partition information. The arithmetic processing device according to attachment 1, which performs control.

(Appendix 3)
After the second cache control unit of the second core group registers the second cache division information, in response to a cache injection request for registering data input from the outside in the second cache memory The cache partition control is performed on the second cache memory based on the registered second cache partition information, and the input data is registered in the cache block selected by the cache partition control. The arithmetic processing unit described in 1.

(Appendix 4)
In response to the memory access request issued by the memory access request source of the first core group, the second cache control unit of the second core group does not register data in the second cache memory. The arithmetic processing unit according to attachment 1, wherein a data response is made to the memory access request source in the first core group.

(Appendix 5)
In response to the memory access request issued by the memory access request source of the first core group, the second cache control unit of the second core group sends data to the main memory managed by the second core group. The arithmetic processing unit according to appendix 1, wherein access processing is performed and data response is made to the memory access request source in the first core group without registering data accessed to the second cache memory.

(Appendix 6)
6. The arithmetic processing device according to appendix 4 or 5, wherein, in response to the data response, the first cache control unit registers the data response data in the first cache memory.

(Appendix 7)
The cache partition information includes the memory access request source and the maximum number of cache blocks allocated to the memory access request source.
When the cache partitioning control registers data in the cache memory, it is assigned to other memory access request sources until the current cache block number assigned to the memory access request source reaches the maximum cache block number. The arithmetic processing unit according to attachment 1, wherein the data is registered by allocating a cache block to the memory access request source.

(Appendix 8)
A first arithmetic processing unit connected via a bus to a second arithmetic processing unit having a plurality of cores and a cache memory,
With multiple cores,
A first cache including a first cache control unit and a first cache memory;
The first cache control unit performs cache division control to divide the first cache memory corresponding to a memory access request source based on the first cache division information;
When the memory access request source of the second processing unit issues a memory access request to the main memory managed by the first processing unit with the first cache division information added, the first processing unit The cache control unit registers the added first cache division information in response to the issued memory access request.

(Appendix 9)
A first cache including a plurality of cores, a first cache control unit, and a first cache memory, wherein the first cache control unit accesses the memory based on the first cache division information; A first core group performing cache partitioning control for partitioning the first cache memory corresponding to a request source;
A second cache including a plurality of cores, a second cache control unit, and a second cache memory, wherein the second cache control unit accesses the memory based on the second cache division information A second core group for performing cache partitioning control for partitioning the second cache memory in response to a request source;
A control method for an arithmetic processing unit having an inter-core group bus provided between the first and second core groups, to which a memory access request is transmitted,
When the memory access request source of the first core group issues a memory access request to the main memory managed by the second core group with the second cache partition information added, the second core A method for controlling an arithmetic processing unit, comprising: a step in which a second cache control unit of a group registers the added second cache partition information in response to the issued memory access request.

(Appendix 10)
After the second cache control unit of the second core group registers the second cache division information, in response to a cache injection request for registering data input from the outside in the second cache memory , Performing the cache partition control on the second cache memory based on the registered second cache partition information, and registering the input data in the cache block selected by the cache partition control. The control method of the arithmetic processing apparatus of Claim 9 which has.

(Appendix 11)
The cache partition information includes the memory access request source and the maximum number of cache blocks allocated to the memory access request source.
When the cache partitioning control registers data in the cache memory, it is assigned to other memory access request sources until the current cache block number assigned to the memory access request source reaches the maximum cache block number. The control method of the arithmetic processing unit according to attachment 9, wherein the cache block is allocated to the memory access request source and the data is registered.

LOCAL_CPU_0: first core group, other arithmetic processing unit HOME_CPU_1: second core group, arithmetic processing unit CORE: core L2_CACHE: L2 cache, cache RC0, RC1: request control unit CC0, CC1: cache control unit RPC0, RPC1 : Replace control unit MW_TBL: Maximum cache block number table, maximum way number table RP_W: Replace way selection unit D_RAM: Data memory (cache memory)
TAG_RAM: Tag memory (cache memory)
BUS_0: Bus between core groups BUS_1: Bus within core group BUS_2: Memory access bus M_MEM_0, M_MEM_2: Main memory MIB: Cache miss control unit, Move-in buffer MAC: Memory access control unit R_BUF: Remote buffer R_PORT: Request port (memory access) Request storage)
MIP: Move import (memory access request storage)
MOP: Move-out port PFP: Prefetch port R_RP: Remote request port

Claims (8)

A first cache including a plurality of cores, a first cache control unit, and a first cache memory, wherein the first cache control unit accesses the memory based on the first cache division information; A first core group performing cache partitioning control for partitioning the first cache memory corresponding to a request source;
A second cache including a plurality of cores, a second cache control unit, and a second cache memory, wherein the second cache control unit accesses the memory based on the second cache division information A second core group for performing cache partitioning control for partitioning the second cache memory in response to a request source;
An inter-core group bus provided between the first and second core groups to which a memory access request is transmitted;
When the memory access request source of the first core group issues a memory access request to the main memory managed by the second core group with the second cache partition information added, the second core An arithmetic processing unit in which a second cache control unit of the group registers the added second cache division information in response to the issued memory access request.   After the second cache control unit of the second core group registers the second cache partition information, the cache partition is performed on the second cache memory based on the registered second cache partition information. The arithmetic processing apparatus according to claim 1, wherein control is performed.   After the second cache control unit of the second core group registers the second cache division information, in response to a cache injection request for registering data input from the outside in the second cache memory And performing the cache partitioning control on the second cache memory based on the registered second cache partitioning information, and registering the input data in the cache block selected by the cache partitioning control. The arithmetic processing apparatus according to 1.   In response to the memory access request issued by the memory access request source of the first core group, the second cache control unit of the second core group does not register data in the second cache memory. The arithmetic processing unit according to claim 1, wherein a data response is made to the memory access request source in the first core group.   In response to the memory access request issued by the memory access request source of the first core group, the second cache control unit of the second core group sends data to the main memory managed by the second core group. The arithmetic processing unit according to claim 1, wherein access processing is performed, and data response is made to the memory access request source in the first core group without registering data accessed to the second cache memory. The cache partition information includes the memory access request source and the maximum number of cache blocks allocated to the memory access request source.
When the cache partitioning control registers data in the cache memory, it is assigned to other memory access request sources until the current cache block number assigned to the memory access request source reaches the maximum cache block number. The arithmetic processing unit according to claim 1, wherein the data is registered by allocating a cache block to the memory access request source. A first arithmetic processing unit connected via a bus to a second arithmetic processing unit having a plurality of cores and a cache memory,
With multiple cores,
A first cache including a first cache control unit and a first cache memory;
The first cache control unit performs cache division control to divide the first cache memory corresponding to a memory access request source based on the first cache division information;
When the memory access request source of the second processing unit issues a memory access request to the main memory managed by the first processing unit with the first cache division information added, the first processing unit The cache control unit registers the added first cache division information in response to the issued memory access request. A first cache including a plurality of cores, a first cache control unit, and a first cache memory, wherein the first cache control unit accesses the memory based on the first cache division information; A first core group performing cache partitioning control for partitioning the first cache memory corresponding to a request source;
A second cache including a plurality of cores, a second cache control unit, and a second cache memory, wherein the second cache control unit accesses the memory based on the second cache division information A second core group for performing cache partitioning control for partitioning the second cache memory in response to a request source;
A control method for an arithmetic processing unit having an inter-core group bus provided between the first and second core groups, to which a memory access request is transmitted,
When the memory access request source of the first core group issues a memory access request to the main memory managed by the second core group with the second cache partition information added, the second core A method for controlling an arithmetic processing unit, comprising: a step in which a second cache control unit of a group registers the added second cache partition information in response to the issued memory access request.

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