JP2016001230A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of suppressing the degradation of display quality.SOLUTION: A liquid crystal display device comprises: a first substrate provided with a first common electrode, a first pixel electrode facing the first common electrode and having a first footprint, a second pixel electrode facing the first common electrode and having a second footprint equal to the first footprint, a third pixel electrode facing the first common electrode and having a third footprint larger than the first footprint, and an interlayer insulator lying between the first common electrode and the first to third pixel electrodes; and a second substrate provided with a second common electrode facing the first to third pixel electrodes and a second common electrode having the same potential as the first common electrode. The shape of a region in which the third pixel electrode and the first common electrode face each other is different from the shape of a region in which each of the first and second pixel electrodes and the first common electrode face each other.

Description

  Embodiments described herein relate generally to a liquid crystal display device.

  In recent liquid crystal display devices, various techniques for improving the ratio of the area contributing to display per pixel have been studied. For example, a technology has been proposed in which an auxiliary capacitor is configured with a transparent pixel electrode and a transparent auxiliary capacitor electrode through an insulating layer instead of using an auxiliary capacitor line formed of a light-shielding material. Yes.

  On the other hand, various techniques for improving display luminance in color display devices have been studied. As an example, a technique has been proposed in which one unit pixel is configured by arranging red (R) pixels, green (G) pixels, blue (B) pixels, and white (W) pixels in a line. ing.

International Publication No. 2013/157336 JP 2008-233803 A

  An object of the present embodiment is to provide a liquid crystal display device capable of suppressing deterioration in display quality.

According to this embodiment,
A first common electrode; a first pixel electrode facing the first common electrode and having a first installation area; and a second installation area facing the first common electrode and equivalent to the first installation area. A second pixel electrode; a third pixel electrode facing the first common electrode and having a third installation area larger than the first installation area; the first common electrode; and the first to third pixel electrodes; A first substrate including an interlayer insulating film interposed between the first color filter, a first color filter facing the first pixel electrode, and a color different from the first color filter while facing the second pixel electrode. The second color filter is opposed to the third pixel electrode and is different from the first to second color filters, and the first color filter is opposed to the first to third pixel electrodes. Common electric A second substrate having a second common electrode having the same potential as the first substrate, and a liquid crystal layer held between the first substrate and the second substrate, and the third pixel electrode and the first electrode. A liquid crystal display device is provided in which the shape of the region facing the common electrode is different from the shape of the region facing each of the first pixel electrode and the second pixel electrode and the first common electrode.

According to this embodiment,
A gate line; a first common electrode having first to third openings facing the gate line; and the first common electrode in a first color pixel having a first area and facing the first common electrode and in the first opening. A first pixel electrode facing the gate wiring, and a second pixel facing the first common electrode in a second color pixel having a second area equivalent to the first area and facing the gate wiring in the second opening. An electrode, a third pixel electrode facing the first common electrode in a third color pixel having a third area larger than the first area and facing the gate wiring in the third opening, and the first common electrode; A first substrate including an interlayer insulating film interposed between the first to third pixel electrodes, a first color filter facing the first pixel electrode, and facing the second pixel electrode Said A second color filter of a color different from the color filter, a third color filter of a color different from the first to second color filters while facing the third pixel electrode, and the first to third pixel electrodes, A second substrate having a second common electrode opposite to and having the same potential as the first common electrode, and a liquid crystal layer held between the first substrate and the second substrate, There is provided a liquid crystal display device in which an area where the first common electrode and each of the first to third pixel electrodes face each other is set so that the penetration voltages in the first to third color pixels are equal. .

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel LPN constituting the liquid crystal display device of the present embodiment. FIG. 2 is a plan view schematically showing a configuration example of one pixel PX of the array substrate AR applicable to the liquid crystal display device of the present embodiment. FIG. 3 is a plan view schematically showing a configuration example of one pixel PX of the counter substrate CT applicable to the liquid crystal display device of the present embodiment. FIG. 4 schematically shows a cross-sectional structure of liquid crystal display panel LPN in the active area including switching element SW shown in FIG. FIG. 5 is a plan view schematically showing an example of the layout of each pixel and color filter in the present embodiment. FIG. 6 is a plan view schematically showing a configuration example of the array substrate AR to which the color filter shown in FIG. 5 is applied. FIG. 7 is a plan view schematically showing a cross-sectional structure of the liquid crystal display panel LPN when the array substrate AR shown in FIG. 6 is cut along the line AB.

  Hereinafter, the present embodiment will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, for the sake of clarity, the drawings may be schematically represented with respect to the width, thickness, shape, etc. of each part as compared to actual aspects, but are merely examples, and The interpretation is not limited. In addition, in the present specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are denoted by the same reference numerals, and repeated detailed description may be omitted as appropriate. .

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel LPN constituting the liquid crystal display device of the present embodiment.

  That is, the liquid crystal display device includes an active matrix type liquid crystal display panel LPN. The liquid crystal display panel LPN includes an array substrate AR that is a first substrate, a counter substrate CT that is a second substrate disposed so as to face the array substrate AR, and a liquid crystal layer that is held between the array substrate AR and the counter substrate CT. LQ. The liquid crystal display panel LPN includes an active area ACT that displays an image. The active area ACT corresponds to a region in which the liquid crystal layer LQ is held between the array substrate AR and the counter substrate CT, and is, for example, a quadrangular shape and includes a plurality of pixels PX arranged in a matrix. .

  The array substrate AR includes a gate line G (G1 to Gn), a source line S (S1 to Sm), a switching element SW, a pixel electrode PE, a first common electrode CE1, and the like in the active area ACT. The gate line G extends, for example, along the first direction X. The source line S extends along a second direction Y that intersects the first direction X. The switching element SW is electrically connected to the gate line G and the source line S in each pixel PX. The pixel electrode PE is electrically connected to the switching element SW in each pixel PX. The first common electrode CE1 extends over substantially the entire surface of the active area ACT and faces the pixel electrode PE of each pixel PX. For example, the auxiliary capacitor CS is formed between the first common electrode CE1 and the pixel electrode PE.

  On the other hand, the counter substrate CT includes a second common electrode CE2. The second common electrode CE2 extends over substantially the entire active area ACT, and faces the pixel electrode PE of each pixel PX via the liquid crystal layer LQ.

  Each gate line G is drawn outside the active area ACT and is connected to the first drive circuit GD. Each source line S is drawn outside the active area ACT and connected to the second drive circuit SD. The first drive circuit GD and the second drive circuit SD are, for example, at least partially formed on the array substrate AR and connected to the drive IC chip 2. The drive IC chip 2 incorporates a controller that controls the first drive circuit GD and the second drive circuit SD, and functions as a signal supply source that supplies signals necessary for driving the liquid crystal display panel LPN. In the illustrated example, the drive IC chip 2 is mounted on the array substrate AR outside the active area ACT of the liquid crystal display panel LPN.

  The first common electrode CE1 and the second common electrode CE2 are electrically connected to each other and have the same potential. The first common electrode CE1 and the second common electrode CE2 are drawn outside the active area ACT and connected to the power supply unit VS. The power supply unit VS is formed on the array substrate AR, for example, outside the active area ACT, and is electrically connected to the first common electrode CE1 and is also electrically connected to the second common electrode CE2 via a conductive member (not shown). Has been. In the power supply unit VS, for example, a common potential is supplied to the first common electrode CE1 and the second common electrode CE2.

  FIG. 2 is a plan view schematically showing a configuration example of one pixel PX of the array substrate AR applicable to the liquid crystal display device of the present embodiment.

  The array substrate AR includes a gate line G1, a source line S1, a source line S2, a switching element SW, a first common electrode CE1, a pixel electrode PE, and the like. In the illustrated example, the pixel PX has a rectangular shape having a pair of short sides parallel to the first direction X and a pair of long sides parallel to the second direction Y, as indicated by a broken line in the drawing. is there. Note that the first direction X and the second direction Y are orthogonal to each other.

  The gate line G1 extends along the first direction X. The source line S1 and the source line S2 are arranged at intervals along the first direction X, and each extend along the second direction Y. The length along the first direction X of the pixel PX is substantially the same as the pitch along the first direction X of the adjacent source lines. The length of the pixel PX along the second direction Y is substantially the same as the pitch along the second direction Y of the adjacent gate wiring.

  In the illustrated pixel PX, the source line S1 is located at the left end and is disposed across the boundary between the pixel PX and the pixel adjacent to the left side, and the source line S2 is located at the right end and the pixel PX and its pixel PX. Arranged across the boundary with the adjacent pixel on the right side. The gate line G1 is disposed so as to cross the central portion of the pixel PX. As illustrated, in the present embodiment, there is no storage capacitor line that crosses the pixel PX in order to form the storage capacitor CS.

  The switching element SW is constituted by, for example, an n-channel thin film transistor (TFT). The switching element SW is electrically connected to the gate line G1 and the source line S1. Further, the switching element SW includes a drain electrode WD.

  For example, the first common electrode CE1 is disposed substantially over the entire area of the pixel PX, as indicated by the slanted line in the drawing, and further extends from the pixel PX across the source line S1 and the source line S2. It extends in the first direction X and also extends in the second direction Y. That is, the first common electrode CE1 faces the source line S1 and the source line S2, and is continuously formed across each pixel adjacent to the pixel PX in the first direction X. Further, the first common electrode CE1 is continuously formed across the pixels adjacent to the pixel PX in the second direction Y. Further, although not described in detail, the first common electrode CE1 is disposed substantially in the entire active area for displaying an image, and a part of the first common electrode CE1 is drawn outside the active area. It is connected to the. The first common electrode CE1 has an opening OP that exposes the drain electrode WD.

  Note that the first common electrode CE1 is disposed in substantially the entire area of the pixel PX, but is interrupted in a region overlapping with the gate line G1, and extends in the first direction X across the source line S1 and the source line S2 from the pixel PX. It may be continuously formed in a strip shape across each pixel adjacent to the pixel PX in the first direction X while facing the source line S1 and the source line S2.

  The pixel electrode PE is formed in an island shape in the pixel PX as shown by a diagonal line rising to the right in the drawing, and is opposed to the first common electrode CE1. In the illustrated example, only the pixel electrode PE arranged in the pixel PX is illustrated, but the same pixel electrode is applied to other pixels adjacent to the pixel PX in the first direction X and the second direction Y. Is arranged. The pixel electrode PE is electrically connected to the drain electrode WD of the switching element SW through the contact hole CH. The shape of the illustrated pixel electrode PE is, for example, a rectangular shape whose length along the first direction X is shorter than the length along the second direction Y, corresponding to the shape of the pixel PX. The contact hole CH is located substantially at the center of the pixel electrode PE. Note that a part of the pixel electrode PE may extend to a position overlapping the source line S1 and the source line S2.

  In this embodiment, the configuration of each pixel in the active area is the same as that in the configuration example described above, but the active area has a pixel size, that is, a length along the first direction X and a length along the second direction Y. Of different pixels.

  FIG. 3 is a plan view schematically showing a configuration example of one pixel PX of the counter substrate CT applicable to the liquid crystal display device of the present embodiment. Here, only the configuration necessary for the description is shown, and the source wiring S1, the source wiring S2, the gate wiring G1, and the pixel electrode PE, which are main parts of the array substrate, are indicated by broken lines, and the first common electrode Is omitted.

  The counter substrate CT includes a second common electrode CE2. The second common electrode CE2 is arranged over the entire area of the pixel PX and is opposed to the pixel electrode PE, as indicated by a diagonal line rising to the right in the drawing. The second common electrode CE2 extends from the pixel PX in the first direction X and the second direction Y, and is also located above the source line S1 and the source line S2. That is, the second common electrode CE2 is not described in detail, but is adjacent to the right and left pixels along the first direction X of the pixel PX, and the upper and lower sides of the pixel PX along the second direction Y. It is formed continuously over adjacent pixels. Furthermore, although not described in detail, the second common electrode CE2 is disposed over substantially the entire active area.

  In the second common electrode CE2, a slit SL is formed at a position facing the pixel electrode PE. In the illustrated example, the slit SL is formed in a strip shape extending along the second direction Y, and is located at the approximate center of the pixel PX. Such a slit SL corresponds to an alignment controller that mainly controls the alignment of liquid crystal molecules. In addition, as long as it has a function to control the alignment of liquid crystal molecules, another alignment control unit such as a protrusion stacked on the second common electrode CE2 may be provided instead of the slit.

  A slit SL extending in the second direction Y is applied to a rectangular pixel PX having a pair of short sides parallel to the first direction X and a pair of long sides parallel to the second direction Y. This shortens the distance from the slit SL to the end of the pixel electrode PE in all directions of one pixel. For this reason, a gradient electric field that avoids a slit SL, which will be described later, is formed between the slit SL and the end portion of the pixel electrode, and the response speed of the liquid crystal molecules can be improved.

  The shape of the slit SL is not limited to the illustrated example, and may be a belt shape extending along the first direction X or a cross shape. In the case of the strip-shaped slit SL along the first direction X, it is desirable that the slit SL is formed at a position overlapping the gate wiring G1. Further, when the cross-shaped slit SL is applied, it is desirable that the horizontal slit along the first direction X is formed at a position overlapping the gate wiring G1. By forming a slit at a position overlapping with the gate wiring G1, it is possible to control the orientation for making one pixel into a multi-domain, and it is possible to reduce a loss of transmittance in a region overlapping with the slit. The brightness per hit can be improved.

  FIG. 4 schematically shows a cross-sectional structure of liquid crystal display panel LPN in the active area including switching element SW shown in FIG.

  The array substrate AR is formed using a first insulating substrate 10 having optical transparency such as a glass substrate or a resin substrate. The array substrate AR has a switching element SW, a first common electrode CE1, a pixel electrode PE, a first insulating film 11, a second insulating film 12, and a third insulating film on a side of the first insulating substrate 10 facing the counter substrate CT. 13, a fourth insulating film 14, a first alignment film AL1, and the like.

  In the illustrated example, the switching element SW is a top gate type and is a thin film transistor having a single gate structure. The structure of the switching element SW is not limited to the illustrated example, and may be a double gate structure. The switching element SW may be a bottom gate type.

  The illustrated switching element SW includes a semiconductor layer SC, a gate electrode WG, a source electrode WS, and a drain electrode WD. The semiconductor layer SC is formed on the first insulating substrate 10. Such a semiconductor layer SC is formed of, for example, polycrystalline silicon (p-Si), amorphous silicon (a-Si), an oxide semiconductor, or the like. An undercoat layer that is an insulating film may be interposed between the first insulating substrate 10 and the semiconductor layer SC. The semiconductor layer SC is covered with the first insulating film 11. The first insulating film 11 is also disposed on the first insulating substrate 10.

  The gate electrode WG is formed on the first insulating film 11 and is located immediately above the semiconductor layer SC. The gate electrode WG is electrically connected to the gate line G1 (or formed integrally with the gate line G1) and is covered with the second insulating film 12. The second insulating film 12 is also disposed on the first insulating film 11.

  The source electrode WS and the drain electrode WD are formed on the second insulating film 12. Similarly, the source line S1 and the source line S2 are formed on the second insulating film 12. The illustrated source electrode WS is electrically connected to the source line S1 (or formed integrally with the source line S1). The source electrode WS and the drain electrode WD are in contact with the semiconductor layer SC through contact holes that penetrate the first insulating film 11 and the second insulating film 12, respectively. The switching element SW having such a configuration is covered with the third insulating film 13 together with the source line S1 and the source line S2. The third insulating film 13 is also disposed on the second insulating film 12. Such a third insulating film 13 is made of, for example, a transparent resin material.

  The first common electrode CE1 is formed on the third insulating film 13. As illustrated, the first common electrode CE1 covers the source line S1 and the source line S2 and extends toward the adjacent pixels. The first common electrode CE1 is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). A fourth insulating film 14 is disposed on the first common electrode CE1. In the third insulating film 13 and the fourth insulating film 14, a contact hole CH penetrating to the drain electrode WD is formed at a position overlapping the opening OP. The contact hole CH includes a contact hole that penetrates the third insulating film 13 and a contact hole that penetrates the fourth insulating film 14. The fourth insulating film 14 is formed to be thinner than the third insulating film 13 and is made of, for example, an inorganic material such as silicon nitride.

  The pixel electrode PE is formed in an island shape on the fourth insulating film 14 and faces the first common electrode CE1. The fourth insulating film 14 corresponds to an interlayer insulating film interposed between the first common electrode CE1 and the pixel electrode PE. The pixel electrode PE is electrically connected to the drain electrode WD of the switching element SW through the contact hole CH. Such a pixel electrode PE is formed of, for example, a transparent conductive material such as ITO or IZO. The pixel electrode PE is covered with the first alignment film AL1. The first alignment film AL1 is also disposed on the fourth insulating film 14.

  On the other hand, the counter substrate CT is formed using a second insulating substrate 30 having optical transparency such as a glass substrate or a resin substrate. The counter substrate CT includes a light shielding layer 31, a color filter 32, an overcoat layer 33, a second common electrode CE2, a second alignment film AL2, and the like on the side of the second insulating substrate 30 facing the array substrate AR.

  The light shielding layer 31 partitions each pixel PX in the active area ACT and forms an opening AP. The light shielding layer 31 is provided at a position facing the boundary of the color pixel, the source wiring or the gate wiring provided on the array substrate AR, the position facing the switching element SW, or the like. The light shielding layer 31 is formed of a light shielding metal material or a black resin material.

  The color filter 32 is formed in the opening AP, and a part thereof overlaps the light shielding layer 31. The color filter 32 includes, for example, a red color filter made of a resin material colored red, a green color filter made of a resin material colored green, a blue color filter made of a resin material colored blue, and the like. . The red color filter is disposed in a red pixel that displays red, the green color filter is disposed in a green pixel that displays green, and the blue color filter is disposed in a blue pixel that displays blue. In addition, a white (or transparent) color filter is disposed in a white pixel that displays white. Note that a color filter may not be disposed in the white pixel, or only the overcoat layer 33 may be disposed. Further, the white color filter may not be strictly an achromatic color filter, but may be a light color filter (for example, light yellow). The boundary between the color filters 32 of different colors is at a position overlapping the light shielding layer 31 above the source line S.

  The overcoat layer 33 covers the color filter 32. The overcoat layer 33 flattens the unevenness of the light shielding layer 31 and the color filter 32. The overcoat layer 33 is formed of a transparent resin material. The overcoat layer 33 is a base for the second common electrode CE2.

  The second common electrode CE2 is formed on the side of the overcoat layer 33 that faces the array substrate AR. As illustrated, the second common electrode CE2 passes over the source line S1 and the source line S2 and extends toward the adjacent pixel. The second common electrode CE2 is formed of a transparent conductive material such as ITO or IZO, for example. The second common electrode CE2 is covered with the second alignment film AL2.

  The first alignment film AL1 and the second alignment film AL2 are formed of a material exhibiting vertical alignment, and have an alignment regulating force that aligns the liquid crystal molecules LM in the normal direction of the substrate without requiring alignment treatment such as rubbing. doing.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, a predetermined cell gap is formed between the array substrate AR and the counter substrate CT by columnar spacers formed on one substrate. The array substrate AR and the counter substrate CT are bonded together with a sealing material in a state where a cell gap is formed. The liquid crystal layer LQ is sealed between the first alignment film AL1 and the second alignment film AL2. The liquid crystal layer LQ is made of, for example, a liquid crystal material having a negative dielectric anisotropy (negative type).

  A backlight BL is arranged on the back side of the liquid crystal display panel LPN having such a configuration. Although various forms can be applied as the backlight BL, a detailed description of the structure is omitted here.

  A first optical element OD1 including a first polarizing plate PL1 is disposed on the outer surface 10B of the first insulating substrate 10. On the outer surface 30B of the second insulating substrate 30, the second optical element OD2 including the second polarizing plate PL2 is disposed. For example, the first polarizing plate PL1 and the second polarizing plate PL2 are arranged so as to have a crossed Nicols positional relationship in which the respective polarization axes are orthogonal to each other.

  FIG. 5 is a plan view schematically showing an example of the layout of each pixel and color filter in the present embodiment. Here, the first direction X and the second direction Y are orthogonal to each other.

  A unit pixel for realizing color display is composed of a plurality of different color pixels. The unit pixel is a minimum unit that constitutes a color image displayed in the active area. Here, two unit pixels UP1 and unit pixels UP2 arranged in the first direction X are illustrated. The unit pixel UP1 and the unit pixel UP2 are each composed of six color pixels.

  The unit pixel UP1 includes a color pixel PX11, a color pixel PX12, a color pixel PX13, a color pixel PX14, a color pixel PX15, and a color pixel PX16. In the drawing, each color pixel has a rectangular shape having a pair of short sides in the first direction X and a pair of long sides in the second direction Y, and is indicated by a dashed line. The color pixel PX12 is a pixel that displays a color different from that of the color pixel PX11, and is adjacent to the first direction X of the color pixel PX11. The color pixel PX13 is a pixel that displays a different color from the color pixel PX11 and the color pixel PX12, and is adjacent to the first direction X of the color pixel PX12. The color pixel PX14 is a pixel that displays the same color as the color pixel PX11, and is adjacent to the color pixel PX11 in the second direction Y. The color pixel PX15 is a pixel that displays the same color as the color pixel PX12, and is adjacent to the second direction Y of the color pixel PX12. The color pixel PX16 is a pixel that displays a different color from the color pixel PX11, the color pixel PX12, and the color pixel PX13, and is adjacent to the second direction Y of the color pixel PX13. Here, the color pixel PX11 and the color pixel PX14 are red pixels, the color pixel PX12 and the color pixel PX15 are green pixels, the color pixel PX13 is a blue pixel, and the color pixel PX16 is a white pixel.

  The color pixel PX11, the color pixel PX12, the color pixel PX14, and the color pixel PX15 have a long side length L1 along the second direction Y. The color pixel PX13 has a long side length L2 that is longer than the long side length L1 along the second direction Y. The color pixel PX16 has a long side length L3 that is shorter than the long side length L1 along the second direction Y. The color pixel PX11, the color pixel PX12, the color pixel PX14, and the color pixel PX15 have a short side length S1 along the first direction X, and the color pixel PX13 and the color pixel PX16 are in the first direction X. And has a short side length S2 longer than the short side length S1. In such a configuration, the areas of the color pixel PX11, the color pixel PX12, the color pixel PX14, and the color pixel PX15 are substantially equal. The area of the color pixel PX13 is larger than the area of the color pixel PX11 and the like, and is the maximum area in the unit pixel UP1. The area of the color pixel PX16 is smaller than the area of the color pixel PX11 and the like, and is the minimum area in the unit pixel UP1. As an example, the sum of the areas of the color pixels PX11 and PX14, which are red pixels, is equivalent to the sum of the areas of the color pixels PX12 and PX15, which are green pixels, and the area of the color pixel PX13, which is a blue pixel. It is almost equivalent.

  The unit pixel UP2 has the same configuration as that of the unit pixel UP1, but differs in that the positions of the white pixel and the blue pixel are interchanged. That is, the unit pixel UP2 is composed of the color pixel PX21, the color pixel PX22, the color pixel PX23, the color pixel PX24, the color pixel PX25, and the color pixel PX26. The color pixel PX21 and the color pixel PX24 are red pixels, the color pixel PX22 and the color pixel PX25 are green pixels, the color pixel PX23 is a white pixel, and the color pixel PX26 is a blue pixel.

  A light shielding layer 31 is disposed at the boundary of each color pixel. Each light shielding layer 31 extends linearly along the second direction Y. Note that the light shielding layer 31 may not be disposed at the boundary between the color pixels of the same color. In the illustrated example, the light shielding layer 31 is not disposed on the boundary between the color pixel PX11 and the color pixel PX14 and on the boundary between the color pixel PX12 and the color pixel PX15. The light shielding layer 31 is arranged at the boundary between different color pixels. In other words, the light shielding layer 31 extending linearly along the first direction X is disposed at the boundary between the color pixel PX13 and the color pixel PX16. For this reason, the color pixel PX13 and the color pixel PX16 are each surrounded by the light shielding layer 31.

  The color filter (first color filter) 32R is formed in a belt shape extending along the second direction Y. The color filter (second color filter) 32G is adjacent to the color filter 32R in the first direction X, and is formed in a strip shape extending along the second direction Y. The color filter (third color filter) 32B is adjacent to the color filter 32G in the first direction X and is formed in an island shape. The color filter (fourth color filter) 32W is adjacent to the second direction Y of the color filter 32B and adjacent to the first direction X of the color filter 32G, and is formed in an island shape. The color filter 32B and the color filter 32W are alternately and repeatedly arranged along the second direction Y. For example, the color filter 32R is a red (R) color filter, the color filter 32G is a green (G) color filter, the color filter 32B is a blue (B) color filter, and the color filter 32W is white (W). It is a color filter.

  The color filter 32R is disposed corresponding to the color pixel PX11 and the color pixel PX14 of the unit pixel UP1, and is disposed corresponding to the color pixel PX21 and the color pixel PX24 of the unit pixel UP2. The color filter 32G is disposed corresponding to the color pixel PX12 and the color pixel PX15 of the unit pixel UP1, and is disposed corresponding to the color pixel PX22 and the color pixel PX25 of the unit pixel UP2. The color filter 32B is disposed corresponding to the color pixel PX13 of the unit pixel UP1, and is disposed corresponding to the color pixel PX26 of the unit pixel UP2. The color filter 32W is disposed corresponding to the color pixel PX16 of the unit pixel UP1, and is disposed corresponding to the color pixel PX23 of the unit pixel UP2.

  The color filter 32R and the color filter 32G have the same width along the first direction X. The color filter 32B and the color filter 32W have the same width along the first direction X, and are wider than the color filter 32R and the like. Adjacent ends of the color filter overlap the light shielding layer 31.

  FIG. 6 is a plan view schematically showing a configuration example of the array substrate AR to which the color filter shown in FIG. 5 is applied. Here, only the configuration of the array substrate AR necessary for explanation is illustrated.

  The gate line G1 extends along the first direction X and crosses the central portion of the color pixel PX11, the color pixel PX12, the color pixel PX13, the color pixel PX21, the color pixel PX22, and the color pixel PX23. The gate line G2 extends along the first direction X, and crosses the center of the color pixel PX14, the color pixel PX15, the color pixel PX16, the color pixel PX24, the color pixel PX25, and the color pixel PX26. The source wirings S1 to S7 each extend along the second direction Y.

  The first common electrode CE1 is disposed over the unit pixel UP1 and the unit pixel UP2, and is further disposed over substantially the entire surface of the array substrate AR. The common electrode CE1 is overlaid on the source wirings S1 to S7.

  In the unit pixel UP1, the pixel electrode (first pixel electrode) PE11 is arranged corresponding to the color pixel PX11, and is connected to the source line S1 via a switching element connected to the gate line G1. The pixel electrode (second pixel electrode) PE12 is disposed corresponding to the color pixel PX12, and is adjacent to the first direction X of the pixel electrode PE11. The pixel electrode PE12 is connected to the source line S2 via a switching element connected to the gate line G1. The pixel electrode (third pixel electrode) PE13 is disposed corresponding to the color pixel PX13, and is adjacent to the first direction X of the pixel electrode PE12. The pixel electrode PE13 is connected to the source line S3 through a switching element connected to the gate line G1. The pixel electrode (fourth pixel electrode) PE14 is arranged corresponding to the color pixel PX14, and is adjacent to the second direction Y of the pixel electrode PE11. The pixel electrode PE14 is connected to the source line S1 through a switching element connected to the gate line G2. The pixel electrode (fifth pixel electrode) PE15 is arranged corresponding to the color pixel PX15, and is adjacent to the second direction Y of the pixel electrode PE12. The pixel electrode PE15 is connected to the source line S2 through a switching element connected to the gate line G2. The pixel electrode (sixth pixel electrode) PE16 is disposed corresponding to the color pixel PX16, and is adjacent to the second direction Y of the pixel electrode PE13. The pixel electrode PE16 is connected to the source line S3 via a switching element connected to the gate line G2.

  The pixel electrode PE11, the pixel electrode PE12, the pixel electrode PE14, and the pixel electrode PE15 have a long side length L11 along the second direction Y. The pixel electrode PE13 has a long side length L12 that is longer than the long side length L11 along the second direction Y. The pixel electrode PE16 has a long side length L13 shorter than the long side length L11 along the second direction Y. The pixel electrode PE11, the pixel electrode PE12, the pixel electrode PE14, and the pixel electrode PE15 have a short side length S11 along the first direction X, and the pixel electrode PE13 and the pixel electrode PE16 along the first direction X. The short side length S12 is longer than the short side length S11. In such a configuration, the pixel electrode PE11, the pixel electrode PE12, the pixel electrode PE14, and the pixel electrode PE15 each have substantially the same installation area. The pixel electrode PE13 has a larger installation area than the installation area of the pixel electrode PE11 and the like, and the installation area is maximum in the unit pixel UP1. The pixel electrode PE16 has a smaller installation area than the installation area of the pixel electrode PE11 and the like, and the installation area is the smallest in the unit pixel UP1.

  These pixel electrodes PE11 to PE16 are all opposed to the first common electrode CE1. However, the first common electrode CE1 has openings OP11 to OP16 at positions facing the pixel electrodes PE11 to PE16. That is, each of the pixel electrodes PE11 to PE16 is partly opposed to the first common electrode CE1. A region where the first common electrode CE1 and each of the pixel electrodes PE11 to PE16 face each other corresponds to a region indicated by hatching in the drawing. In the openings OP11 to OP13, each of the pixel electrodes PE11 to PE13 and the gate line G1 are opposed to each other. In the openings OP14 to OP16, each of the pixel electrodes PE14 to PE16 and the gate line G2 are opposed to each other.

  More specifically, the opening OP11 is formed at a substantially central portion of the pixel PX11 at a position facing the pixel electrode PE11. For this reason, the pixel electrode PE11 faces the first common electrode CE1 in a region sandwiching the opening OP11 (that is, an upper region and a lower region along the second direction Y in the pixel PX11 in the drawing).

  The opening OP12 is formed at a substantially central portion of the pixel PX12 at a position facing the pixel electrode PE12. The opening area of the opening OP12 is equal to the opening area of the opening OP11. The openings OP11 and OP12 have the same shape, and in the illustrated example, are formed in a square shape. The pixel electrode PE12 is opposed to the first common electrode CE1 in a region sandwiching the opening OP12. At this time, the region where the pixel electrode PE12 and the first common electrode CE1 face each other, and the region where the pixel electrode PE11 and the first common electrode CE1 face each other have the same shape. It is formed in a shape, and the area of each of these regions is also equivalent.

  The opening OP13 is formed at a substantially central portion of the pixel PX13 at a position facing the pixel electrode PE13. The opening area of the opening OP13 is larger than the opening area of the opening OP11 and the like. In the illustrated example, the opening OP13 is a cross having a horizontal opening extending from the approximate center of the pixel PX13 in the first direction X and a vertical opening extending from the approximate center of the pixel PX13 to the second direction Y. It is formed in a shape. The lateral opening has a width W1 in the second direction Y. The width W1 is shorter than the long side length L12 of the pixel electrode PE13. The vertical opening has a width W2 in the first direction X. The width W2 is shorter than the short side length S12 of the pixel electrode PE13. In addition, the length along the first direction X of the horizontal opening is equal to or shorter than the short side length S12, and the length along the second direction Y of the vertical opening is shorter than the long side length L12. The region where the pixel electrode PE13 and the first common electrode CE1 face each other has a different shape from the region where the pixel electrode PE11 and the first common electrode CE1 face each other. In the illustrated example, in each of the upper region and the lower region along the second direction Y in the pixel PX13 in the drawing, the region where the pixel electrode PE13 and the first common electrode CE1 face each other is formed in a substantially U shape. Has been. In other words, the pixel electrode PE13 is opposed to the first common electrode CE1 in a region around the opening OP13, that is, a region along the edge of the pixel electrode PE13.

  The opening OP14 is formed at a substantially central portion of the pixel PX14 at a position facing the pixel electrode PE14. The opening area of the opening OP14 is equal to the opening area of the opening OP11. The opening OP14 has the same shape as the opening OP11. The pixel electrode PE14 is opposed to the first common electrode CE1 in a region sandwiching the opening OP14. At this time, the region where the pixel electrode PE14 and the first common electrode CE1 face each other has the same shape as the region where the pixel electrode PE11 and the first common electrode CE1 face each other.

  The opening OP15 is formed at a substantially central portion of the pixel PX15 at a position facing the pixel electrode PE15. The opening area of the opening OP15 is equal to the opening area of the opening OP11. The opening OP15 has the same shape as the opening OP11. The pixel electrode PE15 is opposed to the first common electrode CE1 in a region sandwiching the opening OP15. At this time, the region where the pixel electrode PE15 and the first common electrode CE1 face each other has the same shape as the region where the pixel electrode PE11 and the first common electrode CE1 face each other.

  The opening OP16 is formed at a substantially central portion of the pixel PX16 at a position facing the pixel electrode PE16. The opening area of the opening OP16 is substantially equal to the opening area of the opening OP11, for example. The opening OP14 is formed in a square shape, for example. The pixel electrode PE16 is opposed to the first common electrode CE1 in a region sandwiching the opening OP16. At this time, the region where the pixel electrode PE16 and the first common electrode CE1 face each other is formed in, for example, a square shape.

  The unit pixel UP2 is configured in the same manner as the unit pixel UP1 and will not be described in detail. However, in the unit pixel UP2, the pixel electrode PE21 is arranged corresponding to the color pixel PX21, and the pixel electrode PE22 is a color pixel. The pixel electrode PE23 is disposed corresponding to the color pixel PX23, the pixel electrode PE24 is disposed corresponding to the color pixel PX24, and the pixel electrode PE25 is disposed corresponding to the color pixel PX25. The pixel electrode PE26 is disposed corresponding to the color pixel PX26.

  Note that the layouts shown in FIGS. 5 and 6 are examples, and are not limited to the illustrated examples.

  FIG. 7 is a plan view schematically showing a cross-sectional structure of the liquid crystal display panel LPN when the array substrate AR shown in FIG. 6 is cut along the line AB.

  In the array substrate AR, the source wirings S1 to S4 are formed on the second insulating film 12 and covered with the third insulating film 13. The first common electrode CE <b> 1 is formed on the third insulating film 13 and is covered with the fourth insulating film 14. In the illustrated cross-sectional view, the first common electrode CE1 has an opening OP13 in the pixel PX13. The pixel electrodes PE11 to PE16 are formed on the fourth insulating film 14 and face the first common electrode CE1 with the fourth insulating film 14 interposed therebetween. The pixel electrode PE11 and the pixel electrode PE14 are located between the source line S1 and the source line S2. The pixel electrode PE12 and the pixel electrode PE15 are located between the source line S2 and the source line S3. The pixel electrode PE13 and the pixel electrode PE16 are located between the source line S3 and the source line S4. These pixel electrodes PE11 to PE16 are covered with the first alignment film AL1.

  In the counter substrate CT, the light shielding layer 31 is located above the source wirings S1 to S4, respectively. The color filter 32R is opposed to the pixel electrode PE11 and the pixel electrode PE14. The color filter 32G is opposed to the pixel electrode PE12 and the pixel electrode PE15. The color filter 32B is opposed to the pixel electrode PE13. The color filter 32W is opposed to the pixel electrode PE16. The second common electrode CE2 is formed on the array substrate AR side of the overcoat layer 33, and is covered with the second alignment film AL2. The second common electrode CE2 is opposed to the pixel electrodes PE11 to PE16. In the second common electrode CE2, slits SL11 to SL16 are formed at positions facing the pixel electrodes PE11 to PE16, respectively. The cell gaps of the color pixels PX11 to PX16 are substantially the same.

  Next, the operation of the liquid crystal display device in this embodiment will be described.

  In an off state where no potential difference is formed between the pixel electrode PE and the first common electrode CE1 and the second common electrode CE2 (that is, a state where no voltage is applied to the liquid crystal layer LQ), the pixel electrode PE and the second common electrode CE2 Since no electric field is formed between the common electrode CE2 and the liquid crystal molecules LM included in the liquid crystal layer LQ, as shown in FIG. 4, the first alignment film AL1 and the second alignment film AL2 Initial alignment is performed substantially perpendicularly to the substrate main surface (XY plane).

  At this time, a part of the backlight light from the backlight BL passes through the first optical element OD1 and enters the liquid crystal display panel LPN. The polarization state of the light incident on the liquid crystal display panel LPN hardly changes when transmitted through the liquid crystal layer LQ. For this reason, the light transmitted through the liquid crystal display panel LPN is absorbed by the second optical element OD2 (black display).

  In an on state (that is, a state where a voltage is applied to the liquid crystal layer LQ) in which a potential difference is formed between the pixel electrode PE and the first common electrode CE1 and the second common electrode CE2, the pixel electrode PE and the second common electrode A gradient electric field or a gradient electric field that avoids the slit SL is formed between CE2. For this reason, the liquid crystal molecules LM are aligned in a direction different from the initial alignment direction by the action of a longitudinal electric field or a gradient electric field. That is, the negative liquid crystal molecules LM are aligned so that their major axes intersect the electric field, and therefore, in the ON state, they are aligned obliquely or horizontally with respect to the main surface of the substrate.

  In such an on state, the polarization state of light incident on the liquid crystal display panel LPN changes according to the alignment state of the liquid crystal molecules LM (or the retardation of the liquid crystal layer LQ) when passing through the liquid crystal layer LQ. For this reason, at least part of the light transmitted through the liquid crystal display panel LPN is transmitted through the second optical element OD2 (white display).

  In the ON state, the auxiliary capacitance CS is formed by the pixel electrode PE and the first common electrode CE1 that are opposed to each other through the fourth insulating film 14, and the capacitance necessary for displaying an image is held. That is, the pixel potential written to each pixel via the switching element SW is held for a certain period by the auxiliary capacitor CS.

By the way, in the present embodiment, the area of the region where the first common electrode CE1 and each of the pixel electrodes PE11 to PE13 face each other is set so that the penetration voltage is equal in each of the color pixels PX11 to PX13. . Here, the punch-through voltage Vp is defined by the following expression in the array substrate AR having the above configuration.
Vp = Cgs / (Cs + Cgs + Clc) * ΔVg
Cgs is a parasitic capacitance between the gate wiring and the pixel electrode, Cs is an auxiliary capacitance, Clc is a liquid crystal capacitance, and ΔVg is an amplitude of a voltage applied to the gate wiring.

  As described above, the color pixels PX11 and PX12 are different in shape or area from the color pixels PX13 and PX16. Therefore, although the liquid crystal capacitance Clc and the parasitic capacitance Cgs are the same for the color pixels PX11 and PX12, the color pixel PX13 and the color pixel PX16 are different from the color pixels PX11 and PX12. That is, the punch-through voltage Vp is not uniform among the color pixels constituting the unit pixel. Such a difference in the punch-through voltage Vp may cause flicker or burn-in and may cause a deterioration in display quality. In particular, in the unit pixel, when the punch-through voltage Vp is different by about several hundred mV between the color pixels of the red pixel, the green pixel, and the blue pixel, it is easily recognized as a display defect. According to various studies by the inventors, the penetration voltage Vp between the color pixels is substantially equal, or the difference in the penetration voltage Vp between the color pixels is 100 mV or less, more preferably 80 mV or less. It was found that can be eliminated.

  In the present embodiment, the auxiliary capacitor Cs is formed between the first common electrode CE1 having the common potential and the pixel electrode PE having the pixel potential. In other words, the auxiliary capacitance Cs can be adjusted by changing the shape or area of the region where the first common electrode CE1 and the pixel electrode PE are opposed to each other. The auxiliary capacitance Cs of each color pixel is set so as to cancel the difference between the color pixels of the liquid crystal capacitance Clc and the parasitic capacitance Cgs. Thereby, the penetration voltage Vp of each color pixel can be set substantially equal. Therefore, according to the present embodiment as described above, it is possible to suppress the deterioration of display quality due to the difference in the punch-through voltage Vp between the color pixels.

  In one example, when the auxiliary capacitor Cs contributes more to the punch-through voltage Vp than the parasitic capacitor Cgs, the punch-out voltage Vp between the color pixels can be set to be approximately the same by making the auxiliary capacitor Cs between the color pixels equal. Is possible. Therefore, even if the pixel electrode PE13 of the color pixel PX13 has a larger installation area than the pixel electrode PE11 of the color pixel PX11 and the pixel electrode PE12 of the color pixel PX12 as in the example shown in FIG. The shape of the region where PE13 and first common electrode CE1 face each other is the shape of the region where pixel electrode PE11 and first common electrode CE1 face each other, or the region where pixel electrode PE12 and first common electrode CE1 face each other. While the shape is different, the area of the region where the pixel electrode PE13 and the first common electrode CE1 face each other is the area of the region where the pixel electrode PE11 and the first common electrode CE1 face each other or the pixel electrode PE12 and the first common electrode CE1. It is set to be equal to the area of the region facing the common electrode CE1. Thereby, the auxiliary capacitance Cs between the pixel electrode PE13 and the first common electrode CE1 is equal to the auxiliary capacitance Cs between the pixel electrode PE11 and the first common electrode CE1, or the pixel electrode PE12 and the first common electrode CE1. Is equivalent to the auxiliary capacity Cs. Thereby, in the color pixels PX11 to PX13, the punch-through voltage Vp becomes equal, and deterioration of display quality can be suppressed.

  Further, according to the present embodiment, in the pixel PX13, the first common electrode CE1 is opposed in a region along the edge of the pixel electrode PE13. For this reason, even if a positional shift occurs in the first direction X or the second direction Y between the first common electrode CE1 and the pixel electrode PE13, the area of the region where the first common electrode CE1 and the pixel electrode PE13 face each other (That is, the auxiliary capacitance variation in the pixel PX13) can be reduced.

  Further, according to the present embodiment, the capacity necessary for displaying an image in each pixel can be formed by the pixel electrode PE and the first common electrode CE1 that are opposed to each other with the fourth insulating film 14 interposed therebetween. is there. The pixel electrode PE and the first common electrode CE1 are formed of a transparent conductive material. This eliminates the need for wiring and electrodes made of light-shielding wiring material across the pixels, apart from the first common electrode CE1, when forming the capacitance, and the area contributing to display per pixel can be increased. Become. The fourth insulating film 14 is formed to have a thin film thickness as compared with the third insulating film formed of a resin material or the like. For this reason, a relatively large capacitance can be easily formed by the pixel electrode PE and the first common electrode CE1 via the fourth insulating film 14.

  In addition, according to the present embodiment, the first common electrode CE1 extends above the source line S1 and the source line S2. Therefore, in the ON state, it is possible to shield an undesired leakage electric field from the source line S1 and the source line S2 toward the liquid crystal layer LQ by the first common electrode CE1. That is, it is possible to suppress formation of an undesired electric field or undesired capacitance between the source line S1 and the source line S2 and the pixel electrode PE or the second common electrode CE2, and the source line S1 and the source line S2 It is possible to suppress the alignment disorder of the liquid crystal molecules LM in the region overlapping with the.

  In addition, the first common electrode CE1 and the second common electrode CE2 face each other in a region overlapping with the source line S1 and the source line S2. Therefore, the liquid crystal molecules LM in the region overlapping with the source line S1 and the source line S2 maintain the initial alignment state because the first common electrode CE1 and the second common electrode CE2 are maintained at the same potential even in the ON state. ing. Therefore, the pixel electrode PE adjacent in the first direction X can be brought close to the processing limit, and the area contributing to display per pixel can be further expanded.

  In addition, even if one pixel adjacent to the source wiring is on and the other pixel is off, in the region overlapping the source wiring between the on-state pixel and the off-state pixel, Since no potential difference is formed between the first common electrode CE1 and the second common electrode CE2 facing each other, the liquid crystal molecules LM are maintained in the initial alignment state. For this reason, even when the liquid crystal display panel LPN is observed from an oblique direction, it is possible to suppress deterioration in display quality due to color mixing. In addition, since it is not necessary to increase the width of the light shielding layer 31 in order to prevent color mixing, the area contributing to display per pixel can be further increased.

  Further, according to the present embodiment, the gate wirings G1 and G2 are arranged so as to cross the vicinity of the center of each pixel. In addition to an example where the gate wiring crosses the vicinity of the center of the pixel, there is an example where the gate wiring is arranged above and below the pixel. In the case where a specific pixel is a pixel larger than other pixels as in the present embodiment, or a small pixel, that is, in the case of the pixel configuration as shown in FIGS. When the gate lines are arranged above and below the gate lines, the gate lines are arranged while meandering along the pixel ends in order to increase the aperture ratio. In this case, since the wiring length of the gate wiring is longer than that in the present embodiment in which the gate wiring is arranged in a straight line, the electric resistance and the parasitic capacitance increase, which may cause flicker. On the other hand, in this embodiment, since the gate wiring is arranged near the center of each pixel regardless of the size of the pixel, the wiring length of the gate wiring does not become long, so that deterioration of display quality due to flicker or the like is suppressed. Is done. Furthermore, in this embodiment, since it is not necessary to separately arrange an auxiliary capacitor line in order to form an auxiliary capacitor, the transmittance of the pixel can be improved by arranging the gate wiring as described above.

  As described above, according to the present embodiment, it is possible to provide a liquid crystal display device capable of suppressing deterioration in display quality.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate LQ ... Liquid crystal layer PE ... Pixel electrode CE1 ... First common electrode CE2 ... Second common electrode AL1 ... First alignment film AL2 ... Second alignment film

Claims (8)

A first common electrode; a first pixel electrode facing the first common electrode and having a first installation area; and a second installation area facing the first common electrode and equivalent to the first installation area. A second pixel electrode; a third pixel electrode facing the first common electrode and having a third installation area larger than the first installation area; the first common electrode; and the first to third pixel electrodes; A first substrate comprising an interlayer insulating film interposed between
A first color filter facing the first pixel electrode; a second color filter facing the second pixel electrode; and a color different from the first color filter; and facing the third pixel electrode and the first pixel filter. A second substrate comprising: a third color filter having a color different from that of the first to second color filters; and a second common electrode facing the first to third pixel electrodes and having the same potential as the first common electrode. When,
A liquid crystal layer held between the first substrate and the second substrate,
The shape of the region where the third pixel electrode and the first common electrode face each other is different from the shape of the region where each of the first pixel electrode and the second pixel electrode faces the first common electrode. Liquid crystal display device.   The liquid crystal display device according to claim 1, wherein areas where the first common electrode and each of the first to third pixel electrodes face each other are equal.   The first common electrode includes a first opening having a first opening area at a position facing the first pixel electrode, and a second opening equivalent to the first opening area at a position facing the second pixel electrode. A second opening having an area, and a third opening having a third opening area larger than the first opening area at a position facing the third pixel electrode, and the third pixel electrode and the third pixel electrode The liquid crystal display device according to claim 1, which faces each other in a region along the edge. The first pixel electrode and the second pixel electrode have a first short side length along a first direction, and the third pixel electrode has a second short side longer than the first short side length along the first direction. Have a length,
The first pixel electrode and the second pixel electrode have a first long side length along a second direction, and the third pixel electrode has a second long side longer than the first long side length along the second direction. The liquid crystal display device according to claim 1, having a length. A gate line; a first common electrode having first to third openings facing the gate line; and the first common electrode in a first color pixel having a first area and facing the first common electrode and in the first opening. A first pixel electrode facing the gate wiring, and a second pixel facing the first common electrode in a second color pixel having a second area equivalent to the first area and facing the gate wiring in the second opening. An electrode, a third pixel electrode facing the first common electrode in a third color pixel having a third area larger than the first area and facing the gate wiring in the third opening, and the first common electrode; A first substrate including an interlayer insulating film interposed between the first to third pixel electrodes;
A first color filter facing the first pixel electrode; a second color filter facing the second pixel electrode; and a color different from the first color filter; and facing the third pixel electrode and the first pixel filter. A second substrate comprising: a third color filter having a color different from that of the first to second color filters; and a second common electrode facing the first to third pixel electrodes and having the same potential as the first common electrode. When,
A liquid crystal layer held between the first substrate and the second substrate,
The liquid crystal display device, wherein an area where the first common electrode and each of the first to third pixel electrodes face each other is set such that a punch-through voltage in the first to third color pixels is equal.   6. The liquid crystal display device according to claim 5, wherein a difference between the penetration voltages in the first to third color pixels is 80 mV or less.   The liquid crystal display device according to claim 1, wherein the third color filter is a blue color filter.   6. The liquid crystal display device according to claim 1, wherein a slit is formed in the second common electrode at a position facing the first to third pixel electrodes. 7.

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