JP2016181735A - Phase-to-digital converter and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase-digital converter capable of reducing the power consumption.SOLUTION: A phase-digital converter 1 includes: a first to secondsample hold part that generates first to secondmulti-phase signals by sample-holding a multi-phase cycle signal of first to secondphases (n: an integer larger than 1) synchronously with a reference signal; a selector that generates a monotonous variation signal by selecting a signal period which monotonic-increases or monotonic-decreases included in a first to secondmulti-phase signal based on a n-bit first digital signal at every 1/2cycle; and a quantizer that quantizes the monotonous variation signal into a second digital signal of (m-n) bits (m is an integer larger than 2; m>n).SELECTED DRAWING: Figure 1

Description

  Embodiments of the present invention relate to a phase-to-digital converter and a receiver.

  A conventional time-to-digital converter (TDC) inputs an RF signal to a number of cascaded delay stages, quantizes each output of the delay stage with 1 bit, and outputs a phase. -Digital conversion was performed.

  However, when the frequency of the RF signal is in the GHz band, the number of delay stages has to be increased, which increases the circuit area and current consumption of the entire TDC.

U.S. Pat.

R. Staszewski, “ALL-Digital PLL and Transmitter for Mobile Phones”, IEEE J. of Solid-State Corcuits Vol. 40, No. 12, DEC 2005.

  An object of the present invention is to provide a phase-digital converter and a receiver that can reduce power consumption.

In this embodiment, the first to second ⁿ multiphase signals are generated by sampling and holding the first to second ⁿ phase (n is an integer of 1 or more) in synchronization with the reference signal. First to second ⁿ sample and hold units,
A monotonically increasing or monotonically decreasing signal period included in the first to second ⁿ multiphase signals is selected every 1/2 ⁿ period based on the n-bit first digital signal to generate a monotonic change signal. A selector,
A quantizer that quantizes the monotonic change signal into a second digital signal of (mn) bits (m is an integer of 2 or more, m> n),
The higher-order bits of the phase difference signal between the reference signal and the first to second ^n- phase multiphase signals are the first digital signal, and the lower-order bits of the phase difference signal are the second digital signal. A phase-to-digital converter is provided.

The block diagram which shows schematic structure of the receiver 2 provided with the phase-digital converter (TDC) 1 which concerns on 1st Embodiment. The block diagram which shows an example of an internal structure of the phase-digital converter (TDC) 1. FIG. The figure which shows an example of an internal structure of the selector. FIG. 6 is a signal waveform diagram inside the selector 24. The block diagram which shows the internal structure of the selector 24 which concerns on 2nd Embodiment. The signal waveform diagram of 2nd Embodiment in case the reference voltage _VREF is lower than the optimal voltage _Vopt . The signal waveform diagram of 2nd Embodiment in case the reference voltage _VREF is higher than the optimal voltage _Vopt . The block diagram which shows the internal structure of the selector 24 which concerns on 3rd Embodiment. The signal waveform diagram of 3rd Embodiment when the reference voltage _VREF is lower than the optimal voltage _Vopt . The signal waveform diagram of 3rd Embodiment in case the reference voltage _VREF is higher than the optimal voltage _Vopt . The block diagram which shows the internal structure of the phase-digital converter 1 (TDC) which concerns on 4th Embodiment. FIG. 4 is a signal waveform diagram inside the quantizer 25.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram illustrating a schematic configuration of a receiver 2 including a phase-digital converter (TDC) 1 according to the first embodiment. 1 includes an antenna 3, a low noise amplifier 4, a frequency converter 5, a frequency divider 6, a low pass filter 7, an A / D converter (ADC) 8, and a digital signal. A demodulation unit (Modem) 9 and a frequency synthesizer unit 10 are provided.

  The received signal received by the antenna 3 is amplified by the low noise amplifier 4 and input to the frequency converter 5. The frequency converter 5 detects the phase difference between the reception signal output from the low noise amplifier 4 and the voltage controlled oscillation signal (hereinafter referred to as VCO signal) generated by the frequency synthesizer unit 10 and outputs a phase difference signal. . Two frequency converters 5, two low-pass filters 7, and two A / D converters 8 are provided. One frequency converter 5 generates an I signal, and the other frequency converter 5 generates a Q signal. Generate. The I signal and the Q signal are respectively input to the corresponding A / D converters 8 and sampled to generate a digital value of the I signal and a digital value of the Q signal. These digital values are input to the digital signal demodulator 9 for digital demodulation processing.

  The frequency synthesizer unit 10 includes a reference signal source 11, a phase-digital converter (TDC) 1, a loop gain control unit 12, a voltage controlled oscillator (VCO: Voltage Control Oscillator) 13, and a binary counter 14. .

  The phase-digital converter 1 detects the phase of the VCO signal, as will be described in detail later. The binary counter 14 is used for detecting the phase of the VCO signal. The loop gain control unit 12 performs feedback control so that the phases of the VCO signal and the received signal match.

  FIG. 2 is a block diagram showing an example of the internal configuration of the phase-digital converter (TDC) 1. The TDC 1 in FIG. 2 includes a frequency divider 21, a binary counter 22, a plurality of sample and hold units 23, a selector 24, and a quantizer (ADC) 25.

The frequency divider 21 shown in FIG. 2 divides the VCO signal by two to generate four types of multiphase periodic signals having phases different by 90 °. Note that the polyphase periodic signals generated by the frequency divider 21 are not necessarily four types. When generalized, the frequency divider 21 generates first to second ^n- phase (n is an integer of 1 or more) multiphase periodic signals. Further, the frequency divider 21 may be provided outside the TDC 1. For example, it can be shared with the frequency divider 6 for IQ signal generation of the receiver 2 of FIG.

The sample hold units 23 are provided as many as the number of multiphase periodic signals. In the example of FIG. 2, four sample and hold units 23 are provided. Each sample and hold unit 23 samples and holds the corresponding multiphase periodic signal in synchronization with the reference signal from the reference signal source 11 to generate a multiphase signal. In the example of FIG. 2, four types of multiphase signals Phase [4: 1] are generated. Generally speaking, when there are first to second ^n- phase (n is an integer of 1 or more) multiphase periodic signals, first to second ⁿ multiphase signals are generated.

Based on the first digital signal TDC [5: 4], the selector 24 selects one of a plurality of multiphase signals generated by each sample-and-hold unit 23 at a predetermined time interval, and the monotonous change signal SEL. _out is generated. In the case of FIG. 2, the selector 24 selects a monotonically increasing or monotonically decreasing signal period from the four types of multiphase signals Phase [4: 1] based on the first digital signal TDC [5: 4]. A monotonous change signal SEL _out is generated by selecting every period. When generalized, the selector 24 selects a monotonically increasing or monotonically decreasing signal period included in the first to second ⁿ multiphase signals every 1/2 ⁿ period based on the n-bit first digital signal. The monotonous change signal SEL _out is generated.

It is important that the monotonic change signal SEL _out not only monotonously increases or monotonously decreases but also has linearity. This is because the quantizer 25 quantizes the monotonic change signal SEL _out . More specifically, the quantizer 25 quantizes the monotonic change signal SEL _out into a second digital signal of (mn) bits (m is an integer of 2 or more).

  A digital signal obtained by synthesizing the first digital signal and the second digital signal is a phase difference signal between the reference signal and the VCO signal. More specifically, the upper bit of the phase difference signal is the first digital signal, and the lower bit is the second digital signal. In the case of FIG. 2, the phase difference signal is 5-bit TDC [5: 1], of which the upper bits TDC [5: 4] are the first digital signals, and the lower bits TDC [3: 1] are A second digital signal.

FIG. 3 is a diagram showing an example of the internal configuration of the selector 24, and FIG. 4 is a signal waveform diagram inside the selector 24. As illustrated in FIG. 3, the selector 24 includes a comparator (first comparator) 31, an encoder (encoding unit) 32, and four switches SW1 to SW4. The comparator 31 compares each of the four types of multiphase signals Phase [4: 1] output from the four sample and hold units 23 with the reference voltage V _REF, and binary data PSEL [4: 1] is generated. The encoder 32 generates a first digital signal TDC [5: 4] obtained by encoding a bit string of binary data PSEL [4: 1].

  Each of the four switches SW1 to SW4 switches whether to select each of the four types of multiphase signals Phase [4: 1] based on the corresponding bit value in PSEL [4: 1]. More specifically, the switch SW1 switches whether to select Phase [1] according to the bit value of PSEL [1]. The switch SW2 switches whether to select Phase [2] according to the bit value of PSEL [2]. The switch SW3 switches whether to select Phase [3] according to the bit value of PSEL [3]. The switch SW4 switches whether to select Phase [4] according to the bit value of PSEL [4].

When the signal waveforms of the four types of multiphase signals Phase [4: 1] are sinusoidal signals as shown in FIG. 4A, for example, the output signal PSEL [4: 1] of the comparator 31 is the multiphase signal. 1 is output when the reference voltage _VREF exceeds the reference voltage _VREF, and 0 is output otherwise. Therefore, PSEL [4: 1] becomes a pulse signal as shown in FIG. Since the switch selects the corresponding Phase [4: 1] only during the period in which PSEL [4: 1] is 1, the output signal SEL _out of the selector 24 is monotonically increasing and linear as shown in FIG. Monotonic change signal SEL _out .

The monotonic change signal SEL _out selected by the selector 24 is input to the quantizer 25. Quantizer 25, monotonously change signal _{SEL out} the 8-level second digital signal TDC: quantized to [3 1].

If the monotonic increase and linearity of the phase-voltage characteristics of the multiphase signal are ensured within each selection range of PSEL [4: 1], the digital code TDC obtained by quantizing the output signal SEL _out of the selector 24 is obtained. [3: 1] represents the phase difference from the reference signal REF. The counter 22 shown in FIG. 2 is used to determine the value of the bit string of TDC [3: 1], as will be described later.

  In FIG. 4, for example, at the moment of switching from the selection range of PSEL [4] to the selection range of PSEL [3], the digital code TDC [3: 1] returns to 000 once, so it seems that monotonic increase is not ensured. Each time the selection range changes between PSEL [4: 1], a new monotonic increase characteristic is obtained and TDC [3: 1] is newly set, so that the monotonic increase characteristic is always maintained.

  For example, the phase at point A in FIG. 4A is TDC [3: 1] = (110), which is a value on the multiphase signal Phase [3] that passes through the switch SW4 when PSEL [4] is 1. PSEL [4] is selected when TDC [5: 4] = (00) and the phase difference signal TDC [5: 1] = (00110) with respect to the reference signal REF.

As described above, in the first embodiment, the monotonous change signal SEL _out is generated by selecting the signal periods in which the plurality of multiphase periodic signals generated from the VCO signal monotonously increase or monotonically decrease, and the monotone change signal SEL is generated. _A phase difference signal is generated based on _out . For this reason, it is possible to significantly reduce the power consumption compared to generating the phase difference signal after delaying the VCO signal to generate a plurality of signals having different phases.

(Second Embodiment)
In the second embodiment described below, the internal configuration of the selector 24 is partially different from that of the first embodiment, but the other configurations are the same as those of the first embodiment. The explanation is centered. Further, in the following, as in the first embodiment, an example in which four types of polyphase synchronization signals are generated by the frequency divider 21 will be described. However, in the present embodiment, the first to second ⁿ phases (n is The present invention is also applicable to the case of generating a multiphase periodic signal of an integer of 1 or more.

FIG. 5 is a block diagram showing an internal configuration of the selector 24 according to the second embodiment. The selector 24 in FIG. 5 includes a phase synchronization unit 33 in addition to the configuration of the selector 24 in FIG. The phase synchronization unit 33 generates a reference voltage V _REF that is input to the comparator 32, and includes a phase comparator 34, a charge pump 35, and a loop filter 36. The phase comparator 34 detects the phase difference between the rising edge of the phase following the falling edge of the phase that is early in the two adjacent phases of PSEL [4: 1]. The charge pump 35 integrates the output signal of the phase comparator 34. The loop filter 36 supplies a signal obtained by smoothing the output signal of the charge pump 35 to the comparator 31 as a reference signal.

The reason why the reference voltage V _REF is generated by the phase synchronization unit 33 is that if the reference voltage V _REF varies, the pulse width of PSEL [4: 1] varies, causing malfunction. This is also because it is necessary to cancel the offset of the comparator 31.

6 and 7 are signal waveform diagrams inside the selector 24 in the second embodiment. FIG. 6 is a signal waveform diagram when the reference voltage V _REF is lower than the optimum voltage V _opt , and FIG. 7 is a signal waveform diagram when the reference voltage V _REF is higher than the optimum voltage V _opt .

When the reference voltage V _REF is lower than the optimum voltage V _opt , the pulse periods of PSEL [4: 1] overlap as shown in FIG. Within the overlapped period, it becomes impossible to determine which of the four switches SW1 to SW4 should be turned on, causing malfunction. Further, when the reference voltage V _REF is higher than the optimum voltage V _opt , as shown in FIG. 7, each pulse width of PSEL [4: 1] becomes narrow, and a period in which no switch is turned on occurs.

Therefore, the phase synchronization unit 33 performs feedback control so that the reference voltage V _REF matches the optimum voltage V _opt . More specifically, the phase synchronization unit 33 performs phase adjustment so that the timing of the falling edge of PSEL [4] matches the timing of the rising edge of PSEL [3]. The phase adjustment may be performed using PSEL [1] or PSEL [2]. That is, the phase synchronization unit 33 performs phase adjustment so that the timing of the falling edge of the early phase of the two adjacent phases matches the timing of the rising edge of the subsequent phase.

  For example, PSELb [4] and PSEL [3] obtained by inverting PSEL [4] are input to the phase comparator 34 in the phase synchronization unit 33. The phase comparator 34 determines whether to output the UP signal or the DN signal depending on which rising edge of the two input signals is detected first. For example, when PSEL [3] is first, an UP signal is output, and when PSELb [4] is first, a DN signal is output.

The UP signal and DN signal are integrated by the charge pump 35 and then smoothed by the loop filter 36 to become the reference voltage V _REF of the comparator 31.

As shown in FIG. 6, when the rising edge of PSEL [3] is input to the phase comparator 34 before the falling edge of PSELb [4], the reference voltage V _REF is lower than the optimum voltage V _opt. Therefore, the reference voltage V _REF gradually increases due to the UP signal, and the UP signal is not output, that is, the edges of PSEL [3] and PSELb [4] are at the same timing, and PSEL [4: 1] When there is no overlap, the reference voltage V _REF matches the optimum voltage V _opt .

Also, as shown in FIG. 7, when the falling edge of PSELb [4] is input to the phase comparator 34 before the rising edge of PSEL [3], the reference voltage _VREF is higher than the optimum voltage _Vopt . The reference voltage V _REF matches the optimum voltage V _opt when the DN signal is gradually lowered by the DN signal and the DN signal is not output, that is, when there is no overlap of PSEL [4: 1]. To do.

When PSEL [4: 1] adjusted in this way is used as a switching signal for the switches SW1 to SW4, the monotonic change signal SEL _out obtained by extracting only the linear increase region of the multiphase signal Phase [4: 1] is selected by the selector 24. Can be generated.

As described above, in the second embodiment, since the phase synchronization unit 33 adjusts the reference voltage V _REF so as to match the optimum voltage V _opt , a plurality of switches are prevented from being turned on redundantly. A period in which the switch is not turned on does not appear, and the monotone change signal SEL _out including only a linear monotonously increasing region can be generated.

(Third embodiment)
In a third embodiment described below, the phase synchronization unit 33 described in the second embodiment is digitized.

  FIG. 8 is a block diagram showing an internal configuration of the selector 24 according to the third embodiment. The selector 24 in FIG. 8 is configured in the same manner as in FIG. 5 except that it includes a digital phase synchronization unit 41.

  The digital phase synchronization unit 41 in FIG. 8 includes a digital phase comparator 42, a digital integrator 43, a digital filter 44, and a DA converter 45.

  The digital phase comparator 42 detects a phase difference between a falling edge of an early phase and a rising edge of a succeeding phase among two adjacent phases, and outputs it as a binary digital signal. As shown in FIG. 8, the digital phase comparator 42 can be composed of one D flip-flop. For example, PSEL [3] is input to the D input terminal of the D flip-flop, and PSELb [4] is input to the clock terminal. Whether the rising edge of PSEL [3] or PSELb [4] is input first determines whether the output of the D flip-flop becomes 1 or −1 (0). More specifically, if the rising edge of PSEL [3] is earlier, it becomes +1, and if the rising edge of PSELb [4] is earlier, it becomes −1 (0).

The output of the digital phase comparator 42 is integrated by the digital integrator 43, smoothed by the digital filter 44, and input to the DA converter 45. The DA converter 45 converts the signal into an analog signal and generates the reference voltage _VREF .

9 and 10 are signal waveform diagrams inside the selector 24 in the third embodiment. FIG. 9 is a signal waveform diagram when the reference voltage V _REF is lower than the optimum voltage V _opt , and FIG. 10 is a signal waveform diagram when the reference voltage V _REF is higher than the optimum voltage V _opt .

  9 and 10 are common to FIGS. 6 and 7 except for the output signal waveform of the digital phase comparator 42 described at the end of each figure.

As described above, in the third embodiment, since the reference voltage V _REF is adjusted using the digital phase synchronization unit 33, the configuration can be simplified and the influence of noise is less likely.

(Fourth embodiment)
In the fourth embodiment described below, the internal configuration of the quantizer 25 is characterized.

  FIG. 11 is a block diagram showing an internal configuration of the phase-digital converter 1 (TDC) according to the fourth embodiment. The TDC 1 in FIG. 11 is different from the first to third embodiments in the internal configuration of the quantizer 25, and is otherwise common. Therefore, the following description will focus on the differences.

  The quantizer 25 in FIG. 11 includes an integrator 51, a comparator 52, a reset signal generation unit 53, switches (switching units) SW5 and SW6, and a differentiator 54.

The integrator 51 generates an integration signal whose voltage level increases with time. Comparator 52, the calibration mode (Cal.Mode: first modes) compares the output signal of the reference voltage _{V REF} and an integrator 51 which selector 24 is used, the normal mode (second mode) times the output of the selector 24 Based on the result of comparing the signal and the output signal of the integrator 51, a binary signal is generated.

  The reset signal generation unit 53 outputs the reset signal RST from when the value of the binary signal output from the comparator 52 changes until the rising or falling edge of the reference signal is input. The reset signal generation unit 53 includes, for example, two D flip-flops 55 and 56 and a NAND gate 57 that performs a NAND operation between the output signals of the D flip-flops 55 and 56.

  The switches SW5 and SW6 stop the operation of the integrator 51 during the output period of the reset signal RST. The differentiator 54 generates the second digital signal TDC [3: 1] based on the count value of the counter 22 and the reset signal RST.

The integrator 51 has a switch SW5 interposed between the current source 58 and the capacitor C, and a switch SW6 connected in parallel to the capacitor C. One end of the capacitor C is connected to the + input terminal of the comparator 52. It is connected. The output signal SEL _out of the selector 24 is input to the − input terminal of the comparator 52.

  FIG. 12 is a signal waveform diagram inside the quantizer 25. When the reset signal RST output from the reset signal generator 53 is 1, it is in a reset state, the switch SW5 is off, and the switch SW6 is on.

When the rising edge of the reference signal REF from the reference signal source 11 is input, the reset signal generation unit 53 sets the reset signal to 0 and cancels the reset state (time t1). Thus, the switch SW1 is turned on, the switch SW2 is turned off, the capacitor C in the integrator 51 starts the charge accumulation, the voltage level of the output signal (integration signal) CP _out of the integrator 51, with time It increases linearly (time t1 to t2).

When the integration signal CP _out exceeds the reference voltage V _REF or the output signal SEL _out of the selector 24, the output signal CMP _out of the comparator 52 becomes 1 (time t2 to t3), and the reset signal becomes 1.

Thereafter, when the reference signal REF from the reference signal source 11 becomes high, the reset signal becomes 0 (time t4). Flip-flop 55 in the reset signal generation unit 53 detects the rising edge of the output signal _{CMP out} of the comparator 52, in the reset state by the reset signal RST to 1 (time t5). Thus, the switch SW1 is turned off, the switch SW2 is turned on, the capacitor C in the integrator 51 starts the discharge operation, the integrated signal _{CP out} becomes zero (time t6).

While the quantizer 25 is performing such an operation, the counter 22 continuously performs a count-up operation. The differentiator 54 stores the count value of the counter 22 when the reset signal RST is canceled and the count value of the counter 22 when the reset signal RST is next reset, A differential process for detecting the difference is performed. Differentiator 54, the integrated signal CPout from time 0, the integration signal _{CP out} to detect the time until exceeds the output signal _{SEL out} or the reference voltage _{V REF} of the selector 24.

Since the output signal of the differentiator 54 is a relative digital value and needs to be normalized by the reference voltage V _REF that is the maximum value, a calibration mode is provided. In the calibration mode, the comparator 52 compares the integration signal CP _out with the reference voltage V _REF, and the differentiator 54 starts from the time when the integration signal CP _out is 0 until the integration signal CP _out exceeds the reference voltage V _REF. Detect the time.

  In FIG. 12, time t1 to t4 is a calibration mode period, and after time t5 is a normal mode period.

As described above, the differentiator 54 detects the difference between the two count values and outputs a digital value TDC [3: 1] obtained by normalizing the difference with the reference voltage _VREF .

  As the counter 22 described above, the binary counter 14 originally provided in the receiver 2 of FIG. 1 can be used. The reason why the diversion is possible is that the differentiator 54 calculates the difference between the count values of the counter 22, and therefore the counter 22 only needs to continue the count-up operation and does not depend on the count value.

As described above, in the fourth embodiment, the differentiator 54 calculates the difference between the count value when the reset state is released and the count value when the integration signal CP _out exceeds the output signal SEL _out of the selector 24. Since it detects and determines TDC [3: 1], the processing of the quantizer 25 can be realized by digital signal processing. Further, since the counter 22 only needs to continue the count-up operation, the count value of the counter 14 originally provided in the receiver 2 of FIG. 1 can be used as it is, and it is not necessary to provide the counter 22 separately. The internal configuration of the phase-digital converter 1 can be simplified.

  At least a part of the receiver 2 and the phase-digital converter 1 described in the above-described embodiment may be configured by hardware or software. When configured by software, a program for realizing at least a part of the functions of the receiver 1 and the phase-digital converter 1 is stored in a recording medium such as a flexible disk or a CD-ROM, and is read by a computer and executed. May be. The recording medium is not limited to a removable medium such as a magnetic disk or an optical disk, but may be a fixed recording medium such as a hard disk device or a memory.

  Further, a program for realizing at least a part of the functions of the receiver 1 may be distributed via a communication line (including wireless communication) such as the Internet. Further, the program may be distributed in a state where the program is encrypted, modulated or compressed, and stored in a recording medium via a wired line such as the Internet or a wireless line.

  The aspect of the present invention is not limited to the individual embodiments described above, and includes various modifications that can be conceived by those skilled in the art, and the effects of the present invention are not limited to the contents described above. That is, various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

1 phase-digital converter, 2 receiver, 3 antenna, 4 low noise amplifier, 5 frequency converter, 6 frequency divider, 7 low pass filter, 8 A / D converter, 9 digital signal demodulator, 10 frequency Synthesizer section, 21 frequency divider, 22 binary counter, 23 sample hold section, 24 selector, 25 quantizer, 31 comparator, 32 encoder, 33 phase synchronization section, 34 phase comparator, 35 charge pump, 36 loop filter, 41 digital phase synchronization unit, 42 digital phase comparator, 43 digital integrator, 44 digital filter, 45 DA converter, 51 integrator, 52 comparator, 53 reset signal generation unit, 54 differentiator, 55, 56 D flip-flop 57 NAND gate 2

Claims (10)

The first to second ^n- phase signals are generated by sampling and holding the first to second ^n- phase (n is an integer of 1 or more) multi-phase periodic signals in synchronization with the reference signal. 2 ⁿ sample and hold units;
A monotonically increasing or monotonically decreasing signal period included in the first to second ⁿ multiphase signals is selected every 1/2 ⁿ period based on the n-bit first digital signal to generate a monotonic change signal. A selector,
A quantizer that quantizes the monotonic change signal into a second digital signal of (mn) bits (m is an integer of 2 or more, m> n),
The higher-order bits of the phase difference signal between the reference signal and the first to second ^n- phase multiphase signals are the first digital signal, and the lower-order bits of the phase difference signal are the second digital signal. A phase-to-digital converter. 2. The phase-digital converter according to claim 1, further comprising a frequency divider that divides a voltage-controlled oscillation signal generated by a voltage-controlled oscillator to generate the first to second ^n- phase multiphase periodic signals. The selector is
A first comparator that generates 2 ⁿ binary signals indicating a result of comparing each of the first to second ⁿ multiphase signals and a predetermined reference signal;
An encoding unit that encodes the 2 ⁿ binary signals to generate the first digital signal;
A phase comparator for detecting a phase difference from a falling edge of an early phase of two adjacent phases to a rising edge of a subsequent phase among the first to second ⁿ multiphase signals;
A charge pump for integrating the output of the phase comparator;
The phase-digital converter according to claim 1, further comprising: a loop filter that supplies a signal obtained by smoothing an output signal of the charge pump to the comparator as the reference signal. A digital integrator that integrates an output of a digital signal representing a phase difference detected by the phase comparator;
A digital filter for smoothing the output signal of the digital integrator;
The phase-digital converter of Claim 3 provided with the digital-analog converter which converts the output signal of the said digital filter into the said analog reference signal. A counter that measures the number of rising or falling edges of any of the first to second ⁿ multiphase signals;
The quantizer is
An integrator that generates an integrated signal whose voltage level increases over time;
A second comparator that generates a binary signal based on a result of comparing the output signal of the selector and the output signal of the integrator;
A reset signal generation unit that sets a reset state until the rising or falling edge of the reference signal is input after the value of the binary signal output from the second comparator changes;
During the period of the reset state, a switching unit that stops the operation of the integrator,
5. The phase-digital conversion according to claim 1, further comprising: a differentiator that generates the second digital signal based on a count value of the counter counted within a period in which the reset state is released. vessel.   The differentiator performs a differentiation process based on a count value of the counter when the reset signal is released and a count value of the counter when the reset signal is input next, and performs the second digital processing. 6. A phase-to-digital converter according to claim 5 for generating a signal. The second comparator compares the maximum signal that can be output by the selector with the output signal of the integrator in the first mode, and compares the output signal of the selector with the output signal of the integrator in the second mode. Based on the result, a binary signal is generated,
7. The phase − according to claim 5, wherein the differentiator generates the second digital signal by normalizing the differentiated value based on a comparison result of the second comparator in the first mode. Digital converter. A frequency converter that detects a phase difference between the phase of the received signal and the phase of the voltage controlled oscillation signal generated by the voltage controlled oscillator;
A low-pass filter for removing unnecessary high-frequency components of the frequency converter;
An analog-to-digital converter that converts a signal that has passed through the low-pass filter into a digital signal;
A frequency synthesizer that feedback controls the frequency of the voltage-controlled oscillation signal,
The frequency synthesizer is
A phase-digital converter for detecting the phase of the voltage-controlled oscillation signal;
A counter that detects the phase of the voltage-controlled oscillation signal more coarsely than the phase-digital converter;
A loop gain control unit that generates a control signal for controlling the frequency of the voltage-controlled oscillation signal based on the output value of the phase-digital converter and the count value of the counter;
The phase-to-digital converter is
The first to second ^n- phase signals are generated by sampling and holding the first to second ^n- phase (n is an integer of 1 or more) multi-phase periodic signals in synchronization with the reference signal. 2 ⁿ sample and hold units;
A monotonically increasing or monotonically decreasing signal period included in the first to second ⁿ multiphase signals is selected every 1/2 ⁿ period based on the n-bit first digital signal to generate a monotonic change signal. A selector,
A quantizer that quantizes the monotonic change signal into a second digital signal of (mn) bits (m is an integer of 2 or more, m> n),
The higher-order bits of the phase difference signal between the reference signal and the first to second ^n- phase multiphase signals are the first digital signal, and the lower-order bits of the phase difference signal are the second digital signal. There is a receiver.   The receiver according to claim 8, wherein the quantizer quantizes the second digital signal using a count value of the counter.   The receiver of Claim 8 or 9 provided with the antenna which receives the said received signal.

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