JP2016127193A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of the potential for causing a channel ion implantation region not to be formed so as to sufficiently cover an injection region for LDD formation with refinement.SOLUTION: A semiconductor device manufacturing method comprises: a process of forming resist film having an opening for exposing a part of an off-set film in a region between first gate wiring and second gate wiring; a process of etching the off-set film exposed from the opening by using the resist film as a mask; a process of implanting a first impurity into an active region by using the off-set film as a mask to form a first impurity diffusion layer on the active region; and a process of implanting a second impurity into the active region by using the off-set film as a mask to form on the active region, a second impurity diffusion layer which covers a bottom face and a lateral face of the first impurity diffusion layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In a DRAM (Dynamic Random Access Memory), there is a circuit pattern portion that is used without switching the source and drain of a transistor. In the case where the drive voltage is higher than that in the conventional circuit pattern portion, as disclosed in Patent Document 1, the third impurity diffusion region (P-type impurity diffusion layer) is used as the source constituting the source. A transistor formed only around the first impurity diffusion region (high-concentration N-type impurity region) and the second impurity diffusion region (LDD diffusion region) may be employed. By doing so, the electric field of the drain is relaxed and punch-through between the source and the drain is prevented.

  The transistor disclosed in Patent Document 1 includes a first conductivity type semiconductor substrate, an insulating film formed on the semiconductor substrate, a gate electrode formed on the insulating film, and sandwiching the gate electrode. Formed between the first impurity diffusion region of the pair of second conductivity types that form the source / drain and the first impurity diffusion region, and has a lower concentration than the first impurity diffusion region. And the second impurity diffusion region of the same conductivity type, the first impurity diffusion region constituting the source and the second impurity diffusion region, and the first impurity diffusion region constituting the drain and the first impurity diffusion region. And a third impurity diffusion region having a higher impurity concentration of the first conductivity type than the periphery of the second impurity diffusion region. The third impurity diffusion region is asymmetric with the drain. The third impurity diffusion region is formed by forming the second impurity diffusion region after forming the gate electrode, covering the drain with a resist, and implanting ions of the first conductivity type into the source. .

  Further, Patent Document 2 discloses a method of performing channel ion implantation from an oblique direction with respect to a substrate so that a channel ion implantation region corresponding to the third impurity diffusion region described in Patent Document 1 can reliably enclose the source. It is disclosed.

JP-A-8-186252 JP-A-10-56147

  The following analysis is given by the inventor.

  However, even when channel ion implantation is performed on the common source region between the two gates from an oblique direction with respect to the substrate as in the method of manufacturing a semiconductor device described in Patent Document 2, the channel ion implantation region is not LDD. There is a possibility that the forming implantation region cannot be sufficiently covered. That is, in Patent Document 2, when channel ion implantation is performed, an implantation resist mask opened in a source region between two gates is formed, and with the miniaturization, the interval between the two gates becomes narrower. Because the aspect ratio of the resist mask opening is considerably large, even if channel ion implantation is performed from an oblique direction, the channel is formed only at an angle where the oblique implantation angle (angle from the direction perpendicular to the substrate top surface) is small due to shadowing. There is a possibility that the channel ion implantation region cannot be formed so as to sufficiently cover the LDD formation implantation region. In order to reduce the influence of shadowing, it is conceivable to make the implantation resist mask thinner. However, if the implantation resist mask is made thinner, channel ions to be implanted may penetrate the implantation resist mask. The resist mask for implantation cannot be thinned easily.

  A method of manufacturing a semiconductor device according to a first aspect includes a step of forming an active region surrounded by an element isolation region on a semiconductor substrate, and a first gate adjacent to each other provided so as to cross the active region Forming a wiring and a second gate wiring; forming an offset film so as to cover the active region; the first gate wiring; and the second gate wiring; and the first gate wiring and the second gate wiring. Forming a resist film having an opening exposing a part of the offset film in a region between the gate wiring and etching the offset film exposed from the opening using the resist film as a mask; Removing the resist film, and implanting a first impurity into the active region using the offset film as a mask, thereby expanding the first impurity on the active region. A second impurity diffusion layer that covers a bottom surface or a side surface of the first impurity diffusion layer on the active region by injecting a second impurity into the active region using the offset film as a mask. Forming a sidewall film on the respective sidewalls of the first gate wiring and the second gate wiring via the offset film, the first gate wiring, the second gate wiring, and Forming a third impurity diffusion layer on the active region by injecting a third impurity into the active region using the sidewall film as a mask.

  A semiconductor device according to a second aspect crosses over the semiconductor substrate, an element isolation region formed on the semiconductor substrate, an active region partitioned by the element isolation region in the semiconductor substrate, and the active region. A first gate line and a second gate line adjacent to each other, an offset film covering sidewalls of the first gate line and the second gate line, the first gate line and the second gate line A sidewall film that covers the sidewall of the first gate wiring with the offset film interposed therebetween, wherein the first gate wiring and the second gate wiring are on opposite sides of the first gate wiring in the first direction. And the sidewall film on the side of the second gate wiring in the second direction opposite to the first direction, the offset film is the active film. Covering the side wall facing the horizontal direction of the bottommost portion closest to the region, the sidewall film on the second direction side of the first gate wiring, and the first gate wiring in the first direction The side wall film facing the side does not cover the side wall facing the horizontal direction at the bottom of the offset film closest to the active region.

  A semiconductor device according to a third aspect crosses over a semiconductor substrate, an element isolation region formed on the semiconductor substrate, an active region partitioned by the element isolation region in the semiconductor substrate, and the active region. A first gate line and a second gate line adjacent to each other, and a first offset film provided on a side surface in the first direction on the second gate line side of the first gate line, A second offset film provided on a side surface of the first gate wiring in the second direction opposite to the first direction; and a second offset film provided on a side surface of the second gate wiring in the second direction. A third offset film, a fourth offset film provided on a side surface of the second gate wiring in the first direction, and a first stacked on the first offset film. A sidewall film, a second sidewall film stacked on the second offset film, a third sidewall film stacked on the third offset film, and a second sidewall film stacked on the fourth offset film. 4 sidewall films, and the first offset film is at least partially present between the first sidewall film and the semiconductor substrate in a direction perpendicular to the upper surface of the active region, The third offset film is at least partially present between the third sidewall film and the semiconductor substrate in a direction perpendicular to the upper surface of the active region, and is perpendicular to the upper surface of the active region. The second offset film is entirely present between the second sidewall film and the semiconductor substrate, and the vertical offset is perpendicular to the upper surface of the active region. 4 between the side wall film and said semiconductor substrate, said fourth offset film exists as a whole.

  According to the present invention, it is possible to form the second impurity diffusion layer that sufficiently covers the bottom surface or the side surface of the first impurity diffusion layer even when miniaturized.

FIG. 3 is a cross-sectional view taken along the line XX ′ of FIG. 2 schematically showing the configuration of the active region and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 3 is a partial plan view schematically showing a configuration of an active region and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view corresponding to the section XX ′ in FIG. 2 schematically showing a method for manufacturing a transistor portion and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view corresponding to a line between XX ′ and FIG. 3 schematically illustrating a method for manufacturing a transistor portion and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view corresponding to a line between XX ′ and FIG. 4 schematically illustrating a method for manufacturing a transistor portion and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view corresponding to a line between XX ′ and FIG. 5 schematically showing a method for manufacturing a transistor portion and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view corresponding to a line between XX ′ and FIG. 6 schematically showing a method for manufacturing a transistor portion and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view corresponding to a line between XX ′ and FIG. 7 schematically illustrating a method for manufacturing a transistor portion and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 9 is a cross-sectional view corresponding to the section between XX ′ and FIG. 8 schematically illustrating the method for manufacturing the transistor portion and the peripheral portion thereof in the semiconductor device according to the first embodiment. FIG. 10 is a cross-sectional view corresponding to a line between XX ′ and FIG. 9 schematically illustrating a method for manufacturing a transistor portion and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 11 is a cross-sectional view corresponding to a line between XX ′ and FIG. 10 schematically illustrating a method for manufacturing the transistor portion and the peripheral portion thereof in the semiconductor device according to the first embodiment. FIG. 12 is a cross-sectional view corresponding to a line between XX ′ and FIG. 11 schematically showing a method for manufacturing a transistor portion and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 13 is a cross-sectional view corresponding to the line XX ′ subsequent to FIG. 12 schematically showing a method for manufacturing a transistor portion and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 14 is a cross-sectional view corresponding to a line between XX ′ and FIG. 13 schematically illustrating a method for manufacturing the transistor portion and the peripheral portion thereof in the semiconductor device according to the first embodiment. FIG. 15 is a cross-sectional view corresponding to the line XX ′ following FIG. 14 schematically showing the method for manufacturing the transistor portion and the peripheral portion thereof in the semiconductor device according to the first embodiment. FIG. 16 is a cross-sectional view corresponding to a section taken along line XX ′ in FIG. 15 schematically illustrating a method for manufacturing the transistor portion and the peripheral portion thereof in the semiconductor device according to the first embodiment. FIG. 17 is a cross-sectional view corresponding to the line XX ′ following FIG. 16 schematically illustrating the method for manufacturing the transistor portion and the peripheral portion thereof in the semiconductor device according to the first embodiment. It is sectional drawing which showed typically the manufacturing method of the transistor part and its peripheral part in the semiconductor device which concerns on a comparative example. FIG. 19 is a cross-sectional view following FIG. 18 schematically showing a method for manufacturing a transistor portion and its peripheral portion in a semiconductor device according to a comparative example. FIG. 20 is a cross-sectional view subsequent to FIG. 19, schematically illustrating a method for manufacturing a transistor portion and its peripheral portion in a semiconductor device according to a comparative example. FIG. 21 is a cross-sectional view subsequent to FIG. 20, schematically illustrating a method for manufacturing a transistor portion and its peripheral portion in a semiconductor device according to a comparative example. FIG. 22 is a cross-sectional view subsequent to FIG. 21, schematically illustrating a method for manufacturing a transistor portion and its peripheral portion in a semiconductor device according to a comparative example. FIG. 23 is a cross-sectional view following FIG. 22 schematically showing a method for manufacturing a transistor portion and its peripheral portion in a semiconductor device according to a comparative example. FIG. 24 is a cross-sectional view subsequent to FIG. 23, schematically showing a method for manufacturing a transistor portion and its peripheral portion in a semiconductor device according to a comparative example. 4 is a graph schematically showing a relationship between a driving voltage of a transistor portion and a transistor lifetime in a semiconductor device according to each of Embodiment 1 and a comparative example. FIG. 32 is a plan view of a region R in FIG. 31 schematically showing the configuration of the semiconductor device according to the second embodiment. It is the top view seen from the lower layer rather than FIG. 26 in the area | region R of FIG. 31 which showed the structure of the semiconductor device concerning Embodiment 2 typically. FIG. 28 is a cross-sectional view taken along the line X1-X1 ′ in FIGS. 26 and 27 schematically illustrating the configuration of the semiconductor device according to the second embodiment. FIG. 28 is a cross-sectional view taken along the line X2-X2 ′ in FIGS. 26 and 27 schematically illustrating the configuration of the semiconductor device according to the second embodiment. FIG. 28 is a cross-sectional view taken along the line X3-X3 ′ in FIGS. 26 and 27 schematically illustrating the configuration of the semiconductor device according to the second embodiment. FIG. 6 is a plan view schematically showing a configuration of a semiconductor device according to a second embodiment. 26 and 27 schematically showing the method of manufacturing the semiconductor device according to the second embodiment, corresponding to (a) between X1-X1 ', (b) between X2-X2', and (c) between X3-X3 '. FIG. FIG. 32 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. FIG. 33 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. FIG. 34 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. FIG. 35 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. FIG. 36 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. FIG. 37 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. 38 is a cross-sectional view corresponding to (a) between X1-X1 ′, (b) between X2-X2 ′, and (c) between X3-X3 ′, schematically illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. FIG. 39 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. Sectional view corresponding to (a) X1-X1 ′, (b) X2-X2 ′, (c) X3-X3 ′ following FIG. 40 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. FIG. 41 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. FIG. 42 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. FIG. 43 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. 44, which schematically illustrates the method for manufacturing the semiconductor device according to the second embodiment, is a cross section corresponding to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. FIG. 45 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. 46, which schematically illustrates the method for manufacturing the semiconductor device according to the second embodiment, a cross section corresponding to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. FIG. 47 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. FIG. 48 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG. FIG. 49 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. The cross section corresponds to (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) between X3 and X3 ′. FIG.

  Hereinafter, embodiments will be described with reference to the drawings. Note that, in the present application, where reference numerals are attached to the drawings, these are only for the purpose of helping understanding, and are not intended to be limited to the illustrated embodiments.

[Embodiment 1]
A semiconductor device according to Embodiment 1 will be described with reference to the drawings. 1 is a cross-sectional view taken along the line XX ′ of FIG. 2 schematically showing the configuration of the transistor portion and its peripheral portion in the semiconductor device according to the first embodiment. FIG. 2 is a partial plan view schematically showing the configuration of the transistor portion and its peripheral portion in the semiconductor device according to the first embodiment.

  The semiconductor device according to the first embodiment includes a pair of N-type transistors 2 each having two gate wirings 13 traversing one active region 12 partitioned by the element isolation region 11 in the transistor portion and the peripheral portion thereof. 3.

  In the semiconductor device according to the first embodiment, the element isolation region 11 is embedded in the element isolation groove 10a formed in the semiconductor substrate 10 (for example, a silicon substrate). The element isolation region 11 has an STI (Shallow Trench Isolation) structure. The element isolation region 11 includes a buried insulating film 11b (for example, silicon oxide film) through a liner insulating film 11a (for example, silicon nitride film) formed along the bottom surface or wall surface of the element isolation groove 10a in the element isolation groove 10a. Membrane) is embedded. A portion of the semiconductor substrate 10 in a region surrounded by the element isolation region 11 becomes an active region 12. In the semiconductor substrate 10, a well (not shown) in which a P-type impurity is implanted in the active region 12 is formed.

  A gate wiring 13 is formed on the active region 12 via a gate insulating film (not shown; for example, a silicon oxide film). The gate wiring 13 extends in the Y direction and is formed so as to cross over the active region 12. There are two gate wirings 13 on the active region 12, and they are arranged in parallel. The gate wiring 13 includes, from the bottom, a first DOPOS film 13a (doped polysilicon film), a second DOPOS film 13b (doped polysilicon film), and a conductive laminated film 13c (for example, WSi / TiN / Ti film: tungsten silicide / titanium nitride / titanium). Film), W film 13d (tungsten film), and mask nitride film 13e (for example, silicon nitride film) in this order. The mask nitride film 13e has a recess 18a in which corner portions on the side where the upper two gate wirings 13 face each other are recessed by etching. Sidewall films 21 a are formed on both sides of the side wall of the gate wiring 13 via an offset nitride film 15 (for example, silicon nitride film) and an offset oxide film 16 (for example, silicon oxide film). An offset nitride film 15 and an offset oxide film 16 are interposed between the side wall film 21a on the opposite side of the side where the two gate wirings 13 face each other and the active region 12. On the other hand, there is a portion where the offset nitride film 15 and the offset oxide film 16 are not interposed between the active region 12 and the sidewall film 21a on the side where the two gate wirings face each other.

  In the active region 12, N-type high-concentration impurity diffusion layers 22 a and 22 b serving as drains are formed in regions opposite to the side where the two gate wirings 13 face each other. The active region 12 includes a common source used in common for the two N-type transistors 2 and 3 in a region where the two gate wirings 13 face each other (between the two gate wirings 13). An N-type high concentration impurity diffusion layer 22c is formed.

  In the active region 12, P-type low-concentration impurity diffusion layers 20a and 20b connected to the N-type high-concentration impurity diffusion layers 22a and 22b are formed in the vicinity immediately below the sidewall film 21a. The P-type low-concentration impurity diffusion layers 20a and 20b are formed shallower than the N-type high-concentration impurity diffusion layers 22a and 22b. In the active region 12, an N-type low-concentration impurity diffusion layer 19 connected to the N-type high-concentration impurity diffusion layer 22c is formed near the sidewall film 21a. That is, the N-type high concentration impurity diffusion layer 22 c is formed so as to penetrate the N-type low concentration impurity diffusion layer 19. The N-type low concentration impurity diffusion layer 19 is formed shallower than the N-type high concentration impurity diffusion layer 22c. Further, a P-type asymmetric implantation layer 20 c is formed in the active region 12 so as to cover the lower surface or the side wall of the N-type low concentration impurity diffusion layer 19. The P-type asymmetric implantation layer 20c covers at least the side wall of the N-type high concentration impurity diffusion layer 22c (excluding the portion in contact with the N-type low concentration impurity diffusion layer 19). The N-type low concentration impurity diffusion layer 19 has a lower N-type impurity concentration than the N-type high concentration impurity diffusion layer 22c. The P-type impurity concentration of the P-type low-concentration impurity diffusion layers 20 a and 20 b and the P-type asymmetric injection layer 20 c is higher than the P-type impurity concentration of a well (not shown) in the semiconductor substrate 10. The P-type low-concentration impurity diffusion layers 20a and 20b are shallower than the P-type asymmetric implantation layer 20c, and the P-type impurity concentration is lower than that of the P-type asymmetric implantation layer 20c.

  One (the right side in FIG. 1) gate wiring 13, the N-type high concentration impurity diffusion layer 22c, and the N-type high concentration impurity diffusion layer 22a constitute the N-type transistor 2, and the other (left side in FIG. 1) gate. The wiring 13, the N-type high concentration impurity diffusion layer 22 c, and the N-type high concentration impurity diffusion layer 22 b constitute the N-type transistor 3.

  An interlayer insulating film 24 (for example, a silicon oxide film) is formed on the N-type transistors 2 and 3, the sidewall film 21 a and the element isolation region 11 via a liner nitride film 23 (for example, a silicon nitride film). . The upper surface of the interlayer insulating film 24 is planarized so as to be flush with the uppermost surface of the liner nitride film 23. In the interlayer insulating film 24 and the liner nitride film 23, openings 25a, 25b, and 25c that communicate with the N-type high concentration impurity diffusion layers 22a, 22b, and 22c are formed. Silicide layers 26a, 26b, and 26c are formed in the portions of the N-type high concentration impurity diffusion layers 22a, 22b, and 22c facing the openings 25a, 25b, and 25c. Contact plugs 27, 28, and 29 are formed in the openings 25a, 25b, and 25c or in the vicinity of the upper portions thereof. The contact plugs 27, 28, and 29 are formed of barrier films 27 c, 28 c, and 29 c (for example, a TiN film: titanium nitride film) formed along the bottom surface or the side wall of the openings 25 a, 25 b, and 25 c and the peripheral edge of the upper portion. Plug portions 27a, 28a, 29a and pad portions 27b, 28b, 29b (for example, W film: tungsten film) are formed. The plug portions 27a, 28a, and 29a are portions embedded in the openings 25a, 25b, and 25c. The pad portions 27 b, 28 b and 29 b are portions formed above the upper surface of the interlayer insulating film 24. The plug parts 27a, 28a, 29a and the pad parts 27b, 28b, 29b are integrated.

  The liner nitride film 23 and the mask nitride film 13e are formed with openings (not shown) that communicate with the W film 13d of each gate wiring 13, and contact plugs 30, 31 are formed in the openings or in the vicinity thereof. Is formed. The contact plugs 30 and 31 have the same configuration as the contact plugs 27, 28 and 29.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. 3 to 17 are cross-sectional views schematically showing a method for manufacturing a transistor portion and its peripheral portion in the semiconductor device according to the first embodiment.

  First, an element isolation trench 10a having a predetermined depth (for example, about 300 nm) is formed on a semiconductor substrate 10 (for example, a silicon substrate) (step A1; see FIG. 3). Thereby, the active region 12 is defined.

  Next, a liner insulating film 11a (for example, a silicon nitride film) is formed on the semiconductor substrate 10 along the side wall or the bottom surface of the element isolation groove 10a, and the inside of the element isolation groove 10a is further formed on the liner insulating film 11a. A buried insulating film 11b (for example, a silicon oxide film) is deposited so as to be buried by using a technique such as SOD (Spin On Dielectrics) method or fluid CVD (Flowable Chemical Vapor Deposition) method (step A2; see FIG. 3). ).

  Next, the extra buried insulating film 11b and liner insulating film are formed by CMP (Chemical Mechanical Polishing) so that the upper surface of the semiconductor substrate 10 and the upper surfaces of the buried insulating film 11b and liner insulating film 11a are flush with each other. The element isolation region 11 having the STI structure is formed by polishing 11a (step A3; see FIG. 3).

  Next, a P-type impurity is implanted from the direction perpendicular to the surface of the semiconductor substrate 10 to form a P-well (not shown) in the active region 12 (step A4; see FIG. 3).

  Next, a gate insulating film (not shown) is formed on the semiconductor substrate 10 in the active region 12, and then a first DOPOS film 13a (for forming a gate wiring 13 on the gate insulating film and the element isolation region 11). Doped polysilicon film), second DOPOS film 13b (doped polysilicon film), conductive laminated film 13c (for example, WSi / TiN / Ti film: tungsten silicide / titanium nitride / titanium film), W film 13d (tungsten film), mask A nitride film 13e (for example, a silicon nitride film) is formed in this order (step A5; see FIG. 3). The impurity doping amounts of the first DOPOS film and the second DOPOS film are different, but may be the same.

  Next, a resist film (not shown) for forming a gate pattern is formed on the mask nitride film 13e, and then the gate pattern is transferred to the mask nitride film 13e. The film 13d to the first DOPOS film 13a are etched (step A6; see FIG. 3). As a result, two gate wirings 13 traversing the active region 12 are formed. The height of the gate wiring 13 from the outermost surface of the active region 12 (the surface of the semiconductor substrate 10) can be about 270 nm, for example. The L / S width (line and space width) can be set to 22 nm / 22 nm, for example.

  Next, an offset nitride film 15 (silicon nitride film) is formed on the entire surface of the semiconductor substrate 10 so as to cover the gate wiring 13 with a predetermined thickness (for example, 5 nm), and an offset oxide film 16 (silicon oxide film) with a predetermined thickness ( For example, 5 nm) are formed in this order (step A7; see FIG. 4). Here, the offset film is a laminated film of the offset nitride film 15 and the offset oxide film 16, but may be a single layer of an offset nitride film or an offset oxide film. In consideration of ion implantation, it is convenient to use an offset nitride film having poor ion implantation permeability as a single layer.

  Next, a resist film 17 is applied on the offset oxide film 16 with a predetermined thickness (for example, 370 nm from the lowest surface on the upper surface of the offset oxide film 16) (step A8; see FIG. 5). Here, for example, a KrF resist can be used as the resist film 17, but an i-line resist or an ArF resist may be used as long as a target film thickness and an opening diameter after development can be achieved.

  Next, exposure is performed using a reticle between the two gate wirings 13 on the active region 12, and development is performed (step A9; see FIG. 6). As a result, the resist film 17 between and above the two gate wirings 13 is removed, and an opening 17a is formed in the resist film 17 as shown in FIG.

Next, using the resist film 17 as a mask, the offset nitride film 15 and the offset oxide film 16 are selectively etched (for example, etched back by anisotropic dry etching) (step A10; see FIG. 7). At this time, in addition to the offset nitride film 15 and the offset oxide film 16 positioned between the two gate wirings 13 in the opening 17a, the offset nitride film 15 and the offset positioned at the corners on the upper surface of the two gate wirings 13 The oxide film 16 and the mask nitride film 13e are removed, and a recess 18a and an opening 18b are formed. Note that the offset nitride film 15 and the offset oxide film 16 located on the side wall between the other two gate wirings 13 can be left in a sidewall shape. In the dry etching here, C _x F _y (fluorocarbon) gas such as CF ₄ or C ₂ F ₄ is mainly used to suppress the etching rate of the semiconductor substrate 10 (silicon) as much as possible. adjust.

  Next, the resist film (17 in FIG. 7) is removed (step A11; see FIG. 8).

Next, an N-type impurity (for example, phosphorus) is ion-implanted into the active region 12 exposed from the opening 18b using the offset nitride film 15 and the offset oxide film 16 as a mask, thereby forming an N-type low-concentration impurity diffusion layer 19. (Step A12; see FIG. 9). The ion implantation conditions at this time can be, for example, E (implantation energy) = 4.0 kev, φ (dose amount) = 1.0 × 10 ¹⁴ atoms / cm ^2, and in this case, an N-type low-concentration impurity The implantation depth in the active region 12 of the diffusion layer 19 reaches 8.5 nm.

  Next, using the offset nitride film 15 and the offset oxide film 16 as a mask, P-type impurities (for example, boron) are applied from a direction within a predetermined range (for example, 17 degrees) from the vertical direction with respect to the upper surface of the active region 12. By implanting ions into the active region 12, a P-type asymmetric implantation layer 20c is formed in the active region 12 so as to cover the lower surface or side surface of the N-type low concentration impurity diffusion layer 19 (step A13; see FIG. 10).

  Here, the angle in the predetermined range in step A13 is not fixed but is an angle in a range that can be adjusted in a timely manner. For example, there is no problem even if it is 17 degrees or more and 20 degrees or less. Also, the portion corresponding to the drain other than the active region 12 exposed from the opening 18b is shallower than the P-type asymmetric implantation layer 20c and has a P-type impurity concentration lower than that of the P-type asymmetric implantation layer 20c. Low concentration impurity diffusion layers 20a and 20b are formed.

  Note that the P-type low-concentration impurity diffusion layers 20a and 20b are not essential. The P-type low-concentration impurity diffusion layers 20a and 20b have no adverse effect on the N-type transistors 2 and 3 because the offset nitride film 15 and the offset oxide film 16 serve as a mask and the concentration of P-type impurities is considerably suppressed. Furthermore, there is no particular problem even if the offset nitride film 15 and the offset oxide film 16 are thick and cannot transmit P-type impurities and the P-type low-concentration impurity diffusion layers 20a and 20b cannot be formed.

The ion implantation conditions in step A13 can be, for example, E (implantation energy) = 10.0 kev and φ (dose amount) = 4.2 × 10 ¹³ atoms / cm ² . In this case, the implantation depth in the active region 12 of the P-type asymmetric implantation layer 20c between the two gate wirings 13 reaches 33.0 nm, and the P-type low-concentration impurities that serve as the trains of the two gate wirings 13 respectively. The implantation depth in the active region 12 of the diffusion layers 20a and 20b reaches 15 nm.

  Next, an LDD insulating film 21 is formed so as to cover the entire surface of the semiconductor substrate 10 (step A14; see FIG. 11). Here, the LDD insulating film 21 can be formed using, for example, a vertical LPCVD furnace. The film thickness of the LDD insulating film 21 can be set to 60 nm, for example.

  Next, the LDD insulating film (21 in FIG. 11), the offset nitride film 15 and the offset oxide film 16 are selectively etched back by anisotropic dry etching, so that both sides of each of the two gate wirings 13 are provided. An asymmetric sidewall film 21a is formed on the sidewall (step A15; see FIG. 12). Here, the offset nitride film 15 and the offset oxide film 16 are interposed between the side wall film 21a on the opposite side of the side where the two gate wirings 13 face each other and the active region 12, There is a portion where the offset nitride film 15 and the offset oxide film 16 are not interposed between the sidewall film 21a and the active region 12 on the side where the two gate wirings 13 face each other.

  Next, N-type impurities (for example, phosphorus and arsenic) are ion-implanted into the active region 12 by using the two gate wirings 13 and the sidewall film 21a as a mask, so that the two gate wirings 13 and the respective sidewalls are implanted. N-type high-concentration impurity diffusion layers 22a, 22b, and 22c are formed in the exposed active region 12 without the film 21a (step A16; see FIG. 13).

Here, the ion implantation conditions in step A16 are, for example, that phosphorus among N-type impurities is E (implantation energy) = 15.0 kev, φ (dose amount) = 4.0 × 10 ¹³ atoms / cm ^2, and N-type. Among the impurities, arsenic can be E (implantation energy) = 18.0 kev and φ (dose amount) = 3.0 × 10 ¹⁵ atoms / cm ² . Further, the implantation depth of the N-type high concentration impurity diffusion layers 22a, 22b, and 22c in the active region 12 at the common source and the drain of the two gate wirings 13 can be 35.0 nm. The N-type high concentration impurity diffusion layers 22 a, 22 b and 22 c are deeper than the depths of the P-type low concentration impurity diffusion layers 20 a and 20 b and the N-type low concentration impurity diffusion layer 19.

Next, by performing a heat treatment at 980 ° C. in an N ₂ atmosphere, the N-type low-concentration impurity diffusion layer 19, the P-type low-concentration impurity diffusion layers 20a and 20b, the P-type asymmetric implantation layer 20c, and the N-type high concentration The impurity diffusion layers 22a, 22b, and 22c are activated (step A17; see FIG. 14).

  Next, a liner nitride film 23 (for example, a silicon nitride film) is formed so as to cover the entire surface of the semiconductor substrate 10 (step A18; see FIG. 14). Here, the liner nitride film 23 can be formed in, for example, a vertical LPCVD (Low Pressure Chemical Vapor Deposition) furnace to have a film thickness of 25 nm. The liner nitride film 23 plays a role in preventing oxidation from reaching other than the interlayer insulating film (24 in FIG. 15) in the modification process (heat treatment) of the next process.

  Next, an interlayer insulating film 24 is formed on the entire surface of the semiconductor substrate 10 (step A19; see FIG. 15). Here, the interlayer insulating film 24 can be formed, for example, by applying an SOD (Spin On Dielectric) film and modifying it into an oxide film by heat treatment (steam annealing).

  Next, the interlayer insulating film 24 is planarized by CMP (Chemical Mechanical Polishing) until the upper surface of the liner nitride film 23 appears (step A20; see FIG. 16).

  Next, openings 25a, 25b, and 25c for connecting to the N-type high-concentration impurity diffusion layers 22a, 22b, and 22c serving as the drains and common sources of the adjacent N-type transistors 2 and 3 are formed. Silicide layers 26a, 26b, and 26c are formed in the N-type high concentration impurity diffusion layers 22a, 22b, and 22c exposed from 25a, 25b, and 25c (step A21; see FIG. 17). When the openings 25a, 25b, and 25c are formed, openings (not shown) that communicate with the W film 13d of the gate wiring 13 are formed at the positions of the contact plugs 30 and 31 in FIG.

  Next, a barrier film (for example, TiN film: titanium nitride film) for the barrier films 27c, 28c, and 29c is formed on the entire surface of the semiconductor substrate 10 including the side walls or the bottom surface of the openings 25a, 25b, and 25c. Conductive films (for example, W film: tungsten film) for the plug parts 27a, 28a, 29a and the pad parts 27b, 28b, 29b are formed so as to fill the openings 25a, 25b, 25c (step A22; see FIG. 1). ).

  Finally, by using a lithography technique and an etching technique, the barrier films for the barrier films 27c, 28c, and 29c and the conductive films for the plug parts 27a, 28a, and 29a and the pad parts 27b, 28b, and 29b are etched. Then, contact plugs 27, 28 and 29 are formed (step A23; see FIGS. 1 and 2). At this time, contact plugs (30 and 31 in FIG. 2) respectively connected to the gate wiring 13 are also formed.

  Since the inventor needed to change the driving voltage of the N-type transistor from 2.7 v to 2.9 v in inventing the semiconductor device and the manufacturing method thereof according to Embodiment 1 as described above, FIG. A semiconductor device manufacturing flow according to the comparative example shown in FIG.

  In the manufacturing flow of the semiconductor device according to the comparative example, first, similarly to Step A1 to Step A7 of Embodiment 1, the element isolation region 11, the gate wiring 13, the offset nitride film 15, and the offset oxide film 16 are formed on the semiconductor substrate 10. Then, the offset nitride film 15 and the offset oxide film 16 are selectively etched back by anisotropic dry etching (step B1; see FIG. 18). As a result, a sidewall-like offset nitride film 15 and an offset oxide film 16 are formed on the sidewalls on both sides of each of the two gate wirings 13.

  Next, an N-type impurity (for example, phosphorus) is ion-implanted into the exposed active region 12 using the offset nitride film 15, the offset oxide film 16, and the gate wiring 13 as a mask, thereby forming an N-type low-concentration impurity diffusion layer 19d. , 19e, 19f are formed (step B2; see FIG. 19).

  Next, a resist film 17 for forming the P-type asymmetric implantation layer 20d is formed by a lithography technique, and then a P-type impurity (for example, boron) is applied to the upper surface of the semiconductor substrate 10 using the resist film 17 as a mask. On the other hand, by implanting ions into the semiconductor substrate 10 from an angle within a predetermined range (about 10 degrees) from the vertical direction, the P-type asymmetric implantation layer 20d is formed under the N-type low-concentration impurity diffusion layer 19f in the active region 12. (Step B3; see FIG. 20).

  Next, an LDD insulating film 21 is formed so as to cover the entire surface of the semiconductor substrate 10 (step B4; see FIG. 21).

  Next, the LDD insulating film (21 in FIG. 21) is selectively etched back by anisotropic dry etching, whereby symmetrical sidewall films 21a are formed on the sidewalls on both sides of the two gate wirings 13, respectively. (Step B5; see FIG. 22).

  Next, by using the two gate wirings 13 and the sidewall film 21a as a mask, N-type impurities (for example, phosphorus and arsenic) are ion-implanted into the active region 12, so that the N-type high concentration impurity diffusion layers 22a, 22b, 22c is formed (step B6; see FIG. 23). Note that the N-type high-concentration impurity diffusion layers 22a, 22b, and 22c are deeper than the P-type low-concentration impurity diffusion layers 19d, 19e, and 19f.

  Finally, the liner nitride film 23, the interlayer insulating film 24, the openings 25a, 25b, 25c, the silicide layers 26a, 26b, 26c, and the contact plugs 27, 28, 29 are formed in the same manner as in Step A17 to Step A23. (Step B7; see FIG. 24).

  In the manufacturing flow of the semiconductor device according to the comparative example as described above, as shown in FIG. 20, by introducing the P-type asymmetric injection layer 20d under the N-type low concentration impurity diffusion layer 19f, the electric field of the drain is changed. We thought to alleviate and prevent a decrease in reliability due to HC (Hot Carrier) resistance deterioration.

  However, the P-type asymmetric injection layer 20d of the comparative example cannot cover both side walls of the N-type low-concentration impurity diffusion layer 19f serving as a common source between the two gate wirings 13, and cannot contribute to prevention of punch-through. I understood that. The cause is that when forming the P-type asymmetric injection layer 20d, a resist film 17 having an opening 17b between two gate wirings 13 is used, whereas the thickness of the resist film 17 is 370 nm. The opening 17b is an opening having an upper diameter of 44 nm (lower opening diameter of 22 nm) and a considerably large aspect ratio (8 or more). Therefore, even if oblique implantation is performed, the oblique implantation angle has a limit of 10 degrees at most, and the P-type asymmetric implantation layer 20d can be formed so as to sufficiently cover the side wall of the N-type low-concentration impurity diffusion layer 19f. could not.

  Therefore, in the method of manufacturing the semiconductor device according to the first embodiment, when forming the P-type asymmetric implantation layer 20c, instead of using the resist film 17 as shown in FIG. As shown in FIG. 10, the offset nitride film 15 and the offset oxide film 16 covering the two N-type transistors 2 and 3 and the mask nitride film 13e are used as a mask at the time of ion implantation.

  An offset nitride film 15 and an offset oxide film 16 are formed (see FIG. 4), and then a portion of the offset oxide film 16 that is not masked by the implantation of the P-type asymmetric implantation layer 20c, that is, between the two gate wirings 13 is formed. A resist film 17 having an opening 17a exposing the portion is formed (see FIG. 6), and dry etching is performed using the resist film 17 as a mask (see FIG. 7). Thereafter, the resist film 17 is removed (see FIG. 8), and an N-type low-concentration impurity diffusion layer 19 is formed by ion implantation using the remaining offset nitride film 15 and offset oxide film 16 as a mask for ion implantation (see FIG. 9). Then, a P-type asymmetric implantation layer 20c is formed so as to cover the sidewall of the N-type low concentration impurity diffusion layer 19 using an oblique ion implantation apparatus (see FIG. 10).

  As described above, in the first embodiment, in the step of forming the P-type asymmetric injection layer 20c, a resist film is not used as a mask, and an insulating film (offset nitride film 15 and offset oxidation film) of less than 10 nm covering the side surface of the gate wiring 13 is used. Since the film 16) is used, the aspect ratio of the opening of the ion-implanted portion is reduced. Looking at the aspect ratio in terms of height / opening top diameter, when the resist film 17 shown in FIG. 20 of the comparative example is used as a mask, the resist film 17 is 8.4 (370 nm / 44 nm). When the offset nitride film 15, the offset oxide film 16, and the mask nitride film 13e are used as a mask, it can be improved to 6.1 (270 nm / 44 nm). Thus, in forming the P-type asymmetric implantation layer 20c, the side wall of the N-type low-concentration impurity diffusion layer 19 is sufficiently formed while using an oblique implanter whose angle with the wall surface on the gate wiring 13 side is 17 to 20 degrees. It is possible to form the P-type asymmetric injection layer 20c that can be covered with the substrate.

  As a result, the electric field of the drain can be relaxed, and a decrease in reliability due to deterioration of HC (Hot Carrier) resistance between the source and drain can be prevented, and the reliability of the product can be significantly improved. FIG. 25 shows the transistor lifetime when the first embodiment is applied, and it was confirmed that the transistor lifetime was improved by 3 to 4 times when the comparative example was applied.

  According to the first embodiment, the offset nitride film 15 and the offset oxide film 16 which are thinner than the resist film are used as a mask in the step of forming the P-type asymmetric injection layer 20c (step A13; see FIG. 10). In addition, the degree of freedom in the implantation angle during oblique ion implantation is widened, the effect of oblique ion implantation can be fully exhibited, and transistor performance can be improved. In addition, since the source and the common source have an asymmetric structure, the limitation on the resist film thickness when the resist film is formed can be eliminated. Furthermore, since the corners on the side where the two gate wirings 13 face each other have the recesses 18a that are recessed by etching, the degree of freedom of the implantation angle at the time of oblique ion implantation can be further expanded.

[Embodiment 2]
A semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 26 is a plan view of a region R in FIG. 31 schematically showing the configuration of the semiconductor device according to the second embodiment. FIG. 27 is a plan view seen from a lower layer than FIG. 26 in a region R of FIG. 31 schematically showing the configuration of the semiconductor device according to the second embodiment. FIG. 28 is a cross-sectional view taken along the line X1-X1 ′ of FIGS. 26 and 27, schematically illustrating the configuration of the semiconductor device according to the second embodiment. FIG. 29 is a cross-sectional view taken along the line X2-X2 ′ in FIGS. 26 and 27, schematically illustrating the configuration of the semiconductor device according to the second embodiment. 30 is a cross-sectional view taken along the line X3-X3 ′ of FIGS. 26 and 27, schematically showing the configuration of the semiconductor device according to the second embodiment. FIG. 31 is a plan view schematically showing the configuration of the semiconductor device according to the second embodiment.

  In the second embodiment, the configuration of the first embodiment is applied to the N-type transistor region 33 of the sub-word driver unit 32a in the peripheral circuit unit 32 of the semiconductor device 1 serving as a DRAM chip. FIG. 26 is a plan view showing part of the memory cell portion 35 and the sub word driver portion 32a up to the layer where the capacitor 84 is formed. FIG. 27 is a plan view showing the layers up to the layer where the peripheral contact plugs 50, 51, 52, 56, 57, and 58 are formed in the pre-process stage of the capacitor 84 in the same region as FIG. FIG. 31 is a schematic diagram of the entire semiconductor device 1 serving as a DRAM chip, and a region R surrounded by a thick line corresponds to the region shown in FIGS. 26 and 27. The first embodiment is applied to the portion where the U-shaped first N-type peripheral gate wiring 39 under the solid line X1-X1 ′ in FIGS. 26 and 27 is applied, and the basic configuration is the first embodiment. It is the same. FIG. 28 shows a cross section formed up to the multilayer wiring layer 99 between X1 and X1 ′ in FIGS. For comparison, FIG. 29 shows a cross section between X2 and X2 ′ of the memory cell portion 35 of FIGS. 26 and 27, and the portion where the first embodiment is not applied in the N-type transistor region 33 of FIGS. FIG. 30 shows a cross section between X3 and X3 ′.

  The semiconductor device 1 includes a memory cell unit 35 and a peripheral circuit unit 32 (see FIG. 31). The memory cell portion 35 is a portion having a plurality of memory cells (not shown) arranged in a matrix. The peripheral circuit unit 32 is a circuit unit disposed around the memory cell unit 35. The peripheral circuit unit 32 includes a sub-word driver unit 32a, a sense amplifier unit 32b, and a cross unit 32c. The sub-word driver unit 32a is a circuit unit that drives the potential of the word line (48 in FIGS. 26 and 27). The sub word driver unit 32a is disposed on both sides of the memory cell unit 35 in the Y direction. The sense amplifier unit 32b is a circuit unit that amplifies the potential of data read from a memory cell (not shown) via a bit line (59 in FIGS. 26 and 27). The sense amplifier unit 32b is disposed on both sides of the memory cell unit 35 in the X direction. The cross unit 32c is a circuit unit that relays a control signal from a control circuit (not shown) to the sub word driver unit 32a and the sense amplifier unit 32b. The cross part 32c is arranged at the intersection of the sub word driver part 32a and the sense amplifier part 32b. The sense amplifier section 32b has an N-type transistor region 33 and a P-type transistor region 34 (see FIGS. 26 and 27).

  In the N-type transistor region 33, a first N-type peripheral gate wiring 39 is formed on the first active region 41 via an insulating film (not shown) (see FIGS. 26 and 27). In the N-type transistor region 33, the common source in the first active region 41 is electrically connected to the W (tungsten) wiring 66 through the peripheral contact plug 51, and the drain is connected to the W wiring 37 through the peripheral contact plug 51. And are electrically connected. In the N-type transistor region 33, the first N-type peripheral gate wiring 39 is connected to the first P-type peripheral gate wiring 38. In the N-type transistor region 33, a second N-type peripheral gate wiring 40 is formed on the third active region 43 via an insulating film (not shown). In the N-type transistor region 33, the common source in the third active region 43 is electrically connected to the W wiring 66 through the peripheral contact plug 52, and the drain is electrically connected to the W wiring 37 through the peripheral contact plug 52. It is connected to the. In the N-type transistor region 33, the second N-type peripheral gate wiring 40 is electrically connected to the W wiring 67 through the peripheral contact plug 57.

  In the P-type transistor region 34, a first P-type peripheral gate wiring 38 is formed on the fourth active region 44 via an insulating film (not shown) (see FIGS. 26 and 27). In the P-type transistor region 34, one of the source / drain in the fourth active region 44 is electrically connected to the W wiring 37 via the peripheral contact plug 50, and the other is connected to the W wiring 64 via the peripheral contact plug 50. And are electrically connected. In the P-type transistor region 34, the first P-type peripheral gate wiring 38 is electrically connected to the W wiring 65 via the peripheral contact plug 56.

  In the memory cell portion 35, a word line 48 is formed on the second active region 42 via an insulating film (not shown) (see FIGS. 26 and 27). In the memory cell unit 35, the common source in the second active region 42 is electrically connected to the bit line 59 and the drain is electrically connected to the capacitor 84. In the memory cell portion 35, the first P-type peripheral gate wiring 38 is electrically connected to the W wiring 65 via the peripheral contact plug 58.

  Under the solid line between X1 and X1 ′ in the N-type transistor region 33 of FIG. 26 and FIG. 27, it is as shown in FIG. 28, and details are as follows.

  An element isolation region 11 is embedded in an element isolation groove 10a formed in a semiconductor substrate 10 (for example, a silicon substrate). The element isolation region 11 has an STI structure. The element isolation region 11 includes a buried insulating film 11b (for example, silicon oxide film) through a liner insulating film 11a (for example, silicon nitride film) formed along the bottom surface or wall surface of the element isolation groove 10a in the element isolation groove 10a. (Film) is embedded. A portion of the semiconductor substrate 10 in a region surrounded by the element isolation region 11 becomes a first active region 41. In the semiconductor substrate 10, a well (not shown) into which a P-type impurity is implanted in the first active region 41 is formed.

  On the first active region 41, a first N-type peripheral gate wiring 39 is formed through a gate insulating film (not shown; for example, a silicon oxide film). The first N-type peripheral gate wiring 39 extends in the Y direction and is formed so as to cross over the first active region 41. Two first N-type peripheral gate wirings 39 are provided on one first active region 41, are arranged in parallel, and are not connected to each other. The first N-type peripheral gate wiring 39 includes, from below, a first DOPOS film 13a (doped polysilicon film), a second DOPOS film 13b (doped polysilicon film), and a conductive laminated film 13c (for example, WSi / TiN / Ti film: tungsten silicide / Titanium nitride / titanium film), W film 13d (tungsten film), and mask nitride film 13e (for example, silicon nitride film) are stacked in this order. The mask nitride film 13e has a recess 18a in which corner portions on the side where the upper two first N-type peripheral gate wirings 39 face each other are recessed by etching. Sidewall films 21a are formed on both sides of the side wall of the first N-type peripheral gate wiring 39 with an offset nitride film 15 (for example, silicon nitride film) and an offset oxide film 16 (for example, silicon oxide film) interposed therebetween. The offset nitride film 15 and the offset oxide film 16 are interposed between the first active region 41 and the side wall film 21a on the side opposite to the side where the two first N-type peripheral gate wirings 39 face each other. ing. On the other hand, there is a portion where the offset nitride film 15 and the offset oxide film 16 are not interposed between the side wall film 21a on the side where the two gate wirings face each other and the first active region 41.

  In the first active region 41, N-type high-concentration impurity diffusion layers 22a and 22b serving as drains are formed in regions opposite to the side where the two first N-type peripheral gate wirings 39 face each other. Further, in the first active region 41, two N-type transistors 2 are provided in a region where two first N-type peripheral gate wirings 39 face each other (between the two first N-type peripheral gate wirings 39). Thus, an N-type high concentration impurity diffusion layer 22c serving as a common source used in common is formed.

  In the first active region 41, P-type low-concentration impurity diffusion layers 20a and 20b connected to the N-type high-concentration impurity diffusion layers 22a and 22b are formed in the vicinity immediately below the sidewall film 21a. The P-type low-concentration impurity diffusion layers 20a and 20b are formed shallower than the N-type high-concentration impurity diffusion layers 22a and 22b. In the first active region 41, an N-type low-concentration impurity diffusion layer 19a connected to the N-type high-concentration impurity diffusion layer 22c is formed in the vicinity immediately below the sidewall film 21a. That is, the N-type high concentration impurity diffusion layer 22c is formed so as to penetrate the N-type low concentration impurity diffusion layer 19a. The N-type low concentration impurity diffusion layer 19a is formed shallower than the N-type high concentration impurity diffusion layer 22c. Further, in the first active region 41, a P-type asymmetric injection layer 20c is formed so as to cover the lower surface or side wall of the N-type low concentration impurity diffusion layer 19a. The P-type asymmetric implantation layer 20c covers at least the side wall of the N-type high concentration impurity diffusion layer 22c (excluding the portion in contact with the N-type low concentration impurity diffusion layer 19a). The N-type low concentration impurity diffusion layer 19a has a lower N-type impurity concentration than the N-type high concentration impurity diffusion layer 22c. The impurity concentrations of the P-type low-concentration impurity diffusion layers 20 a and 20 b and the P-type asymmetric injection layer 20 c are higher than the concentration of P-type impurities in a well (not shown) in the semiconductor substrate 10. The P-type low-concentration impurity diffusion layers 20a and 20b are shallower than the P-type asymmetric implantation layer 20c, and the P-type impurity concentration is lower than that of the P-type asymmetric implantation layer 20c.

  One (the right side of FIG. 28) first N-type peripheral gate wiring 39, N-type high-concentration impurity diffusion layer 22c, and N-type high-concentration impurity diffusion layer 22a constitute the N-type transistor 2, and the other (FIG. 28). The first N-type peripheral gate wiring 39, the N-type high concentration impurity diffusion layer 22c, and the N-type high concentration impurity diffusion layer 22b on the left side constitute the N-type transistor 3.

  An interlayer insulating film 24 (for example, a silicon oxide film) is formed on the N-type transistors 2 and 3, the sidewall film 21 a and the element isolation region 11 via a liner nitride film 23 (for example, a silicon nitride film). . The upper surface of the interlayer insulating film 24 is planarized so as to be flush with the uppermost surface of the liner nitride film 23. In the interlayer insulating film 24 and the liner nitride film 23, an opening 25 is formed that communicates with the N-type high concentration impurity diffusion layers 22a, 22b, and 22c. Silicide layers 26a, 26b and 26c are formed in the portions of the N-type high concentration impurity diffusion layers 22a, 22b and 22c facing the opening 25. A peripheral contact plug 51 is formed in the opening 25. The peripheral contact plug 51 is formed with a plug portion 54a (for example, W film: tungsten film) through a barrier film 53a (for example, TiN film: titanium nitride film) formed along the bottom surface or side wall of the opening 25. ing.

  W (tungsten) wiring 37 and W wiring 66 are formed at predetermined positions on the interlayer insulating film 24 including the peripheral contact plug 51. The W wiring 37 is a wiring electrically connected to the N-type high-concentration impurity diffusion layers 22 a and 22 b serving as drains via the peripheral contact plug 51, and is a predetermined on the interlayer insulating film 24 including the peripheral contact plug 51. A W film 37b (tungsten film) is formed at a position via a WN film 37a (tungsten nitride film). The W wiring 66 is a wiring electrically connected to the N-type high-concentration impurity diffusion layer 22 c serving as a common source via the peripheral contact plug 51, and a predetermined position on the interlayer insulating film 24 including the peripheral contact plug 51. The W film 66b is formed through the WN film 66a.

  An interlayer insulating film 61 (for example, a silicon oxide film) is formed on the entire surface of the interlayer insulating film 24 including the W wirings 37 and 66 through a stopper nitride film 60 (for example, a silicon nitride film). A pilot hole 62 communicating with the W wiring 66 is formed in the interlayer insulating film 61 and the stopper nitride film 60, and a via plug 63 is formed in the pilot hole 62. The via plug 63 has a structure in which a W film 63 b is embedded in a pilot hole 62 via a TiN film 63 a formed along the bottom surface or wall surface of the pilot hole 62.

  A first wiring 93 (for example, copper) is formed at a predetermined position on the interlayer insulating film 61 including the via plug 63. An interlayer insulating film 94 (for example, a silicon oxide film) is formed on the entire surface of the interlayer insulating film 61 including the first wiring 93. A second wiring 95 (for example, copper) is formed at a predetermined position on the interlayer insulating film 94. An interlayer insulating film 96 (for example, a silicon oxide film) is formed on the entire surface of the interlayer insulating film 94 including the second wiring 95. A third wiring 97 (for example, copper) is formed at a predetermined position on the interlayer insulating film 96. An interlayer insulating film 98 (for example, a silicon oxide film) is formed on the entire surface of the interlayer insulating film 96 including the third wiring 97. The wirings 93, 95, 97 and the interlayer insulating films 94, 96, 98 constitute a multilayer wiring layer 99.

  In the N-type transistor region 33 of FIGS. 26 and 27, the solid line between X2 and X2 ′ is as shown in FIG. 29, and details are as follows.

  An element isolation region 11 is embedded in an element isolation groove 10a formed in a semiconductor substrate 10 (for example, a silicon substrate). The element isolation region 11 has an STI structure. The element isolation region 11 includes a buried insulating film 11b (for example, silicon oxide film) through a liner insulating film 11a (for example, silicon nitride film) formed along the bottom surface or wall surface of the element isolation groove 10a in the element isolation groove 10a. Membrane) is embedded. A portion of the semiconductor substrate 10 in a region surrounded by the element isolation region 11 becomes a second active region 42. In the semiconductor substrate 10, a well (not shown) in which a P-type impurity is implanted in the second active region 42 is formed. A mask oxide film 76 (for example, a silicon oxide film) is formed on the semiconductor substrate 10 including the element isolation region 11.

  In the mask oxide film 76 and the semiconductor substrate 10, two trenches 70 for embedding the word lines 48 are formed. The trench 70 extends in the Y direction and is formed so as to cross over the second active region 42. A word line 48 is buried under the trench 70 through an insulating film 72. The insulating film 72 is formed along the bottom surface or side wall of the trench 70. The word line 48 has a structure in which a W film 48b (tungsten film) is embedded through a TiN film 48a (titanium nitride film) formed along the insulating film 72. A cap insulating film 73 (for example, a silicon nitride film) is buried above the trench 70 on the word line 48. An interlayer insulating film 77 (for example, a silicon oxide film) is formed on the mask oxide film 76 including the cap insulating film 73.

  In the interlayer insulating film 77 and the mask oxide film 76, an opening 71 is formed which communicates with the semiconductor substrate 10 in a portion serving as a common source. A bit N-type high-concentration impurity diffusion layer 75 into which an N-type impurity for electrical connection to the bit line 59 is implanted is formed in the semiconductor substrate 1 that appears from the opening 71. The bit N type high concentration impurity diffusion layer 75 serves as a common source for the buried transistors 4 and 5. A bit line 59 is formed on the bit N-type high concentration impurity diffusion layer 75. The bit line 59 is not in contact with the wall surface of the opening 71. The bit line 59 includes, from the bottom, a second DOPOS film 13b (doped polysilicon film), a conductive laminated film 13c (for example, WSi / TiN / Ti film: tungsten silicide / titanium nitride / titanium film), a W film 13d (tungsten film), The mask nitride films 13e (for example, silicon nitride films) are stacked in this order. On the interlayer insulating film 77 including the bit line 59 and the opening 71, the interlayer insulating film 24 (for example, the silicon nitride film) and the liner nitride film 23 (for example, the silicon nitride film) are interposed via the offset nitride film 15 (for example, the silicon nitride film). A silicon oxide film) is formed. The offset nitride film 15 is buried in the gap between the bit line 59 and the opening 71. The upper surface of the interlayer insulating film 24 is flush with the upper surface of the liner nitride film 23.

  In the interlayer insulating film 24, the offset oxide film 16, the offset nitride film 15, the interlayer insulating film 77, and the mask oxide film 76, an opening 78 that communicates with the semiconductor substrate 10 in a portion that becomes a drain is formed. In the semiconductor substrate 1 that appears from the opening 78, a capacitor N-type high-concentration impurity diffusion layer 74 into which N-type impurities for electrical connection to the capacitor contact plug 80 are implanted is formed. The capacitor N type high concentration impurity diffusion layer 74 serves as the drain of the buried transistors 4 and 5. A capacitance contact plug 80 is formed in the opening 78 via a liner insulating film 79 (for example, a silicon nitride film) formed on the side wall surface of the opening 78. The capacitor contact plug 80 has a DOPOS film 81 connected to the capacitor N-type high concentration impurity diffusion layer 74, and a silicide layer 26f is formed on the DOPOS film 81 (doped polysilicon film). The capacitor contact plug 80 has a plug portion 54b (for example, W film: via a barrier film 53b (for example, TiN film: titanium nitride film)) formed on the silicide layer 26f in the opening 78 along the wall surface or bottom surface. Tungsten film) is formed.

  On the interlayer insulating film 24, an interlayer insulating film 82 (for example, silicon oxide film) is formed via a stopper nitride film 60 (for example, silicon nitride film). An opening 83 communicating with the capacitor contact plug 80 is formed in the interlayer insulating film 82 and the stopper nitride film 60. In the opening 83, a lower electrode 85 formed along the bottom surface or the side wall of the opening 83 is formed. An upper electrode 87 is formed at a predetermined position on the interlayer insulating film 82 including the lower electrode 85 via a capacitive insulating film 86 formed along the surfaces of the lower electrode 85 and the interlayer insulating film 82. The upper electrode 87 is filled in the opening 83. The lower electrode 85, the capacitor insulating film 86, and the upper electrode 87 become the capacitor 84. An interlayer insulating film 88 (for example, a silicon oxide film) is formed on the interlayer insulating film 82 including the capacitor 84. A plate nitride film 91 (for example, a silicon nitride film) is formed at a predetermined position on the interlayer insulating film 88 via the plate electrode 90. An interlayer insulating film 92 (for example, silicon oxide film) is formed on the interlayer insulating film 88 including the plate electrode 90 and the plate nitride film 91.

  A first wiring 93 (for example, copper) is formed at a predetermined position on the interlayer insulating film 92. An interlayer insulating film 94 (for example, a silicon oxide film) is formed on the entire surface of the interlayer insulating film 92 including the first wiring 93. A second wiring 95 (for example, copper) is formed at a predetermined position on the interlayer insulating film 94. An interlayer insulating film 96 (for example, a silicon oxide film) is formed on the entire surface of the interlayer insulating film 94 including the second wiring 95. A third wiring 97 (for example, copper) is formed at a predetermined position on the interlayer insulating film 96. An interlayer insulating film 98 (for example, a silicon oxide film) is formed on the entire surface of the interlayer insulating film 96 including the third wiring 97. The wirings 93, 95, 97 and the interlayer insulating films 94, 96, 98 constitute a multilayer wiring layer 99.

  In the N-type transistor region 33 of FIGS. 26 and 27, the solid line between X3 and X3 ′ is as shown in FIG. 30, and the details are as follows.

  An element isolation region 11 is embedded in an element isolation groove 10a formed in a semiconductor substrate 10 (for example, a silicon substrate). The element isolation region 11 has an STI structure. The element isolation region 11 includes a buried insulating film 11b (for example, silicon oxide film) through a liner insulating film 11a (for example, silicon nitride film) formed along the bottom surface or wall surface of the element isolation groove 10a in the element isolation groove 10a. (Film) is embedded. A portion of the semiconductor substrate 10 in a region surrounded by the element isolation region 11 becomes a third active region 43. In the semiconductor substrate 10, a well (not shown) in which a P-type impurity is implanted in the third active region 43 is formed.

  A second N-type peripheral gate wiring 40 is formed on the third active region 43 via a gate insulating film (not shown; for example, a silicon oxide film). The second N-type peripheral gate wiring 40 is formed to extend in the X direction and cross over the third active region 43. Two second N-type peripheral gate wirings 40 are provided on one third active region 43, are arranged in parallel, and are not connected to each other. The second N-type peripheral gate wiring 40 includes, from below, a first DOPOS film 13a (doped polysilicon film), a second DOPOS film 13b (doped polysilicon film), and a conductive laminated film 13c (for example, WSi / TiN / Ti film: tungsten silicide / Titanium nitride / titanium film), W film 13d (tungsten film), and mask nitride film 13e (for example, silicon nitride film) are stacked in this order. Sidewall films 21 a are formed on both sides of the sidewall of the second N-type peripheral gate wiring 40 via an offset nitride film 15 (for example, a silicon nitride film) and an offset oxide film 16 (for example, a silicon oxide film).

  In the third active region 43, N-type high-concentration impurity diffusion layers 22d and 22e serving as drains are formed in regions opposite to the side where the two second N-type peripheral gate lines 40 face each other. The third active region 43 includes two N-type transistors 2 in a region on the side where the two second N-type peripheral gate wires 40 face each other (between the two second N-type peripheral gate wires 40). Thus, an N-type high-concentration impurity diffusion layer 22f is formed as a common source used in common.

  In the third active region 43, N-type low-concentration impurity diffusion layers 19b and 19c connected to the N-type high-concentration impurity diffusion layers 22d and 22e are formed in the vicinity immediately below the sidewall film 21a. The N-type low concentration impurity diffusion layers 19b and 19c are formed shallower than the N-type high concentration impurity diffusion layers 22a and 22b, and the concentration of the N-type impurities is low. In the third active region 43, an N-type low-concentration impurity diffusion layer 19d connected to the N-type high-concentration impurity diffusion layer 22f is formed in the vicinity immediately below the sidewall film 21a. That is, the N-type high concentration impurity diffusion layer 22f is formed so as to penetrate the N-type low concentration impurity diffusion layer 19d. The N-type low concentration impurity diffusion layer 19d is formed shallower than the N-type high concentration impurity diffusion layer 22f. The N-type low concentration impurity diffusion layer 19d has a lower N-type impurity concentration than the N-type high concentration impurity diffusion layer 22f.

  One (the right side of FIG. 30) second N-type peripheral gate wiring 40, N-type high-concentration impurity diffusion layer 22d, and N-type high-concentration impurity diffusion layer 22f constitute N-type transistor 6 and the other (FIG. 30). The second N-type peripheral gate wiring 40, the N-type high concentration impurity diffusion layer 22e, and the N-type high concentration impurity diffusion layer 22f on the left side constitute the N-type transistor 7.

  On the N-type transistors 6 and 7, the sidewall film 21 a and the element isolation region 11, an interlayer insulating film 24 (for example, a silicon oxide film) is formed via a liner nitride film 23 (for example, a silicon nitride film). . The upper surface of the interlayer insulating film 24 is planarized so as to be flush with the uppermost surface of the liner nitride film 23. In the interlayer insulating film 24 and the liner nitride film 23, openings 49 are formed which communicate with the N-type high concentration impurity diffusion layers 22d and 22e. Silicide layers 26d and 26e are formed in the portions of the N-type high concentration impurity diffusion layers 22d and 22e facing the opening 49. A peripheral contact plug 52 is formed in the opening 49. The peripheral contact plug 52 is formed with a plug portion 54c (for example, W film: tungsten film) through a barrier film 53c (for example, TiN film: titanium nitride film) formed along the bottom surface or side wall of the opening 49. ing.

  A W (tungsten) wiring 37 is formed at a predetermined position on the interlayer insulating film 24 including the peripheral contact plug 52. The W wiring 37 is a wiring electrically connected to the N-type high-concentration impurity diffusion layers 22 d and 22 e serving as the drain through the peripheral contact plug 52, and is a predetermined wiring on the interlayer insulating film 24 including the peripheral contact plug 52. A W film 37b (tungsten film) is formed at a position via a WN film 37a (tungsten nitride film). An interlayer insulating film 61 (for example, a silicon oxide film) is formed on the entire surface of the interlayer insulating film 24 including the W wiring 37 via a stopper nitride film 60 (for example, a silicon nitride film).

  A first wiring 93 (for example, copper) is formed at a predetermined position on the interlayer insulating film 61 including the via plug 63. An interlayer insulating film 94 (for example, a silicon oxide film) is formed on the entire surface of the interlayer insulating film 61 including the first wiring 93. A second wiring 95 (for example, copper) is formed at a predetermined position on the interlayer insulating film 94. An interlayer insulating film 96 (for example, a silicon oxide film) is formed on the entire surface of the interlayer insulating film 94 including the second wiring 95. A third wiring 97 (for example, copper) is formed at a predetermined position on the interlayer insulating film 96. An interlayer insulating film 98 (for example, a silicon oxide film) is formed on the entire surface of the interlayer insulating film 96 including the third wiring 97. The wirings 93, 95, 97 and the interlayer insulating films 94, 96, 98 constitute a multilayer wiring layer 99.

  Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to the drawings. 32 to 50 schematically show the method of manufacturing the semiconductor device according to the second embodiment, and are (a) between X1 and X1 ′, (b) between X2 and X2 ′, and (c) in FIGS. It is sectional drawing corresponded between X3-X3 '.

  First, an element isolation trench 10a having a predetermined depth (for example, about 300 nm) is formed on a semiconductor substrate 10 (for example, a silicon substrate) (step C1; see FIG. 32). Thereby, the active regions 41, 42 and 43 are defined. Here, the active region corresponding to the first N-type peripheral gate wiring 39 of the sub-word driver section 32a is defined as the first active region 41 (see FIG. 32A), and the active region corresponding to the second N-type peripheral gate wiring 40 is defined as the first active region 41. Three active regions 43 (see FIG. 32C) are used, and one corresponding to one of the active regions in the memory cell portion 35 is a second active region 42 (see FIG. 32B).

  Next, a liner insulating film 11a (for example, a silicon nitride film) is formed on the semiconductor substrate 10 along the side wall or the bottom surface of the element isolation groove 10a, and the inside of the element isolation groove 10a is further formed on the liner insulating film 11a. A buried insulating film 11b (for example, a silicon oxide film) is deposited by using a technique such as SOD (Spin On Dielectrics) method or flowable CVD (Flowable Chemical Vapor Deposition) method so as to be buried (step C2; see FIG. 32). ).

  Next, the extra buried insulating film 11b and liner insulating film are formed by CMP (Chemical Mechanical Polishing) so that the upper surface of the semiconductor substrate 10 and the upper surfaces of the buried insulating film 11b and liner insulating film 11a are flush with each other. The element isolation region 11 having the STI structure is formed by polishing 11a (step C3; see FIG. 32).

  Next, by using a lithography technique and an ion implantation technique, a P-type impurity is implanted from a direction perpendicular to the surface of the semiconductor substrate 10 in the active regions 41, 42, 43 to form a P well (not shown). Then, an N well (not shown) is formed by implanting N-type impurities from a direction perpendicular to the surface of the semiconductor substrate 10 in the fourth active region 44 (step C4; see FIGS. 32 and 27).

  Next, a mask oxide film 76 (for example, a silicon oxide film) is formed on the entire surface of the semiconductor substrate 10 including the element isolation region 11 in the memory cell portion (35 in FIG. 27) by a known method, and then mask oxidation is performed. A word 70 in which a trench 70 for the word line 48 is formed in the film 76 and the semiconductor substrate 10, and then a TiN film 48a and a W film 48b are formed below the trench 70 via an insulating film 72 (for example, a silicon oxide film). A line 48 is formed, and then a cap insulating film 73 (for example, a silicon nitride film) is embedded on the word line 48 in the trench 70, and then an interlayer insulating film 77 (for example, on the mask oxide film 76 including the cap insulating film 73). , A silicon oxide film) is formed, and thereafter an opening 71 is formed to communicate with the semiconductor substrate 10 in a portion serving as a common source, and then the opening 71 The semiconductor substrate 10 et appearing forming bit N-type high concentration impurity diffusion layer 75 (step C5; see FIG. 32). As a result, the second active region 42 is further divided into three regions by the two word lines 48.

  Next, a gate insulating film (not shown) is formed on the first active region 41 and the third active region 43, and then a first DOPOS film 13a (doped polysilicon film) is formed on the gate insulating film, Thereafter, the second DOPOS film 13b is formed on the first DOPOS film 13a in the first active region 41 and the third active region 43, and on the interlayer insulating film 77 and the bit N-type high concentration impurity diffusion layer 75 in the second active region 42, respectively. (Doped polysilicon film), conductive laminated film 13c (for example, WSi / TiN / Ti film: tungsten silicide / titanium nitride / titanium film), W film 13d (tungsten film), mask nitride film 13e (for example, silicon nitride film) Are formed in this order (step C6; see FIG. 32). The impurity doping amounts of the first DOPOS film and the second DOPOS film are different, but may be the same.

  Next, a resist film (not shown) is formed on the mask nitride film 13e, and then the gate pattern of the resist film is transferred to the mask nitride film 13e, and then the first pattern is formed using the mask nitride film 13e as a mask. In the active region 41 and the third active region 43, the W film 13d to the first DOPOS film 13a are etched, and in the second active region 42, the W film 13d to the second DOPOS film 13b are etched (step C7; see FIG. 32). As a result, a pair of first N-type peripheral gate lines 39 crossing over the first active region 41, a pair of second N-type peripheral gate lines 40 crossing over the third active region 43, and the second active region 42 are observed. Crossing bit lines 59 are formed. In step C7, the first P-type peripheral gate wiring 38 shown in FIG. 27 is also formed simultaneously with the same material configuration as the first N-type peripheral gate wiring 39 in the sub-word driver section 32a (see FIG. 27).

  Here, in the first N-type peripheral gate wiring 39 and the second N-type peripheral gate wiring 40, the height from the outermost surface of the corresponding active regions 41 and 43 can be about 270 nm. Further, the L / S width of the first N-type peripheral gate wiring 39 can be set to 22 nm / 25 nm, for example. The L / S width of the second N-type peripheral gate wiring 40 can be set to, for example, 20 nm / 30 nm.

  Next, an offset nitride film 15 (silicon nitride film) is formed on the entire surface of the semiconductor substrate 10 so as to cover the first N-type peripheral gate wiring 39, the second N-type peripheral gate wiring 40, and the bit line 59 (for example, 5 nm), and an offset oxide film 16 (silicon oxide film) is formed in this order (for example, 5 nm) (step C8; see FIG. 33). Here, a laminated film of the offset nitride film 15 and the offset oxide film 16 is formed, but it may be a single layer of an offset nitride film or an offset oxide film. In consideration of ion implantation, it is convenient to use an offset nitride film having poor ion implantation permeability as a single layer.

  Next, a resist film 17 is applied on the offset oxide film 16 with a predetermined thickness (for example, 370 nm from the lowest surface on the upper surface of the offset oxide film 16) (step C9; see FIG. 34). Here, for example, a KrF resist can be used as the resist film 17, but an i-line resist or an ArF resist may be used as long as a target film thickness and an opening diameter after development can be achieved.

  Next, exposure is performed between the two first N-type peripheral gate wirings 39 on the second active region 42 and the entire region of the third active region 43 using a reticle and developed (step C10; FIG. 35). reference). As a result, the resist film 17 between the two first N-type peripheral gate wirings 39, the upper part thereof, and the entire region of the third active region 43 is removed, and the resist film 17 is opened as shown in FIG. A portion 17a is formed. Although not shown, the resist film 17 in the entire area of the fourth active region (44 in FIG. 27) is also removed.

  Next, using the resist film 17 as a mask, the offset nitride film 15 and the offset oxide film 16 are selectively etched back by anisotropic dry etching (step C11; see FIG. 36).

  In Step C11, in the first active region 41, the upper surfaces of the two gate wirings 13 in addition to the offset nitride film 15 and the offset oxide film 16 positioned between the two first N-type peripheral gate wirings 39 in the opening 17a. The offset nitride film 15, the offset oxide film 16, and the mask nitride film 13e located at the corners are removed to form the recesses 18a and the openings 18b. The recessed portion 18a is slightly emphasized. The offset nitride film 15 and the offset oxide film 16 located on the side walls between the other first N-type peripheral gate wirings 39 can be left in a sidewall shape.

  In Step C11, since the third active region 43 is not covered with the resist film 17, the sidewall-like offset nitride film 15 and the offset oxide film 16 are formed only on the side wall portions on both sides of the second N-type peripheral gate wiring 40. Can leave. Although not shown in the figure, the fourth active region (44 in FIG. 27) is not covered with the resist film 17, so that it is offset only on the side walls on both sides of the first P-type peripheral gate wiring (38 in FIG. 27). The nitride film 15 and the offset oxide film 16 can be left.

In the dry etching in step C11, CF ₄ and _C 2 _{F 4 C} x _{F y} type, such as using mainly (fluorocarbon) gas, suppressed as much as possible as the etching rate of the semiconductor substrate 10 (silicon) Adjust to.

  Next, the resist film (17 in FIG. 36) is removed (step C12; see FIG. 37).

Next, a resist film (not shown) is formed all over the fourth active region (44 in FIG. 27) and the memory cell portion 35, and then the opening 18b using the offset nitride film 15 and the offset oxide film 16 as a mask. N-type low concentration impurity diffusion layers 19a, 19b, 19c and 19d are formed by ion-implanting N-type impurities (for example, phosphorus) into the first active region 41 and the third active region 43 exposed from (Step C13; see FIG. 38). The ion implantation conditions at this time can be, for example, E (implantation energy) = 4.0 kev, φ (dose amount) = 1.0 × 10 ¹⁴ atoms / cm ^2, and the N-type low-concentration impurity diffusion layer 19a , 19b, 19c, 19d reach 8.5 nm.

  Next, the resist film (not shown) on the fourth active region (44 in FIG. 27) and the memory cell portion 35 is removed (step C14).

  Next, a region other than the fourth active region (44 in FIG. 27) is covered with a resist film (not shown), and then a P-type impurity (for example, boron) is ion-implanted into the fourth active region 44. A P-type low concentration impurity diffusion layer (not shown) is formed (step C15).

  Next, the resist film (not shown) on the region other than the fourth active region (44 in FIG. 27) is removed (step C16).

  Next, a region other than the first active region 41 is covered with a resist film 46, and then a P-type impurity (for example, boron) is applied to the upper surface of the semiconductor substrate 10 at an angle within a predetermined range (for example, 17 degrees). ) Is implanted into the semiconductor substrate 10 to form a P-type asymmetric implantation layer 20c in the first active region 41 so as to cover the lower surface or side surface of the N-type low-concentration impurity diffusion layer 19a (step C17; FIG. 39).

  Here, the angle of the predetermined range in step C17 is not fixed, but is a range for timely adjustment. For example, there is no problem even if it is 20 degrees. In addition, P-type low-concentration impurity diffusion layers 20a and 20b having a depth smaller than that of the P-type asymmetric implantation layer 20c are also formed in the first active region 41 in the region corresponding to the drain other than the region exposed from the opening 18b. The

  Note that the P-type low-concentration impurity diffusion layers 20a and 20b are not essential. The P-type low-concentration impurity diffusion layers 20a and 20b have no adverse effect on the N-type transistors 2 and 3 because the offset nitride film 15 and the offset oxide film 16 serve as a mask and the concentration of P-type impurities is considerably suppressed. Furthermore, there is no particular problem even if the offset nitride film 15 and the offset oxide film 16 are thick and cannot transmit P-type impurities and the P-type low-concentration impurity diffusion layers 20a and 20b cannot be formed.

The ion implantation conditions in step C17 can be, for example, E (implantation energy) = 10.0 kev and φ (dose amount) = 4.2 × 10 ¹³ atoms / cm ² . In this case, the implantation depth in the first active region 41 serving as a common source between the two first N-type peripheral gate wirings 39 is 33.0 nm, and the drains of the two first N-type peripheral gate wirings 39 The implantation depth in the first active region 41 reaches 15 nm.

  Next, an LDD insulating film 21 is formed so as to cover the entire surface of the semiconductor substrate 10 (step C18; see FIG. 40). Here, the LDD insulating film 21 can be formed using, for example, a vertical LPCVD furnace. The film thickness of the LDD insulating film 21 can be set to 60 nm, for example.

  Next, a region other than the memole cell portion (35 in FIG. 27) is covered with a resist film 47 (step C19; see FIG. 41).

  Next, the LDD insulating film 21 and the offset oxide film 16 formed in the memory cell portion (35 in FIG. 27) are removed, and then the resist film (47 in FIG. 41) is removed (step C20; see FIG. 42). . Here, in the removal of the LDD insulating film 21 and the offset oxide film 16, for example, a hydrofluoric acid-based chemical solution can be used using the resist film (47 in FIG. 41) as a mask.

  Next, a resist film (not shown) is formed on the memory cell portion 35, and the LDD insulating film 21, the offset nitride film 15, and the offset oxide film 16 are selectively etched back by anisotropic dry etching. The sidewall films 21a are formed on the sidewalls on both sides of each of the first N-type peripheral gate wiring 39 and the second N-type peripheral gate wiring 40, and then the resist film (not shown) on the memory cell portion 35 is removed (see FIG. Step C21; see FIG. 43)

  Here, the offset nitride film 15 and the offset oxide film 16 are formed between the first active region 41 and the side wall film 21a on the side opposite to the side where the two first N-type peripheral gate lines 39 face each other. The offset nitride film 15 and the offset oxide film 16 are interposed between the side wall film 21a and the first active region 41 on the side where the two first N-type peripheral gate wirings 39 are opposed to each other. There are parts that do not intervene. An offset nitride film 15 and an offset oxide film 16 are interposed between the sidewall film 21 a on the both sides of the second N-type peripheral gate wiring 40 and the third active region 43. Although not shown, in the fourth active region (44 in FIG. 27), there is a gap between the sidewall film 21a on both sides of the first P-type peripheral gate wiring 38 and the fourth active region (44 in FIG. 27). An offset nitride film 15 and an offset oxide film 16 are interposed.

  Next, a resist film (not shown) is formed on the memory cell portion (35 in FIG. 27) and the P-type transistor region (34 in FIG. 27), and then N-type impurities (for example, phosphorus and arsenic) are ionized. By implantation, N-type high concentration impurity diffusion layers 22a to 22f are formed in the exposed portions of the first active region 41 and the third active region 43, and then the memory cell portion (35 in FIG. 27) and the P-type transistor region. The resist film (not shown) is removed on (34 in FIG. 27) (step C22; see FIG. 44).

Here, the ion implantation conditions in step C22 are, for example, that phosphorous of N-type impurities is E (implantation energy) = 15.0 kev, φ (dose amount) = 4.0 × 10 ¹³ atoms / cm ^2, and N-type. Among the impurities, arsenic can be E (implantation energy) = 18.0 kev and φ (dose amount) = 3.0 × 10 ¹⁵ atoms / cm ² . Moreover, the implantation depth in the active regions 41 and 43 serving as the common source and each drain can be 35.0 nm.

  Next, a resist film (not shown) is formed in a region other than the fourth active region (44 in FIG. 27), and then a P-type impurity (for example, boron or germanium) is ion-implanted, thereby A P-type high-concentration impurity diffusion layer (not shown) is formed in an exposed portion of the active region (44 in FIG. 27), and then a resist film (not shown) is formed in a region other than the fourth active region (44 in FIG. 27). ) Is removed (step C23).

Next, the impurity diffusion layers 19a to 19d, 20a, 20b, 22a to 22f and the P-type asymmetric implantation layer 20c are activated by applying a heat treatment at 980 ° C. in an N ₂ atmosphere (step C24; see FIG. 45). ).

  Next, a liner nitride film 23 (for example, a silicon nitride film) is formed so as to cover the entire surface of the semiconductor substrate 10. Here, the liner nitride film 23 can be formed, for example, in a vertical LPCVD furnace, and the film thickness can be 25 nm (step C25; see FIG. 45). Further, the liner nitride film 23 plays a role of preventing oxidation from extending to other than the interlayer insulating film (24 in FIG. 15) in the modification process (heat treatment) in the next step.

  Next, the interlayer insulating film 24 is formed on the entire surface of the semiconductor substrate 10 (step C26; see FIG. 46). Here, the interlayer insulating film 24 can be formed, for example, by applying an SOD film and modifying it into an oxide film by heat treatment (steam annealing).

  Next, the interlayer insulating film 24 is planarized by CMP until the upper surface of the liner nitride film 23 appears (step C27; see FIG. 47).

  Next, in the interlayer insulating film 24 and the liner nitride film, an opening 78 that leads to a portion that becomes the drain of the second active region 42 is formed using a well-known technique, and then the second active exposed from the opening 78 is formed. An N-type impurity (for example, phosphorus) is ion-implanted into the region 42 to form a capacitive N-type high-concentration impurity diffusion layer 74, and then a liner insulating film 79 is formed on the sidewall of the opening 78, and then the opening is opened. A DOPOS film 81 (doped polysilicon film) filled in the lower portion of the portion 78 is formed (step C28; see FIG. 48).

  Next, using well-known techniques, openings 25 and 49 that lead to the common source and drain portions in the sub word driver section (32a in FIG. 27), and the peripheral gate wirings 38, 39, An opening (not shown, see FIGS. 26 and 27) and an opening (not shown, see FIGS. 26 and 27) communicating with the word line 48 at the end of the memory cell portion 35 are formed. Thereafter, the portions exposed from the openings 25 and 49 (including openings not shown) (N-type high-concentration impurity diffusion layers 22a to 22f, etc.) and the DOPOS film 81 exposed from the openings 78 are respectively formed. Silicide layers 26a to 26f (including a silicide layer not shown, for example, CoSi) are formed (step C29; see FIG. 49).

  Next, using a well-known technique, the plug portions 54a to 54c are filled in the upper portions of the openings 25, 49 and 78 (including openings not shown) via the barrier films 53a to 53c, and then the sub word driver. W (tungsten) wiring 37 (W film 37b: tungsten film / WN film 37a: tungsten nitride film) connected to the plug parts 54a, 54b is formed at a predetermined position on the interlayer insulating film 24 in the part 32a (step). C30; see FIG. 50).

  Finally, a stopper nitride film 60, an interlayer insulating film 61, a via plug 63 (W film 63b (tungsten film) / TiN film 63a (titanium nitride film)), an interlayer insulating film 82, a capacitor 84 (upper electrode 87) by a known method. , Capacitive insulating film 86, lower electrode 85), interlayer insulating film 88, plate electrode 90, plate nitride film 91, interlayer insulating film 92, multilayer wiring layer 99 (first wiring 93, interlayer insulating film 94, second wiring 95, An interlayer insulating film 96, a third wiring 97, and an interlayer insulating film 98) are formed (step C31; see FIGS. 28 to 30).

(effect)
According to the second embodiment, as in the first embodiment, in the step of forming the P-type asymmetric injection layer 20c (step C17; see FIG. 39), the offset nitride film 15 and the offset oxide film that are thinner than the resist film are used as masks. 16 is used, the degree of freedom is widened in the implantation angle at the time of oblique ion implantation, the effect of oblique ion implantation can be fully exhibited, and the transistor performance can be improved. In addition, since the source and the common source have an asymmetric structure, the limitation on the resist film thickness when the resist film is formed can be eliminated. In addition, since the two first N-type peripheral gate wirings 39 have the recesses 18a in which the corners facing each other are recessed by etching, the degree of freedom of the implantation angle during oblique ion implantation can be further increased.

  In the second embodiment, the first embodiment is applied to the portion serving as a common source between the two first N-type peripheral gate lines 39 shown in FIGS. 26 and 27. However, the two second N-type peripheral gate lines 40 are used. It can also be applied to parts that are common sources.

  Moreover, although Embodiment 1, 2 has shown the example used for the N-type transistor (FIG. 1, 2, 3 of FIG. 28), it can be applied also to a P-type transistor, and it has been confirmed that the same effect is acquired. . Furthermore, the first and second embodiments are not limited to DRAMs, and can be applied to all devices.

(Appendix)
A method of manufacturing a semiconductor device according to a first aspect includes a step of forming an active region surrounded by an element isolation region on a semiconductor substrate, and a first gate adjacent to each other provided so as to cross the active region Forming a wiring and a second gate wiring; forming an offset film so as to cover the active region; the first gate wiring; and the second gate wiring; and the first gate wiring and the second gate wiring. Forming a resist film having an opening exposing a part of the offset film in a region between the gate wiring and etching the offset film exposed from the opening using the resist film as a mask; Removing the resist film, and implanting a first impurity into the active region using the offset film as a mask, thereby expanding the first impurity on the active region. A second impurity diffusion layer that covers a bottom surface or a side surface of the first impurity diffusion layer on the active region by injecting a second impurity into the active region using the offset film as a mask. Forming a sidewall film on the respective sidewalls of the first gate wiring and the second gate wiring via the offset film, the first gate wiring, the second gate wiring, and Forming a third impurity diffusion layer on the active region by injecting a third impurity into the active region using the sidewall film as a mask.

  In the method of manufacturing a semiconductor device, the first impurity diffusion layer is an N-type or P-type impurity diffusion layer, and the second impurity diffusion layer is an impurity diffusion having a conductivity type opposite to that of the first impurity diffusion layer. The third impurity diffusion layer may be an impurity diffusion layer having the same conductivity type as the first impurity diffusion layer.

  In the method of manufacturing the semiconductor device, in the step of forming the second impurity diffusion layer, the second impurity is implanted into the active region from a direction perpendicular to the upper surface of the active region. Can be injected.

  In the method for manufacturing a semiconductor device, the angle in the predetermined range may be not less than 17 degrees and not more than 20 degrees.

  In the method of manufacturing the semiconductor device, in the step of forming the second impurity diffusion layer, the active region covered with the offset film is implanted into the active region, thereby covering the active region covered with the offset film. A fourth impurity diffusion layer can be formed at a position on the region.

  In the method for manufacturing a semiconductor device, the fourth impurity diffusion layer is formed of the third impurity diffusion layer formed on the active region opposite to the side where the first gate wiring and the second gate wiring face each other. Can be connected to the layer.

  In the semiconductor device manufacturing method, the offset film may be an insulating film.

  In the semiconductor device manufacturing method, the offset film may be an insulating film including a silicon nitride film.

  In the semiconductor device manufacturing method, the sidewall film may be an insulating film.

  In the semiconductor device manufacturing method, the sidewall film may be a silicon oxide film.

  In the semiconductor device, a first impurity diffusion layer of a first conductivity type and a second conductivity type are formed on the active region on a side where the first gate wiring and the second gate wiring face each other. A second impurity diffusion layer covering a bottom surface or a side wall of the first impurity diffusion layer.

  In the semiconductor device, the first conductivity type may be a p-type or an n-type, and the second conductivity type may be a conductivity type opposite to the first conductivity type.

  In the semiconductor device, the first impurity diffusion layer has the first conductivity type on the active region on the side where the first gate wiring and the second gate wiring face each other and on the opposite side thereof. A third impurity diffusion layer penetrating through the first impurity diffusion layer.

  In the semiconductor device, the impurity concentration of the first impurity diffusion layer may be lower than the impurity concentration of the third impurity diffusion layer.

  In the semiconductor device, between the third impurity diffusion layer and the second impurity diffusion layer on the active region opposite to the side where the first gate wiring and the second gate wiring face each other, The first gate line and the second gate line are connected to the third impurity diffusion layer on the active region opposite to the opposite side, and a fourth impurity diffusion layer of the second conductivity type is formed. Can have.

  In the semiconductor device, the fourth impurity diffusion layer may be shallower than the second impurity diffusion layer.

  In the semiconductor device, a first impurity diffusion layer of a first conductivity type and a second conductivity type are formed on the active region on a side where the first gate wiring and the second gate wiring face each other. A second impurity diffusion layer covering a bottom surface or a side wall of the first impurity diffusion layer.

  In the semiconductor device, the first conductivity type may be a p-type or an n-type, and the second conductivity type may be a conductivity type opposite to the first conductivity type.

  It should be noted that the embodiments or examples can be changed or adjusted within the scope of the entire disclosure (including claims and drawings) of the present invention and based on the basic technical concept. In addition, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible within the scope of the entire disclosure of the present invention. It is. That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea. Further, regarding numerical values and numerical ranges described in the present application, it is considered that any intermediate value, lower numerical value, and small range are described even if not specified.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2, 3 N-type transistor 4, 5 Embedded transistor 6, 7 N-type transistor 10 Semiconductor substrate 10a Element isolation groove 11 Element isolation region 11a Liner insulating film 11b Embedded insulating film 12 Active region 13 Gate wiring 13a First 1 DOPOS film 13b Second DOPOS film 13c Conductive laminated film 13d W film 13e Mask nitride film 15 Offset nitride film (offset film)
16 Offset oxide film (offset film)
17 resist film 17a, 17b opening 18a recess 18b opening 19, 19a-19f N-type low concentration impurity diffusion layer (first impurity diffusion layer)
20a, 20b P-type low concentration impurity diffusion layer (fourth impurity diffusion layer)
20c P-type asymmetric injection layer (second impurity diffusion layer)
20d P-type asymmetric injection layer 21 LDD insulating film 21a Side wall film 22a, 22b, 22c N-type high concentration impurity diffusion layer (third impurity diffusion layer)
22d, 22e, 22f N-type high concentration impurity diffusion layer (third impurity diffusion layer)
23 liner nitride film 24 interlayer insulating film 25, 25a, 25b, 25c opening 26a, 26b, 26c, 26d, 26e, 26f silicide layer 27, 28, 29, 30, 31 contact plug 27a, 28a, 29a plug part 27b, 28b, 29b Pad part 27c, 28c, 29c Barrier film 32 Peripheral circuit part 32a Sub word driver part 32b Sense amplifier part 32c Cross part 33 N-type transistor area 34 P-type transistor area 35 Memory cell part 37 W wiring 37a WN film 37b W film 38 1st P-type peripheral gate wiring 39 1st N-type peripheral gate wiring 40 2nd N-type peripheral gate wiring 41 1st active region 42 2nd active region 43 3rd active region 44 4th active region 46, 47 Resist film 48 Word line 48a TiN film 48b W film 49 Opening 50, 51, 52 Peripheral contact plug 53a, 53b, 53c Barrier film 54a, 54b, 54c Plug 56, 57, 58 Peripheral contact plug 59 Bit line 60 Stopper nitride film 61 Interlayer insulating film 62 Pilot hole 63 Via plug 63a TiN Film 63b W film 64, 65, 66, 67 W wiring 66a WN film 66b W film 70 Trench 71 Opening 72 Insulating film 73 Cap insulating film 74 Capacitance N type high concentration impurity diffusion layer 75 Bit N type high concentration impurity diffusion layer 76 Mask oxide film 77 Interlayer insulating film 78 Opening 79 Liner insulating film 80 Capacitor contact plug 81 DOPOS film 82 Interlayer insulating film 83 Opening 84 Capacitor 85 Lower electrode 86 Capacitor insulating film 87 Upper electrode 88 Interlayer insulating film 90 Plate electrode 91 Plate nitriding Membrane 92 layers Insulating film 93 First wiring 94 Interlayer insulating film 95 Second wiring 96 Interlayer insulating film 97 Third wiring 98 Interlayer insulating film 99 Multilayer wiring layer

Claims (20)

Forming an active region surrounded by an element isolation region on a semiconductor substrate;
A step of forming a first gate line and a second gate line adjacent to each other provided to cross the active region;
Forming an offset film so as to cover the active region, the first gate wiring, and the second gate wiring;
Forming a resist film having an opening exposing a part of the offset film in a region between the first gate wiring and the second gate wiring;
Etching the offset film exposed from the opening using the resist film as a mask;
Removing the resist film;
Forming a first impurity diffusion layer on the active region by implanting a first impurity into the active region using the offset film as a mask;
Forming a second impurity diffusion layer covering a bottom surface or a side surface of the first impurity diffusion layer on the active region by injecting a second impurity into the active region using the offset film as a mask;
Forming a sidewall film on the respective sidewalls of the first gate wiring and the second gate wiring via the offset film;
Forming a third impurity diffusion layer on the active region by injecting a third impurity into the active region using the first gate wiring, the second gate wiring, and the sidewall film as a mask;
A method of manufacturing a semiconductor device including: The first impurity diffusion layer is an N-type or P-type impurity diffusion layer,
The second impurity diffusion layer is an impurity diffusion layer having a conductivity type opposite to that of the first impurity diffusion layer,
The method of manufacturing a semiconductor device according to claim 1, wherein the third impurity diffusion layer is an impurity diffusion layer having the same conductivity type as that of the first impurity diffusion layer.   2. The semiconductor according to claim 1, wherein in the step of forming the second impurity diffusion layer, the second impurity is implanted into the active region from a direction at a predetermined angle from a direction perpendicular to an upper surface of the active region. Device manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, wherein the angle in the predetermined range is not less than 17 degrees and not more than 20 degrees.   In the step of forming the second impurity diffusion layer, by implanting the second impurity also into the active region covered with the offset film, the fourth impurity is covered at the position on the active region covered with the offset film. The method of manufacturing a semiconductor device according to claim 1, wherein a diffusion layer is formed.   6. The fourth impurity diffusion layer is connected to the third impurity diffusion layer formed on the active region on a side opposite to a side where the first gate wiring and the second gate wiring face each other. The manufacturing method of the semiconductor device of description.   The method of manufacturing a semiconductor device according to claim 1, wherein the offset film is an insulating film.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the offset film is an insulating film including a silicon nitride film.   The method of manufacturing a semiconductor device according to claim 1, wherein the sidewall film is an insulating film.   The method for manufacturing a semiconductor device according to claim 9, wherein the sidewall film is a silicon oxide film. A semiconductor substrate;
An element isolation region formed on the semiconductor substrate;
An active region partitioned by the element isolation region in the semiconductor substrate;
A first gate line and a second gate line adjacent to each other provided to traverse the active region;
An offset film covering sidewalls of the first gate wiring and the second gate wiring;
A sidewall film that covers sidewalls of the first gate wiring and the second gate wiring through the offset film;
With
The sidewall film on the first direction side of the first gate wiring, the first gate wiring and the second gate wiring facing each other; and the first direction of the second gate wiring; The sidewall film on the opposite second direction side covers the horizontally-facing side wall of the bottom where the offset film is closest to the active region,
The sidewall film on the second direction side of the first gate wiring and the sidewall film on the first direction side of the second gate wiring are such that the offset film is in the active region. A semiconductor device which does not cover the side wall facing the horizontal direction of the bottommost part which is closest. On the active region on the side where the first gate line and the second gate line face each other,
A first impurity diffusion layer of a first conductivity type;
A second impurity diffusion layer having a second conductivity type and covering a bottom surface or a side wall of the first impurity diffusion layer;
The semiconductor device according to claim 11. The first conductivity type is p-type or n-type,
The semiconductor device according to claim 12, wherein the second conductivity type is a conductivity type opposite to the first conductivity type.   A third conductivity type of the first gate line and the second gate line on the opposite sides of the first gate line and the second gate line and the opposite sides of the first gate line and the second gate line, and penetrating the first impurity diffusion layer. The semiconductor device according to claim 12, comprising an impurity diffusion layer.   The semiconductor device according to claim 14, wherein an impurity concentration of the first impurity diffusion layer is lower than an impurity concentration of the third impurity diffusion layer.   The first gate line is disposed between the third impurity diffusion layer and the second impurity diffusion layer on the active region opposite to the side where the first gate line and the second gate line are opposed to each other. 15. The fourth impurity diffusion layer of the second conductivity type is connected to the third impurity diffusion layer on the active region on the opposite side of the opposite side to the second gate wiring. Semiconductor device.   The semiconductor device according to claim 16, wherein the fourth impurity diffusion layer is shallower than the second impurity diffusion layer. A semiconductor substrate;
An element isolation region formed on the semiconductor substrate;
An active region partitioned by the element isolation region in the semiconductor substrate;
A first gate line and a second gate line adjacent to each other provided to traverse the active region;
A first offset film provided on a side surface in the first direction on the second gate wiring side of the first gate wiring;
A second offset film provided on a side surface in a second direction opposite to the first direction in the first gate wiring;
A third offset film provided on a side surface in the second direction of the second gate wiring;
A fourth offset film provided on a side surface of the second gate wiring in the first direction;
A first sidewall film stacked on the first offset film;
A second sidewall film stacked on the second offset film;
A third sidewall film stacked on the third offset film;
A fourth sidewall film stacked on the fourth offset film;
With
The first offset film is at least partially present between the first sidewall film and the semiconductor substrate in a direction perpendicular to the upper surface of the active region;
The third offset film is at least partially present between the third sidewall film and the semiconductor substrate in a direction perpendicular to the upper surface of the active region;
The second offset film is entirely present between the second sidewall film and the semiconductor substrate in a direction perpendicular to the upper surface of the active region,
A semiconductor device in which the fourth offset film entirely exists between the fourth sidewall film and the semiconductor substrate in a direction perpendicular to the upper surface of the active region. On the active region on the side where the first gate line and the second gate line face each other,
A first impurity diffusion layer of a first conductivity type;
A second impurity diffusion layer having a second conductivity type and covering a bottom surface or a side wall of the first impurity diffusion layer;
The semiconductor device according to claim 18. The first conductivity type is p-type or n-type,
The semiconductor device according to claim 19, wherein the second conductivity type is a conductivity type opposite to the first conductivity type.

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