JP2016225371A - Wafer dividing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wafer dividing method capable of reducing the amount of cutting edge of a cutting blade. SOLUTION: A plurality of devices disposed in respective regions partitioned by a plurality of intersecting scheduled lines and having a plurality of electrodes, respectively, and a plurality of metal posts respectively connected to the plurality of electrodes of the device A wafer dividing method for dividing a wafer that is sealed with a resin and has a plurality of electrode bumps connected to each metal post protruding on the sealing resin, the wafer being protruded from the electrode bump A protective member adhering step for adhering a protective member to one surface; a holding step for holding the wafer via the protective member with a chuck table having a holding surface; and the other surface of the wafer held on the chuck table A dividing step of forming a cutting groove from the protective member to the protective member along the planned dividing line with a cutting blade, and dividing the wafer into a plurality of chips. In the material sticking step, the electrode bumps are buried in the protective member and the wafer is stuck. [Selection] Figure 5

Description

  The present invention relates to a wafer dividing method, and more particularly to a WL (Wafer-level) package wafer dividing method.

  WL-CSP (Wafer-level Chip Size Package) wafer is a technology that forms a redistribution layer and electrodes (metal posts) in the wafer state, then encapsulates the surface side with resin and divides it into packages using a cutting blade Since the size of the package obtained by dividing the wafer into pieces becomes the size of the semiconductor device chip, it is widely adopted from the viewpoint of miniaturization and weight reduction.

  In the WL-CSP wafer manufacturing process, after forming a redistribution layer on the device surface side of a device wafer on which a plurality of devices are formed, and further forming a metal post connected to an electrode in the device via the redistribution layer The metal post and the device are sealed with resin.

  Next, after the sealing material is thinned and the metal posts are exposed on the surface of the sealing material, external terminals called electrode bumps are formed on the end faces of the metal posts. Then, it cuts with a cutting device etc. and divides | segments into each CSP.

  In order to protect the semiconductor device from impact, moisture and the like, it is important to seal with a sealing material. Normally, by using a sealing material in which a filler made of SiC is mixed in an epoxy resin as the sealing material, the thermal expansion coefficient of the sealing material is brought close to the thermal expansion coefficient of the semiconductor device chip, and the difference in thermal expansion coefficient Prevents damage to the package during heating.

  Since the WL-CSP wafer is almost entirely sealed with a resin and a plurality of electrode bumps connected to each metal post are disposed on the surface of the resin, the WL-CSP wafer is generally on the resin of the WL-CSP wafer. The division planned lines are determined by using the electrode bumps formed in the above as targets, and the division planned lines are cut with a cutting blade to be divided into individual CSPs.

Japanese Patent Laid-Open No. 2015-28980 Japanese Patent Laying-Open No. 2015-53468

  However, when the WL-CSP wafer is cut from the surface side, the cutting blade cuts away the electrode bumps disposed on the upper surface of the resin, so the height of the electrode bumps is included in addition to the thickness of the wafer and the resin. A thick wafer is cut.

  Therefore, the cutting blade must be cut with the long blade edge exposed, and the cutting edge amount is very long compared to the blade thickness, so the cutting blade is easy to meander during cutting or the blade edge is damaged. There was a problem that it was easy to do.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a wafer dividing method capable of reducing the amount of cutting edge of a cutting blade.

  According to the present invention, a plurality of devices disposed in each region divided by a plurality of intersecting scheduled lines and having a plurality of electrodes, respectively, and a plurality of metal posts respectively connected to the plurality of electrodes of the device Is a wafer dividing method of dividing a wafer in which a plurality of electrode bumps connected to each metal post are protruded and disposed on the sealing resin, the wafer having the electrode bumps protruding A protective member adhering step for adhering a protective member to one side of the wafer, a holding step for holding the wafer via the protective member with a chuck table having a holding surface, and the other of the wafers held on the chuck table A dividing step of forming a cutting groove extending from the surface to the protection member along the planned dividing line with a cutting blade, and dividing the wafer into a plurality of chips. The member sticking step, a method of dividing wafer, comprising adhering the wafer to obscure the electrode bump on the protective member.

  Preferably, the wafer is composed of a package wafer in which semiconductor chips are respectively disposed in each of the regions divided by the plurality of division lines, and is formed in a wafer shape by a resin that seals the semiconductor chips, The division line is made of resin.

  According to the wafer dividing method of the present invention, the cutting edge of the cutting blade is obtained by fixing the wafer by embedding a high electrode bump in the adhesive layer (glue layer) of the protective member and dicing from the back side of the wafer. The amount of stock can be reduced, and the problems of the cutting blade meandering or the blade edge of the blade being damaged during cutting, which has been a problem in the past, can be suppressed.

1A is an exploded perspective view of a WL-CSP wafer, and FIG. 1B is a perspective view of the WL-CSP wafer. It is an expanded sectional view of a WL-CSP wafer. It is a perspective view which shows a mode that the outer peripheral part adheres the surface side of a WL-CSP wafer to the dicing tape with which the annular frame was mounted | worn. It is a perspective view of a cutting device. It is a partial cross section side view which shows the division | segmentation step of a WL-CSP wafer. 6A is a perspective view of a FO-WLP (Fun-Out Wafer Level Package) wafer, and FIG. 6B is a cross-sectional view thereof. It is a partial cross section side view which shows the division | segmentation step of a FO-WLP wafer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1A, an exploded perspective view of the WL-CSP wafer 11 is shown. FIG. 1B is a perspective view of the WL-CSP wafer 11.

  As shown in FIG. 1A, devices 17 such as LSIs are formed on the surface 13a of the device wafer 13 in each region partitioned by a plurality of division lines (streets) 15 formed in a lattice pattern. Has been.

  A device wafer (hereinafter sometimes simply referred to as a wafer) 13 has a rear surface 13b ground in advance and thinned to a predetermined thickness (about 200 to 300 μm), and then a rewiring layer 21 is formed on the surface 13a. Is done.

  Further, after forming a plurality of metal posts 23 electrically connected to the electrodes 19 in the device 17 on the rewiring layer 21, a sealing material 25 is used so that the metal posts 23 are buried on the surface 13 a side of the wafer 13. Seal.

  As the sealing material 25, it is preferable to use a resin such as an epoxy resin mixed with a filler made of SiC in order to make the thermal expansion coefficient of the sealing material 25 close to the thermal expansion coefficient of the device wafer 13.

  In another embodiment, after forming a plurality of metal posts 23 electrically connected to the electrodes 19 in the device 17 without forming the redistribution layer 21 on the surface 13 a of the device wafer 13, You may make it seal the surface 13a side with the sealing material 25 so that the metal post 23 may be buried.

  Next, the resin sealing material 25 is thinned using a plane cutting device (surface planar) having a cutting tool made of single crystal diamond or a grinding device called a grinder. After thinning the resin sealing material 25, the end face of the metal post 23 is exposed, for example, by etching.

  Next, metal bumps (metal balls) 27 such as solder are formed on the exposed end surfaces of the metal posts 23 by a well-known method, and the WL-CSP wafer 11 is completed. In the WL-CSP wafer 11 of this embodiment, the resin sealing material 25 has a thickness of about 100 μm.

  When cutting the WL-CSP wafer 11 with a cutting device, as shown in FIG. 3, the dicing tape as a protective member, preferably the outer peripheral portion of the WL-CSP wafer 11 is bonded to the annular frame F as shown in FIG. Adhere to T. As a result, the WL-CSP wafer 11 is supported by the annular frame F via the dicing tape T.

  However, when the WL-CSP wafer 11 is cut with a cutting device, the dicing tape T may be attached to the surface of the WL-CSP wafer 11 without using the annular frame F.

  Referring to FIG. 4, a perspective view of a cutting device 2 suitable for cutting the WL-CSP wafer 11 is shown. Reference numeral 4 denotes a base of the cutting apparatus 2. On the base 4, a chuck table 6 is disposed so as to be rotatable and reciprocally movable in the X-axis direction by a cutting feed mechanism (not shown). A plurality of clamps 8 for clamping the annular frame F are attached to the chuck table 6. Reference numeral 10 denotes a bellows for protecting the cutting feed mechanism.

  A gate-shaped column 12 is erected on the base 4. A pair of guide rails 14 extending in the Y-axis direction are fixed to the column 12. A Y-axis moving block 16 is mounted on the column 12 so as to be movable in the Y-axis direction along the guide rail 14 by an index feed mechanism 20 including a ball screw 18 and a pulse motor (not shown).

  A pair of guide rails 22 extending in the Z-axis direction are fixed to the Y-axis moving block 16. A Z-axis moving block 24 is mounted on the Y-axis moving block 16 so as to be movable in the Z-axis direction by being guided by the guide rail 22 by a Z-axis moving mechanism 30 including a ball screw 26 and a pulse motor 28. .

  A cutting unit 32 and an alignment unit 36 are attached to the Z-axis moving block 24. A spindle 33 (see FIG. 5) is rotatably accommodated in the spindle housing of the cutting unit 32, and a cutting blade 34 is attached to the tip of the spindle 33.

  The alignment unit 36 is equipped with a first imaging unit 38 having a macro microscope and a standard camera for imaging with visible light and an infrared camera, and a second imaging unit 40 having a micro microscope, a standard camera and an infrared camera. .

  As shown in FIG. 5, the dicing tape T is formed by applying an acrylic adhesive layer (glue layer) 31 to the surface of a base material 29 such as polyvinyl chloride or polyolefin. By increasing the thickness, the electrode bumps 27 can be buried in the adhesive layer 31 of the dicing tape T, and the WL-CSP wafer 11 can be adhered to the dicing tape T.

  Next, a method for dividing the WL-CSP wafer 11 using the cutting device 2 will be described. First, the WL-CSP wafer 11 supported by the annular frame F via the dicing tape T is placed on the holding surface of the chuck table 6 and sucked and held by the chuck table 6, and the annular frame F is clamped by the clamp 8. And fix.

  Next, the WL-CSP wafer 11 is imaged from the back side using the first imaging unit 38 and the second imaging unit 40, and the division schedule formed on the front surface 13 a of the device wafer 13 through the device wafer 13. A division line detection step for detecting the line 15 is performed.

  After performing the division line detection step, as shown in FIG. 5, the cutting blade 34 rotating at high speed is cut from the back side of the WL-CSP wafer 11 along the division line 15 to the dicing tape T, and the chuck table. By cutting and feeding 6 in the X-axis direction, a cutting groove is formed along the planned division line 15.

  By indexing and feeding the cutting unit 32 in the Y-axis direction, similar cutting grooves are formed along all the planned division lines 15 extending in the first direction. Next, after the chuck table 6 is rotated by 90 °, similar cutting grooves are formed along all the planned dividing lines 15 orthogonal to the first direction and extending in the second direction, and the WL-CSP wafer 11 is formed. Is divided into individual CSPs.

  In the wafer dividing method of the present embodiment, the WL-CSP wafer 11 is fixed so that the electrode bumps 27 having a height are embedded in the adhesive layer 31 of the dicing tape T, and dicing is performed by dicing from the back side of the wafer 11. The amount of cutting edge of the blade 34 can be reduced. As a result, meandering of the cutting blade 34 can be prevented during dicing, and breakage of the cutting blade of the cutting blade 34 can be suppressed.

  Next, a method for dividing the FO-WLP wafer 35 will be described with reference to FIGS. 6A is a perspective view of the FO-WLP wafer 35, and FIG. 6B is a cross-sectional view thereof.

  A manufacturing method of the FO-WLP wafer 35 is described in, for example, Japanese Patent Application Laid-Open No. 2015-53468, and semiconductor chips 37 are respectively arranged in each region partitioned by a plurality of division scheduled lines 43. A package wafer in which these semiconductor chips 37 are sealed with a resin 39 and formed into a wafer shape. A plurality of electrode bumps 41 are formed on the surface of each semiconductor chip 37.

  In cutting the FO-WLP wafer 35, as in the first embodiment shown in FIG. 3, the dicing tape as a protective member having the outer peripheral portion adhered to the annular frame F on the surface side of the FO-WLP wafer 35. Adhere to T. As a result, the FO-WLP wafer 35 is supported by the annular frame F via the dicing tape T.

  By thickening the adhesive layer 31 of the dicing tape T, the electrode bumps 41 are buried in the adhesive layer 31 of the dicing tape T, and the FO-WLP wafer 35 is attached to the dicing tape T.

  Similarly to the first embodiment described above, the infrared camera of the first imaging unit 38 and the second imaging unit 40 images the planned division line 43 on the front side through the sealing resin 39 from the back side of the FO-WLP wafer 35. Then, an alignment step for detecting the division line 43 is performed.

  In addition, a mark indicating a division planned line may be set on the back side of the FO-WLP wafer 35, and the alignment step may be performed by imaging the mark with the first imaging unit and the second imaging unit.

  After the alignment step, the cutting blade 34 that rotates at high speed is cut from the back side of the FO-WLP wafer 35 to the dicing tape T along the division line 43 by the cutting blade 34, and the chuck table 6 is processed and fed in the X-axis direction. Thus, a cutting groove is formed along the division line 43.

  While indexing and feeding the cutting unit 32 in the Y-axis direction, similar cutting grooves are formed along all the planned division lines 43 extending in the first direction. Next, after the chuck table 6 is rotated by 90 °, similar cutting grooves are formed along all the planned dividing lines 43 extending in the second direction orthogonal to the first direction, and the FO-WLP wafer 35 is formed. Is divided into individual device packages.

  In the wafer dividing method of this embodiment, the FO-WLP wafer 35 is fixed so that the electrode bumps 41 of the FO-WLP wafer 35 are embedded in the adhesive layer 31 of the dicing tape T, and the FO-WLP wafer 35 is attached from the back side. Dicing allows the cutting edge amount of the cutting blade 34 to be reduced.

2 Cutting device 6 Chuck table 11 WL-CSP wafer 13 Device wafer 15 Scheduled division line 17 Device 19 Electrode 21 Redistribution layer 23 Metal post 25 Resin sealing material 27 Electrode bump 32 Cutting unit 34 Cutting blade 35 FO-WLP wafer 37 Semiconductor Chip 39 Resin encapsulant 41 Electrode bump

Claims (2)

A plurality of devices arranged in each region divided by a plurality of intersecting scheduled lines and each having a plurality of electrodes and a plurality of metal posts respectively connected to the plurality of electrodes of the device are sealed with resin And a wafer dividing method for dividing a wafer in which a plurality of electrode bumps connected to each metal post are projected and disposed on a sealing resin,
A protective member attaching step of attaching a protective member to one surface of the wafer from which the electrode bumps protrude;
A holding step of holding the wafer via the protective member with a chuck table having a holding surface;
A dividing step of forming a cutting groove from the other surface of the wafer held by the chuck table to the protection member along the planned dividing line with a cutting blade, and dividing the wafer into a plurality of chips, and
In the protective member attaching step, the wafer is attached by attaching the wafer by burying the electrode bumps in the protective member.   The wafer is composed of a package wafer in which semiconductor chips are respectively disposed in each of the regions divided by the plurality of division lines and formed into a wafer shape by a resin that seals the semiconductor chips. 2. The wafer dividing method according to claim 1, wherein the line is formed of a resin.

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