JP2017069269A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that has an alignment mark that can be recognized by observation from a rear face side of a semiconductor substrate covered with a conductive film that does not transmit visible light nor infrared ray, and to provide a method of manufacturing the same.SOLUTION: A semiconductor substrate has an element formation region where a plurality of semiconductor elements are formed and an outer peripheral region that surrounds an outer periphery of the element formation region, on a first principal surface, and has a recessed part recessed toward the first principal surface side in a region corresponding to the element formation region, on a second principal surface at an opposite side to the first principal surface. In the semiconductor substrate, a reforming part provided in a region corresponding to the recessed part is provided. On a bottom face of the recessed part, a convex or concave structure portion is provided at a formation position of the reforming part. The structure portion and the bottom face of the recessed part are coated with a conductive film.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  With the spread of system-in-package in recent years, attention has been focused on thin processing technology for semiconductor wafers. For example, in the field of a stack package used in a mobile phone or the like, a product in which a plurality of chips thinned to 100 μm or less are stacked inside the package has been developed. The thinning process of the semiconductor wafer is performed by forming a circuit element or the like on the semiconductor wafer and then grinding the back surface of the semiconductor wafer using a grinding wheel. As the semiconductor wafer becomes thinner, chipping, chip cracking, warpage of the semiconductor wafer, and the like occur, causing problems such as a decrease in yield and a decrease in productivity. In order to solve this problem, a technique is known in which, when a semiconductor wafer is ground, an outer peripheral portion of, for example, about 3 mm is left from the outer edge of the semiconductor wafer, and only the inner peripheral portion is ground and thinned. By introducing such a technique, the handling of the semiconductor wafer becomes easy, and the warpage of the semiconductor wafer can be reduced.

  As a technique related to the manufacture of a semiconductor device in which the above technique is introduced, for example, in Patent Document 1, a process of attaching an adhesive tape to the back surface of a wafer and a cutting plan from the front surface side of the wafer to which the adhesive tape is attached are disclosed. A processing direction including a step of forming a cutting groove along the line and a step of expanding the adhesive tape in a state where the surface of the wafer is held downward after the cutting groove forming step is described.

  On the other hand, Patent Document 2 describes a technique for forming an alignment mark at an arbitrary position in the depth direction of a semiconductor wafer. In Patent Document 2, a multiphoton absorption process is caused in a specific portion of a semiconductor wafer by irradiating a laser beam with a focus on an arbitrary depth position of the semiconductor wafer from one surface of the semiconductor wafer, It is described that an alignment mark for aligning a semiconductor wafer is formed.

JP 2010-93005 A JP 2011-200897 A

  In a dicing process for dividing a semiconductor wafer into chips, the semiconductor wafer is usually set in a dicing apparatus with a dicing tape attached to the back side thereof and supported on the dicing tape. Thereafter, dicing is performed by recognizing a dicing line defined on the surface of the semiconductor wafer and scanning the dicing blade along the dicing line.

  However, the semiconductor wafer thinned by grinding only the inner peripheral portion of the back surface of the semiconductor wafer as described above has a step between the outer peripheral portion and the inner peripheral portion. In order to perform dicing of a semiconductor wafer having a step on the back surface as described above, a dicing apparatus having a dedicated stage for stably supporting the back surface of the semiconductor wafer is required. In order to use the existing dicing apparatus, it is necessary to grind the outer peripheral portion of the back surface of the semiconductor wafer in a further grinding process after the back surface electrode forming process and the inspection process, and to remove the step. However, in this case, two grinding steps are required, resulting in an increase in cost.

  In order to avoid the above problem, a method is conceivable in which the semiconductor wafer is set in a dicing apparatus using the front side of the semiconductor wafer as a support surface, and dicing is performed from the back side of the semiconductor wafer. When dicing is performed from the back side of the semiconductor wafer, it is necessary to recognize the position of the dicing line from the back side of the semiconductor wafer. As the method, for example, as described in Patent Document 1, there is a method using an infrared camera using a wavelength that transmits a semiconductor wafer. However, superjunction, which is a vertical type high-voltage semiconductor element, IGBT (Insulated Gate Bipolar Transistor), etc. have an electrode formed of a conductive film that does not transmit infrared light on the back surface of the semiconductor wafer. It is difficult to recognize the dicing line by observing the back side. Further, even if an alignment mark for estimating a dicing line is formed on the back surface of the semiconductor wafer using the method described in Patent Document 2, if the back surface of the semiconductor wafer is covered with a conductive film, The alignment mark cannot be recognized.

  The present invention has been made in view of the above points, and a semiconductor device having an alignment mark that can be recognized by observation from the back side of a semiconductor substrate covered with a conductive film that does not transmit visible light or infrared light, and its manufacture It aims to provide a method.

  A semiconductor device according to a first aspect of the present invention includes an element forming region in which a plurality of semiconductor elements are formed on a first main surface, and an outer peripheral region surrounding an outer periphery of the element forming region. A semiconductor substrate having a recess recessed toward the first main surface in a region corresponding to the element formation region of the second main surface opposite to the surface; and the recess inside the semiconductor substrate Covers the modified portion provided in the corresponding region, the convex or concave structural portion provided at the formation position of the modified portion on the bottom surface of the concave portion, and the structural portion and the bottom surface of the concave portion A conductive film.

  A semiconductor device according to a second aspect of the present invention has an element forming region in which a plurality of semiconductor elements are formed on a first main surface, and an outer peripheral region surrounding the outer periphery of the element forming region. A semiconductor substrate having a recess recessed toward the first main surface in a region corresponding to the element formation region of the second main surface opposite to the surface; and provided on an outer edge portion of the semiconductor substrate. A notch and a conductive film covering a bottom surface of the recess of the semiconductor substrate.

  According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: an element forming region in which a plurality of semiconductor elements are formed on a first main surface; and a semiconductor substrate having an outer peripheral region surrounding an outer periphery of the element forming region. Forming a modified portion in which the state of the semiconductor substrate has changed at a predetermined depth position in a region corresponding to the element formation region; and a second portion opposite to the first main surface of the semiconductor substrate. Forming a recess recessed toward the first main surface in a region corresponding to the element formation region of the second main surface, exposing the modified portion on the bottom surface of the recess, and a bottom surface of the recess A step of forming a convex or concave structure portion at the formation position of the modified portion by etching, and a thickness at which the irregularities formed on the bottom surface of the concave portion by the convex or concave structure portion can be recognized With the conductive film on the bottom of the recess And a step of covering, the.

  According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method including an element forming region in which a plurality of semiconductor elements are formed on a first main surface and an outer peripheral region surrounding an outer periphery of the element forming region. A step of forming a notch in the portion, and the first main surface side of the second main surface opposite to the first main surface of the semiconductor substrate in a region corresponding to the element formation region A step of forming a concave recess, and a step of covering the bottom surface of the recess with a conductive film.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which has the alignment mark which can be recognized by observation from the back surface side of the semiconductor substrate covered with the electrically conductive film which does not permeate | transmit visible light and infrared rays, and its manufacturing method are provided.

It is sectional drawing which shows the structure of the semiconductor device which concerns on embodiment of this invention. It is a top view which shows an example of arrangement | positioning of the modification part which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows the concave structure part which concerns on embodiment of this invention. It is a figure which shows the convex structure part which concerns on embodiment of this invention. It is a top view which shows the other example of arrangement | positioning of the modification part which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on embodiment of this invention. It is a top view which shows an example of arrangement | positioning of the notch part which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or equivalent components and parts are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate.

[First embodiment]
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate (semiconductor wafer) 10 made of a semiconductor such as silicon. The first main surface S1 of the semiconductor substrate 10 has an element formation region R1 in which a plurality of semiconductor elements 11 are formed inside the outer peripheral region R2 of the semiconductor substrate 10. The semiconductor element 11 may be a discrete element such as a MOSFET, a bipolar transistor, or an IGBT, or may be an integrated circuit including a plurality of semiconductor elements.

  In a region corresponding to the element formation region R1 of the second main surface S2 opposite to the first main surface S1 of the semiconductor substrate 10, a recess 13 that is recessed toward the first main surface S1 side is provided. ing. That is, in the semiconductor substrate 10, the thickness T1 at the inner peripheral portion is thinner than the thickness T2 at the outer peripheral portion. The thickness T1 in the inner peripheral portion where the element forming region R1 of the semiconductor substrate 10 exists is, for example, 100 μm or less, and the thickness T2 in the outer peripheral portion where the outer peripheral region R2 of the semiconductor substrate 10 exists is, for example, about 600 μm. The thickness T1 is determined according to the breakdown voltage of the semiconductor element 11, for example. For example, when the target breakdown voltage of the semiconductor element 11 is 1000 V, the thickness T1 is set to about 100 μm, and when the target breakdown voltage of the semiconductor element 11 is 600 V, the thickness T1 is set to about 60 μm. The

  As described above, by setting the thickness of the semiconductor element 11 to the minimum thickness necessary for ensuring the withstand voltage, the thickness of the semiconductor package incorporating the semiconductor element 11 can be reduced. Further, when the semiconductor substrate 10 is thinned to 100 μm or less, by maintaining the initial thickness in the outer peripheral region R2, the semiconductor substrate 10 can be easily handled and the warpage of the semiconductor substrate 10 can be reduced. It becomes possible.

  The semiconductor device 100 includes a plurality of modified portions 12 in which the state (material) of the semiconductor substrate 10 has changed in a region corresponding to the element formation region R <b> 1 inside the semiconductor substrate 10. That is, in the present embodiment, the semiconductor substrate 10 is mainly composed of single crystal silicon, whereas the modified portion 12 is mainly composed of amorphous silicon. FIG. 2 is a plan view showing an example of the arrangement of the reforming unit 12. As shown in FIG. 2, the modified portion 12 may be provided at a position corresponding to the dicing line 60 in a region corresponding to the element formation region R1.

  On the bottom surface S3 of the concave portion 13 provided on the second main surface S2 of the semiconductor substrate 10, a concave structure portion 14 is provided at the position where the modified portion 12 is formed. The concave structure portion 14 recognizes the dicing line 60 from the second main surface S2 side of the semiconductor substrate 10 in a dicing process for dividing the plurality of semiconductor elements 11 formed on the semiconductor substrate 10 into individual pieces. Functions as an alignment mark.

  The bottom surface S <b> 3 of the recess 13 is covered with a conductive film 15 that constitutes an electrode of the semiconductor element 11. For example, the conductive film 15 may have a stacked structure in which a nickel layer and a gold layer are stacked. The conductive film 15 is formed with a thickness that allows the concave and convex portions formed on the bottom surface S3 of the concave portion 13 to be recognized by the concave structure portion 14. That is, the alignment mark formed on the bottom surface S3 of the recess 13 can be recognized even when the conductive film 15 is formed.

  A method for manufacturing the semiconductor device 100 will be described below. 3A to 3D and FIGS. 4A to 4C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device 100.

  First, a semiconductor substrate 10 whose main material is single crystal silicon is prepared. Subsequently, a plurality of semiconductor elements 11 are formed in the element formation region R1 inside the outer peripheral region R2 of the first main surface S1 of the semiconductor substrate 10 (FIG. 3A). The semiconductor element 11 may be a discrete element such as a MOSFET, a bipolar transistor, or an IGBT, or may be an integrated circuit including a plurality of semiconductor elements. The semiconductor element 11 is formed by a known process including a film forming process, an ion implantation process, an etching process, a wiring process, and the like.

  Next, by irradiating the semiconductor substrate 10 with the laser light L from the first main surface S1 side using the laser irradiation device 20, a plurality of regions in the region corresponding to the element formation region R1 inside the semiconductor substrate 10 are provided. A modified portion 12 in which the state (material) of the semiconductor substrate 10 made of single crystal silicon is changed is formed at a location (FIG. 3B). The reforming portion 12 is a portion where single crystal silicon constituting the semiconductor substrate 10 is changed to amorphous silicon. A femtosecond laser is used as the laser light L, and the amount of energy (fluence) per unit area is set to a predetermined range equal to or less than a processing threshold at which no ablation occurs. By irradiating the single crystal silicon with such laser light L, a high-density amorphous silicon layer is formed inside the single crystal silicon. For example, as shown in FIG. 2, the modified portion 12 may be provided at a position corresponding to the dicing line 60 in the region corresponding to the element formation region R1. The reforming part 12 is formed so as to reach the depth position of the bottom surface S3 of the recess 13 formed in the grinding process described later.

  Next, a protective tape 30 is attached to the first main surface S1 of the semiconductor substrate 10 so as to cover the plurality of semiconductor elements 11 (FIG. 3C).

  Next, the semiconductor substrate 10 is ground from the second main surface S2 side to thin the semiconductor substrate 10. In this step, the semiconductor substrate 10 is placed on the stage 40 of the back grinding apparatus so that the first main surface S1 side to which the protective tape 30 is attached is directed downward and the second main surface S2 side is directed upward. Using the grinding wheel 41, the second main surface S2 side is ground. The grinding is performed only on the region corresponding to the element formation region R1, and the region corresponding to the outer peripheral region R2 is not ground. Thereby, the initial thickness (for example, about 600 μm) of the semiconductor substrate 10 is maintained in the outer peripheral portion of the semiconductor substrate 10, while the inner peripheral portion of the semiconductor substrate 10 is in accordance with the target breakdown voltage of the semiconductor element 11. For example, the thickness is reduced to about 100 μm. As a result, the recess 13 is formed in a region corresponding to the element formation region R1 of the second main surface S2 of the semiconductor substrate 10. Further, the modified portion 12 is exposed at the bottom surface S3 of the recess 13 (FIG. 3D). As described above, by grinding the semiconductor substrate 10 while securing the thickness of the outer peripheral portion of the semiconductor substrate 10, it is possible to suppress the warpage of the semiconductor substrate 10 and to ensure the strength of the semiconductor substrate 10 after thinning. It becomes possible. Thereby, the handling property of the semiconductor substrate 10 can be improved, and the process after this process becomes easy.

  Next, for example, by etching the bottom surface S3 of the concave portion 13 of the semiconductor substrate 10 using a mixed acid containing hydrofluoric acid or nitric acid, the processing strain is removed and the bottom surface S3 of the concave portion 13 is flattened. When the etching rate of the modified portion 12 is higher than the etching rate of the bottom surface S3 of the concave portion 13, the concave structure portion 14 is formed at the position where the modified portion 12 is formed. That is, the portion where the modified portion 12 made of amorphous silicon is etched at an etching rate higher than the bottom surface S3 of the recess 13 made of single crystal silicon becomes the concave structure portion 14 (FIG. 4A). In this etching, the modified portion 12 may be completely removed from the bottom surface S3 of the concave portion 13, or the modified portion 12 may be partially left. Moreover, you may perform this etching process using a dry etching process.

  Next, the conductive film 15 constituting the electrode of the semiconductor element 11 is formed on the bottom surface S3 of the recess 13 by using a sputtering method or a plating method (FIG. 4B). Here, FIG. 5 is an enlarged view of a portion A surrounded by a broken line in FIG. 4B. As shown in FIGS. 4B and 5, even after the formation of the conductive film 15, the conductive film 15 is formed with such a thickness that the concave and convex portions formed on the bottom surface S <b> 3 of the concave portion 13 can be recognized by the concave structure portion 14. That is, the conductive film 15 is formed with a film thickness that does not completely fill the concave structure portion 14. Thus, even after the conductive film 15 is formed, the concave structure portion 14 is made recognizable by the concave structure portion 14 on the bottom surface S3 of the concave portion 13, so that the concave structure portion 14 can be formed in a dicing process described later. It can function as an alignment mark for positioning the dicing blade.

  Next, the semiconductor substrate 10 is cut along the dicing line 60 (see FIG. 2) to divide the plurality of semiconductor elements 11 into individual pieces. In this step, the semiconductor substrate 10 is set in the dicing apparatus such that the dicing tape 31 is attached to the first main surface S1 having a flat surface, and the first main surface S1 faces the stage 50 of the dicing apparatus. The The dicing blade 51 provided in the dicing apparatus is inserted into the semiconductor substrate 10 from the second main surface S2 side. The dicing apparatus estimates the position of the dicing line 60 and positions the dicing blade 51 by recognizing an image of the concave structure portion 14 that functions as an alignment mark formed on the bottom surface S3 of the concave portion 13. Thereby, the semiconductor substrate 10 is cut along the dicing line 60, and the semiconductor element 11 is cut out (FIG. 4C).

  As described above, according to the semiconductor device 100 and the manufacturing method thereof according to the first embodiment of the present invention, the bottom surface of the recess 13 corresponding to the modified portion 12 formed at a predetermined position in the semiconductor substrate 10. A concave structure portion 14 is formed in S3. Since the concave structure portion 14 forms irregularities on the bottom surface S3 of the concave portion 13, a conductive film 15 that does not transmit visible light and infrared rays constituting the electrodes of the semiconductor element 11 is formed on the bottom surface S3 of the concave portion 13. However, as long as the conductive film 15 is formed with a thickness that does not completely fill the concave structure portion 14, the concave structure portion 14 can be recognized. Therefore, the concave structure portion 14 formed on the second main surface S2 side of the semiconductor substrate 10 can be used as an alignment mark for positioning the dicing blade 51 in the dicing process of the semiconductor substrate 10. . That is, the semiconductor device 100 according to the present embodiment includes the alignment mark that can be recognized by observation from the second main surface S2 side of the semiconductor substrate covered with the conductive film that does not transmit visible light or infrared light. The semiconductor substrate 10 can be diced from the second main surface S2 side using an existing dicing apparatus.

  In the above embodiment, the etching rate of the modified portion 12 is higher than the etching rate of the bottom surface S3 of the recess 13, and the concave structure portion 14 is formed at the position where the modified portion 12 is formed. did. However, when the etching rate of the modified portion 12 is lower than the etching rate of the bottom surface S3 of the concave portion 13, a convex structure portion 14 is formed at the formation position of the modified portion 12 as shown in FIG. The Rukoto. That is, when the bottom surface S3 of the concave portion 13 made of single crystal silicon is etched at a higher etching rate than the modified portion 12 made of amorphous silicon, the modified portion 12 is formed on the bottom surface S3 of the concave portion 13. A convex structure portion 14 is formed to protrude.

  Whether the etching rate of the modified portion 12 is higher or lower than the etching rate of the bottom surface S3 of the recess 13 depends on the plane orientation of the single crystal silicon exposed at the bottom surface S3 of the recess 13. That is, when the crystal plane of the single crystal silicon exposed at the bottom surface S3 of the recess 13 is a surface with a relatively low etching rate, the modification portion 12 is preceded by etching, so that the modification portion 12 is formed. A concave structure portion 14 may be formed at the location. On the other hand, when the crystal plane of the single crystal silicon exposed at the bottom surface S3 of the recess 13 is a crystal surface with a relatively high etching rate, the etching of the bottom surface S3 of the recess 13 precedes. A convex structure portion 14 is formed at the formation position.

  In the above embodiment, the semiconductor substrate 10 is thinned by grinding (see FIG. 3D). However, the semiconductor substrate 10 may be thinned by etching. That is, the recess 13 may be formed in the second main surface S2 of the semiconductor substrate 10 by etching the second main surface S2 of the semiconductor substrate 10. In this case, the concave or convex structure portion 14 can be formed on the bottom surface S3 of the concave portion 13 at the stage where the concave portion 13 is formed. In other words, the formation of the concave portion 13 and the formation of the concave or convex structure portion 14 can be performed by a common etching process, and the number of steps can be reduced compared to the case where the semiconductor substrate 10 is thinned by grinding. Can be reduced.

  In the above embodiment, the case where the reforming unit 12 is provided at a position corresponding to the dicing line 60 is illustrated (see FIG. 2), but the present invention is not limited to this mode. The reforming unit 12 only needs to be disposed in the element formation region R1 to be subjected to the thinning process. For example, as illustrated in FIG. 7, the reforming unit 12 is provided at a position away from the position corresponding to the dicing line 60. May be. That is, even when the alignment mark formed at the position where the modified portion 12 is formed does not exist at the position corresponding to the dicing line 60, the dicing blade 51 can be positioned based on the alignment mark.

[Second Embodiment]
FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device 101 according to the second embodiment of the present invention. Similar to the semiconductor device 100 according to the first embodiment, the semiconductor device 101 includes a semiconductor substrate (semiconductor wafer) 10 made of a semiconductor such as silicon, for example, and is formed on the first main surface S1 of the semiconductor substrate 10. Has an element formation region R1 in which a plurality of semiconductor elements 11 are formed inside the outer peripheral region R2 of the semiconductor substrate 10. In a region corresponding to the element formation region R1 of the second main surface S2 opposite to the first main surface S1 of the semiconductor substrate 10, a recess 13 that is recessed toward the first main surface S1 side is provided. ing.

  The semiconductor device 101 has cutout portions 70 obtained by cutting out the semiconductor substrate 10 at a plurality of locations on the outer edge portion (edge portion) of the semiconductor substrate 10. FIG. 9 is a plan view showing an example of the arrangement of the cutout portions 70. As shown in FIG. 9, the notch portion 70 may be provided on the dicing line 60 at the outer edge portion (edge portion) of the semiconductor substrate 10. The plurality of cutout portions 70 provided on the outer edge portion (edge portion) of the semiconductor substrate 10 position the dicing blade in a dicing process for separating the plurality of semiconductor elements 11 formed on the semiconductor substrate 10. It functions as an alignment mark for performing.

  The bottom surface S <b> 3 of the recess 13 is covered with a conductive film 15 that constitutes an electrode of the semiconductor element 11. The alignment mark formed by the cutout portion 70 formed at the outer edge portion (edge portion) of the semiconductor substrate 10 can be recognized even when the conductive film 15 is formed.

  A method for manufacturing the semiconductor device 101 will be described below. 10A to 10C, FIG. 11A, and FIG. 11B are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device 101.

  First, a semiconductor substrate 10 whose main material is single crystal silicon is prepared. Subsequently, a plurality of semiconductor elements 11 are formed in the element formation region R1 inside the outer peripheral region R2 of the first main surface S1 of the semiconductor substrate 10 (FIG. 10A). The semiconductor element 11 may be a discrete element such as a MOSFET, a bipolar transistor, or an IGBT, or may be an integrated circuit including a plurality of semiconductor elements. The semiconductor element 11 is formed by a known process including a film forming process, an ion implantation process, an etching process, a wiring process, and the like.

  Next, the laser irradiation device 20 is used to irradiate the laser beam L from the first main surface S1 side, thereby forming the cutout portions 70 at a plurality of locations on the outer edge portion (edge portion) of the semiconductor substrate 10. (FIG. 10B). As in the first embodiment, a femtosecond laser can be used as the laser light L, but the amount of energy (fluence) per unit area is increased as compared with the case where the modified portion 12 is formed. . By increasing the fluence of the laser beam L and causing ablation, the semiconductor substrate 10 can be mechanically processed. Since the semiconductor substrate 10 has an outer edge portion (edge portion) inclined and a relatively small thickness, the cutout portion 70 can be easily formed on the outer edge portion (edge portion) of the semiconductor substrate 10 by laser irradiation. Can be formed. For example, as shown in FIG. 9, the notch portion 70 is formed on a dicing line 60 on the outer edge portion (edge portion) of the semiconductor substrate 10.

  Next, the protective tape 30 is attached to the first main surface S1 of the semiconductor substrate 10 so as to cover the plurality of semiconductor elements 11. Thereafter, the semiconductor substrate 10 is ground from the second main surface S2 side to thin the semiconductor substrate 10 (FIG. 10C). In this step, the semiconductor substrate 10 is placed on the stage 40 of the back grinding apparatus so that the first main surface S1 side to which the protective tape 30 is attached is directed downward and the second main surface S2 side is directed upward. Using the grinding wheel 41, the second main surface S2 side is ground. The grinding is performed only on the region corresponding to the element formation region R1, and the region corresponding to the outer peripheral region R2 is not ground. Thereby, the initial thickness (for example, about 600 μm) of the semiconductor substrate 10 is maintained in the outer peripheral portion of the semiconductor substrate 10, while the inner peripheral portion of the semiconductor substrate 10 is in accordance with the target breakdown voltage of the semiconductor element 11. For example, the thickness is reduced to about 100 μm. As a result, the recess 13 is formed in a region corresponding to the element formation region R1 of the second main surface S2 of the semiconductor substrate 10.

  Next, for example, by etching the bottom surface S3 of the concave portion 13 of the semiconductor substrate 10 using a mixed acid containing hydrofluoric acid or nitric acid, the processing strain is removed and the bottom surface S3 of the concave portion 13 is flattened. Thereafter, the conductive film 15 constituting the electrode of the semiconductor element 11 is formed on the bottom surface S3 of the recess 13 by using a sputtering method or a plating method (FIG. 11A).

  Next, the semiconductor substrate 10 is cut along the dicing line 60 (see FIG. 9) to divide the plurality of semiconductor elements 11 into individual pieces. In this step, the semiconductor substrate 10 is set in the dicing apparatus such that the dicing tape 31 is attached to the first main surface S1 having a flat surface, and the first main surface S1 faces the stage 50 of the dicing apparatus. The The dicing blade 51 provided in the dicing apparatus is inserted into the semiconductor substrate 10 from the second main surface S2 side. The dicing apparatus estimates the position of the dicing line 60 and positions the dicing blade 51 by recognizing an image of the notch 70 functioning as an alignment mark formed on the outer edge (edge) of the semiconductor substrate 10. . Thereby, the semiconductor substrate 10 is cut along the dicing line 60, and the semiconductor element 11 is cut out (FIG. 11B).

  As described above, according to the semiconductor device 101 and the method for manufacturing the same according to the second embodiment of the present invention, the cutout portion 70 is formed in the outer edge portion (edge portion) of the semiconductor substrate 10. Even if the conductive film 15 that does not transmit visible light and infrared light that constitute the electrodes of the semiconductor element 11 is formed on the bottom surface S3 of the semiconductor substrate 10, the cutout portion 70 can be recognized from the second main surface S2 side of the semiconductor substrate 10. It becomes possible. Therefore, the cutout portion 70 can be used as an alignment mark for positioning the dicing blade 51 in the dicing process of the semiconductor substrate 10. That is, the semiconductor device 101 according to the present embodiment includes the alignment mark that can be recognized by observation from the second main surface S2 side of the semiconductor substrate covered with the conductive film that does not transmit visible light or infrared light. Can be diced from the second main surface S2 side using an existing dicing apparatus.

  In the above embodiment, the case where the cutout portion 70 is formed by laser irradiation is exemplified. However, the cutout portion 70 is formed by cutting out the outer edge portion (edge portion) of the semiconductor substrate 10 with a dicing blade. It is also possible.

  Moreover, although the case where the notch part 70 was provided on the dicing line 60 was illustrated in said embodiment (refer FIG. 9), you may provide the notch part 70 in the position remove | deviated from the dicing line 60. FIG. That is, even when the alignment mark constituted by the notch portion 70 does not exist on the dicing line 60, the dicing blade 51 can be positioned based on the alignment mark.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Semiconductor element 12 Modification | denaturation part 13 Recessed part 14 Structure part 15 Conductive film 70 Notch part R1 Element formation area R2 Peripheral area | regions 100 and 101

Claims (13)

An element forming region in which a plurality of semiconductor elements are formed on a first main surface; and an outer peripheral region surrounding an outer periphery of the element forming region; and the second main surface opposite to the first main surface A semiconductor substrate having a recess recessed toward the first main surface in a region corresponding to an element formation region;
A modified portion provided in a region corresponding to the concave portion inside the semiconductor substrate;
A convex or concave structure portion provided at the formation position of the modified portion on the bottom surface of the concave portion;
A conductive film covering the structural portion and the bottom surface of the recess;
A semiconductor device including: The semiconductor device according to claim 1, wherein the convex or concave structure portion is provided on a bottom surface of the concave portion corresponding to a dividing line that partitions each of the plurality of semiconductor elements. The semiconductor device according to claim 1, wherein the conductive film does not transmit visible light and infrared light. The semiconductor substrate comprises single crystal silicon;
The semiconductor device according to claim 1, wherein the modified portion includes amorphous silicon. An element forming region in which a plurality of semiconductor elements are formed on a first main surface; and an outer peripheral region surrounding an outer periphery of the element forming region; and the second main surface opposite to the first main surface A semiconductor substrate having a recess recessed toward the first main surface in a region corresponding to an element formation region;
A notch provided in an outer edge of the semiconductor substrate;
A conductive film covering a bottom surface of the recess of the semiconductor substrate;
A semiconductor device including: A semiconductor substrate having an element forming region in which a plurality of semiconductor elements are formed on the first main surface and an outer peripheral region surrounding the outer periphery of the element forming region at a predetermined depth position in a region corresponding to the element forming region. Forming a modified portion in which the state of the semiconductor substrate has changed,
Forming a recess recessed toward the first main surface in a region corresponding to the element formation region of the second main surface opposite to the first main surface of the semiconductor substrate; Exposing the modified portion on the bottom surface;
Forming a convex or concave structure portion at a formation position of the modified portion by etching the bottom surface of the concave portion; and
A step of covering the bottom surface of the recess with a conductive film with a thickness capable of recognizing irregularities formed on the bottom surface of the recess by the convex or concave structure portion;
A method of manufacturing a semiconductor device including: The manufacturing method according to claim 6, wherein the modified portion is formed by irradiating the semiconductor substrate with a laser. The manufacturing method according to claim 6, wherein the recess is formed by grinding the second main surface of the semiconductor substrate. The manufacturing method according to claim 6, wherein the concave portion is formed by etching the second main surface of the semiconductor substrate, and the convex or concave structural portion is formed. 10. The method according to claim 6, further comprising a step of dividing the plurality of semiconductor elements into individual pieces by using the unevenness formed on the bottom surface of the concave portion by the convex or concave structure portion as an alignment mark. The manufacturing method as described in. Forming a notch in an outer edge portion of a semiconductor substrate having an element forming region in which a plurality of semiconductor elements are formed on the first main surface and an outer peripheral region surrounding the outer periphery of the element forming region;
Forming a recess recessed toward the first main surface in a region corresponding to the element formation region of the second main surface opposite to the first main surface of the semiconductor substrate;
Coating the bottom surface of the recess with a conductive film;
A method of manufacturing a semiconductor device including: The manufacturing method according to claim 11, wherein the notch is formed by irradiating the semiconductor substrate with a laser. The manufacturing method according to claim 11, further comprising a step of separating the plurality of semiconductor elements using the notch as an alignment mark.