JP2017033963A - Thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor in which an Al alloy having a low electric resistivity and excellent heat resistance is used for a gate electrode, a source/drain electrode, or the like.SOLUTION: A thin film transistor has a gate electrode, a gate insulation film, an oxide semiconductor layer, a source/drain electrode and a protection film of the source/drain electrode at least on a substrate in this order. The oxide semiconductor layer contains In, Ga, O and at least one of Zn and Sn; and at least one electrode of the gate electrode and the source/drain electrode is an Al alloy containing at least one element selected from a group A consisting of Ni and Co, at least one element selected from a group B consisting of Cu and Ge, and at least one element selected from a group C consisting of La, Gd and Nd, in which a total content rate of the group A to the Al alloy is not less than 0.05 atom% and not more than 5 atom%, a total content rate of the group B to the Al alloy is not less than 0.10 atom% and not more than 2 atom%, and a total content rate of the group C to the Al alloy is not less than 0.10 atom% and not more than 1 atom%.SELECTED DRAWING: None

Description

  The present invention relates to a thin film transistor, and more particularly to a thin film transistor used in a display device such as a liquid crystal display or an organic EL display.

  The Al alloy has a low electrical resistivity and is easy to process. For this reason, a liquid crystal display (LCD), a plasma display panel (PDP), an electroluminescence display (ELD), and so on. ), Field Emission Display (FED: Field Emission Display), Micro Electro Mechanical Systems (MEMS), and other flat panel displays (FPD: Flat Panel Display), touch panels, and electronic paper. , Wiring film, electrode film, It is utilized in materials such morphism electrode film.

  For example, an active matrix liquid crystal display includes a TFT substrate having a thin film transistor (TFT) that is a switching element, a pixel electrode formed of a conductive oxide film, and a wiring including a scanning line and a signal line. The scanning lines and signal lines are electrically connected to the pixel electrodes. In general, pure Al or Al—Nd alloy thin films are used as the wiring material constituting the scanning lines and signal lines. However, when these thin films are brought into direct contact with the pixel electrodes, insulating aluminum oxide or the like is brought into the interface. As a result, the contact electric resistance increases.

  Therefore, in order to provide a technique (direct contact technique) capable of directly contacting the conductive oxide film constituting the pixel electrode with the wiring material without using the barrier metal layer, as the wiring material, Al—Ni alloy or A method of using a thin film of an Al—Ni—rare earth element alloy further containing rare earth elements such as Nd and Y has been proposed (Patent Document 1). By using the alloy, the contact electrical resistance can be kept low, and the heat resistance can be further increased.

  In Patent Documents 2 and 3, the contact electrical resistance is reduced by providing a barrier layer having a laminated structure of a refractory metal thin film and a Si thin film or a Ti oxide film, thereby achieving fine workability. We have proposed an excellent wiring structure and a wiring structure capable of forming a stable interface between an oxide semiconductor layer and a metal wiring film such as a source / drain electrode. Further, pure Al having a low electrical resistivity is used for the metal wiring film.

  On the other hand, in the sputtering method used for the formation of an Al alloy thin film, in recent years, the film forming rate during the sputtering process tends to be higher than before in order to cope with the improvement in productivity of FPD. Increasing the sputtering power is the easiest way to increase the deposition rate. However, increasing the sputtering power causes sputtering defects such as splash (fine molten particles) and defects in the wiring film. As a result, adverse effects such as a decrease in the yield and operating performance of the FPD are brought about.

Therefore, various methods for preventing the occurrence of splash have been studied. In Patent Document 4, an Al— (Ni, Co) — (Cu, Ge) — (La, Gd, Nd) alloy is used as a sputtering target. A sputtering target having a Vickers hardness (HV) of 35 or more has been disclosed as a sputtering target that can effectively prevent splashing.
In addition, Patent Document 5 discloses a sputtering that can be generated when a film is formed using an Al—Ni—La—Cu-based Al-based alloy sputtering target containing Ni, La, and Cu, and in particular, a sputtering that can reduce initial splash. As a target, the total area of an Al—Ni-based intermetallic compound having an average particle size in the range of 0.3 μm to 3 μm and an Al—La—Cu intermetallic compound having an average particle size of 0.2 μm to 2 μm is used. A suitable sputtering target is disclosed.

JP 2004-214606 A JP 2012-119664 A JP 2012-94853 A JP 2009-263768 A JP 2009-242909 A

  However, in a thin film transistor including an oxide semiconductor layer (hereinafter sometimes referred to as “oxide semiconductor TFT”), materials used for a gate electrode and a source / drain electrode include, in addition to low electrical resistivity, Excellent heat resistance is also required. The reason is as follows.

When manufacturing an oxide semiconductor TFT, it is necessary to pass through a specific high-temperature and long-time heating step a plurality of times.
As the oxide semiconductor TFT, for example, there are an ESL (Etch Stop Layer) type as shown in FIG. 1A and a BCE (Back Channel Etching) type as shown in FIG.
The ESL type is manufactured by, for example, the process shown in FIG. 1B, and includes five heat treatment processes ([1] gate insulating film formation, [2] pre-annealing, [3] ESL film formation, [ 4) protective film formation and [6] post-annealing).
The BCE type is manufactured by, for example, the process shown in FIG. 1D, and includes six heat treatment processes ([1] gate insulating film formation, [2] pre-annealing, [4] protective film formation, [5] recovery annealing, [4 ′] protective film formation, and [6] post annealing).

  For this reason, the material used for at least one of the gate electrode and the source / drain electrode is required to have excellent heat resistance capable of withstanding such a high temperature, a long time, and a plurality of heating processes.

Further, a material used for at least one of the gate electrode and the source / drain electrode used for the oxide semiconductor TFT is required to have a low electric resistivity so as not to cause a delay of an electric signal.
An example of a material having a low electrical resistivity is pure Al. However, pure Al has insufficient heat resistance, and when a pure Al thin film is subjected to the above-described high temperature, long time, and multiple heating steps, Al crystal grains grow and the surface of the thin film becomes rough. If the surface of the thin film becomes rough, the surface of the thin film formed on the upper layer of the thin film also becomes rough, and the step coverage of the protective film becomes insufficient. Hydrogen diffuses through the portion where the step coverage is insufficient and reaches the oxide semiconductor layer, so that the performance of the oxide semiconductor TFT is deteriorated.

  That is, the present invention has been made in view of the above circumstances, and an object thereof is to provide a thin film transistor using an Al alloy having a low electrical resistivity and excellent heat resistance as a gate electrode and source / drain electrodes.

  As a result of intensive studies, the inventors of the present invention have made the gate electrode and the source / drain electrode an Al alloy having a specific composition, and made the oxide semiconductor layer O and at least one of Zn, Sn, and O. And the present invention has been completed.

That is, the present invention relates to the following [1] to [3].
[1] A thin film transistor having at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source / drain electrode, and a protective film for the source / drain electrode in this order on a substrate,
The oxide semiconductor layer includes In, Ga, at least one of Zn and Sn, and O;
At least one element selected from the group A consisting of Ni and Co, and at least one element selected from the group B consisting of Cu and Ge, at least one of the gate electrode and the source / drain electrode; Al alloy containing at least one element selected from C group consisting of La, Gd and Nd,
The total content of the Al alloy in the group A is 0.05 atomic% or more and 5 atomic% or less,
The total content of the B group with respect to the Al alloy is 0.10 atomic% or more and 2 atomic% or less, and the total content with respect to the Al alloy of the C group is 0.10 atomic% or more and 1 atomic% or less. A thin film transistor.
[2] The Al alloy contains Ni, Cu and La,
The content of Ni with respect to the Al alloy is 0.05 atomic% or more and 5 atomic% or less,
The content of Cu with respect to the Al alloy is 0.10 atomic% or more and 2 atomic% or less, and the content of La with respect to the Al alloy is 0.10 atomic% or more and 1 atomic% or less. The thin film transistor according to [1].
[3] The thin film transistor according to [1] or [2], wherein the oxide semiconductor layer is In—Ga—Zn—O, In—Ga—Sn—O, or In—Ga—Zn—Sn—O.

  According to the present invention, since the Al alloy used for at least one of the gate electrode and the source / drain electrode is excellent in heat resistance, the performance of the oxide semiconductor TFT deteriorated due to the growth of Al crystal grains. Can be prevented. Further, since the Al alloy has a low electrical resistivity, it is possible to prevent a delay of the electrical signal. That is, according to the present invention, an oxide semiconductor TFT with good performance can be manufactured.

FIG. 1A is a schematic cross-sectional view for explaining an ESL type of an oxide semiconductor TFT, and FIG. 1B is a flowchart showing an example of a manufacturing process of the ESL type. FIG. 1C is a schematic cross-sectional view for explaining a BCE type of an oxide semiconductor TFT, and FIG. 1D is a flowchart showing an example of a manufacturing process of the BCE type. FIG. 2 is a SEM photograph of a cross section after the first heating step of the pure Al gate electrode of Test Example 1-1. FIG. 3 is an SEM photograph of a cross section of the pure Al gate electrode of Test Example 1-1 after the second heating step. FIG. 4 is an SEM photograph of a cross section after the first heating step of the pure Al gate electrode of Test Example 1-2. FIG. 5 is an SEM photograph of a cross section of the pure Al gate electrode of Test Example 1-2 after the second heating step. FIG. 6 is an SEM photograph of a cross section of the Al—Ni—Cu—La alloy gate electrode of Test Example 2-1 after the second heating step. FIG. 7 is an SEM photograph of a cross section after the second heating step of the Al—Ni—Cu—La alloy gate electrode of Test Example 2-2. FIG. 8 is a graph showing the relationship between the electrical resistivity of the Al—Ni—Cu—La alloy layer of Test Example 3 and the heat treatment temperature.

  The thin film transistor (TFT) of the present invention has at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source / drain electrode, and a protective film for the source / drain electrode in this order on a substrate. The layer includes at least one of In, Ga, Zn and Sn, and O, and at least one of the gate electrode and the source / drain electrode is an Al alloy having a specific composition. To do.

<Gate electrode and source / drain electrode>
At least one of the gate electrode and the source / drain electrode is made of an Al alloy.
The Al alloy is selected from at least one element selected from the A group consisting of Ni and Co, at least one element selected from the B group consisting of Cu and Ge, and the C group consisting of La, Gd and Nd. Al alloy containing at least one element. By including the elements of Group A to Group C, the heat resistance is excellent and a low electrical resistivity can be obtained.
The contents of Group A, Group B and Group C contained in the Al alloy are such that the total content of Group A with respect to the Al alloy is 0.05 atomic% or more and 5 atomic% or less, and the total content of Group B is 0.10 atoms. % To 2 atomic% and the total content of group C is 0.10 atomic% to 1 atomic%.
By setting the A group, the B group, and the C group as the above lower limits, it is possible to effectively exhibit the effect of preventing deterioration of the TFT performance caused by the growth of Al crystal grains. Moreover, the low electrical resistivity of an Al alloy thin film can be maintained by setting it as the said upper limit.

  The total content of Group A is preferably 0.1 atomic percent or more, more preferably 0.2 atomic percent or more. On the other hand, it is preferably 4 atom% or less, more preferably 3 atom% or less.

  The total content of Group B is preferably 0.2 atomic percent or more, and more preferably 0.3 atomic percent or more. On the other hand, it is preferably 1.5 atomic percent or less, more preferably 1 atomic percent or less.

  The total content of Group C is preferably 0.2 atomic percent or more, and more preferably 0.3 atomic percent or more. On the other hand, it is preferably 0.8 atomic% or less, more preferably 0.6 atomic% or less.

Since both Ni and Co have the properties of low electrical resistance and improved heat resistance associated with the addition, it is sufficient that the group A contains at least one element of Ni and Co.
Since Cu and Ge both have the property of suppressing the growth of crystal grains when added, it is sufficient that at least one element of Cu and Ge is contained as the B group.
Since all of La, Gd, and Nd have the property of improving heat resistance when added, it is sufficient that at least one element selected from La, Gd, and Nd is included as the C group.

Among them, the Al alloy contains Ni, Cu and La, the Ni content with respect to the Al alloy is 0.05 atomic% to 5 atomic%, the Cu content is 0.10 atomic% to 2 atomic%, And it is more preferable that the content rate of La is 0.10 atomic% or more and 1 atomic% or less.
By setting Ni, Cu, and La to the above lower limits, the effect of preventing deterioration of TFT performance caused by the growth of Al crystal grains can be exhibited more effectively. Moreover, the low electrical resistivity of an Al alloy thin film can be maintained by setting it as the said upper limit.

  Ni is preferably 0.05 atomic percent or more and 5 atomic percent or less, more preferably 0.1 atomic percent or more, and still more preferably 0.2 atomic percent or more. On the other hand, it is more preferably 4 atomic% or less, still more preferably 3 atomic% or less.

  Cu is preferably 0.10 atomic% or more and 2 atomic% or less, more preferably 0.2 atomic% or more, and still more preferably 0.3 atomic% or more. On the other hand, it is more preferably 1.5 atomic% or less, still more preferably 1 atomic% or less.

  La is preferably 0.10 atomic% or more and 1 atomic% or less, more preferably 0.2 atomic% or more, and still more preferably 0.3 atomic% or more. On the other hand, it is more preferably 0.8 atomic% or less, and still more preferably 0.6 atomic% or less.

The reason why the Al alloy is excellent in heat resistance while having a low electrical resistivity is considered as follows.
The elements constituting Group A (Ni, Co), Group B (Cu, Ge), and Group C (La, Gd, Nd) are all elements with a small increase in electrical resistivity relative to an increase in the content of the element. is there. Therefore, it is possible to increase the content of the elements of the A group to the C group while maintaining the low electrical resistivity of the entire Al alloy.
In particular, since Ni, Cu and La are all elements having a smaller electrical resistivity increase rate with respect to an increase in the content of the element, Ni, Cu are maintained while maintaining the low electrical resistivity of the entire Al alloy. And the content rate of La can be made higher.

Moreover, when forming Al alloy by sputtering method, the element of A group, B group, and C group after forming by sputtering method exists in a solid solution state. In the first heating step, these are solid-solution strengthened and the Al crystal grain growth is suppressed, whereby the flatness of the thin film can be maintained. By this first heating step, the elements of Group A, Group B, and Group C form an intermetallic compound with Al.
This intermetallic compound strengthens the precipitation in the second and subsequent heating steps, and suppresses Al crystal grain growth, whereby the flatness of the thin film (the state where the average roughness Ra is small) can be maintained. As a result, it is considered that TFT performance deterioration can be prevented and a TFT with good performance can be manufactured.

  Examples of Al alloys including A group, B group and C group include Al-Ni-Cu-La alloy, Al-Ni-Cu-Gd alloy, Al-Ni-Cu-Nd alloy, Al-Ni-Ge- La alloy, Al—Ni—Ge—Gd alloy, Al—Ni—Ge—Nd alloy, Al—Co—Cu—La alloy, Al—Co—Cu—Gd alloy, Al—Co—Cu—Nd alloy, Al— Examples include a Co—Ge—La alloy, an Al—Co—Ge—Gd alloy, and an Al—Co—Ge—Nd alloy. Among these, an Al—Ni—Cu—La alloy is particularly preferable.

  Al alloy is used for at least one of a gate electrode and a source / drain electrode. It is more preferable from the viewpoint of heat resistance that both the gate electrode and the source / drain electrode are made of the Al alloy. When both the gate electrode and the source / drain electrode are made of an Al alloy, the composition thereof may be the same or different, but the gate electrode is more preferably lower in resistance from the subsequent heat treatment temperature.

Moreover, what formed Mo thin film on this Al alloy is good also as a gate electrode. The Mo thin film may be a Mo single layer or a laminated film containing Mo, and can be formed by a commonly used method such as a sputtering method.
The film thickness of the Mo thin film is preferably 100 to 500 μm from the viewpoint of electrical resistance, and more preferably 200 to 300 μm. The film thickness can be changed by adjusting the sputtering time and the current value. The film thickness can be measured by step measurement or SEM observation.

As the source / drain electrodes other than the Al alloy, those conventionally used in general can be used. Among these, a Mo film, a Mo alloy film, a Cu film, a Cu alloy film, a Ti film, a Ti alloy film, and a laminated film obtained by laminating them are preferable from the viewpoint of corrosion resistance and contact resistance.
These films can be formed by a sputtering method.

As the gate electrode other than the Al alloy, those conventionally used in general can be used. Of these, pure Mo thin film, Mo / Al / Mo, Cu / Mo, Cu / Ti, and the like are preferable in terms of heat resistance and resistivity.
These films can be formed by a sputtering method.

When an Al alloy is used for the gate electrode, it can be formed by a known method such as sputtering or vapor deposition. In the case of a sputtering method, a sputtering target having the same composition as the gate electrode can be used. As the sputtering method, a DC sputtering method, an RF sputtering method, or the like is preferably used.
When an Al alloy is used for the source / drain electrodes, it can be formed on the oxide semiconductor layer by a known method such as a sputtering method or a vapor deposition method. In the case of sputtering, it can be formed by using a sputtering target having the same composition as the source / drain electrodes. As the sputtering method, a DC sputtering method, an RF sputtering method, or the like is preferably used.

  The composition of the gate electrode and the source / drain electrode can be measured by ICP analysis.

The gate electrode preferably has a thickness of 100 to 500 μm from the viewpoint of electrical resistance, and more preferably 150 to 350 μm. In the case of the sputtering method, the film thickness can be changed by adjusting the sputtering time and the current value.
The source / drain electrodes preferably have a thickness of 100 to 400 μm from the viewpoint of electrical resistance, and more preferably 150 to 250 μm. In the case of the sputtering method, the film thickness can be changed by adjusting the sputtering time and the current value.
The thickness of the gate electrode and the source / drain electrode can be measured by SEM observation or a step meter.

<Oxide semiconductor layer>
The oxide semiconductor layer contains In, Ga, at least one of Zn and Sn, and O. That is, In—Ga—Zn—O, In—Ga—Sn—O, or In—Ga—Zn—Sn—O is preferable. By containing Sn, etching of the oxide semiconductor layer can be suppressed and damage to the surface of the oxide semiconductor layer can be suppressed even when exposed to an etching solution such as an inorganic etching solution containing fluoride in hydrogen peroxide solution. Is more preferable.

The oxide semiconductor layer preferably has a thickness of 20 to 100 μm from the viewpoint of TFT characteristics and uniformity of film thickness maintenance, and more preferably 30 to 50 μm. In the case of the sputtering method, the film thickness can be changed by adjusting the sputtering time and the current value.
The thickness of the oxide semiconductor layer can be measured by level difference measurement or SEM observation.

<Board>
As the substrate, those usually used can be used, and examples thereof include a transparent substrate, a Si substrate, a thin metal plate such as stainless steel, and a resin substrate such as a PET film. Among these, a glass substrate, quartz, and the like are preferable from the viewpoint of transparency, and examples include an alkali-free glass substrate, a high strain point glass substrate, and a soda lime glass substrate.
The thickness of the substrate is preferably 0.3 mm to 1.0 mm from the viewpoint of workability.

<Gate insulation film and protective film>
Each of the gate insulating film and the protective film may be a single layer or two or more layers, and those conventionally used can be used. For example, a silicon oxide film (SiOx film), a silicon nitride film (SiNx film), an oxide such as Al ₂ O ₃ or Y ₂ O ₃ , a laminated film of these, and the like can be given. The layer and the second and subsequent layers are preferably films having different components.

In the case of a single layer or in the case of two or more layers, the first layer (the layer directly bonded to the gate electrode or the source / drain electrode) is preferably an SiOx film because the optical stress resistance can be further improved.
The hydrogen concentration in the SiOx film is preferably 3 atomic% or less.

When the gate insulating film or the protective film has two or more layers, the SiOx film is preferable as the gate insulating film or the protective film in direct contact with the oxide semiconductor from the viewpoint of the hydrogen content.
The hydrogen concentration in the SiOx film is preferably 4.5 atomic% or less.

  By having the protective film, damage due to an etching solution containing fluoride in hydrogen peroxide used for etching such as patterning can be suppressed without deteriorating the static characteristics of the TFT. That is, a TFT having a uniform oxide semiconductor layer thickness and excellent static characteristics and stress resistance can be obtained.

Both the gate insulating film and the protective film can be formed by a commonly used method, and examples thereof include a CVD (Chemical Vapor Deposition) method.
For example, in the case of a gate insulating film, it is preferable to form a SiOx film by performing plasma CVD using SiH ₄ gas or N ₂ O gas as a carrier gas.
Further, for example, in the case of a protective film, it is also preferable to perform a plasma CVD method using SiH ₄ gas or N ₂ O gas as a carrier gas to form a SiOx film and to form a SiNx film as the uppermost layer.

The thickness of the gate insulating film is preferably 50 to 300 μm from the viewpoint of the capacitance of the thin film transistor, and more preferably 100 to 250 μm. When the gate insulating film is a laminated film of two or more layers, the total film thickness is preferably in the above range.
In the case of the CVD method, the film thickness can be changed by adjusting the film formation time.
The thickness of the gate insulating film can be measured by optical measurement, level difference measurement, or SEM observation.

The protective film preferably has a thickness of 100 to 500 μm, more preferably 250 to 300 μm. When the protective film is a laminated film of two or more layers, the total film thickness is preferably in the above range.
In the case of the CVD method, the film thickness can be changed by adjusting the film formation time.
The thickness of the protective film can be measured by optical measurement, level difference measurement, or SEM observation.

<Method for Manufacturing Thin Film Transistor>
The thin film transistor according to the present invention is not limited to the BCE type and the ESL type, and can be manufactured by the same method and conditions as in the past. The BCE TFT has a smaller number of mask forming steps than the ESL TFT, and can sufficiently reduce the cost. Further, since there is no overlap between the etch stopper layer and the source / drain electrodes, the size can be reduced as compared with the ESL type TFT.

TFT can be manufactured by a normal method. Although an example of the manufacturing method of TFT is described in FIG.1 (b), FIG.1 (d), and an Example, it is not limited to these.
That is, the manufacturing method in FIG.1 (b) and FIG.1 (d) is as follows.
A gate electrode is formed on the substrate by sputtering or the like, patterned, and then a gate insulating film is formed by CVD or the like. Patterning can be performed by a usual method. Further, heating is performed in the formation of the gate insulating film.
Next, an oxide semiconductor layer is formed by sputtering or the like and patterned. Thereafter, pre-annealing is performed, and in the case of an ESL type TFT, an ESL layer is formed and patterned.
Subsequently, source / drain electrodes are formed by sputtering or the like and patterned, and then a protective film is formed. Heating is also performed in the formation of the protective film. In the case of a BCE type TFT, after performing recovery annealing, a protective film is formed again.
Thereafter, contact holes are etched and post-annealed to obtain TFTs.

EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples, but the present invention is not limited to these examples.
[Test Example 1-1]
On a glass substrate (Corning Eagle XG, diameter 100 mm × thickness 0.7 mm), a pure Al film of 200 nm is formed as a gate electrode, and a Mo thin film of 100 nm is formed thereon, and then a SiOx film (film) is formed as a gate insulating film. A film having a thickness of 250 nm) was formed. This is referred to as a “first heating step” because heating is involved in the formation of the gate insulating film. The deposition conditions for the pure Al film, the Mo thin film, and the SiOx film are as follows.

(Pure Al film formation conditions)
Film formation method: DC sputtering method Apparatus: ULVAC, CS-200
Sputtering target: Pure Al
Deposition temperature: Room temperature Deposition power: 300W

(Mo thin film formation conditions)
Film formation method: DC sputtering method Apparatus: ULVAC, CS-200
Sputtering target: Pure Al
Deposition temperature: Room temperature Deposition power: 300W

(SiOx film formation conditions)
Film formation method: plasma CVD method apparatus: PD-220NL, manufactured by Samco
Carrier gas: SiH ₄ , N ₂ O
Deposition temperature: 320 ° C
Deposition time: 18 minutes

  The SEM photograph of the cross section after the first heating step is shown in FIG. As a result, Al crystal grains of a pure Al gate electrode (pure Al (200 nm)) grow, the surface of the thin film becomes rough, the Mo thin film (Mo (100 nm)) on the upper layer of the thin film, and the gate insulator (Gate insulator). It was found that the surface of (SiOx) was also roughened. Note that the oxide semiconductor layer (Active) and the protective film (C protective layer) in FIG. 2 are experimentally formed for SEM observation, and are different from the oxide semiconductor layer and protective film for TFT.

Next, as an oxide semiconductor layer, a Ga—In—Zn—Sn—O film was formed to a thickness of 40 nm under the following conditions. Thereafter, pre-annealing treatment was performed at 350 ° C. for 1 hour in an air atmosphere. This pre-annealing process is called a “second heating step”.
The SEM photograph of the cross section after the second heating step is shown in FIG. As a result, the surfaces of the pure Al gate electrode (pure Al (200 nm)), the Mo thin film (Mo (100 nm)), the gate insulating film (Gate insulator SiOx), and the oxide semiconductor layer (Active) must be rough. Was confirmed. In addition, the protective film (C protective layer) in FIG. 3 is formed on a trial basis for SEM observation, and is different from the protective film for TFT.

(Oxide semiconductor layer formation conditions)
Film formation method: DC sputtering method Equipment: ULVAC, CS2000
Sputtering target: Ga: In: Zn: Sn = 16.8: 16.6: 47.2: 19.4 (atomic ratio)
Deposition temperature: room temperature

(Test Example 1-2)
Film formation is performed for the gate insulating film to be a SiOx / SiNx laminated film in which the first layer (layer directly bonded to the gate electrode) is a 100 nm thick SiOx film and the second layer is a 150 nm thick SiNx film. The first heating step was performed in the same manner as in Test Example 1-1 except that the carrier gas was changed to N ₃ and NH ₂ to NH ₃ as conditions.

The SEM photograph of the cross section after the first heating step is shown in FIG.
As a result, Al crystal grains of a pure Al gate electrode (pure Al (200 nm)) grow, the surface of the thin film becomes rough, the Mo thin film (Mo (100 nm)) on the upper layer of the thin film, and the gate insulator (Gate insulator). It was found that the surface of (SiOx) was also roughened. Note that the oxide semiconductor layer (Active) and the protective film (C protective layer) in FIG. 4 are experimentally formed for SEM observation, and are different from the oxide semiconductor layer and the protective film for TFT.

Next, an oxide semiconductor layer having the same composition was formed as in Test Example 1-1, and pre-annealing treatment (second heating step) was performed under the same conditions.
The SEM photograph of the cross section after the second heating step is shown in FIG. As a result, the surfaces of the pure Al gate electrode (pure Al (200 nm)), the Mo thin film (Mo (100 nm)), the gate insulating film (Gate insulator SiOx), and the oxide semiconductor layer (Active) must be rough. Was confirmed. In addition, the protective film (C protective layer) in FIG. 5 is formed on a trial basis for SEM observation, and is different from the protective film for TFT.

(Test Example 2-1)
A gate electrode was formed in the same manner as in Test Example 1-1 except that a sputtering target having an Al-1.0 atomic% Ni-0.5 atomic% Cu-0.3 atomic% La composition was used and the film formation time was changed. One heating step and a second heating step were performed. The SEM photograph of the cross section after the second heating step is shown in FIG.
As a result, an intermetallic compound is formed in the Al-1.0 atomic% Ni-0.5 atomic% Cu-0.3 atomic% La alloy layer, Al crystal grain growth is suppressed, and the surface flatness of the thin film is suppressed. Was confirmed to be maintained. It was confirmed that the surface flatness of the Mo thin film (Mo (100 nm)), the gate insulating film (Gate insulator SiOx), and the oxide semiconductor layer (Active) as the upper layer of the thin film was also maintained. In addition, the protective film (C protective layer) in FIG. 6 is formed on a trial basis for SEM observation, and is different from the protective film for TFT.

(Test Example 2-2)
The first heating step and the second heating step were performed in the same manner as in Test Example 2-1, except that the gate insulating film was the same SiOx / SiNx laminated film as in Test Example 1-2. The SEM photograph of the cross section after the second heating step is shown in FIG.
As a result, an intermetallic compound is formed in the Al-1.0 atomic% Ni-0.5 atomic% Cu-0.3 atomic% La alloy layer, Al crystal grain growth is suppressed, and the surface flatness of the thin film is suppressed. Was confirmed to be maintained. It was confirmed that the flatness of the surfaces of the Mo thin film (Mo (100 nm)), the gate insulating film (Gate insulator SiOx / SiNx), and the oxide semiconductor layer (Active) as the upper layer of the thin film was also maintained. Note that the protective film (C protective layer) in FIG. 7 is formed on a trial basis for SEM observation, and is different from the protective film for TFT.

(Test Example 3)
About the same Al-1.0 atomic% Ni-0.5 atomic% Cu-0.3 atomic% La alloy thin film (film thickness 200 nm) used in Test Example 2-1 and Test Example 2-2, the atmosphere Heat treatment was performed at 200 ° C., 250 ° C., 300 ° C. and 350 ° C. for 60 minutes in an atmosphere. The electrical resistivity after the heat treatment was measured. The measurement conditions are shown below.

(Conditions for measuring electrical resistivity)
Measurement method: DC 4-terminal method Device: manufactured by Hioki Electric Co., Ltd., milliohm high tester 3540
Measurement atmosphere: Air Measurement temperature: Room temperature

The relationship between electrical resistivity and heat treatment temperature is shown in FIG.
As a result, a low electrical resistivity of about 4 μΩ · cm or less was obtained by performing the heat treatment at 250 ° C. or higher as compared with the case without heat treatment (25 ° C.).

(Comparative Example 1)
On a glass substrate (Corning Eagle XG, diameter 100 mm × thickness 0.7 mm), a pure Al film of 200 nm is formed as a gate electrode, and a Mo thin film of 100 nm is formed thereon, and then a SiOx film (film) is formed as a gate insulating film. A film having a thickness of 250 nm) was formed. Next, a Ga—In—Zn—Sn—O film with a thickness of 40 nm was formed as the oxide semiconductor layer.
The deposition conditions for the pure Al film, the Mo thin film, the SiOx film, and the oxide semiconductor layer are all the same as in Test Example 1-1.
Next, source / drain electrodes were formed. Specifically, a pure Mo film was formed to a thickness of 100 nm under the same conditions as the gate electrode. Thereafter, patterning was performed by photolithography and wet etching. For patterning, a mixed acid etching solution composed of phosphoric acid, nitric acid, acetic acid, and water was used. The channel length of the TFT was set to 10 μm and the channel width was set to 200 μm by patterning the source / drain electrodes. In order to prevent the source / drain electrodes from being short-circuited, 50% over-etching was performed on the electrode film thickness.

  Thereafter, a SiOx film having a thickness of 200 nm and a SiNx film having a thickness of 150 nm were formed as protective films, and a thin film transistor TFT-1 was produced. The conditions for forming the protective film are shown below.

(SiOx film formation conditions)
Film formation method: plasma CVD method apparatus: PD-220NL, manufactured by Samco
Carrier gas: SiH ₄ , N ₂ O
Deposition temperature: 230 ° C
Film forming power: 100W
(SiNx film formation conditions)
Film formation method: plasma CVD method apparatus: PD-220NL, manufactured by Samco
Carrier gas: SiH ₄ , NH ₃
Deposition temperature: 150 ° C
Film forming power: 100W

(Comparative Example 2)
A thin film transistor TFT-2 was produced in the same manner as in Comparative Example 1 except that the gate electrode and the source / drain electrode were made of an Al-1.0 atomic% Si alloy layer.
The film forming conditions for the Al-1.0 atomic% Si alloy layer are as follows.

(Al-1.0 atomic% Si alloy layer deposition conditions)
Film formation method: DC sputtering method Apparatus: ULVAC, CS-200
Sputtering target: Al-1.0 atomic% Si
Deposition temperature: Room temperature Deposition power: 300W
Gas pressure: 2 mTorr

(Comparative Example 3)
A thin film transistor TFT-3 was produced in the same manner as in Comparative Example 1 except that the gate electrode and the source / drain electrode were made of an Al-1.0 atomic% Mg alloy layer.
The film forming conditions for the Al-1.0 atomic% Mg alloy layer are as follows.

(Al-1.0 atomic% Mg alloy layer deposition conditions)
Film formation method: DC sputtering method Apparatus: ULVAC, CS-200
Sputtering target: Al-1.0 atomic% Mg
Deposition temperature: Room temperature Deposition power: 300W
Gas pressure: 2 mTorr

Example 1
A thin film transistor TFT-4 is manufactured in the same manner as in Comparative Example 1 except that the gate electrode and the source / drain electrode are made of an Al-1.0 atomic% Ni-0.5 atomic% Cu-0.3 atomic% La alloy layer. did.
The film forming conditions for the Al-1.0 atomic% Ni-0.5 atomic% Cu-0.3 atomic% La alloy layer are as follows.

(Al-1.0 atomic% Ni-0.5 atomic% Cu-0.3 atomic% La alloy layer deposition condition)
Film formation method: DC sputtering method Apparatus: ULVAC, CS-200
Sputtering target: Al-1.0 atomic% Ni-0.5 atomic% Cu-0.3 atomic% La
Deposition temperature: Room temperature Deposition power: 300W
Gas pressure: 2 mTorr

[Evaluation of stress tolerance (S value)]
Stress resistance (S value) was evaluated as follows using the thin film transistors TFT-1 to TFT-4 of Example 1 and Comparative Examples 1 to 3.
The gate voltage and the source / drain electrode voltage were set as follows, and the I _d -V _g characteristics were measured using a prober and a semiconductor parameter analyzer (Keithley 4200SCS). “S value (V / dec)” obtained from the result of the I _d -V _g characteristic is shown in Table 1.
・ Gate voltage: -30-30V (step 0.25V)
・ Source voltage: 0V
・ Drain voltage: 10V
・ Measurement temperature: Room temperature

[Evaluation of light stress tolerance]
Using the thin film transistor TFT of Example 1 and Comparative Examples 1 to 3, a light stress application test was performed in which light was applied while applying a negative bias to the gate electrode, and the light stress resistance was evaluated as follows.
The light stress application conditions are as follows.
・ Gate voltage: -20V
・ Source-drain voltage: 10V
-Substrate temperature: 60 ° C
・ Light stress conditions:
Light stress application time: 2 hours Light intensity: 25000 NIT
Light source: White LED
・ Measurement temperature: Room temperature

The difference (ΔV _th ) in the threshold value (V _th , the difference in gate voltage when the drain current flows 10 ⁻⁹ A) before and after the optical stress application was measured. The evaluation results are summarized in “light stress resistance: absolute value of ΔV _th [V]” in Table 1.

In addition, “GIZTO” in Table 1 represents “Ga—In—Zn—Sn—O”.
“Comprehensive judgment” means that the S value is evaluated as “◯” when the S value is 0.45 V / dec or less, “△” when the S value is more than 0.45 V / dec and 1.00 V / dec or less, When the S value exceeds 1.00 V / dec, “X” is given, and when the optical stress resistance is evaluated, ΔV _{th has} an absolute value of 4.50 V or less, “◯”, and ΔV _{th has} an absolute value exceeding 4.50 V A value of 6.00 V or less is indicated by “Δ”, a value of ΔV _{th having} an absolute value exceeding 6.00 V is indicated by “X”, a value having both the S value and the absolute value of ΔV _th being “◯”, and “×”. The thing was made into "x".

  From the above evaluation results, the performance deterioration occurred in the thin film transistors TFT-1 to TFT-3 of Comparative Examples 1 to 3, whereas the gate electrode and the source / drain electrodes were made of Al-1.0 atomic% Ni-0.5. The thin film transistor TFT-4 of Example 1 in which the atomic% Cu-0.3 atomic% La alloy layer was used exhibited good performance.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate electrode 3 Gate insulating film 4 Oxide semiconductor layer 5 Source / drain electrode 6 Protective film 7 Contact hole 9 Etch stopper layer

Claims (3)

A thin film transistor having at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source / drain electrode, and a protective film for the source / drain electrode in this order on a substrate,
The oxide semiconductor layer includes In, Ga, at least one of Zn and Sn, and O;
At least one element selected from the group A consisting of Ni and Co, and at least one element selected from the group B consisting of Cu and Ge, at least one of the gate electrode and the source / drain electrode; Al alloy containing at least one element selected from C group consisting of La, Gd and Nd,
The total content of the Al alloy in the group A is 0.05 atomic% or more and 5 atomic% or less,
The total content of the B group with respect to the Al alloy is 0.10 atomic% or more and 2 atomic% or less, and the total content with respect to the Al alloy of the C group is 0.10 atomic% or more and 1 atomic% or less. A thin film transistor. The Al alloy contains Ni, Cu and La;
The content of Ni with respect to the Al alloy is 0.05 atomic% or more and 5 atomic% or less,
The content of Cu with respect to the Al alloy is 0.10 atomic% or more and 2 atomic% or less, and the content of La with respect to the Al alloy is 0.10 atomic% or more and 1 atomic% or less. Item 10. The thin film transistor according to Item 1.   The thin film transistor according to claim 1, wherein the oxide semiconductor layer is In—Ga—Zn—O, In—Ga—Sn—O, or In—Ga—Zn—Sn—O.