JP2017147573A - Ring oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ring oscillator in which a frequency is stabilized and an oscillation output with high accuracy can be obtained. SOLUTION: A ring oscillator in which odd-stage inverters 11, 12, and 13 operating by using an internal power supply voltage of a regulator 1 as a power source are connected in a ring shape and resistance elements R1, R2 connected between the inverters. , R3, a delay circuit composed of first capacitors C11, C21, C31 and second capacitors C12, C22, C32. Each output of the inverter becomes an input of the inverter of the next stage via the resistance element, and each input node of the inverter is connected to the internal power supply voltage via the first capacitor. Grounded via the second capacitor, which has the same capacitance value as the first capacitor, all inverting voltages of the inverter are half of the internal power supply voltage. [Selection diagram] Fig. 1

Description

  The present invention relates to a ring oscillation circuit that can stabilize the frequency and obtain a highly accurate oscillation output.

  The ring oscillation circuit is configured by connecting an odd number of inverters in series and connecting the output terminal of the final stage inverter to the input terminal of the frontmost stage inverter (see Patent Document 1 (particularly, see FIG. 4)). Each inverter oscillates if it cannot make a stable combination of input and output voltages. The oscillation frequency at this time is determined by the total delay time per stage of each inverter. Therefore, the adjustment of the oscillation frequency of the ring oscillation circuit is performed by adjusting the delay time of the delay circuit constituting the ring oscillation circuit.

  FIG. 2 shows an example of a conventional ring oscillation circuit. In the figure, inverters 101, 102, and 103 are connected in series between a first power supply voltage Vdd and a second power supply voltage Vss (GND), and the input of the inverter 101 and the output of the inverter 103 are connected in a ring shape. Has been. The resistor element 111 is connected between the output of the inverter 103 and the input of the inverter 101, and one end of the capacitor 121 connected to the second power supply voltage Vss is connected between the resistor element 111 and the input of the inverter 101. The other end is connected. Similarly, a resistance element 112 is connected between the output of the inverter 101 and the input of the inverter 102, and one end of the capacitor 122 is connected between the resistance element 112 and the input of the inverter 102 to the second power supply voltage Vss. Are connected at the other end. Further, a resistance element 113 is connected between the output of the inverter 102 and the input of the inverter 103, and one end of the capacitor 123 whose one end is connected to the second power supply voltage Vss is connected between the resistance element 113 and the input of the inverter 103. The other end is connected. That is, in FIG. 2, these inverters form a ring oscillation circuit with a delay circuit composed of each resistance element and capacitor interposed therebetween.

  When the output voltage of the inverter 101 changes from a low level to a high level, the capacitor 122 is charged through the inverter 101 and the resistance element 112 from the first power supply voltage Vdd. Since the equivalent resistance of the inverter 101 is usually negligibly small, the charging current of the capacitor 122 is determined by the resistance value of the resistance element 112, and the temporal change in the voltage rise of the capacitor 122 is the capacitance of the capacitor 122 and the charging current flowing through the resistance element 112. Determined by. In this way, the voltage of the capacitor 122 rises with time, and when the output voltage of the next inverter 102 reaches a voltage (threshold voltage Vt) necessary for inversion, the output voltage of the inverter 102 increases from a high level. Change to low level. Therefore, the output voltage of inverter 102 changes later than when the output voltage of inverter 101 changes. This delay is determined by a change in the voltage of the capacitor 122 over time. The delay time is approximately equal to the product of the capacitance value of the capacitor 122 and the resistance value of the resistance element 112, that is, the time constant of the delay circuit including the capacitor 122 and the resistance element 112.

When the output voltage of the inverter 102 changes from a high level to a low level, charging of the capacitor 122 changes to discharging through the inverter 102. In this way, the output voltage of the next inverter 103 also changes with a delay. Then, the output of the first inverter 101 changes next after the output voltage of the inverter 103 changes, after the capacitor 121 is charged and the input voltage of the inverter 101 becomes the threshold voltage.
Thus, the output voltage of the inverter changes with a period substantially equal to that of the delay circuit constituted by the resistance element and the capacitor connected to the output of each inverter.

  Patent Document 1 discloses a ring oscillator in which a plurality of CMOS inverters are connected in an odd number of stages, a resistance element connected between the output of the preceding CMOS inverter and the input of the next CMOS inverter, There is disclosed a temperature detection circuit using a ring oscillation circuit having a capacitor having one end connected to a connection point with the input of the CMOS inverter and a ground voltage applied to the other end.

Japanese Patent Laid-Open No. 2-147828

Assuming that a ring oscillator is used for a clock such as a clock, it is desirable to achieve high stabilization at a slow frequency divided by 1 sec or more. When integrating a ring oscillator on a single chip, the frequency fluctuates depending on the 1 / f noise generated by the active elements of the regulator and the oscillator. Compared to the oscillators etc., it is much worse. For example, when a three-stage ring oscillator is considered, there is a problem that the frequency of the inversion voltage Vt of the input greatly fluctuates due to fluctuation of 1 / f noise.
The present invention has been made under such circumstances, and provides a ring oscillator in which the frequency is stabilized and a highly accurate oscillation output can be obtained.

  One aspect of the ring oscillator according to the present invention includes a regulator that generates an internal power supply voltage, a ring oscillation unit configured by cascading an odd number of inverters that operate using the internal power supply voltage as a power supply, and the inverter A delay circuit composed of a resistor element, a first capacitor, and a second capacitor connected in between, and each output of the inverter is input to the inverter of the next stage through the resistor element, respectively. Each input node of the inverter is connected to the internal power supply voltage via the first capacitor and grounded via the second capacitor having the same capacitance value as the first capacitor. The inversion voltages of the inverters are one half of the internal power supply voltage.

  In the ring oscillator of the present invention, even if the inversion voltage (Vt) of the ring oscillator fluctuates greatly due to 1 / f noise of the regulator and the oscillation unit active element, the sum (one period) of the high (H) pulse period and the low (L) pulse period Becomes constant and is not affected by 1 / f noise. For this reason, the unstable frequency due to 1 / f noise is stabilized and a highly accurate oscillation output can be obtained.

1 is a circuit diagram for explaining a ring oscillator according to Embodiment 1. FIG. The circuit diagram explaining the conventional ring oscillator.

The ring oscillator of the present invention has an oscillation circuit composed of a plurality of inverters that operate by an internal power supply voltage, and an oscillation frequency is determined by a delay circuit composed of a resistance element and a capacitor connected between the inverters. The configuration is characterized in that the inversion level (threshold voltage Vt) of the inverter is accurately adjusted to ½ of the internal power supply, and the capacitor capacity is also divided and connected in half.
Hereinafter, embodiments of the invention will be described with reference to examples.

    The ring oscillator in this embodiment has a regulator circuit 1 that generates an internal power supply voltage Vreg and an odd number of stages (three in this embodiment) of inverters 11 to 13 that operate using the internal power supply voltage Vreg as a power supply. A delay composed of a ring oscillating unit configured as described above, resistance elements R1, R2, and R3, first capacitors C11, C21, and C31, and second capacitors C12, C22, and C32 connected between the inverters. Circuit. The output of each of these inverters becomes the input of the next-stage inverter through each resistance element. The input node of each of these inverters is connected to the internal power supply voltage Vreg via a first capacitor, and is grounded via a second capacitor having the same capacitance value as the first capacitor. And all the inversion voltages of an inverter are comprised so that it may be 1/2 of the internal power supply voltage Vreg.

FIG. 1 shows a ring oscillation circuit of this embodiment. In the figure, inverters 11, 12, and 13 are connected in series between the internal power supply voltage Vreg generated from the regulator circuit 1 and the ground voltage Vss (GND), and the input of the inverter 11 and the output of the inverter 13 are in a ring shape. To form a ring oscillator.
A resistance element R <b> 1 is connected between the output of the inverter 13 and the input of the inverter 11. The input node between the resistance element R1 and the input of the inverter 11 is connected to the internal power supply voltage Vreg via the first capacitor C11, and at the same time, the second capacitor C12 having the same capacitance value as the first capacitor C11 is connected. To the ground voltage Vss.

In addition, a resistance element R <b> 2 is connected between the output of the inverter 11 and the input of the inverter 12. The input node between the resistance element R2 and the input of the inverter 12 is connected to the internal power supply voltage Vreg via the first capacitor C21 and via the second capacitor C22 having the same capacitance value as the first capacitor C21. Are connected to the ground voltage Vss.
As shown in FIG. 1, this ring oscillation circuit is composed of an oscillation unit configured by connecting odd-numbered inverters in a ring shape, and a delay circuit including a resistance element and a capacitor arranged between the inverters. Has been.

Further, a resistance element R3 is connected between the output of the inverter 12 and the input of the inverter 13. The input node between the resistor element R3 and the input of the inverter 11 is connected to the internal power supply voltage Vreg via the first capacitor C31 and via the second capacitor C32 having the same capacitance value as the first capacitor C31. Are connected to the ground voltage Vss.
Furthermore, all the inversion voltages of the inverters used here are half of the internal power supply voltage Vreg generated from the regulator circuit 1.

  For example, when the output voltage of the inverter 11 changes from a low level to a high level, the capacitors C21 and C22 are charged from the internal power supply voltage Vreg through the inverter 11 and the resistance element R2. The charging current of these capacitors is substantially determined by the resistance value of the resistance element R2, and the temporal change in the voltage rise of the capacitors C21 and C22 is determined by the capacitance of the capacitors C21 and C22 and the charging current flowing through the resistance element C2. In this way, the voltages of the capacitors C21 and C22 rise with time, and when the output voltage of the next inverter 12 reaches a voltage (threshold voltage Vt) necessary for inversion, the output voltage of the inverter 12 is Change from high level to low level. Therefore, the output voltage of the inverter 12 changes later than when the output voltage of the inverter 11 changes. This delay is determined by the time variation of the voltages of the capacitors C21 and C22. The delay time is approximately equal to the product of the capacitance values of the capacitors C21 and C22 and the resistance value of the resistance element R2, that is, the time constant of the delay circuit including the capacitors C21 and C22 and the resistance element R2.

When the output voltage of the inverter 12 changes from a high level to a low level, the charging of the capacitors C31 and C32 changes to discharging through the inverter 12. In this way, the output voltage of the next inverter 13 also changes with a delay. Then, the output of the first inverter 11 changes next after the output voltage of the inverter 13 changes, after the capacitors C11 and C12 are charged and the input voltage of the inverter 11 becomes the threshold voltage.
Thus, the output voltage of the inverter changes with a period substantially equal to that of the delay circuit constituted by the resistance element and the capacitor connected to the output of each inverter.

As described above, the ring oscillator is configured by connecting inverters in odd stages in a ring shape in series, and basically has a configuration in which a signal is fed back after passing through an inverting delay circuit. Then, the state is inverted at regular time intervals and does not have a stable state and functions as an oscillation circuit. In the oscillation circuit, when the number of stages is n and the delay time per stage is represented by Td, the oscillation frequency f of the ring oscillator is represented by 1 / (2n · Td).
In this embodiment, n = 3, and the initial condition is that the output voltage of the inverter 11 starts from Vreg. Under this condition, the output voltage of the inverter 12 is Vss, and the output voltage of the inverter 13 is Vreg. When the operation starts, since the high voltage Vreg is input to the first inverter 11, this output voltage drops, the output voltage of the inverter 12 changes toward Vreg with a delay time Td, and further, The output voltage changes to the Vss level after the delay time Td. In this way, oscillation occurs so that the delay time of the voltage of the continuous nodes becomes Td.

In this embodiment, the ring oscillator is integrated on one chip. In this case, the oscillation frequency fluctuates depending on the 1 / f noise generated by the active elements of the regulator and the oscillation unit. The deterioration becomes worse. For example, the inversion level Vt greatly fluctuates due to 1 / f noise fluctuation. Therefore, in this embodiment, the inversion voltage Vt of the inverter is accurately adjusted to ½ of the internal power supply voltage Vreg which is a constant voltage from the regulator circuit. And the capacity | capacitance used for all the delay circuits divides and uses the 1st and 2nd capacitor.
With such a configuration, even if the inversion voltage Vt of the ring oscillator fluctuates greatly due to 1 / f noise of the regulator and the oscillation unit active element, it is one cycle (the sum of the high (H) pulse period and the low (L) pulse period). Becomes constant and is less susceptible to 1 / f noise. As a result, the unstable frequency due to 1 / f noise is stabilized and a highly accurate oscillation output can be obtained.

DESCRIPTION OF SYMBOLS 1 ... Regulator circuit 11, 12, 13 ... Inverter

Claims (1)

A regulator that generates an internal power supply voltage; a ring oscillation unit configured by cascading an odd number of inverters that operate using the internal power supply voltage as a power supply; a resistance element connected between the inverters; Each of the inverters becomes an input of the inverter of the next stage through the resistance element, and each input node of the inverter is And connected to the internal power supply voltage via the first capacitor and grounded via the second capacitor having the same capacitance value as the first capacitor, and all the inverted voltages of the inverter are A ring oscillator characterized by being half the internal power supply voltage.

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