JP2018051804A - Liquid ejection device and drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid discharge device and a drive circuit for improving the reproducibility of a waveform of a drive signal with respect to the waveform of the original drive signal. A first drive circuit 120a drives a piezoelectric element by a drive signal COM-A that is output from a node N1 and has a constant voltage over a certain period of time. The first drive circuit 120a amplifies the signal Ain, which is the source of the drive signal COM-A, during a period in which the voltage of the signal Ain changes, and outputs the amplifier circuit 200a from the node N1. It includes a voltage source E2a and a switch Sw2a that apply, for example, a voltage Vmin to the node N1 over a portion or all of them. [Selection diagram] Fig. 11

Description

  The present invention relates to a liquid ejection device and a drive circuit.

  2. Related Art An ink jet printer that prints an image or a document by ejecting ink is known that uses a piezoelectric element (for example, a piezo element). The piezoelectric element is provided corresponding to each of the plurality of nozzles in the head unit, and each is driven according to a drive signal. By this driving, a predetermined amount of ink (liquid) is ejected from the nozzles at a predetermined timing, and dots are formed. Since the piezoelectric element is a capacitive load such as a capacitor when viewed electrically, it is necessary to supply a sufficient current to operate the piezoelectric element of each nozzle.

  Therefore, the ink jet printer is configured to drive the piezoelectric element by amplifying the original drive signal, which is the source of the drive signal, with an amplifier circuit and supplying the amplified signal to the head unit as the drive signal. As the amplifier circuit, for example, class D amplification has been proposed (see Patent Document 1). In short, class D amplification modulates the original drive signal in pulses and switches the high-side and low-side transistors inserted in series between the power supply voltages in accordance with the modulation signal. The original drive signal is amplified by smoothing with a filter.

JP 2010-114711 A

By the way, in the liquid ejection device, if the waveform of the drive signal is not faithfully reproduced with respect to the waveform of the original drive signal, the liquid ejection accuracy is adversely affected.
Accordingly, one of the objects of some aspects of the present invention is to provide a liquid ejection apparatus and a drive circuit having good waveform reproducibility.

In order to achieve one of the above objects, a liquid ejection apparatus according to an aspect of the present invention is driven by a drive signal that is output from a predetermined output end and is constant at a first voltage over a first period. A discharge unit that includes a piezoelectric element and discharges liquid by driving the piezoelectric element, and an original drive signal that is a source of the drive signal is amplified during a period in which the voltage of the original drive signal is changed, and is supplied to the output terminal. An amplifier circuit to be supplied; and a constant voltage output circuit for applying the first voltage to the output terminal over part or all of the first period.
According to the liquid ejecting apparatus according to the above aspect, the portion of the drive signal in which the voltage changes is obtained by amplifying the original drive signal by the amplifier circuit, and the portion that is constant is constant. Since the voltage to which the first voltage is applied is used, it is possible to suppress the error at the time of transition from change to constant and the occurrence of ripples at a certain portion, thereby improving the waveform reproducibility.

In the liquid ejection apparatus according to the above aspect, the driving signal is constant at a second voltage different from the first voltage over a second period different from the first period, and the constant voltage output circuit is configured to output the second voltage from the second voltage period. The second voltage may be applied to the output terminal over part or all of the period.
In the above configuration, the constant voltage output circuit may variably output at least one of the first voltage and the second voltage.

In the liquid ejection apparatus according to the above aspect, the amplification circuit includes a high-side transistor connected between the output terminal and a power supply point of a power supply high-side voltage, and a power supply point of the output terminal and a power supply low-side voltage. A low-side transistor connected between, a differential amplifier that outputs a control signal obtained by amplifying a difference voltage between the voltage of the original drive signal and a voltage corresponding to the drive signal, and a voltage change of the original drive signal is increased In the first case, the control signal is selected and supplied to the gate terminal of the high side transistor, and in the second case, the voltage change of the original drive signal is in the decreasing direction, the control signal is selected. And a selector for supplying to the gate terminal of the low-side transistor.
In the above configuration, the selector selects a signal for turning off the low-side transistor in the first case and supplies the signal to the gate terminal of the low-side transistor, and a signal for turning off the high-side transistor in the second case. May be selected and supplied to the gate terminal of the high-side transistor.
In the above configuration, the selector selects a signal for turning off the high-side transistor for at least the first period, supplies the signal to the gate terminal of the high-side transistor, and selects a signal for turning off the low-side transistor. Then, it may be supplied to the gate terminal of the low-side transistor.

In order to achieve one of the above objects, the liquid ejection device according to another aspect of the present invention is output from the first output terminal, becomes constant at the first voltage over the first period, A first drive circuit that outputs a first drive signal that is constant at a second voltage over a period, and the first voltage that is output from a second output terminal and over a third period that overlaps a part of the first period. A second drive circuit that outputs a second drive signal that is constant at a time, and an ejection unit that ejects droplets in response to the first drive signal or the second drive signal, the first drive circuit comprising: A first amplification circuit that amplifies a first drive signal that is a source of the first drive signal during a period in which the voltage of the first drive signal changes and supplies the first drive signal to the first output terminal; and the first period The first voltage is applied to the output terminal over part or all of And a first constant voltage output circuit that applies the second voltage to the first output terminal over part or all of the second period, wherein the second drive circuit is a source of the second drive signal. A second amplification circuit that amplifies the second original drive signal during the period when the voltage of the second original drive signal changes and supplies the second original drive signal to the second output terminal, and part or all of the third period And a second constant voltage output circuit for applying the first voltage to the second output terminal.
According to the liquid ejection device according to another aspect, the waveform reproducibility can be improved, the configuration can be simplified, and the first voltage in the first drive circuit and the second drive circuit can be simplified. Variation can be suppressed.

The liquid ejecting apparatus may be any apparatus that ejects liquid, and includes a three-dimensional modeling apparatus (so-called 3D printer), a textile printing apparatus, and the like in addition to a printing apparatus described later.
Further, the present invention is not limited to the liquid ejection device, and can be realized in various modes. For example, the present invention can be conceptualized as a drive circuit that drives a capacitive load such as the piezoelectric element. .

1 is a diagram illustrating a schematic configuration of a printing apparatus. It is a figure which shows the arrangement | sequence etc. of the nozzle in the head unit of a printing apparatus. It is a figure which expands and shows the arrangement | sequence of a nozzle. It is sectional drawing which shows the principal part structure in a head unit. FIG. 3 is a block diagram illustrating an electrical configuration of the printing apparatus. It is a figure for demonstrating the waveform etc. of a drive signal. It is a figure which shows the structure of a selection control part. It is a figure which shows the decoding content of a decoder. It is a figure which shows the structure of a selection part. It is a figure which shows the drive signal supplied to a piezoelectric element from a selection part. It is a figure which shows the structure of the 1st drive circuit of a printing apparatus. It is a figure which shows the structure of the 2nd drive circuit of a printing apparatus. It is a figure which shows the structure of the amplifier circuit (the 1) in a 1st drive circuit. It is a figure for demonstrating operation | movement of a 1st drive circuit. It is a figure which shows another structure of the 1st drive circuit applicable to a printing apparatus. It is a figure which shows the structure of the amplifier circuit (the 2) applicable to a 1st drive circuit. It is a figure which shows the structure of the amplifier circuit (the 3) applicable to a 1st drive circuit.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings, taking a printing apparatus as an example.

FIG. 1 is a perspective view illustrating a schematic configuration of the printing apparatus 1.
The printing apparatus 1 shown in this figure forms ink dot groups on a medium P such as paper by ejecting ink, which is an example of a liquid, thereby printing an image (including characters, graphics, etc.). This is a kind of liquid ejection device.

As shown in FIG. 1, the printing apparatus 1 includes a moving mechanism 6 that moves (reciprocates) the carriage 20 in the main scanning direction (X direction).
The moving mechanism 6 includes a carriage motor 61 that moves the carriage 20, a carriage guide shaft 62 that is fixed at both ends, a timing belt 63 that extends substantially parallel to the carriage guide shaft 62, and is driven by the carriage motor 61, have.
The carriage 20 is supported by the carriage guide shaft 62 so as to be reciprocally movable, and is fixed to a part of the timing belt 63. Therefore, when the timing belt 63 is moved forward and backward by the carriage motor 61, the carriage 20 is guided by the carriage guide shaft 62 and reciprocates.

A print head 22 is mounted on the carriage 20. The print head 22 has a plurality of nozzles that individually eject ink in the Z direction at a portion facing the medium P. The print head 22 is roughly divided into four blocks for color printing. Each of the four blocks ejects black (Bk), cyan (C), magenta (M), and yellow (Y) ink, respectively.
The carriage 20 is configured to be supplied with various control signals and the like from a main board (not shown in the figure) via a flexible flat cable 190.

  The printing apparatus 1 includes a transport mechanism 8 that transports the medium P on the platen 80. The transport mechanism 8 includes a transport motor 81 that is a driving source, and a transport roller 82 that is rotated by the transport motor 81 and transports the medium P in the sub-scanning direction (Y direction).

In such a configuration, the surface of the medium P is repeatedly ejected from the nozzles of the print head 22 according to the print data in accordance with the main scanning of the carriage 20 and the operation of conveying the medium P by the conveyance mechanism 8 is repeated. An image is formed.
In the present embodiment, the main scan is executed by moving the carriage 20, but it may be executed by moving the medium P, or both the carriage 20 and the medium P may be moved. In short, any configuration is acceptable as long as the medium P and the carriage 20 (print head 22) move relatively.

  FIG. 2 is a diagram illustrating a configuration when the ink ejection surface of the print head 22 is viewed from the medium P. As shown in this figure, the print head 22 has four head units 3. Each of the four head units 3 corresponds to black (Bk), cyan (C), magenta (M), and yellow (Y), and is arranged along the X direction which is the main scanning direction.

FIG. 3 is a diagram illustrating an arrangement of nozzles in one head unit 3.
As shown in this figure, in one head unit 3, a plurality of nozzles N are arranged in two rows. Here, for convenience of explanation, these two rows are referred to as nozzle rows Na and Nb, respectively.

In the nozzle arrays Na and Nb, a plurality of nozzles N are arranged at a pitch P1 along the Y direction that is the sub-scanning direction. The nozzle rows Na and Nb are separated from each other by a pitch P2 in the X direction. The nozzles N belonging to the nozzle row Na and the nozzles N belonging to the nozzle row Nb have a relationship shifted in the Y direction by half the pitch P1.
In this way, by arranging the nozzles N in the two rows of nozzle rows Na and Nb and shifting by half of the pitch P1 in the Y direction, the resolution in the Y direction is substantially compared with the case of one row. Can be doubled.
For convenience, the number of nozzles N in one head unit 3 is m (m is an integer of 2 or more).

As will be described later, the head unit 3 includes a circuit board in which various elements are mounted on an actuator substrate including m nozzles N and piezoelectric elements provided corresponding to the m nozzles N, respectively. It is a connected configuration. For convenience of explanation, the structure of the actuator substrate will be described.
In this description, the connection means direct and indirect coupling between two or more elements, and includes that one or more intermediate elements exist between the two or more elements. In the above example, the circuit board is connected to the actuator board via, for example, FPC (Flexible Printed Circuits).

FIG. 4 is a cross-sectional view showing the structure of the actuator substrate. In detail, it is a figure which shows the cross section at the time of fracture | ruptured by the gg line in FIG.
As shown in FIG. 4, the actuator substrate 40 includes a pressure chamber substrate 44 and a diaphragm 46 on a negative side surface in the Z direction of the flow path substrate 42, while a positive side surface in the Z direction. It is a structure in which the nozzle plate 41 is installed on the top.
Each element of the actuator substrate 40 is a substantially flat member that is long in the Y direction, and is fixed to each other by, for example, an adhesive. The flow path substrate 42 and the pressure chamber substrate 44 are formed of, for example, a silicon single crystal substrate.

  The nozzle N is formed on the nozzle plate 41. The structure corresponding to the nozzles belonging to the nozzle row Na and the structure corresponding to the nozzles belonging to the nozzle row Nb are shifted by half the pitch P1 in the Y direction. Therefore, in the following, the structure of the actuator substrate 40 will be described focusing on the nozzle row Na.

  The flow path substrate 42 is a flat plate material that forms an ink flow path, and an opening 422, a supply flow path 424, and a communication flow path 426 are formed. The supply channel 424 and the communication channel 426 are formed for each nozzle, and the opening 422 is formed so as to be continuous over a plurality of nozzles, and has a structure in which ink of a corresponding color is supplied. The opening 422 functions as the liquid storage chamber Sr, and the bottom surface of the liquid storage chamber Sr is constituted by, for example, the nozzle plate 41. Specifically, the flow path substrate 42 is fixed to the bottom surface of the flow path substrate 42 so as to close the opening 422, each supply flow path 424, and the communication flow path 426.

A diaphragm 46 is installed on the surface of the pressure chamber substrate 44 opposite to the flow path substrate 42. The vibration plate 46 is a plate-like member that can elastically vibrate, and is configured by stacking an elastic film formed of an elastic material such as silicon oxide and an insulating film formed of an insulating material such as zirconium oxide. Is done. The diaphragm 46 and the flow path substrate 42 oppose each other with an interval inside each opening 422 of the pressure chamber substrate 44. A space sandwiched between the flow path substrate 42 and the diaphragm 46 inside each opening 422 functions as a cavity 442 that applies pressure to the ink. Each cavity 442 communicates with the nozzle N via the communication channel 426 of the channel substrate 42.
A piezoelectric element Pzt is formed for each nozzle N (cavity 442) on the surface of the vibration plate 46 opposite to the pressure chamber substrate 44.

  The piezoelectric element Pzt includes a common drive electrode 72 over a plurality of piezoelectric elements Pzt formed on the surface of the diaphragm 46, a piezoelectric body 74 formed on the surface of the drive electrode 72, and a surface of the piezoelectric body 74. It includes individual drive electrodes 76 formed on each piezoelectric element Pzt. In such a configuration, a region facing the piezoelectric body 74 with the drive electrodes 72 and 76 functions as the piezoelectric element Pzt.

  The piezoelectric body 74 is formed by a process including heat treatment (firing), for example. Specifically, the piezoelectric material applied on the surface of the diaphragm 46 on which the plurality of drive electrodes 72 are formed is fired by heat treatment in a firing furnace and then shaped for each piezoelectric element Pzt (for example, using plasma). The piezoelectric body 74 is formed by milling.

Similarly, the piezoelectric element Pzt corresponding to the nozzle row Nb includes the drive electrode 72, the piezoelectric body 74, and the drive electrode 76.
In this example, the common drive electrode 72 is the lower layer and the individual drive electrode 76 is the upper layer with respect to the piezoelectric body 74, but conversely, the drive electrode 72 is the upper layer and the drive electrode 76 is the lower layer. Also good.

A drive signal voltage Vout corresponding to the amount of ink to be ejected is individually applied from the circuit board to the drive electrode 76 which is one end of the piezoelectric element Pzt, while the drive electrode 72 which is the other end of the piezoelectric element Pzt is applied to the drive electrode 72 which is the other end of the piezoelectric element Pzt. , the holding signal of the voltage V _BS is commonly applied.
For this reason, the piezoelectric element Pzt is displaced upward or downward according to the voltage applied to the drive electrodes 72 and 76. Specifically, when the voltage Vout of the drive signal applied via the drive electrode 76 is lowered, the central portion of the piezoelectric element Pzt is bent upward with respect to both end portions, while when the voltage Vout is increased, the downward direction It is the composition which bends to.
Here, if the ink is bent upward, the internal volume of the cavity 442 is expanded (the pressure is decreased). Since the pressure increases, an ink droplet is ejected from the nozzle N depending on the degree of reduction. Thus, when an appropriate drive signal is applied to the piezoelectric element Pzt, ink is ejected from the nozzle N due to the displacement of the piezoelectric element Pzt. For this reason, at least the piezoelectric element Pzt, the cavity 442, and the nozzle N constitute an ejection unit that ejects ink.

  Next, the electrical configuration of the printing apparatus 1 will be described.

FIG. 5 is a block diagram illustrating an electrical configuration of the printing apparatus 1.
As shown in this figure, the printing apparatus 1 has a configuration in which the head unit 3 is connected to the main board 100 via a flexible flat cable 190. The head unit 3 is roughly divided into an actuator substrate 40 and a circuit substrate 50.
In the printing apparatus 1, four head units 3 are provided, and the main substrate 100 controls the four head units 3 independently. Since the four head units 3 are not different except for the color of the ink to be ejected, for the sake of convenience, the one head unit 3 will be described as a representative.

As shown in FIG. 5, the main board 100 includes a control unit 110 and an offset voltage generation circuit 130.
Among these, the control unit 110 is a kind of microcomputer having a CPU, a RAM, a ROM, and the like. When image data to be printed is supplied from a host computer or the like, a predetermined program is executed to execute each unit. Various signals for control are output.

Specifically, first, the control unit 110 supplies the data dA and dB and the signal groups Oa and Ob to the circuit board 50, respectively.
Here, the data dA defines the waveform of the drive signal COM-A in time series. The signal group Oa is an aggregate of a plurality of signals having a logic level corresponding to the voltage change of the waveform of the drive signal COM-A defined by the data dA, and details will be described later.
The data dB defines the waveform of the drive signal COM-B in time series. The signal group Ob is an aggregate of a plurality of signals having a logic level corresponding to the voltage change of the waveform of the drive signal COM-A defined by the data dB, and details will be described later.

Secondly, the control unit 110 supplies various control signals Ctr to the head unit 3 in synchronization with the control of the moving mechanism 6 and the transport mechanism 8. The control signal Ctr includes print data SI (ejection control signal) that defines the amount of ink ejected from the nozzle N, a clock signal Sck that is used to transfer the print data, and signals LAT and CH that define the printing cycle. included.
Note that the control unit 110 controls the moving mechanism 6 and the transport mechanism 8, but since such a configuration is known, description thereof is omitted.

Further, the offset voltage generating circuit 130 generates a hold signal voltage _{V BS.} The holding signal of the voltage V _BS via a flexible flat cable 190 and the circuit board 50, is applied to the common across the other end of the plurality of piezoelectric elements Pzt in the actuator substrate 40. Holding signal of the voltage V _BS is the other of the plurality of piezoelectric elements Pzt, is provided to maintain each in a constant state.

On the other hand, in the head unit 3, the circuit board 50 includes a first drive circuit 120a, a second drive circuit 120b, a selection control unit 510, and a selection unit 520 corresponding to the piezoelectric element Pzt on a one-to-one basis.
As will be described in detail later, the first drive circuit 120a converts the data dA into an analog signal, and uses the signal group Oa to increase the drive capability (convert it to a low impedance) and convert the converted signal into a drive signal COM−. Output as A.
Similarly, the second drive circuit 120b converts the data dB to analog, and outputs the converted signal as a drive signal COM-B with the drive capability increased (converted to low impedance) using the signal group Ob.
The drive signals COM-A and COM-B are trapezoidal waveforms as will be described later.

Selection control unit 510 controls selection in each of selection units 520. More specifically, the selection control unit 510 temporarily accumulates print data supplied from the control unit 110 in synchronization with the clock signal for several nozzles (piezoelectric elements Pzt) of the head unit 3, and each selection unit In response to the print data, 520 is instructed to select the drive signals COM-A and COM-B at the start timing of the print cycle defined by the timing signal.
Each selection unit 520 selects one of the drive signals COM-A and COM-B according to an instruction from the selection control unit 510 (or neither is selected), and corresponds as a drive signal of the voltage Vout. Applied to one end of the piezoelectric element Pzt.

On the other hand, the actuator substrate 40 in the head unit 3 is provided with one piezoelectric element Pzt for each nozzle N as described in FIG. The other end of each of the piezoelectric elements Pzt are connected in common, to the other end voltage V _BS by the offset voltage generating circuit 130 is applied.
In the head unit 3, the circuit board 50 is connected to the actuator substrate 40, and the first drive circuit 120a, the second drive circuit 120b, the selection control unit 510, and the plurality of selection units 520 are connected to the circuit board 50. Each of the elements constituting is mounted.

In the present embodiment, with respect to one dot, by ejecting ink from one nozzle N at most twice, four gradations of large dot, medium dot, small dot, and non-printing are expressed. In order to express these four gradations, in this embodiment, two types of drive signals COM-A and COM-B are prepared, and a first half pattern and a second half pattern are provided in each one period. In the first half and the second half of one cycle, the drive signals COM-A and COM-B are selected (or not selected) according to the gradation to be expressed and supplied to the piezoelectric element Pzt. Yes.
Accordingly, the drive signals COM-A and COM-B will be described first, and then the detailed configurations of the selection control unit 510 and the selection unit 520 for selecting the drive signals COM-A and COM-B will be described.

FIG. 6 is a diagram illustrating waveforms of the drive signals COM-A and COM-B.
As shown in the figure, the drive signal COM-A has a trapezoidal waveform Adp1 arranged in the period T1 from the output of the control signal LAT (rise) to the output of the control signal CH in the printing cycle Ta. In the printing cycle Ta, the waveform repeats a trapezoidal waveform Adp2 arranged in a period T2 from when the control signal CH is output until the next control signal LAT is output.

  In the present embodiment, the trapezoidal waveforms Adp1 and Adp2 are substantially the same waveform, and if each is supplied to the drive electrode 76 which is one end of the piezoelectric element Pzt, the nozzle N corresponding to the piezoelectric element Pzt To a predetermined amount, specifically, a waveform for ejecting a medium amount of ink.

  The drive signal COM-B has a waveform that repeats a trapezoidal waveform Bdp1 arranged in the period T1 and a trapezoidal waveform Bdp2 arranged in the period T2. In the present embodiment, the trapezoidal waveforms Bdp1 and Bdp2 are different from each other. Among these, the trapezoidal waveform Bdp1 is a waveform for finely vibrating the ink near the nozzle N to prevent the ink viscosity from increasing. For this reason, even if the trapezoidal waveform Bdp1 is supplied to one end of the piezoelectric element Pzt, ink droplets are not ejected from the nozzle N corresponding to the piezoelectric element Pzt. The trapezoidal waveform Bdp2 is different from the trapezoidal waveform Adp1 (Adp2). If the trapezoidal waveform Bdp2 is supplied to one end of the piezoelectric element Pzt, it is a waveform for ejecting an amount of ink smaller than the predetermined amount from the nozzle N corresponding to the piezoelectric element Pzt.

  Note that the voltage at each start timing and the voltage at each end timing in the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 are all common to the voltage Vcen. That is, each of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 has a waveform that starts with the voltage Vcen and ends with the voltage Vcen.

Further, each of the trapezoidal waveform drive signals COM-A and COM-B has a plurality of periods in which the voltage is constant.
The driving signal COM-A has three values including a constant voltage including the above Vcen. These three values are expressed as Vmax, Vcen, and Vmin in descending order. Note that both the voltage Vmax and the voltage Vmin exist in each of the trapezoidal waveforms Adp1 and Adp2.
In the drive signal COM-B, there are four voltage values including the above Vcen that are constant. These four values are expressed in descending order as V1, Vcen, V2, and V3. The voltage V1 and the voltage V3 are both present in the trapezoidal waveform Bdp2, and the voltage V2 is present in both the trapezoidal waveforms Bdp1 and Bdp2.

The control unit 110 outputs data dA, the first drive circuit 120a converts the data dA into analog, converts the converted signal into low impedance, and outputs it as a drive signal COM-A. Similarly, the control unit 110 outputs data dB, the second drive circuit 120b converts the data dB into analog, converts the converted signal into low impedance, and outputs it as a drive signal COM-B.
For this reason, the control 110 is prescribed | regulated by the control part 110 about the trapezoid waveform of the drive signal COM-A and the drive signal COM-B, respectively.

The control unit 110 outputs the following signals as a signal group Oa according to the trapezoidal waveform of the drive signal COM-A.
That is, the control unit 110 outputs signals O1a, Oda, O2a, and OCa as the signal group Oa. Among these, the signal O1a is at the H level in the period P4 in which the drive signal COM-A is constant at the voltage Vmax. In other periods, the signal Oda is output as the L level, and the signal Oda is set to the H level in the periods P3, P4, P5, and P6 in which the drive signal COM-A is constant at the voltage Vcen, and is output in the other periods. The signal O2a is output as the H level during the period P2 in which the drive signal COM-A is constant at the voltage Vmin, and is output as the L level during other periods. Details of the signal OCa and the periods P1 to P6 will be described later.

The control unit 110 outputs the following signals as a signal group Ob according to the trapezoidal waveform of the drive signal COM-B.
That is, the control unit 110 outputs signals O1b, ODb, O2b, O3ba, and OCb as the signal group Ob. Among these, the signal O1b is H in a period in which the drive signal COM-B is constant at the voltage V1. The signal ODb is output as the L level in other periods, and the signal ODb is output as the H level in the period in which the drive signal COM-B is constant at the voltage Vcen, and is output as the L level in the other periods. Is set to H level during a period in which the drive signal COM-B is constant at the voltage V2, and is output as L level in other periods, and the signal O3b is a period in which the drive signal COM-B is constant at the voltage V3. At H level, and output at L level during other periods. The signal ODb will be described later.

FIG. 7 is a diagram showing the configuration of the selection control unit 510 in FIG.
As shown in this figure, the selection control unit 510 is supplied with a clock signal Sck, print data SI, and control signals LAT and CH. In the selection control unit 510, a set of a shift register (S / R) 512, a latch circuit 514, and a decoder 516 is provided corresponding to each piezoelectric element Pzt (nozzle N).

The print data SI is data that defines dots to be formed by all the nozzles N in the head unit 3 of interest over the print cycle Ta. In this embodiment, in order to express four gradations of non-recording, small dots, medium dots, and large dots, the print data for one nozzle is composed of 2 bits, an upper bit (MSB) and a lower bit (LSB). Composed.
The print data SI is supplied from the control unit 110 in accordance with the conveyance of the medium P for each nozzle N (piezoelectric element Pzt) in synchronization with the clock signal Sck. A configuration for temporarily holding the print data SI for 2 bits corresponding to the nozzle N is a shift register 512.
Specifically, a total of m stages of shift registers 512 corresponding to each of the m piezoelectric elements Pzt (nozzles) are connected in cascade, and the print data supplied to the one stage shift register 512 located at the left end in the figure. The SI is sequentially transferred to the subsequent stage (downstream side) according to the clock signal Sck.
In the figure, in order to distinguish the shift register 512, the first stage, the second stage,..., And the m stage are shown in order from the upstream side to which the print data SI is supplied.

The latch circuit 514 latches the print data SI held by the shift register 512 at the rising edge of the control signal LAT.
The decoder 516 decodes the 2-bit print data SI latched by the latch circuit 514 and outputs selection signals Sa and Sb for each of the periods T1 and T2 defined by the control signal LAT and the control signal CH. The selection by the selection unit 520 is defined.

FIG. 8 is a diagram showing the decoding contents in the decoder 516.
In this figure, the latched 2-bit print data SI is represented as (MSB, LSB). For example, if the latched print data SI is (0, 1), the decoder 516 sets the logic levels of the selection signals Sa and Sb to H and L levels in the period T1, respectively, and to L and H levels in the period T2, respectively. , Which means output.
Note that the logic levels of the selection signals Sa and Sb are shifted to higher amplitude logic by a level shifter (not shown) than the logic levels of the clock signal Sck, the print data SI, and the control signals LAT and CH.

FIG. 9 is a diagram illustrating a configuration of the selection unit 520 in FIG.
As shown in this figure, the selection unit 520 includes inverters (NOT circuits) 522a and 522b and transfer gates 524a and 524b.
The selection signal Sa from the decoder 516 is supplied to a positive control terminal that is not circled in the transfer gate 524a, while being logically inverted by the inverter 522a, and negative control that is circled in the transfer gate 524a. Supplied to the end. Similarly, the selection signal Sb is supplied to the positive control terminal of the transfer gate 524b, while being logically inverted by the inverter 522b and supplied to the negative control terminal of the transfer gate 524b.
The drive signal COM-A is supplied to the input terminal of the transfer gate 524a, and the drive signal COM-B is supplied to the input terminal of the transfer gate 524b. The output ends of the transfer gates 524a and 524b are connected in common and connected to one end of the corresponding piezoelectric element Pzt.
The transfer gate 524a conducts (turns on) between the input end and the output end if the selection signal Sa is at the H level, and does not conduct between the input end and the output end if the selection signal Sa is at the L level. (Off). Similarly, the transfer gate 524b is turned on / off between the input terminal and the output terminal according to the selection signal Sb.

As shown in FIG. 6, the print data SI is supplied for each nozzle in synchronization with the clock signal Sck, and sequentially transferred in the shift register 512 corresponding to the nozzle. When the supply of the clock signal Sck is stopped, the print data SI corresponding to each nozzle is held in each of the shift registers 512.
Here, when the control signal LAT rises, each of the latch circuits 514 latches the print data SI held in the shift register 512 at the same time. In FIG. 6, numbers in L1, L2,..., Lm indicate print data SI latched by the latch circuit 514 corresponding to the first, second,.

The decoder 516 outputs the logic levels of the selection signals Sa and Sa with the contents as shown in FIG. 8 in each of the periods T1 and T2 in accordance with the dot size defined by the latched print data SI.
That is, first, when the print data SI is (1, 1) and the size of a large dot is defined, the decoder 516 sets the selection signals Sa and Sb to the H and L levels in the period T1, and the period At T2, the H and L levels are set. Second, when the print data SI is (0, 1) and the size of the medium dot is defined, the decoder 516 sets the selection signals Sa and Sb to the H and L levels in the period T1, and in the period T2. L and H levels. Third, when the print data SI is (1, 0) and the size of the small dot is defined, the decoder 516 sets the selection signals Sa and Sb to L and L levels in the period T1, and in the period T2. L and H levels. Fourth, when the print data SI is (0, 0) and non-recording is specified, the decoder 516 sets the selection signals Sa and Sb to L and H levels in the period T1 and L and L in the period T2. Set to L level.

FIG. 10 is a diagram illustrating a voltage waveform of a drive signal selected according to the print data SI and supplied to one end of the piezoelectric element Pzt.
When the print data SI is (1, 1), the selection signals Sa and Sb are at the H and L levels in the period T1, so that the transfer gate 524a is turned on and the transfer gate 524b is turned off. For this reason, the trapezoidal waveform Adp1 of the drive signal COM-A is selected in the period T1. Since the selection signals Sa and Sb are at the H and L levels also during the period T2, the selection unit 520 selects the trapezoidal waveform Adp2 of the drive signal COM-A.
As described above, when the trapezoidal waveform Adp1 is selected in the period T1, and the trapezoidal waveform Adp2 is selected in the period T2, and supplied to one end of the piezoelectric element Pzt as a drive signal, the nozzle N corresponding to the piezoelectric element Pzt A certain amount of ink is ejected in two steps. For this reason, the respective inks land on the medium P and coalesce, and as a result, large dots as defined by the print data SI are formed.

When the print data SI is (0, 1), the selection signals Sa and Sb are at the H and L levels in the period T1, so that the transfer gate 524a is turned on and the transfer gate 524b is turned off. For this reason, the trapezoidal waveform Adp1 of the drive signal COM-A is selected in the period T1. Next, since the selection signals Sa and Sb are at the L and H levels in the period T2, the trapezoidal waveform Bdp2 of the drive signal COM-B is selected.
Therefore, medium and small amounts of ink are ejected from the nozzle in two steps. Therefore, the respective inks land on the medium P and coalesce, and as a result, medium dots as defined by the print data SI are formed.

When the print data SI is (1, 0), since the selection signals Sa and Sb are both at the L level in the period T1, the transfer gates 524a and 524b are turned off. For this reason, neither trapezoidal waveform Adp1 nor Bdp1 is selected in the period T1. When both the transfer gates 524a and 524b are turned off, the path from the connection point between the output ends of the transfer gates 524a and 524b to one end of the piezoelectric element Pzt is in a high impedance state that is not electrically connected to any part. . However, at both ends of the piezoelectric element Pzt, the voltage (Vcen−V _BS ) immediately before the transfer gate is turned off is held by the capacitance of the piezoelectric element Pzt.
Next, since the selection signals Sa and Sb are at the L and H levels in the period T2, the trapezoidal waveform Bdp2 of the drive signal COM-B is selected. For this reason, since a small amount of ink is ejected from the nozzle N only in the period T2, small dots as defined by the print data SI are formed on the medium P.

When the print data SI is (0, 0), the selection signals Sa and Sb are at the L and H levels in the period T1, so that the transfer gate 524a is turned off and the transfer gate 524b is turned on. For this reason, the trapezoidal waveform Bdp1 of the drive signal COM-B is selected in the period T1. Next, since the selection signals Sa and Sb are both at the L level in the period T2, neither of the trapezoidal waveforms Adp2 and Bdp2 is selected.
For this reason, the ink in the vicinity of the nozzle N only slightly vibrates in the period T1, and the ink is not ejected. As a result, no dot is formed, that is, non-recording is performed as defined by the print data SI.

As described above, the selection unit 520 selects (or does not select) the drive signals COM-A and COM-B in accordance with an instruction from the selection control unit 510 and applies them to one end of the piezoelectric element Pzt. For this reason, each piezoelectric element Pzt is driven according to the dot size defined by the print data SI.
Note that the drive signals COM-A and COM-B illustrated in FIG. 6 are merely examples. Actually, various combinations of waveforms prepared in advance are used according to the property of the medium P, the conveyance speed, and the like.
Here, the example in which the piezoelectric element Pzt bends upward as the voltage decreases has been described. However, when the voltage applied to the drive electrodes 72 and 76 is reversed, the piezoelectric element Pzt causes the voltage to decrease. Along with this, it will bend downward. For this reason, in the configuration in which the piezoelectric element Pzt bends downward as the voltage decreases, the drive signals COM-A and COM-B illustrated in the figure have waveforms that are inverted with respect to the voltage Vcen.

  Next, the first drive circuit 120a and the second drive circuit 120b in the circuit board 50 will be described.

FIG. 11 is a diagram illustrating a configuration of the first drive circuit 120a. As shown in this figure, the first drive circuit 120a includes a DAC 122a, a voltage amplifier 124a, an amplifier circuit 200a, voltage sources E1a, EDa, and E2a, and switches Sw1a, SwDa, and Sw2a.
Among them, the DAC 122a converts the digital data dA into an analog signal, and the voltage amplifier 124a amplifies the voltage of the analog signal, for example, 10 times and outputs it as a signal Ain. The amplifier circuit 200a converts the signal Ain input to the input end into a low impedance at least during the voltage change period of the signal Ain, and outputs it from the output end.
Details of the amplifier circuit 200b will be described later.

The voltage source E1a outputs a voltage Vmax, the positive output terminal is connected to one end of the switch Sw1a, and the negative output terminal is grounded to the ground Gnd having zero voltage. The voltage source EDa outputs the voltage Vcen, the positive output terminal is connected to one end of the switch SwDa and one end of a switch SwDb described later, and the negative output terminal is grounded to the ground Gnd. The voltage source E2a outputs the voltage Vmin, the positive output terminal is connected to one end of the switch Sw3a, and the negative output terminal is grounded to the ground Gnd.
The switch Sw1a is turned on when the signal O1a is at the H level and turned off when the signal O1a is at the L level. Similarly, the switch SwDa is turned on when the signal Oda is at the H level and turned off when the signal Oda is at the L level, and the switch Sw3a is turned on when the signal O2a is at the H level and turned off when the signal O2a is at the L level.
The voltage sources E1a, EDa, and E2a and the switches Sw1a, SwDa, and Sw2a function as a constant voltage output circuit (or a first constant voltage output circuit).

  The output end of the amplifier circuit 200a, the other end of the switch Sw1a, the other end of the switch SwDa, and the other end of the switch Sw3a are commonly connected to form a node N1.

FIG. 12 is a diagram illustrating a configuration of the second drive circuit 120b. As shown in this figure, the second drive circuit 120b includes a DAC 122b, a voltage amplifier 124b, an amplifier circuit 200b, voltage sources E1b, E2b, and E3b, and switches Sw1b, SwDb, Sw2b, and Sw3b. .
Among these, the DAC 122b converts the digital data dB into an analog signal, and the voltage amplifier 124b amplifies the voltage of the analog signal by, for example, 10 times and outputs it as a signal Bin. The amplifier circuit 200b converts the signal Bin input to the input end into a low impedance at least during the voltage change period of the signal Bin, and outputs the converted signal from the output end.
Details of the amplifier circuit 200b will be described later.

The voltage source E1b outputs the voltage V1, the positive output terminal is connected to one end of the switch Sw1b, and the negative output terminal is grounded to the ground Gnd. The voltage source E2b outputs the voltage V2, the positive output terminal is connected to one end of the switch Sw2b, and the negative output terminal is grounded to the ground Gnd. The voltage source E3b outputs the voltage V3, the positive output terminal is connected to one end of the switch Sw3b, and the negative output terminal is grounded to the ground Gnd.
Note that the voltage Vcen from the voltage source E2a in the first drive circuit 120a is applied to one end of the switch SwDb.

The switch Sw1b is turned on when the signal O1b is at the H level and turned off when the signal O1b is at the L level. Similarly, the switch SwDb is turned on when the signal ODb is at the H level, and turned off when the signal ODb is at the L level. The switch Sw2b is turned on when the signal O2b is at the H level, and is turned off when the signal O2b is at the L level. Sw3b is turned on when the signal O3b is at the H level and turned off when the signal O3b is at the L level.
The voltage sources E1b, (EDa), E2b, and E3b and the switches Sw1b, SwDb, Sw2b, and Sw3b function as a second constant voltage output circuit.

  The output end of the amplifier circuit 200b, the other end of the switch Sw1b, the other end of the switch SwDb, the other end of the switch Sw2b, and the other end of the switch Sw3b are connected in common to the node N2 that is the output end of the second drive circuit 12b. It has become.

  Next, an example of the amplifier circuit 200a applied to the first drive circuit 120a will be described. Since there are several modes for the amplifier circuit 200a, in order to distinguish, for example, an amplifier circuit (part 1) and an amplifier circuit (part 2) are given parentheses instead of symbols. There is a case.

FIG. 13 is a diagram illustrating a configuration of an amplifier circuit (part 1) applicable to the first drive circuit 120a.
As shown in this figure, the amplifier circuit (part 1) includes a differential amplifier 221, a selector 223, a transistor pair, and a capacitor C0.

  In the differential amplifier 221, the signal Ain (original drive signal) is supplied to the negative input terminal (−), while the drive signal COM-A as an output is fed back to the positive input terminal (+). . For this reason, the differential amplifier 221 has a difference voltage obtained by subtracting the voltage at the negative input terminal (−) from the voltage at the positive input terminal (+), that is, a signal that is an input from the voltage of the drive signal COM-A that is an output. The difference voltage obtained by subtracting the voltage of Ain is amplified and output.

The differential amplifier 221 has a voltage V _D (= 42V) on the higher power supply side and a ground Gnd (= 0V) on the lower power supply side, although not particularly illustrated. Therefore, the output voltage of the differential amplifier 221 is a range from the ground Gnd to the voltage V _D.
However, since the output signal of the differential amplifier 221 is used to switch the transistor pair in this embodiment, it is a binary logic signal of H level (voltage V _D ) and L level (ground Gnd). That is, the differential amplifier 221 functions as a comparator.
Further, while the drive signal is stepped down and fed back, the original drive signal may be amplified and output as a drive signal, so that a signal based on the drive signal is fed back to the differential amplifier 221. .

The selector 223 selects the output signal of the differential amplifier 221 as the signal Gt1 and supplies it to the gate terminal of the transistor 231 if the signal OEa is at the L level and the signal OCa is at the L level. The L level is selected as Gt 2 and supplied to the gate terminal of the transistor 232.
On the other hand, when the signal OEa is at the L level and the signal OCa is at the H level, the selector 223 selects the H level as the signal Gt1, supplies it to the gate terminal of the transistor 231, and differentially selects the signal Gt2. The output signal of the amplifier 221 is selected and supplied to the gate terminal of the transistor 232.
If the signal OEa is at the H level, the selector 223 supplies the H level as the signal Gt1 to the gate terminal of the transistor 231 and the L level as the signal Gt2 regardless of the logic level of the signal OCa. Supply to the terminal.

Here, the signal OEa is at the L level over a period in which the voltage of the drive signal COM-A is changed, and is at the H level over a period in which the voltage of the other drive signal COM-A is constant. The signal OEa may be configured to be supplied from the control unit 110, or may be configured to obtain and use a logical sum signal (not shown) of the above-described signals O1a, Oda, and O2a.
The signal OCa is at the L level over the period when the voltage of the drive signal COM-A is increased, and is at the H level over the other periods. This signal OEa is supplied from the control unit 110 as described above.
In FIG. 13, the points where the signals OEa and OCa are supplied to the amplifier circuit 200a are shown, but in FIG. 11, these points are omitted for convenience.

In other words, the selector 223 supplies the output signal of the differential amplifier 221 to the gate terminal of the transistor 231 and the gate of the transistor 232 in the first case where the drive signal COM-A (signal Ain) is in the voltage rising period. A signal for turning off the transistor 232 is supplied to the terminal.
On the other hand, the selector 223 supplies a signal for turning off the transistor 231 to the gate terminal of the transistor 231 and a differential signal to the gate terminal of the transistor 232 in the second case in which the voltage of the drive signal COM-A is falling. An output signal of the amplifier 221 is supplied.
Note that the selector 223 supplies a signal for turning off the transistor 231 to the gate terminal of the transistor 231 and the transistor 232 is turned off to the gate terminal of the transistor 232 during the voltage flat period of the drive signal COM-A. Supply the signal.

The transistor pair is constituted by transistors 231 and 232. Of these, high-side transistor 231 (the high side transistor) is, for example, a field-effect transistor of P-channel type, high-side voltage V _D of the power supply is applied to the source terminal. The low-order transistor 232 (low-side transistor) is, for example, an N-channel field effect transistor, and its source terminal is grounded to the ground Gnd that is the low-order side of the power supply.
The drain terminals of the transistors 231 and 232 are connected to each other and serve as a node N1 that is an output terminal of the first drive circuit 120a.
The capacitor C0 is provided to prevent abnormal oscillation and the like. One end of the capacitor C0 is connected to the node N1, and the other end is grounded to a constant potential, for example, the ground Gnd.

Although the amplifier circuit 200a in the first drive circuit 120a has been described, the amplifier circuit 200b in the second drive circuit 120b is the same as the amplifier circuit 200a, and only the input / output signals are different. That is, the signal OEb is input to the amplifier circuit 200b instead of the signal OEa, the signal OCb is input instead of the signal OCa, and the signal Bin is input instead of the signal Ain, while the drive signal COM-B is received from the node N2. The configuration is output.
Here, the signal OEb is at the L level over a period during which the voltage of the drive signal COM-B is changed, and is at the H level over a period during which the voltage of the other drive signal COM-B is constant. The signal OEa may be configured to be supplied from the control unit 110, or may be configured to obtain and use the logical sum of the above-described signals O1b, ODb, O2b, and O3b by a logic circuit (not shown).
The signal OCb is at the L level over the period when the voltage of the drive signal COM-B increases, and is at the H level over the other periods. The point that the signal OCa is supplied from the control unit 110 is as described above.
Here, it has been described that the signals OEb and OCb are supplied to the amplifier circuit 200b. However, in FIG. 12, the supply of the signals OEb and OCb is omitted for the sake of convenience.

  Next, operations of the first drive circuit 120a and the second drive circuit 120b will be described. First, the operation of the first drive circuit 120a will be described.

FIG. 14 is a diagram showing voltage waveforms at various parts for explaining the operation of the first drive circuit 120a.
In this figure, since the signal Ain is a signal before the impedance conversion of the drive signal COM-A, it has almost the same waveform as the drive signal COM-A. Further, as described above, since the drive signal COM-A is a waveform in which two identical trapezoidal waveforms Adp1 and Adp2 are repeated in the printing cycle Ta, the signal Ain is also a similar repeated waveform.

FIG. 14 shows one trapezoidal waveform among such repetitive waveforms. In this figure, a period P1 is a period in which the signal Ain drops from the voltage Vcen to the voltage Vmin, a period P2 following the period P1 is a period in which the signal Ain is constant at the voltage Vmin, and the period P2 A period P3 following the period P3 is a period during which the signal Ain rises from the voltage Vmin to the voltage Vmax. A period P4 following the period P3 is a period during which the signal Ain is constant at the voltage Vmax, and a period P5 following the period P4. Is a period during which the signal Ain drops from the maximum value max to the voltage Vcen.
For each of the plurality of voltage waveforms in FIG. 14, the vertical scale is not necessarily aligned for convenience of explanation.

First, the period P1 is a voltage drop period of the drive signal COM-A (Ain). For this reason, since the signals O1a, Oda, and O2a are all at the L level, the switches Sw1a, SwDa, and Sw2a are turned off.
In the period P1, since the signal OEa is at the L level and the signal OCa is at the H level, in FIG. 13, the selector 223 selects the H level as the signal Gt1, and the output signal of the differential amplifier 221 as the signal Gt2. Select.
In the period P1, since the signal Gt1 is at the H level, the P-channel transistor 231 is turned off.
On the other hand, in the period P1, the voltage of the signal Ain first decreases before the voltage of the node N1. Conversely, the voltage at the node N1 is equal to or higher than the voltage of the signal Ain. For this reason, the voltage of the output signal of the differential amplifier 221 selected as the signal Gt2 becomes high according to the difference voltage between them, and swings substantially to the H level. When the signal Gt2 becomes H level, the transistor 232 is turned on, so that the voltage at the node N1 decreases. Note that the voltage at the node N1 does not actually drop to the ground Gnd at a stretch, but slowly decreases due to the capacitance of the capacitor C0 and the piezoelectric element Pzt as the load.

When the voltage of the node N1 becomes lower than the voltage of the signal Ain, the signal Gt2 becomes L level and the transistor 232 is turned off. Even when the transistor 232 is turned off, the voltage of the node N1 is not indefinite because it is held by the capacitance of the capacitor C0 and the piezoelectric element Pzt.
When the transistor 232 is turned off, the voltage drop at the node N1 is interrupted, but since the voltage drop at the signal Ain continues, the voltage at the node N1 again becomes equal to or higher than the voltage of the signal Ain. For this reason, the signal Gt2 becomes H level and the transistor 232 is turned on again.
In the period P1, the signal Gt2 is alternately switched between the H level and the L level, whereby the transistor 232 performs an operation of repeatedly turning on and off, that is, a switching operation. By this switching operation, the voltage of the node N1 is controlled to follow the voltage drop of the signal Ain.

Next, the period P2 is a period in which the drive signal COM-A (Ain) is constant at the voltage Vmin. Therefore, since the signal OEa becomes H level in the period P2, the selector 223 selects the H level as the signal Gt1 and the L level as the signal Gt2, so that both the transistors 231 and 232 are turned off.
On the other hand, in the period P2, since the signal O2a becomes H level (see FIG. 5), the switch Sw2a is turned on. Therefore, the node N1 becomes the voltage Vmin.

The period P3 is a voltage increase period of the drive signal COM-A (Ain). For this reason, since the signals O1a, Oda, and O2a are all at the L level, the switches Sw1a, SwDa, and Sw2a are turned off.
In the period P3, since the signal OEa becomes L level and the signal OCa becomes L level, the selector 223 selects the output signal of the differential amplifier 221 as the signal Gt1, and selects the L level as the signal Gt2.
In the period P3, since the signal Gt2 is at the L level, the N-channel transistor 232 is turned off.
On the other hand, in the period P3, first, the voltage of the signal Ain rises before the voltage of the node N1. Conversely, the voltage at the node N1 is lower than the voltage of the signal Ain. For this reason, the voltage of the output signal of the differential amplifier 221 selected as the signal Gt1 becomes low according to the difference voltage between them, and swings substantially to the L level. When the signal Gt1 becomes L level, the transistor 231 is turned on, so that the voltage at the node N1 rises. Note that the voltage at the node N1 does not actually increase to the voltage V _D at a stroke but increases slowly due to the capacitor C0 and the piezoelectric element Pzt.
When the voltage of the node N1 becomes equal to or higher than the voltage of the signal Ain, the signal Gt2 becomes H level and the transistor 231 is turned off. Even when the transistor 231 is turned off, the voltage of the node N1 is not indefinite because it is held by the capacitance of the capacitor C0 and the piezoelectric element Pzt.
When the transistor 231 is turned off, the voltage increase at the node N1 stops, but the voltage increase at the signal Ain continues, so the voltage at the node N1 again becomes lower than the voltage at the signal Ain. For this reason, the signal Gt1 becomes L level, and the transistor 231 is turned on again.
In the period P3, the signal Gt1 is alternately switched between the H level and the L level, whereby the transistor 231 performs a switching operation. By this switching operation, the voltage at the node N1 is controlled so as to follow the increase in the voltage of the signal Ain.

The period P4 is a period in which the drive signal COM-A (Ain) is constant at the voltage Vmax. For this reason, since the signal OEa becomes H level in the period P4, the selector 223 selects the H level as the signal Gt1 and the L level as the signal Gt2, so that both the transistors 231 and 232 are turned off.
On the other hand, since the signal O1a becomes H level in the period P4 (see FIG. 5), the switch Sw1a is turned on. Therefore, the node N1 becomes the voltage Vmax.

  The period P5 is a voltage drop period of the drive signal COM-A (Ain). For this reason, the operation in the period P5 is the same as that in the period P1. That is, the switches Sw1a, SwDa, and Sw2a are turned off, while the signal Gt2 is alternately switched between H and L levels, whereby the transistor 232 is switched and the voltage at the node N1 follows the decrease in the voltage of the signal Ain. To be controlled.

A period P6 after the period P5 is a period in which the drive signal COM-A (Ain) is constant at the voltage Vcen. For this reason, since the signal OEa becomes H level in the period P6, the selector 223 selects the H level as the signal Gt1 and the L level as the signal Gt2, so that both the transistors 231 and 232 are turned off.
On the other hand, in the period P6, the signal Oda becomes H level (see FIG. 5), so that the switch SwDa is turned on. Therefore, the node N1 becomes the voltage Vcen.

According to the first drive circuit 120a shown in FIG. 11, the following operation is performed every period P1 to P6.
That is, in the periods P1 and P5 in which the voltage of the signal Ain decreases, the voltage at the node N1 is controlled to follow the voltage decrease of the signal Ain by the switching operation of the transistor 232 in the amplifier circuit 200a.
In the period P3, the voltage of the node N1 is controlled to follow the voltage increase of the signal Ain by the switching operation of the transistor 231.
In the period P2, P4, or P6 in which the voltage of the signal Ain is constant, the voltage of the node N1 is determined by the application of any one of the voltage sources E1a, EDa, or E2a, not the transistors 231 and 232.
Specifically, the node N1 becomes the voltage Vmin of the voltage source E2a when the switch Sw2a is turned on during the period P2, and becomes the voltage Vmax of the voltage source E1a when the switch Sw1a is turned on during the period P4. When SwDa is turned on, the voltage Vcen of the voltage source EDa is obtained.

  Although the operation of the first drive circuit 120a has been described here, the same applies to the operation of the second drive circuit 120b. Specifically, in the second drive circuit 120b, the voltage of the node N2 is controlled to follow the voltage change of the signal Bin by the amplifier circuit 200a during the voltage change period of the signal Bin. When the signal ODb is at the H level, the switch SwDb is turned on to set the voltage Vcen of the voltage source EDa. When the signal O3b is at the H level, the switch Sw3b is turned on to set the voltage V3 of the voltage source E3b. The switch Sw2b is turned on to set the voltage V2 of the voltage source E2b during the H level period, and the switch Sw1b is turned on to set the voltage V1 of the voltage source E1b when the signal O1b is at the H level.

According to the first drive circuit 120a, in the periods P2, P4, and P6 in which the voltage of the signal Ain is constant, the transistors 231 and 232 are compared with the class D amplification in which the high-side transistor and the low-side transistor are constantly switched. Does not switch. The same applies to the second drive circuit 120b, and the transistors 231 and 232 do not perform a switching operation during a period in which the voltage of the signal Bin is constant.
Further, in class D amplification, an LPF (Low Pass Filter) that demodulates the switching signal, particularly an inductor such as a coil, is required. In each of the first drive circuit 120a and the second drive circuit 120b, such an LPF is used. Is unnecessary.
Therefore, according to each of the first drive circuit 120a and the second drive circuit 120b, it is possible to suppress the power consumed by the switching operation and the LPF as compared with the class D amplification, respectively, and simplify the circuit. Miniaturization can be achieved.

In the first drive circuit 120a, during the voltage change period of the signal Ain, the voltage of the node N1 is controlled to follow the voltage change of the signal Ain by the switching operation of the transistor 231 or 232.
On the other hand, in the first drive circuit 120a, the transistors 231 and 232 are both turned off for a certain period of the voltage of the signal Ain. When any of the switches Sw1a, SwDa, or Sw2a is turned on, the voltage source corresponding to the turned on switch Is applied to the node N1. For this reason, even if the transistors 231 and 232 are turned off, the node N1 is stabilized at the voltage of any voltage source.

In particular, when the voltage of the drive signal COM-A changes from a change period to a certain period, the switching operation by the transistors 231 and 232 is stopped and both transistors are turned off. Stopping the switching operation means stopping control for causing the voltage at the node N1 to follow the voltage of the signal Ain. Therefore, immediately after the switching operation is stopped, the voltage at the node N1 may deviate from the voltage of the signal Ain. May occur and cause a deterioration in waveform reproducibility.
In contrast, in the present embodiment, immediately after the switching operation of the transistor 231 or 232 is stopped, one of the switches Sw1a, SwDa, or Sw2a is turned on, and the voltage of the voltage source corresponding to the turned on switch Is applied to the node N1, the above-described divergence can be prevented and the waveform reproducibility can be improved.
Similarly, in the second drive circuit 120b, the waveform reproducibility can be improved.

By the way, each trapezoidal waveform in the drive signals COM-A and COM-B is a waveform that starts at the voltage Vcen and ends at the voltage Vcen. The reason for this is that, for example, when switching from one of the drive signals COM-A and COM-B to the other during the printing period Ta from the time period T1 to the time period T2, it is applied to one end of the piezoelectric element Pzt. This is to prevent the applied voltage from changing.
Here, in the configuration in which the signal Ain is amplified only by the amplifier circuit 200a and the signal Bin is amplified only by the amplifier circuit 200b, if there is a difference in the characteristics of the amplifier circuits 200a and 200b, for example, from the period T1 to the period T2, When the drive signals COM-A and COM-B are switched from one to the other, the voltage applied to one end of the piezoelectric element Pzt changes, leading to a reduction in print quality such as erroneous ink ejection. become.
On the other hand, the voltage Vcen output from the first drive circuit 120a and the second drive circuit 120b in the present embodiment is the output voltage of the shared voltage source EDa, so that the drive signals COM-A and COM-B There is no difference when switching from one to the other.
For this reason, according to the first drive circuit 120a and the second drive circuit 120b, it is possible to simplify the configuration by sharing the voltage source EDa, and to suppress deterioration in print quality such as erroneous ink ejection.

FIG. 15 is a diagram illustrating another configuration of the first drive circuit 120 a applicable to the printing apparatus 1.
11 differs from FIG. 11 in that the voltage Vmax output from the voltage source E1a, the voltage Vcen output from the voltage source EDa, and the voltage Vmin output from the voltage source E2a are respectively obtained. The point is that it is variable. The reason why the output voltage of each voltage source is variable for the first drive circuit 120a is as follows.
That is, in order to compensate for fluctuations in the output voltage of the voltage source due to aging or the surrounding environment, and to enable setting of the voltage amplitude of the drive signal COM-A in accordance with the characteristics of the piezoelectric element Pzt. It is.
The reason why the voltage amplitude of the drive signal COM-A is set in accordance with the characteristics of the piezoelectric element Pzt will be described below.
First, the characteristics of the piezoelectric element Pzt, specifically, the characteristics of bending of the piezoelectric element Pzt with respect to the voltage change are relatively uniform among a plurality of piezoelectric elements Pzt in the same actuator substrate 40, but the piezoelectricity of different actuator substrates 40 is different. The elements Pzt may not be aligned due to manufacturing variations. Therefore, for example, the piezoelectric element Pzt in one actuator substrate 40 bends by the same amount with a smaller voltage amplitude than the piezoelectric element Pzt in another actuator substrate 40, in other words, discharges the same amount of liquid. Nevertheless, higher efficiency can result in smaller voltage amplitudes.
Conversely, a piezoelectric element Pzt on one actuator substrate 40 is less efficient than a piezoelectric element Pzt on another actuator substrate 40. As a result, a larger voltage amplitude is required to eject the same amount of liquid. Can happen.
The voltage amplitude here refers to the voltage range from the highest voltage value to the lowest voltage value of the drive signal, and the drive signal COM-A refers to the range from the highest voltage Vmax to the lowest voltage Vmin.

Therefore, in order to cope with the case where the characteristics of the piezoelectric element Pzt are different for each actuator substrate 40 (head unit 3), the characteristics of the piezoelectric element Pzt are measured in advance, and the voltage amplitude of the drive signal is set in accordance with the measured characteristics. The measure to do is taken. Specifically, for the actuator substrate 40 composed of the highly efficient piezoelectric element Pzt, the voltage amplitude of the drive signal COM-A is reduced, and for the actuator substrate 40 composed of the low efficiency piezoelectric element Pzt. Therefore, a measure is taken to increase the voltage amplitude of the drive signal COM-A.
In order to set the voltage amplitude of the drive signal COM-A according to the characteristics of the piezoelectric element Pzt, for example, the control unit 110 multiplies the original data dA (each discrete value thereof) by a predetermined coefficient and outputs it. On the other hand, in order to set the voltage amplitude of the drive signal COM-A, the first drive circuit 120a
In the set voltage amplitude, the voltage Vmax that is the output of the voltage source E1a, the voltage Vcen that is the output of the voltage source Eda, and the voltage Vmin that is the output of the voltage source E2a are matched so as to match three voltages that are constant values. Because it is necessary to change each.

  Although another configuration of the first drive circuit 120a has been described here, the other configuration of the second drive circuit 120 is not particularly illustrated, but is the voltage V1 that is the output of the voltage source E1b and the output of the voltage source E2b. The certain voltage V2 and the voltage V3 that is the output of the voltage source E3b may be variable.

  For the amplifier circuit 200a (200b), a set of voltage sources and switches is provided according to the number of voltages at which the voltage of the signal Ain (Bin) or the drive signal COM-A (COM-B) is constant. For example, in the amplifier circuit 200a, the voltage source outputs the voltage Vmin during the period P2, the switch is turned on, and the voltage source supplies the voltage Vmax during the period P4. The switch may be turned on, and the voltage source may output the voltage Vcen and the switch may be turned on in the period P6.

The amplifier circuit 200a (200b) has a configuration in which the signal Ain (Bin) is impedance-converted and output as the drive signal COM-A (COM-B). However, the signal Ain (Bin) is voltage-amplified and impedance-converted. Also good.
Specifically, in the first drive circuit 120a, the voltage amplifier 124a is eliminated, and the output signal of the DAC 122a is directly supplied to the amplifier circuit 200a. In the amplifier circuit 200a, the voltage at the node N1 is, for example, 1/10. The differential amplifier 221 may be configured to output a differential voltage between the step-down voltage and the output signal of the DAC 122.

The amplifier circuit 200a (200b) is not limited to the configuration shown in FIG. 13, but may be any configuration as long as the signal Ain (Bin) is converted into a low impedance during the voltage change period of the signal Ain (Bin) and output.
Therefore, another example of the amplifier circuit 200a (200b) applicable to the first drive circuit 120a (second drive circuit 120b) will be described next.

FIG. 16 is a diagram illustrating a configuration of an amplifier circuit (part 2) applicable to the first drive circuit 120a.
As shown in this figure, the amplifier circuit (part 2) has comparators 241 and 242 instead of the voltage amplifier 221 and the selector 223 in the amplifier circuit (part 1) shown in FIG. .
In the amplifier circuit (part 2), the signal Ain is supplied to each of the negative input terminal (−) of the comparator 241 and the negative input terminal (−) of the comparator 242. The node N 1 is connected to the positive input terminal (+) of the comparator 241 and the positive input terminal (+) of the comparator 242 together with the drain terminal of the transistor 231 and the drain terminal of the transistor 232.
Note that the one end of the capacitor C0 is connected to the node N1, and the other end of the capacitor C0 is grounded to the ground Gndn, as in the amplifier circuit (No. 1).

The comparators 241 and 242 compare the voltages after offsetting the voltage of one or both of the positive input terminal (+) and the negative input terminal (−).
Specifically, when the voltage of the signal Ain is expressed as Vin and the voltage of the node N1 is expressed as Out, the comparator 241 indicates that the signal Gt1 is at the H level if the voltage Out is equal to or higher than the voltage (Vin−V ₁ ). If the voltage Out is lower than the voltage (Vin−V ₁ ), the signal Gt1 is output at the L level. The voltage V ₁ is an offset amount set in the comparator 241.
The comparator 242, the voltage Out outputs signals Gt2 if the voltage (Vin + _{V 2)} or more H-level, the voltage Out outputs a low if the signal Gt2 than the voltage (Vin + _{V 2)} at the L level. The voltage V ₂ is an offset amount set in the comparator 242.

In the amplifier circuit (part 2) having such a configuration, if the voltage Out at the node N1 is lower than the voltage (Vin−V ₁ ), the signal Gt1 becomes L level and the transistor 231 is turned on. On the other hand, if the voltage Out is higher than the voltage (Vin + V ₂ ), the signal Gt2 becomes H level and the transistor 232 is turned on, so that the voltage Out is controlled to be lowered. .
Further, if the voltage Out at the node N1 is equal to or higher than the voltage (Vin−V ₁ ) and lower than the voltage (Vin + V ₂ ), that is, the voltage Out is V ₁ downward with respect to the voltage Vin of the signal Ain. only the shifted voltage, if within the range for the voltage which is shifted upward by V _2, transistors 231 and 232 are both turned off.
That is, in the amplifier circuit (part 2), the voltage Out is compared to the voltage Vin.
Vin−V ₁ ≦ Out <Vin + V ₂
It is controlled to become.

  In the amplifier circuit (No. 2), in a period in which the voltage of the signal Ain is constant, the voltage Out is within the above range with respect to the voltage Vin and the transistors 231 and 232 are turned off, but the output of the voltage source E1a One of the voltage Vmax, the voltage Vcen that is the output of the voltage source EDa, or the voltage Vmin that is the output of the voltage source E2a is applied to the node N1.

In the amplifier circuit (part 2), the amplifier circuit 200a that impedance-converts the signal Ain and outputs it as the drive signal COM-A has been described as an example. However, the amplifier circuit that impedance-converts the signal Bin and outputs it as the drive signal COM-B. The same configuration is applied to 200b.
Note that the first drive circuit 120a and the second drive circuit 120b to which the amplification circuit (part 2) is applied also share the voltage source EDa that outputs the voltage Vcen. Similarly, in the first drive circuit 120a and the second drive circuit 120b to which the amplifier circuit (part 2) is applied, the output voltage of each voltage source may be made variable.

FIG. 17 is a diagram illustrating a configuration of an amplifier circuit (part 3) applicable to the first drive circuit 120a.
As shown in this figure, the amplifier circuit (part 3) includes a modulation circuit 251, a gate driver 252, instead of the voltage amplifier 221, the selector 223, and the capacitor C0 in the amplifier circuit (part 1) shown in FIG. The configuration includes an inductor L1 and a capacitor C1.
The modulation circuit 251 converts the signal Ain into a modulation signal (pulse width modulation signal) having a pulse width corresponding to the voltage of the signal Ain. For example, the modulation circuit 251 outputs the modulation signal by comparing the voltage of the signal Ain with the voltage of the triangular wave signal.
The modulation circuit 251 may output not a pulse width modulation signal but a pulse density modulation signal, that is, a modulation signal having a density corresponding to the voltage of the signal Ain. Further, the modulation circuit 251 may correct the pulse width or the pulse density by feeding back the voltage of the node N1.

The gate driver 252 outputs a signal Gt1 to the gate terminal of the transistor 231 based on the modulation signal output from the modulation circuit 251 and outputs a signal Gt2 obtained by inverting the logic level of the signal Gt1 to the gate terminal of the transistor 232. . Thus, the transistors 231 and 232 are exclusively turned on / off according to the modulation signal, and an amplified modulation signal obtained by amplifying the modulation signal appears at the connection point of the drain terminals of the transistors 231 and 232.
One end of the inductor L1 is connected to the drain terminals of the transistors 231 and 232, and the other end of the inductor L1 is connected to one end of the capacitor C1 and the node N1. The other end of the capacitor C1 is grounded to the ground Gnd. As a result, the inductor L1 and the capacitor C1 function as a low-pass filter that smoothes (demodulates) the amplified modulated signal and outputs it as the drive signal COM-A.

In the amplifier circuit (part 3), during the period in which the voltage of the signal Ain is constant, the output point A13 of the low-pass filter (the connection point between the other end of the inductor L1 and one end of the capacitor C1) has almost the same voltage as the signal Ain. However, in the low-pass filter, the ripple component cannot be completely removed and may remain. However, according to the first drive circuit 120a to which the amplifier circuit (part 3) is applied, the node N1 includes the voltage Vmax that is the output of the voltage source E1a, the voltage Vcen that is the output of the voltage source EDa, or the voltage source E2a. Since any one of the output voltages Vmin is applied, it is possible to suppress a ripple in a period that should be constant.
If the ripple appearing at the output point A13 of the low-pass filter is large during the period when the voltage of the signal Ain is constant, the current flowing from the output point A13 toward the voltage source (or in the reverse direction) may not be ignored. . In this case, a switch may be provided between the output point A13 and the node N1 that is turned off when the signal OEa is at the H level and turned on when the signal OEa is at the L level.

In the amplifier circuit (part 3), the amplifier circuit 200a that impedance-converts the signal Ain and outputs it as the drive signal COM-A has been described as an example. However, the amplifier circuit that impedance-converts the signal Bin and outputs it as the drive signal COM-B. The same configuration is applied to 200b.
Note that the first drive circuit 120a and the second drive circuit 120b to which the amplifier circuit (part 3) is applied also share the voltage source EDa that outputs the voltage Vcen. Similarly, in the first drive circuit 120a and the second drive circuit 120b to which the amplifier circuit (part 2) is applied, the output voltage of each voltage source may be made variable.

  Since the target driven by the first drive circuit 120a and the second drive circuit 120b is a capacitor such as the piezoelectric element Pzt, even if both the transistors 231 and 232 are turned off after the voltage Out becomes constant, The voltage Out is kept constant. Therefore, it is not necessary to turn on any of the switches Sw1a, SwDa, or Sw2a (Sw1b, SwDb, Sw2b, or Sw3b) over the entire period in which the voltage of the signal Ain (Bin) is constant. May be part.

  In the above description, the liquid ejecting apparatus has been described as the printing apparatus 1, but a three-dimensional modeling apparatus that ejects liquid to form a solid, a textile printing apparatus that ejects liquid to dye a fabric, and the like may be used.

Each of the first drive circuit 120a and the second drive circuit 120b is configured to be mounted on the head unit 3, but may be configured to be mounted on the main board 100.
However, in the configuration in which the first drive circuit 120a and the second drive circuit 120b are mounted on the main board 100, a large amplitude signal needs to be supplied to the head unit 3 via the long flexible flat cable 190. It is disadvantageous in terms of power consumption and noise resistance. In other words, in the configuration in which the first drive circuit 120a and the second drive circuit 120b are mounted on the head unit 3, it is not necessary to supply a signal with a large amplitude to the flexible flat cable 190, so that power consumption and noise resistance are improved. Is advantageous.

  Furthermore, in the above description, the piezoelectric element Pzt for ejecting ink has been described as an example of the driving target of the first driving circuit 120a and the second driving circuit 120b. However, the first driving circuit 120a and the second driving circuit 120b are printed. When considered separately from the device, the drive target is not limited to the piezoelectric element Pzt, and can be applied to all loads having capacitive components such as an ultrasonic motor, a touch panel, an electrostatic speaker, and a liquid crystal panel. is there.

DESCRIPTION OF SYMBOLS 1 ... Printing apparatus (liquid discharge apparatus), 3 ... Head unit, 100 ... Main board, 120a 1st drive circuit, 120b ... 2nd drive circuit, 200a, 200b ... Unit circuit, 221 ... Differential amplifier, 223 ... Selector, 231, 231 ... transistor, 241,242 ... comparator, 251 ... modulation circuit, 252 ... gate driver, 442 ... cavity, Pzt ... piezoelectric element, N ... nozzle, C0, C1 ... condenser.

Claims (8)

A discharge unit that includes a piezoelectric element that is output from a predetermined output terminal and that is driven by a drive signal that is constant at a first voltage over a first period, and that discharges liquid by driving the piezoelectric element;
An amplification circuit that amplifies the original drive signal that is the source of the drive signal during a period in which the voltage of the original drive signal changes and supplies the amplified signal to the output terminal;
A constant voltage output circuit for applying the first voltage to the output terminal over part or all of the first period;
A liquid ejection apparatus comprising: The drive signal is constant at a second voltage different from the first voltage over a second period different from the first period;
The constant voltage output circuit is:
Applying the second voltage to the output terminal over part or all of the second period;
The liquid ejection apparatus according to claim 1, wherein The liquid discharge apparatus according to claim 2, wherein the constant voltage output circuit variably outputs at least one of the first voltage and the second voltage. The amplifier circuit is
A high-side transistor connected between the output terminal and a power supply point of the power supply high-side voltage;
A low-side transistor connected between the output end and the power supply point of the lower power supply voltage;
A differential amplifier that outputs a control signal obtained by amplifying a difference voltage between the voltage of the original drive signal and a voltage corresponding to the drive signal;
In the first case where the voltage change of the original drive signal is in the increasing direction, the control signal is selected and supplied to the gate terminal of the high-side transistor,
In the second case where the voltage change of the original drive signal is in a decreasing direction, a selector that selects the control signal and supplies it to the gate terminal of the low-side transistor;
The liquid ejecting apparatus according to claim 1, wherein the liquid ejecting apparatus includes: The selector is
In the first case, a signal for turning off the low-side transistor is selected and supplied to the gate terminal of the low-side transistor,
In the second case, a signal for turning off the high-side transistor is selected and supplied to the gate terminal of the high-side transistor.
The liquid ejecting apparatus according to claim 4, wherein the liquid ejecting apparatus is a liquid ejecting apparatus. The selector is
Over at least the first period,
A signal for turning off the high-side transistor is selected and supplied to the gate terminal of the high-side transistor,
A signal for turning off the low-side transistor is selected and supplied to the gate terminal of the low-side transistor;
The liquid ejection apparatus according to claim 4, wherein the liquid ejection apparatus is a liquid ejection apparatus. A first drive circuit that outputs a first drive signal that is output from the first output terminal and is constant at the first voltage over a first period and constant at the second voltage over a second period;
A second drive circuit that outputs a second drive signal that is constant at the first voltage over a third period that is output from the second output terminal and overlaps a part of the first period;
An ejection unit that ejects liquid droplets according to the first drive signal or the second drive signal;
Have
The first drive circuit includes:
A first amplification circuit that amplifies a first original drive signal that is a source of the first drive signal during a period in which the voltage of the first original drive signal changes, and supplies the amplified first drive signal to the first output terminal;
A first constant voltage output that applies the first voltage to the output terminal over part or all of the first period, and applies the second voltage to the first output terminal over part or all of the second period. Circuit,
Including
The second driving circuit includes:
A second amplification circuit that amplifies a second original drive signal that is a source of the second drive signal during a period in which the voltage of the second original drive signal changes, and supplies the amplified second drive signal to the second output terminal;
A second constant voltage output circuit for applying the first voltage to the second output terminal over part or all of the third period;
including,
A liquid discharge apparatus characterized by that. A drive circuit that drives a capacitive load with a drive signal that is output from a predetermined output terminal and is constant at a first voltage over a first period,
An amplification circuit that amplifies the original drive signal that is the source of the drive signal during a period in which the voltage of the original drive signal changes, and outputs the amplified signal from the output end;
A constant voltage output circuit for applying the first voltage to the output terminal over part or all of the first period;
A drive circuit comprising:

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