JP2019176454A - Power amplification circuit - Google Patents

Abstract

To provide a power amplification circuit having improved power addition efficiency.SOLUTION: A power amplification circuit 1 includes an amplification transistor 20, a variable voltage power supply 11 supplying a variable voltage Vcc2 to a collector of the amplification transistor 20, a bias circuit 22 having a constant current amplification transistor 220 outputting a DC bias current to a base of the amplification transistor 20, and a current limiting circuit 23 limiting the DC bias current. The current limiting circuit 23 includes a current limiting transistor 230, a resistance element 232 connected to a collector of the current limiting transistor 230 and the variable voltage power supply 11, and a resistance element 231 connected to a base of the current limiting transistor 230 and a base of a constant current amplification transistor 220. A DC limiting current flowing to the collector of the current limiting transistor 230 from the base of the constant current amplification transistor 220 is increased as a potential difference between a reference voltage and a variable voltage becomes larger.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power amplifier circuit.

  Along with miniaturization and weight reduction of mobile communication devices, there is a demand for miniaturization and low power consumption of power amplifiers as well as miniaturization and long life of batteries to be mounted. As a measure for reducing the power consumption of the power amplifier, a method has been proposed in which the power amplitude (envelope) of a high-frequency signal is tracked (envelope tracking method) and the voltage supply level to the power amplifier is varied according to the envelope (envelope tracking method) For example, Patent Document 1). Specifically, the voltage supply level to the power amplifier is increased according to the increase in the envelope of the high frequency signal, and the voltage supply level to the power amplifier is decreased according to the decrease in the envelope. As a result, the power consumption (current consumption) of the power amplifier can be reduced.

JP-A-2006-32301

  However, for example, in a conventional power amplifier using a grounded-emitter bipolar transistor, even if the power supply voltage (collector voltage) is varied according to the power amplitude of the high-frequency signal, the DC bias supplied to the base terminal of the transistor The current is substantially constant.

  The collector-emitter current (drive current) that strongly affects the power added efficiency is correlated with the base-emitter current (DC bias current). Therefore, if the base-emitter current is substantially constant, the collector-emitter current The current is also substantially constant. For this reason, even if the power supply voltage (collector voltage) is varied according to the power amplitude, the power added efficiency is not improved so much, and effective reduction in power consumption is not realized.

  Therefore, the present invention has been made to solve the above-described problems, and an object thereof is to provide a power amplifier circuit with improved power added efficiency.

  In order to achieve the above object, a power amplifier circuit according to an aspect of the present invention is a power amplifier circuit that amplifies a high-frequency signal and includes a first terminal, a second terminal, and a first control terminal, A first amplifying transistor that amplifies the high-frequency signal input from the first control terminal, and outputs the power-amplified high-frequency signal from the first terminal; and a variable voltage power supply that supplies a variable voltage to the first terminal A bias circuit that outputs a DC bias current, and a current limiting circuit that limits the DC bias current, the bias circuit having a third terminal, a fourth terminal, and a second control terminal, A constant current amplification transistor that outputs the DC bias current from a fourth terminal toward the first control terminal; and the current limiting circuit includes a fifth terminal, a sixth terminal, and a third control terminal, Above A current limiting transistor having six terminals connected to the fourth terminal, one end connected to the fifth terminal, the other end connected to the variable voltage power source, and one end connected to the third terminal; A second resistance element connected to the control terminal and having the other end connected to the second control terminal, and the current limiting circuit has the reference voltage when the variable voltage becomes smaller than the reference voltage. And the variable voltage are increased, the direct current limiting current flowing from the second control terminal to the fifth terminal via the third control terminal is increased.

  According to the present invention, it is possible to provide a power amplifier circuit with improved power added efficiency.

1 is a configuration diagram of a power amplifier circuit and its peripheral circuits according to a first embodiment. FIG. 6 is a configuration diagram of a power amplifier circuit and its peripheral circuits according to a first modification of the first embodiment. It is a schematic circuit diagram showing the connection of an amplification transistor and its peripheral circuit. It is a graph showing the relationship between the power supply voltage and collector current of the power amplifier circuit which concerns on a comparative example. 3 is a graph showing a relationship between a power supply voltage and a collector current of the power amplifier circuit according to the first embodiment. It is a graph showing the relationship between the high frequency output power of the power amplifier circuit which concerns on a comparative example, and power addition efficiency. 3 is a graph showing a relationship between high frequency output power and power added efficiency of the power amplifier circuit according to the first embodiment. 3 is a graph for explaining the operation of the current limiting circuit according to the first embodiment. FIG. 6 is a configuration diagram of a power amplifier circuit and its peripheral circuits according to a second modification of the first embodiment. FIG. 10 is a configuration diagram of a power amplifier circuit and its peripheral circuits according to a third modification of the first embodiment. 6 is a graph comparing the AM-AM characteristics of the power amplifier circuit according to Embodiment 1 and the power amplifier circuit according to Modification 2. 6 is a graph comparing the AM-PM characteristics of the power amplifier circuit according to the first embodiment and the power amplifier circuit according to Modification 2. FIG. 3 is a configuration diagram of a power amplifier circuit and its peripheral circuits according to a second embodiment. It is a graph which shows the relationship between the transmission power of a portable terminal, and its frequency. It is a schematic waveform diagram explaining the APT mode. It is a schematic waveform diagram explaining ET mode. (A) is a graph showing the relationship between the high frequency output power of the power amplifier circuit which concerns on a comparative example, a gain, an APT variable voltage, etc. FIG. (B) is a graph showing the relationship between the high frequency output power of the power amplifier circuit according to Embodiment 2, the gain, the APT variable voltage, and the like. (A) is a graph showing the relationship between the high frequency output power of the power amplifier circuit which concerns on a comparative example, a gain, a collector current, etc. FIG. (B) is a graph showing the relationship between the high frequency output power of the power amplifier circuit according to Embodiment 2, the gain, the collector current, and the like. FIG. 10 is a configuration diagram of a power amplifier circuit and its peripheral circuits according to a modification of the second embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the embodiments and the drawings. It should be noted that each of the embodiments described below shows a comprehensive or specific example. Numerical values, shapes, materials, constituent elements, arrangement of constituent elements, connection forms, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. Among the constituent elements in the following embodiments, constituent elements not described in the independent claims are described as optional constituent elements. In addition, the size or size ratio of the components shown in the drawings is not necessarily strict.

(Embodiment 1)
[1. Configuration of power amplifier circuit]
FIG. 1 is a configuration diagram of a power amplifier circuit 1 and its peripheral circuits according to the first embodiment. The figure shows the power amplifier circuit 1 and the constant current sources 14 and 24 according to the present embodiment. As shown in the figure, the power amplifier circuit 1 includes a high frequency input terminal 100, a high frequency output terminal 200, amplification transistors 10 and 20, variable voltage power supplies 11 and 21, bias circuits 12 and 22, and a current limiting circuit. 23, resistance elements 151 and 251, capacitors 152, 153 and 252, and an impedance matching circuit 254.

  With the above configuration, the power amplifier circuit 1 amplifies the high-frequency signal input from the high-frequency input terminal 100 by the amplification transistors 10 and 20 and outputs the amplified high-frequency signal from the high-frequency output terminal 200.

  The amplification transistor 10 has a base terminal, a collector terminal, and an emitter terminal, and is a previous stage amplification transistor that amplifies the power of a high-frequency signal input from the base terminal and outputs the power-amplified high-frequency signal from the collector terminal. .

  The amplification transistor 20 has a base terminal (first control terminal), a collector terminal (first terminal), and an emitter terminal (second terminal), and power amplifies a high-frequency signal input from the base terminal (first control terminal). Thus, the first amplifying transistor in the subsequent stage outputs the power-amplified high-frequency signal from the collector terminal (first terminal).

  The amplification transistors 10 and 20 are, for example, bipolar transistors having a base terminal, an emitter terminal, and a collector terminal. The amplifying transistors 10 and 20 are not limited to bipolar transistors, and may be, for example, MOS field effect transistors (Metal-Oxide-Semiconductor Field-Effect-Transistors: MOSFETs).

  The variable voltage power supply 11 supplies the variable voltage Vcc1 to the collector terminal of the amplification transistor 10. The variable voltage power supply 21 supplies the variable voltage Vcc2 to the collector terminal of the amplification transistor 20. Note that the variable voltages Vcc1 and Vcc2 vary synchronously. That is, when the variable voltage Vcc1 increases, the variable voltage Vcc2 also increases. When the variable voltage Vcc1 decreases, the variable voltage Vcc2 also decreases.

  The bias circuit 12 outputs a DC bias current toward the base terminal of the amplification transistor 10. More specifically, the bias circuit 12 includes a constant current amplification transistor 120, diode-connected transistors 121 and 122, a capacitor 123, and a resistance element 124.

  The constant current amplification transistor 120 has a collector terminal, an emitter terminal, and a base terminal, and outputs a DC bias current from the emitter terminal toward the base terminal of the amplification transistor 10. With this configuration, the constant current output from the constant current source 14 is input to the base terminal of the constant current amplification transistor 120, the constant current is amplified to become a DC bias current, and the resistance element from the emitter terminal of the constant current amplification transistor 120 The voltage is applied to the base terminal of the amplification transistor 10 via 151.

  The bias circuit 22 outputs an effective DC bias current Ief toward the base terminal of the amplification transistor 20. More specifically, the bias circuit 22 includes a constant current amplification transistor 220, diode-connected transistors 221 and 222, a capacitor 223, and a resistance element 224.

  The constant current amplification transistor 220 has a collector terminal (third terminal), an emitter terminal (fourth terminal), and a base terminal (second control terminal), and amplifies the DC bias current Ief from the emitter terminal (fourth terminal). It is a constant current amplification transistor that outputs toward the base terminal (first control terminal) of the transistor 20. With this configuration, the constant current output from the constant current source 24 is input to the base terminal of the constant current amplifying transistor 220, and the constant current is amplified to become the DC bias current Ief. 4 terminal) via the resistance element 251 and applied to the base terminal of the amplification transistor 20.

  The current limiting circuit 23 is a circuit that limits the DC bias current output from the bias circuit 22. More specifically, the current limiting circuit 23 includes a current limiting transistor 230 and resistance elements 231 and 232.

  The current limiting transistor 230 has a collector terminal (fifth terminal), an emitter terminal (sixth terminal), and a base terminal (third control terminal). The emitter terminal (sixth terminal) is the emitter of the constant current amplification transistor 220. It is connected to a terminal (fourth terminal).

  The resistance element 232 is a first resistance element having one end connected to the collector terminal (fifth terminal) of the current limiting transistor 230 and the other end connected to the variable voltage power supply 11. The other end of the resistance element 232 may be connected to the variable voltage power source 21.

  The resistance element 231 has a first end connected to the base terminal (third control terminal) of the current limiting transistor 230 and a second end connected to the base terminal (second control terminal) of the constant current amplification transistor 220. It is.

  When the variable voltage Vcc1 (Vcc2) becomes smaller than the reference voltage due to the connection configuration described above, the current limiting circuit 23 has a larger potential difference between the variable voltage Vcc1 (Vcc2) and the reference voltage, so that the constant current amplification transistor 220 A direct current limiting current which is a direct current flowing from the base terminal (second control terminal) to the collector terminal (fifth terminal) of the current limiting transistor 230 via the base terminal (third control terminal) of the current limiting transistor 230 is increased. . Note that the reference voltage is, for example, a maximum variable voltage that is set when a high-frequency input signal input to the power amplifier circuit 1 has the maximum power amplitude.

  Capacitors 152, 153, and 252 are DC-cut capacitance elements that remove the DC component of the high-frequency signal.

  The impedance matching circuit 254 is a circuit that matches the output impedance of the amplification transistor 10 and the input impedance of the amplification transistor 20.

  In the power amplifier circuit according to the present invention, the resistor elements 151 and 251, the capacitors 152, 153 and 252, and the impedance matching circuit 254 are appropriately deleted or replaced with other circuit elements according to the required specifications of the power amplifier circuit. It is a substitute and not an essential component.

  The power amplifying circuit 1 according to the present embodiment includes an amplifying transistor 20, a variable voltage power supply 11 that supplies a variable voltage Vcc2 (and Vcc1) to the collector terminal of the amplifying transistor 20, and a DC bias current to the base terminal of the amplifying transistor 20. Is provided with a constant current amplifying transistor 220 and a current limiting circuit 23 for limiting the DC bias current. The current limiting circuit 23 includes a current limiting transistor 230, a resistance element 232 connected to the collector terminal of the current limiting transistor 230 and the variable voltage power supply 11, a base terminal of the current limiting transistor 230, and a base terminal of the constant current amplification transistor 220. As the potential difference between the reference voltage and the variable voltage Vcc2 (and Vcc1) is larger, the direct current limiting current flowing from the base terminal of the constant current amplification transistor 220 to the collector terminal of the current limiting transistor 230 is increased. Enlarge.

  With this configuration, since the base current (base-emitter current) of the amplification transistor 20 is limited as the variable voltage Vcc2 (and Vcc1) decreases, the collector current (collector-emitter current) of the amplification transistor 20 can be reduced. That is, since the optimum DC bias current Ief according to the magnitude of the variable voltage Vcc2 (and Vcc1) can be flowed, it is possible to improve the power added efficiency (PAE: Power-Additive Efficiency) of the power amplifier circuit 1. It becomes. The circuit operation of the current limiting circuit 23 will be described later with reference to FIG.

  Further, as the variable voltage Vcc2 (and Vcc1) for driving the amplification transistor 20 decreases, the DC bias current Ief for optimizing the operating point of the amplification transistor 20 includes one transistor (current limiting transistor 230) and two resistance elements 231. And 232 are limited by the current limiting circuit 23. Thereby, the current limiting circuit 23 can be realized with a simplified circuit configuration, and can contribute to the miniaturization of the power amplifier circuit 1.

  In the present embodiment, the two-stage power amplifier circuit 1 in which the amplification transistors 10 and 20 are cascade-connected is shown, but the number of stages of the amplification transistors may be three or more. Thereby, the gain of the power amplifier circuit can be adjusted by the number of stages of the amplification transistors, and the gain can be increased as the number of stages is increased.

  Further, in the case of a power amplifier circuit having a configuration in which a plurality of amplifier transistors are connected in cascade, the amplifier transistor to which the current limiting circuit 23 is connected is a plurality of amplifier transistors as in the power amplifier circuit 1 according to the present embodiment. It is desirable that the amplifier transistor be disposed at the last stage closest to the output terminal of the power amplifier circuit.

  That is, the power amplifier circuit 1 according to the present embodiment includes a plurality of cascaded amplifier transistors including the amplifier transistor 20 that is the first amplifier transistor. Further, among the plurality of amplification transistors, the amplification transistor 20 arranged at the last stage closest to the output terminal of the power amplification circuit 1 is the first amplification transistor. In the last stage, a variable voltage power supply 21, a bias circuit 22, and a current limiting circuit 23 are arranged.

  As a result, in the last stage where the power level of the high-frequency signal is the highest, the optimum DC bias current Ief corresponding to the magnitude of the variable voltage can be supplied, so that the power addition efficiency of the power amplifier circuit is effectively improved. It becomes possible to improve.

[2. Configuration of Power Amplifier Circuit According to Modification 1]
FIG. 2 is a configuration diagram of the power amplifier circuit 1A and its peripheral circuits according to the first modification of the first embodiment. In the figure, a power amplifier circuit 1A according to this modification, constant current sources 14 and 24, an envelope detection circuit 3, an RF signal processing circuit (RFIC) 4, and a baseband signal processing circuit (BBIC) 5 are shown. It is shown.

  The power amplifier circuit 1A is different from the power amplifier circuit 1 according to the first embodiment only in that a power control circuit 2 is further added. Hereinafter, the power amplifier circuit 1A according to the present modification will be described with the same points as the power amplifier circuit 1 according to the first embodiment omitted, and different points will be mainly described.

The power supply control circuit 2 controls the variable voltages Vcc1 and Vcc2 according to the power amplitude (√ (i ² + Q ² )) of the high frequency input signal (or high frequency output signal) output from the envelope detection circuit 3. Examples of the power supply control circuit 2 include a DC-DC converter. When the power supply control circuit 2 is configured by a DC-DC converter, the variable voltage power supplies 11 and 21 may also be included in the DC-DC converter.

  Note that i and Q are as follows: i (t) = A (t) cosφ (t), where the high-frequency signal (voltage) is Acos (2πfct + φ) (A: voltage amplitude, fc: frequency, φ: phase) And Q (t) = A (t) sinφ (t).

The envelope detection circuit 3 extracts the i / Q data of the BBIC 5, detects the high frequency power amplitude (√ (i ² + Q ² )) of the high frequency input signal (or high frequency output signal), and outputs it to the power supply control circuit 2. .

  The BBIC 5 is a circuit that performs signal processing using an intermediate frequency band that is lower in frequency than the high-frequency input signal input to the power amplifier circuit 1A. The BBIC 5 has i / Q data of the high-frequency input signal.

  The RFIC 4 generates a high frequency input signal to be input to the power amplifier circuit 1A based on the i / Q data output from the BBIC 5 and the like.

According to the above configuration, the power supply control circuit 2 receives the information of the high frequency power amplitude (√ (i ² + Q ² )) of the high frequency input signal (or high frequency output signal) and controls the variable voltage Vcc2 (and Vcc1). . That is, the power amplifier circuit 1A varies the variable voltage Vcc2 (and Vcc1) based on an envelope tracking (ET) method that tracks the power amplitude of the high-frequency input signal. Therefore, according to the power amplifying circuit 1A according to the present modification, the power addition efficiency of the power amplifying circuit 1A based on the ET method is simplified as in the power amplifying circuit 1 according to the first embodiment. This can be improved by the configuration of the circuit 23.

  Here, the relationship between the high frequency output power of the power amplifier circuit 1A and the variable voltage Vcc2 (and Vcc1) in the ET system is shown.

  FIG. 3 is a schematic circuit diagram showing the connection between the amplification transistor and its peripheral circuit. The figure shows a grounded-emitter bipolar transistor, a power supply voltage Vcc, a load impedance (50Ω), and an impedance matching inductor.

  In the circuit shown in FIG. 3, when a high-frequency input signal is input from the base terminal and a high-frequency output signal is output from the collector terminal, the output power Pout and the power supply voltage Vcc of the high-frequency output signal are Satisfies the relational expression.

In the above formula 1, Vsat represents a collector-emitter voltage, and _RL represents a load impedance, for example, 50 (Ω).

  When the ET method is employed as in this modification, the amplification transistor operates in the saturation region, so Vsat is substantially zero. Therefore, when Vsat = 0 is substituted into Expression 1, the output power Pout (W) is expressed as Expression 2, and the voltage component Pout (V) of the output power is expressed as Expression 3.

  Here, k1 and k2 are constants.

  As shown in Equation 3, in the case of the ET method, the voltage component Pout (V) of the output power of the high-frequency output signal is expressed as a linear function of the power supply voltage Vcc. Thus, in the power amplifier circuit 1A according to the present modification, when operating the current limiting circuit 23, the power level of the high-frequency signal is not monitored, but the power supply voltage having a linear (primary function) relationship with the power level. Monitor Vcc.

  More specifically, the current limiting circuit 23 monitors the variable voltage Vcc2 (and Vcc1) by the ET method, and provides a sufficient DC bias current at the high variable voltage Vcc2 (and Vcc1) (≈high high-frequency signal power) as a bias circuit. The DC bias current is not allowed to flow through the bias circuit 22 unnecessarily at the low variable voltage Vcc2 (and Vcc1) (≈low high frequency signal power). As a result, a collector current (drive current) Icc2 that conforms to the ET method can flow, so that the power added efficiency of the power amplifier circuit 1A based on the ET method can be effectively improved.

[3. Amplification characteristics of power amplifier circuit]
FIG. 4A is a graph showing the relationship between the variable voltage Vcc and the collector current Ic of the power amplifier circuit according to the comparative example. FIG. 4B is a graph showing the relationship between the variable voltage Vcc2 and the collector current Icc2 of the power amplifier circuit 1 according to the first embodiment. The power amplifier circuit according to the comparative example has a circuit configuration in which the current limiting circuit 23 in the power amplifier circuit 1 according to the first embodiment is not provided and the bias circuit 22 is directly connected to the base terminal of the amplifier transistor 20. Yes.

4A and 4B show the static characteristics (DC characteristics) of the variable voltage-collector current when the base-emitter voltage (V _BE ) of the amplification transistor 20 is changed.

  In the power amplifier circuit according to the comparative example, as shown in FIG. 4A, the collector current Ic is substantially constant with respect to the change of the variable voltage Vcc (0.5V to 4.0V). In the power amplifier circuit according to the comparative example, even if the variable voltage Vcc is decreased in accordance with the power amplitude of the high frequency signal by, for example, the ET method, the DC bias current supplied directly from the bias circuit 22 to the base terminal of the amplifier transistor 20 The (base-emitter current) becomes substantially constant by the constant current output from the constant current source 24. Therefore, the collector current Ic that flows depending on the DC bias current is also substantially constant without corresponding to the decrease in the variable voltage Vcc.

  On the other hand, in the power amplifier circuit 1 according to the present embodiment, as shown in FIG. 4B, the collector current Icc2 decreases corresponding to the decrease in the variable voltage Vcc2 (0.5V to 4.0V). This is because, in the power amplifier circuit 1 according to the present embodiment, the current limiting circuit 23 limits (reduces) the DC bias current Ief output from the bias circuit 22 in response to the decrease in the variable voltage Vcc2. caused by. That is, in the power amplifier circuit 1 according to the present embodiment, for example, when the variable voltage Vcc2 is decreased in accordance with the power amplitude of the high-frequency signal by the ET method, the direct current supplied from the bias circuit 22 to the base terminal of the amplifier transistor 20 The bias current Ief (base-emitter current) is limited by the current limiting circuit 23 and decreases. Therefore, the collector current Icc2 that flows depending on the DC bias current Ief also decreases corresponding to the decrease in the variable voltage Vcc2.

  FIG. 5A is a graph showing the relationship between the high frequency output power and the power added efficiency of the power amplifier circuit according to the comparative example. FIG. 5B is a graph showing the relationship between the high-frequency output power of the power amplifier circuit 1 according to Embodiment 1 and the power added efficiency. More specifically, FIG. 5A shows the characteristics of high-frequency output power Pout-power added efficiency when the variable voltage Vcc is changed by the ET method in the power amplifier circuit according to the comparative example. FIG. 5B shows the characteristics of the high-frequency output power Pout-power added efficiency when the variable voltage Vcc2 is changed by the ET method in the power amplifier circuit 1 according to the first embodiment.

  As shown in FIGS. 5A and 5B, the power added efficiency increases as the variable voltage Vcc2 (or Vcc) is decreased at a predetermined high-frequency output power Pout. However, comparing FIG. 5A and FIG. 5B, for example, when the high-frequency output power Pout is 20 dBm, the power added efficiency in the power amplifier circuit according to the comparative example (FIG. 5A) is 49%, whereas the embodiment In the power amplifier circuit 1 (FIG. 5B) according to 1, the power added efficiency is improved to 52%. When the high-frequency output power Pout is 15 dBm, the power added efficiency in the power amplifier circuit according to the comparative example (FIG. 5A) is 37%, whereas the power amplifier circuit 1 according to the first embodiment (FIG. 5B). Then, the power added efficiency is improved to 43%.

  When the variable voltage Vcc2 (or Vcc) is decreased in accordance with the power amplitude of the high-frequency signal by the ET method, the power added efficiency increases as the variable voltage decreases. However, in the power amplifier circuit according to the comparative example, the variable voltage Vcc decreases, but the collector current Ic is substantially constant. On the other hand, in the power amplifier circuit 1 according to the first embodiment, the collector current Icc2 also decreases as the variable voltage Vcc2 decreases. Therefore, in power amplifying circuit 1 according to the first embodiment, the power added efficiency defined by the product of variable voltage Vcc2 (and Vcc1) and collector current Icc2 can be effectively improved.

  Next, the operation of the current limiting circuit 23 according to the present embodiment will be described.

  FIG. 6 is a graph for explaining the operation of the current limiting circuit 23 according to the first embodiment. FIG. 6A shows a graph showing the relationship between the collector-emitter voltage Vce (see FIG. 1) of the current limiting transistor 230 and the variable voltage Vcc2. FIG. 4B shows a graph showing the relationship between the DC bias current Ief (see FIG. 1) output from the bias circuit 22 to the base terminal of the amplification transistor 20 and the variable voltage Vcc2. FIG. 6C shows a graph showing the relationship between the collector current Icc2 (see FIG. 1) of the amplification transistor 20 and the variable voltage Vcc2. (D) of the same figure shows the relationship between the variable voltage Vcc2 and the current Isub_c (see FIG. 1) flowing through the resistance element 232 from the variable voltage power supply 11 (or 21) toward the collector terminal of the current limiting transistor 230. It is shown. FIG. 4E shows a graph showing the relationship between the variable voltage Vcc2 and the current Isub_b (see FIG. 1) flowing through the resistance element 231 from the bias circuit 22 toward the base terminal of the current limiting transistor 230. . FIG. 5F is a graph showing the relationship between the current Isub (see FIG. 1) flowing from the emitter terminal of the current limiting transistor 230 toward the connection point between the current limiting circuit 23 and the bias circuit 22 and the variable voltage Vcc2. It is shown. Here, Isub = Isub_b + Isub_c is established.

  When the variable voltage Vcc2 (and Vcc1) decreases and Vcc2 becomes lower than 1.5V, the collector potential becomes lower than the base potential of the current limiting transistor 230, and current flows from the base terminal of the current limiting transistor 230 toward the collector terminal. Flows out (in FIG. 6D, Isub_c becomes a negative current). At this time, a part of the constant current supplied to the base terminal of the constant current amplification transistor 220 of the bias circuit 22 is branched toward the resistance element 231, and Isub_b flows (in FIG. 6E, Isub_b is positive). Current). Thereby, the DC bias current Ief output from the emitter terminal of the constant current amplification transistor 220 decreases corresponding to the amount of the constant current branched toward the resistance element 231 (in FIG. 6B, Ief decreases). As the DC bias current Ief decreases, the collector current Icc2 also decreases ((c) in FIG. 6). That is, the current limiting circuit 23 reduces the DC bias current Ief by taking in a constant current before being amplified to the DC bias current Ief in accordance with the decrease in the variable voltage Vcc2. It should be noted that Isub_b from which the constant current is branched toward the resistance element 231 is the current level before current amplification to the DC bias current Ief, and therefore toward the connection point between the current limiting circuit 23 and the bias circuit 22. The flowing current Isub is also sufficiently smaller than the DC bias current Ief ((f) in FIG. 6). For this reason, the current Isub does not affect the increase / decrease of the DC bias current Ief with respect to the increase / decrease of the variable voltage Vcc2.

  That is, when the variable voltage Vcc2 (and Vcc1) becomes smaller than the reference voltage, the current limiting circuit 23 increases the base terminal of the constant current amplification transistor 220 as the potential difference between the reference voltage and the variable voltage Vcc2 (and Vcc1) increases. The direct current limiting current (-Isub_c), which is a direct current flowing from the current through the base terminal of the current limiting transistor 230 to the collector terminal of the current limiting transistor 230, is increased.

  By the above operation of the current limiting circuit 23, the simplified circuit composed of one current limiting transistor 230 and two resistance elements 231 and 232 reduces the collector voltage Icc2 of the amplifying transistor 20 as the variable voltage Vcc2 decreases. it can.

  Note that, as described with reference to FIGS. 6A to 6F, according to the current limiting circuit 23 according to the present embodiment, in particular, power addition at intermediate power (≈20 Bm) and low power (<15 dBm). Efficiency can be improved effectively.

  In the current limiting circuit 23, a resistance element may be inserted in series with the emitter terminal of the current limiting transistor 230. Thereby, it is possible to adjust the rate of change of DC bias current Ief with respect to the change of variable voltage Vcc2 (and Vcc1).

[4. Configuration of Power Amplifier Circuit According to Modification 2]
FIG. 7A is a configuration diagram of a power amplifier circuit 1B and its peripheral circuits according to the second modification of the first embodiment. The figure shows a power amplifier circuit 1B and constant current sources 14 and 24 according to this modification. As shown in the figure, the power amplifier circuit 1B includes a high frequency input terminal 100, a high frequency output terminal 200, amplification transistors 10 and 20, variable voltage power supplies 11 and 21, bias circuits 12 and 22, and a current limiting circuit. 23A. Similarly to power amplification circuit 1 according to the first embodiment, power amplification circuit 1B further includes a resistance element, a capacitor, and an impedance matching circuit. The power amplifying circuit 1B shown in the figure is different from the power amplifying circuit 1 according to the first embodiment in the configuration of the current limiting circuit 23A. Hereinafter, regarding the power amplifying circuit 1B according to this modification, the description of the same configuration as that of the power amplifying circuit 1 according to the first embodiment will be omitted, and a description will be given focusing on a different configuration.

  The current limiting circuit 23 </ b> A is a circuit that limits the DC bias current output from the bias circuit 22. More specifically, the current limiting circuit 23A includes a current limiting transistor 230, resistance elements 231, 232A, and 232B, and capacitors 233 and 234.

  The current limiting transistor 230 has a collector terminal (fifth terminal), an emitter terminal (sixth terminal), and a base terminal (third control terminal). The emitter terminal (sixth terminal) is the emitter of the constant current amplification transistor 220. It is connected to a terminal (fourth terminal).

  The resistance element 231 has a first end connected to the base terminal (third control terminal) of the current limiting transistor 230 and a second end connected to the base terminal (second control terminal) of the constant current amplification transistor 220. It is.

  The resistance element 232A is a first divided resistor having one end connected to the collector terminal (fifth terminal) of the current limiting transistor 230 and the other end connected to one end of the resistance element 232B. The resistance element 232 </ b> B is a second divided resistor whose other end is connected to the variable voltage power supply 11. The other end of the resistance element 232B may be connected to the variable voltage power source 21.

  Capacitor 233 is a first capacitance element connected in parallel to resistance element 232A. The capacitor 234 is a second capacitance element connected between the base terminal (third control terminal) and the collector terminal (fifth terminal) of the current limiting transistor 230.

  Note that a resistance element may be inserted in series between the emitter terminal of the current limiting transistor 230 and the emitter terminal of the constant current amplification transistor 220. Thereby, it is possible to adjust the rate of change of DC bias current Ief with respect to the change of variable voltage Vcc2 (and Vcc1).

[5. Configuration of Power Amplifier Circuit According to Modification 3]
FIG. 7B is a configuration diagram of a power amplifier circuit 1C and its peripheral circuits according to Modification 3 of Embodiment 1. In the figure, a power amplifier circuit 1C according to this modification and constant current sources 14 and 24 are shown. As shown in the figure, the power amplifier circuit 1C includes a high frequency input terminal 100, a high frequency output terminal 200, amplification transistors 10 and 20, variable voltage power supplies 11 and 21, bias circuits 12 and 22, and a current limiting circuit. 23B. Similarly to power amplification circuit 1 according to the first embodiment, power amplification circuit 1C further includes a resistance element, a capacitor, and an impedance matching circuit. The power amplifying circuit 1C shown in the figure is different from the power amplifying circuit 1 according to the first embodiment in the configuration of the current limiting circuit 23B. Hereinafter, regarding the power amplifying circuit 1C according to the present modification, the description of the same configuration as that of the power amplifying circuit 1 according to the first embodiment will be omitted, and a description will be given focusing on a different configuration.

  The current limiting circuit 23B is a circuit that limits the DC bias current output from the bias circuit 22. More specifically, the current limiting circuit 23B includes a current limiting transistor 230, resistance elements 231, 232A, and 232B, and capacitors 234 and 236.

  The current limiting transistor 230 has a collector terminal (fifth terminal), an emitter terminal (sixth terminal), and a base terminal (third control terminal), and the emitter terminal (sixth terminal) is fixed via a resistance element 235. The current amplifying transistor 220 is connected to the emitter terminal (fourth terminal).

  The resistance element 231 has a first end connected to the base terminal (third control terminal) of the current limiting transistor 230 and a second end connected to the base terminal (second control terminal) of the constant current amplification transistor 220. It is.

  The resistance element 232A is a first divided resistor having one end connected to the collector terminal (fifth terminal) of the current limiting transistor 230 and the other end connected to one end of the resistance element 232B. The resistance element 232 </ b> B is a second divided resistor whose other end is connected to the variable voltage power supply 11. The other end of the resistance element 232B may be connected to the variable voltage power source 21.

  Capacitor 236 is a first capacitive element connected between the connection point of resistance elements 232A and 232B and the emitter terminal (sixth terminal) of current limiting transistor 230. The capacitor 234 is a second capacitance element connected between the base terminal (third control terminal) and the collector terminal (fifth terminal) of the current limiting transistor 230.

  Note that a resistance element may be inserted in series between the emitter terminal of the current limiting transistor 230 and the emitter terminal of the constant current amplification transistor 220. Thereby, it is possible to adjust the rate of change of DC bias current Ief with respect to the change of variable voltage Vcc2 (and Vcc1).

[6. Distortion Characteristics of Power Amplifier Circuits According to Modification 2 and Modification 3]
FIG. 8A is a graph comparing AM (amplitude modulation) -AM (amplitude modulation) characteristics of the power amplifier circuit 1 according to the first embodiment and the power amplifier circuit 1B according to the second modification. FIG. 8B is a graph comparing AM (amplitude modulation) -PM (phase modulation) characteristics of the power amplifier circuit 1 according to Embodiment 1 and the power amplifier circuit 1B according to Modification 2. Here, the AM-AM characteristic is a characteristic representing a ratio between the input signal amplitude and the output signal amplitude of the power amplifier circuit. The AM-PM characteristic is a characteristic representing the ratio between the input signal amplitude and the output signal phase of the power amplifier circuit. FIG. 8A shows the relationship between high-frequency output power and AM-AM characteristics, and FIG. 8B shows the relationship between high-frequency output power and AM-PM characteristics.

  Compared with the power amplifier circuit 1 according to the first embodiment, the power amplifier circuit 1B according to the second modification example has both an AM-AM characteristic (Gradient of Voltage Gain) and an AM-PM characteristic (Gradient of Voltage Phase). , Approaching 0. That is, in the power amplifier circuit 1B according to the second modification, the capacitors 233 and 234 are added in the current limiting circuit 23A, so that nonlinearity is improved and distortion characteristics can be improved.

  The power amplification circuit 1C according to the modification 3 can be said to be the same as the power amplification circuit 1B according to the modification 2, and the nonlinearity is improved by adding the capacitors 234 and 236 in the current limiting circuit 23B. As a result, the distortion characteristics can be improved.

(Embodiment 2)
In the first embodiment, in the two-stage power amplification circuit 1 in which the amplification transistors 10 and 20 are connected in cascade, the configuration in which the current limiting circuit 23 is connected to the amplification transistor 20 in the subsequent stage (power stage) is illustrated. On the other hand, in this embodiment, a configuration in which a current limiting circuit is connected to the amplification transistor 10 in the previous stage (drive stage) is illustrated.

  FIG. 9 is a configuration diagram of a power amplifier circuit 1D and its peripheral circuits according to the second embodiment. In the figure, a power amplifier circuit 1D according to the present embodiment and constant current sources 14 and 24 are shown. As shown in the figure, a power amplifier circuit 1D includes a high frequency input terminal 100, a high frequency output terminal 200, amplification transistors 10 and 20, variable voltage power supplies 11 and 21, bias circuits 12 and 22, and a current limiting circuit. 13 and 23, resistance elements 151 and 251, capacitors 152, 153 and 252, and an impedance matching circuit 254.

  With the above configuration, the power amplifier circuit 1D amplifies the high-frequency signal input from the high-frequency input terminal 100 by the amplification transistors 10 and 20, and outputs the amplified high-frequency signal from the high-frequency output terminal 200.

  The power amplifier circuit 1D according to the second embodiment is different from the power amplifier circuit 1 according to the first embodiment in that a current limiting circuit 13 is added. Hereinafter, regarding the power amplifying circuit 1D according to the present embodiment, the description of the same configuration as that of the power amplifying circuit 1 according to the first embodiment will be omitted, and a description will be given focusing on a different configuration.

  The amplification transistor 10 has a base terminal (first control terminal), a collector terminal (first terminal), and an emitter terminal (second terminal), and power amplifies a high-frequency signal input from the base terminal (first control terminal). The first amplification transistor in the previous stage (drive stage) that outputs the power-amplified high-frequency signal from the collector terminal (first terminal).

  The amplification transistor 20 has a base terminal (first control terminal), a collector terminal (first terminal), and an emitter terminal (second terminal), and power amplifies a high-frequency signal input from the base terminal (first control terminal). Thus, it is a first amplification transistor in the subsequent stage (power stage) that outputs the power-amplified high-frequency signal from the collector terminal (first terminal).

  The bias circuit 12 outputs an effective DC bias current Ief1 toward the base terminal of the amplification transistor 10. More specifically, the bias circuit 12 includes a constant current amplification transistor 120, diode-connected transistors 121 and 122, a capacitor 123, and a resistance element 124.

  The constant current amplification transistor 120 has a collector terminal (third terminal), an emitter terminal (fourth terminal), and a base terminal (second control terminal), and amplifies the DC bias current Ief1 from the emitter terminal (fourth terminal). It is a constant current amplification transistor that outputs toward the base terminal (first control terminal) of the transistor 10. With this configuration, the constant current output from the constant current source 14 is input to the base terminal of the constant current amplifying transistor 120, the constant current is amplified to become the DC bias current Ief1, and the emitter terminal (the first terminal of the constant current amplifying transistor 120) (4 terminals) via the resistance element 151 and applied to the base terminal of the amplification transistor 10.

  The bias circuit 22 outputs an effective DC bias current Ief2 toward the base terminal of the amplification transistor 20. More specifically, the bias circuit 22 includes a constant current amplification transistor 220, diode-connected transistors 221 and 222, a capacitor 223, and a resistance element 224.

  The constant current amplification transistor 220 has a collector terminal (third terminal), an emitter terminal (fourth terminal), and a base terminal (second control terminal), and amplifies the DC bias current Ief from the emitter terminal (fourth terminal). It is a constant current amplification transistor that outputs toward the base terminal (first control terminal) of the transistor 20. With this configuration, the constant current output from the constant current source 24 is input to the base terminal of the constant current amplification transistor 220, the constant current is amplified to become the DC bias current Ief2, and the emitter terminal of the constant current amplification transistor 220 (the first terminal) 4 terminal) via the resistance element 251 and applied to the base terminal of the amplification transistor 20.

  The current limiting circuit 13 is a circuit that limits the DC bias current output from the bias circuit 12. More specifically, the current limiting circuit 13 includes a current limiting transistor 130 and resistance elements 131 and 132.

  The current limiting transistor 130 has a collector terminal (fifth terminal), an emitter terminal (sixth terminal), and a base terminal (third control terminal), and the emitter terminal (sixth terminal) is the emitter of the constant current amplification transistor 120. It is connected to a terminal (fourth terminal).

  The resistance element 132 is a first resistance element having one end connected to the collector terminal (fifth terminal) of the current limiting transistor 130 and the other end connected to the variable voltage power supply 11. The other end of the resistance element 132 may be connected to the variable voltage power source 21.

  The resistor element 131 has one end connected to the base terminal (third control terminal) of the current limiting transistor 130 and the other end connected to the base terminal (second control terminal) of the constant current amplification transistor 120. It is.

  When the variable voltage Vcc1 (Vcc2) becomes smaller than the reference voltage due to the connection configuration described above, the current limiting circuit 13 increases the potential difference between the variable voltage Vcc1 (Vcc2) and the reference voltage as the potential of the constant current amplification transistor 120 increases. A direct current limiting current that is a direct current flowing from the base terminal (second control terminal) to the collector terminal (fifth terminal) of the current limiting transistor 130 via the base terminal (third control terminal) of the current limiting transistor 130 is increased. . The reference voltage is, for example, the maximum variable voltage that is set when the high-frequency input signal input to the power amplifier circuit 1D has the maximum power amplitude.

  The current limiting circuit 23 is a circuit that limits the DC bias current output from the bias circuit 22. More specifically, the current limiting circuit 23 includes a current limiting transistor 230 and resistance elements 231 and 232.

  The current limiting transistor 230 has a collector terminal (fifth terminal), an emitter terminal (sixth terminal), and a base terminal (third control terminal). The emitter terminal (sixth terminal) is the emitter of the constant current amplification transistor 220. It is connected to a terminal (fourth terminal).

  The resistance element 232 is a first resistance element having one end connected to the collector terminal (fifth terminal) of the current limiting transistor 230 and the other end connected to the variable voltage power supply 11. The other end of the resistance element 232 may be connected to the variable voltage power source 21.

  The resistance element 231 has a first end connected to the base terminal (third control terminal) of the current limiting transistor 230 and a second end connected to the base terminal (second control terminal) of the constant current amplification transistor 220. It is.

  When the variable voltage Vcc1 (Vcc2) becomes smaller than the reference voltage due to the connection configuration described above, the current limiting circuit 23 has a larger potential difference between the variable voltage Vcc1 (Vcc2) and the reference voltage, so that the constant current amplification transistor 220 A direct current limiting current which is a direct current flowing from the base terminal (second control terminal) to the collector terminal (fifth terminal) of the current limiting transistor 230 via the base terminal (third control terminal) of the current limiting transistor 230 is increased. .

  That is, the power amplifier circuit 1D according to the present embodiment includes a plurality of cascaded amplifier transistors including the amplifier transistors 10 and 20 that are the first amplifier transistors. Further, among the plurality of amplification transistors, the amplification transistor 20 arranged at the last stage closest to the output terminal of the power amplification circuit 1D is the first amplification transistor. In the last stage, a variable voltage power supply 21, a bias circuit 22, and a current limiting circuit 23 are arranged. Further, among the plurality of amplification transistors, the amplification transistor 10 disposed in at least one stage before the last stage closest to the output terminal of the power amplification circuit 1D is the first amplification transistor. In the preceding stage, a variable voltage power supply 11, a bias circuit 12, and a current limiting circuit 13 are arranged.

  With this configuration, the base current (base-emitter current) of the amplification transistors 10 and 20 is limited as the variable voltage Vcc2 (and Vcc1) decreases, so the collector current (collector-emitter current) of the amplification transistors 10 and 20 is limited. Can be reduced. That is, since the optimum DC bias currents Ief1 and Ief2 corresponding to the magnitude of the variable voltage Vcc2 (and Vcc1) can be flowed, it is possible to improve the power added efficiency (PAE) of the power amplifier circuit 1D. Note that the circuit operations of the current limiting circuits 13 and 23 are the same as the circuit operation (FIG. 6) of the current limiting circuit 23 in the first embodiment, and thus the description thereof is omitted in this embodiment.

  Further, as the variable voltage Vcc2 (and Vcc1) for driving the amplifying transistors 10 and 20 decreases, the DC bias currents Ief1 and Ief2 for optimizing the operating point of the amplifying transistors 10 and 20 are each one transistor (current limiting transistor 130). Or 230) and two resistance elements 231 and 232 (or resistance elements 131 and 132). Thereby, the current limiting circuits 13 and 23 can be realized by a simplified circuit configuration, and can contribute to the miniaturization of the power amplifier circuit 1D.

  FIG. 10 is a graph showing the relationship between the transmission power of the mobile terminal and its frequency. This figure shows the distribution of transmission power in WCDMA (registered trademark) (Wideband Code Division Multiple Access), and specifically shows the frequency of use for each transmission power in WCDMA (registered trademark). From the figure, it can be seen that the frequency at which the transmission power is 0 dBm or less occupies 50% or more. From this, it can be seen that reducing the current consumption of the power amplifier circuit when using low transmission power of 0 dBm or less greatly contributes to the reduction of power consumption of the portable terminal and the long-time operation of the battery.

  FIG. 11A is a schematic waveform diagram illustrating an APT (Average Power Tracking) mode. FIG. 11B is a schematic waveform diagram for explaining an ET (envelope tracking) mode. As described in the first embodiment, the ET mode is a mode in which the power amplitude (envelope) of the high-frequency signal is tracked and the voltage supply level to the power amplifier circuit is varied according to the envelope. In contrast, the APT mode is a mode in which the average power amplitude of the high-frequency signal calculated every predetermined period is tracked and the voltage supply level to the power amplifier circuit is varied according to the average power amplitude.

  In the case of the ET mode, the power added efficiency (PAE) can be improved by arranging the current limiting circuit 23 in the subsequent stage (power stage) as in the power amplifier circuit 1 according to the first embodiment. On the other hand, in the case of the APT mode, by arranging the current limiting circuit 13 in the previous stage (drive stage) like the power amplifier circuit 1D according to the present embodiment, for example, high frequency output power (RF output) At a low output level such that the power Pout) is 0 dBm or less, the collector current Icc1 can be reduced according to the variable voltage, similarly to the characteristic shown in FIG. 4B. For this reason, the low collector current Icc1 that conforms to the low output power can be realized, and the power added efficiency (PAE) can be effectively improved.

  FIG. 12A shows a high frequency output power (RF output power Pout), a gain (Gain), an APT variable voltage (APT_Vcc), and a noise level (E-UTRA) in the E-UTRA according to the comparative example. It is a graph showing the relationship with). FIG. 12B shows high-frequency output power (RF output power Pout), gain (Gain), APT variable voltage (APT_Vcc), and noise level in E-UTRA of the power amplifier circuit according to the second embodiment. It is a graph showing the relationship with (E-UTRA).

  The power amplifying circuit according to the comparative example does not have the current limiting circuits 13 and 23 in the power amplifying circuit 1D according to the second embodiment, the bias circuit 12 is directly connected to the base terminal of the amplifying transistor 10, and the bias circuit 22 is The circuit configuration is directly connected to the base terminal of the amplification transistor 20.

  In both the power amplifier circuit according to the comparative example and the power amplifier circuit 1D according to the second embodiment, the variable voltage Vcc1 (Vcc2) is adjusted in accordance with the magnitude of the high-frequency output power by adopting the APT mode ( APT_Vcc (V) in FIG. However, in the region where the high-frequency output power is low, the gain of the power amplifier circuit 1D according to the second embodiment is lower. According to the power amplifying circuit 1D according to the second embodiment, the base current (base-emitter current) of the amplifying transistors 10 and 20 increases / decreases in accordance with the increase / decrease of the variable voltage Vcc1 (Vcc2). Is possible.

  FIG. 13A shows the high frequency output power (RF output power Pout), gain (Gain), collector current Icc (collected value of collector currents Icc1 and Icc2), and E-UTRA of the power amplifier circuit according to the comparative example. It is a graph showing the relationship with the noise level (E-UTRA) in. FIG. 13B shows the high-frequency output power (RF output power Pout), gain (Gain), collector current Icc (collected value of collector currents Icc1 and Icc2) of the power amplifier circuit according to the second embodiment, It is a graph showing the relationship with the noise level (E-UTRA) in E-UTRA. In the region where the high-frequency output power is low, the power amplifier circuit 1D according to the second embodiment has a lower collector current Icc. According to the power amplifying circuit 1D according to the second embodiment, the collector current can be changed to the minimum by changing the base current (base-emitter current) of the amplifying transistors 10 and 20 corresponding to the decrease in the variable voltage Vcc1 (Vcc2). The current can be reduced.

  According to the power amplifying circuit 1D according to the present embodiment, the power limiting efficiency (PAE) in the case of the APT mode is effectively achieved by connecting the current limiting circuit 13 to the amplifying transistor 10 in the previous stage (drive stage). Can be improved. In addition, since the current limiting circuit 23 is connected to the amplification transistor 20 in the subsequent stage (power stage), the optimum DC bias corresponding to the magnitude of the variable voltage in the last stage where the power level of the high frequency signal is the highest. Since the current Ief can flow, the power added efficiency (PAE) in the case of the ET mode can be effectively improved.

  FIG. 14 is a configuration diagram of a power amplifier circuit 1E and its peripheral circuits according to a modification of the second embodiment. In the figure, a power amplifier circuit 1E according to this modification and constant current sources 14 and 24 are shown. As shown in the figure, the power amplifier circuit 1E includes a high frequency input terminal 100, a high frequency output terminal 200, amplification transistors 10 and 20, variable voltage power supplies 11 and 21, bias circuits 12 and 22, and a current limiting circuit. 13, resistance elements 151 and 251, capacitors 152, 153 and 252, and an impedance matching circuit 254.

  With the above configuration, the power amplifier circuit 1E amplifies the high-frequency signal input from the high-frequency input terminal 100 by the amplification transistors 10 and 20, and outputs the amplified high-frequency signal from the high-frequency output terminal 200.

  The power amplifying circuit 1E according to the present modification differs from the power amplifying circuit 1D according to the second embodiment in that the current limiting circuit 23 is not added. Hereinafter, regarding the power amplifying circuit 1E according to this modification, the description of the same configuration as that of the power amplifying circuit 1D according to the second embodiment will be omitted, and a description will be given focusing on a different configuration.

  The amplification transistor 20 has a base terminal, a collector terminal, and an emitter terminal. The amplification transistor 20 is a subsequent amplification transistor that amplifies the high-frequency signal input from the base terminal and outputs the power-amplified high-frequency signal from the collector terminal. .

  The bias circuit 22 outputs a DC bias current toward the base terminal of the amplification transistor 20. More specifically, the bias circuit 22 includes a constant current amplification transistor 220, diode-connected transistors 221 and 222, a capacitor 223, and a resistance element 224.

  The constant current amplification transistor 220 has a collector terminal, an emitter terminal, and a base terminal, and outputs a DC bias current from the emitter terminal toward the base terminal of the amplification transistor 20. With this configuration, the constant current output from the constant current source 24 is input to the base terminal of the constant current amplification transistor 220, the constant current is amplified to become a DC bias current, and the resistance element from the emitter terminal of the constant current amplification transistor 220 The voltage is applied to the base terminal of the amplification transistor 20 via 251.

  That is, the power amplifier circuit 1E according to the present modification includes a plurality of cascaded amplifier transistors including the amplifier transistor 10 that is the first amplifier transistor. Further, among the plurality of amplification transistors, the amplification transistor 10 arranged in at least one stage before the last stage closest to the output terminal of the power amplification circuit 1E is the first amplification transistor. In the preceding stage, a variable voltage power supply 11, a bias circuit 12, and a current limiting circuit 13 are arranged.

  According to the power amplifying circuit 1E according to the present modification, the current limiting circuit 13 is connected to the amplifying transistor 10 in the previous stage (drive stage), thereby effectively increasing the power added efficiency (PAE) in the APT mode. Can be improved.

(Other embodiments, etc.)
As described above, the power amplifier circuit according to the embodiment of the present invention has been described with reference to the embodiment and its modification. However, the power amplifier circuit of the present invention is limited to the above-described embodiment and its modification. is not. A person skilled in the art can conceive of another embodiment realized by combining arbitrary constituent elements in the above-described embodiment and its modifications, and the above-mentioned embodiment and its modifications without departing from the gist of the present invention. Modifications obtained by various modifications and various devices incorporating the power amplification circuit according to the present invention are also included in the present invention.

  For example, the power amplifying circuit 1 according to the embodiment and the power amplifying circuits 1A to 1C according to the modifications are not only applied to the ET system as described above, but also an average of high-frequency signals calculated every predetermined period. The present invention can be applied to an APT (Average Power Tracking) method for tracking power amplitude.

  Further, in the power amplifier circuit according to the above-described embodiment and its modification, another high-frequency circuit element and wiring may be inserted between the circuit elements disclosed in the drawings and the path connecting the signal paths. .

  The present invention can be widely used in communication equipment as a power amplifier circuit that amplifies a high-frequency signal.

1, 1A, 1B, 1C, 1D, 1E Power amplification circuit 2 Power supply control circuit 3 Envelope detection circuit 4 RF signal processing circuit (RFIC)
5 Baseband signal processing circuit (BBIC)
DESCRIPTION OF SYMBOLS 10, 20 Amplification transistor 11, 21 Variable voltage power supply 12, 22 Bias circuit 13, 23, 23A, 23B Current limiting circuit 14, 24 Constant current source 100 High frequency input terminal 120, 220 Constant current amplification transistor 121, 122, 221, 222 Transistors 123, 152, 153, 223, 233, 234, 236, 252 Capacitors 124, 131, 132, 151, 224, 231, 232, 232A, 232B, 235, 251 Resistance element 130, 230 Current limiting transistor 200 High frequency output terminal 254 Impedance matching circuit

Claims (8)

A power amplification circuit for amplifying power of a high frequency signal,
A first terminal having a first terminal, a second terminal, and a first control terminal, amplifies the high frequency signal input from the first control terminal, and outputs the power amplified high frequency signal from the first terminal An amplification transistor;
A variable voltage power supply for supplying a variable voltage to the first terminal;
A bias circuit that outputs a DC bias current;
A current limiting circuit for limiting the DC bias current,
The bias circuit includes:
A constant current amplification transistor having a third terminal, a fourth terminal, and a second control terminal, and outputting the DC bias current from the fourth terminal toward the first control terminal;
The current limiting circuit is:
A current limiting transistor having a fifth terminal, a sixth terminal, and a third control terminal, wherein the sixth terminal is connected to the fourth terminal;
A first resistance element having one end connected to the fifth terminal and the other end connected to the variable voltage power source;
A second resistance element having one end connected to the third control terminal and the other end connected to the second control terminal;
When the variable voltage becomes smaller than a reference voltage, the current limiting circuit increases the potential difference between the reference voltage and the variable voltage from the second control terminal via the third control terminal. Increase the DC limiting current flowing to the 5 terminals,
Power amplifier circuit. The first resistance element includes a first divided resistor and a second divided resistor connected in series,
The current limiting circuit further includes:
A first capacitive element connected in parallel to the first divided resistor;
A second capacitive element connected between the third control terminal and the fifth terminal,
The power amplifier circuit according to claim 1. The first resistance element includes a first divided resistor and a second divided resistor connected in series,
The current limiting circuit further includes:
A first capacitive element connected between a connection point of the first divided resistor and the second divided resistor and the sixth terminal;
A second capacitive element connected between the third control terminal and the fifth terminal,
The power amplifier circuit according to claim 1. The power amplifier circuit includes a plurality of cascaded amplification transistors including the first amplification transistor.
The power amplifier circuit according to claim 1. Among the plurality of amplification transistors, the amplification transistor arranged at the last stage closest to the output terminal of the power amplification circuit is the first amplification transistor,
In the last stage, the variable voltage power supply, the bias circuit, and the current limiting circuit are arranged.
The power amplifier circuit according to claim 4. Among the plurality of amplification transistors, an amplification transistor disposed in at least one stage before the last stage closest to the output terminal of the power amplification circuit is the first amplification transistor,
The variable voltage power source, the bias circuit, and the current limiting circuit are arranged in at least one stage of the previous stage,
The power amplifier circuit according to claim 4 or 5. further,
A power control circuit that controls the variable voltage according to a high-frequency power amplitude of a high-frequency input signal input to the power amplifier circuit;
The power amplifier circuit according to claim 1. The power supply control circuit controls the variable voltage so that the variable voltage is a linear function of the high-frequency power amplitude.
The power amplifier circuit according to claim 7.

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