JP2019191796A - High-level synthesis method, high-level synthesis program, and high-level synthesis apparatus - Google Patents

Abstract

A high-level synthesis apparatus and a high-level synthesis method capable of reducing the number of clocks consumed by a logic circuit and accelerating the operation by arranging the timings on the logic circuit clock of the memory read that occur during array reading at the same timing. , And a high-level synthesis program. SOLUTION: When an operation description including a plurality of read descriptions for different memories is input, the operation description is changed so that the read descriptions for different memories are read at the same timing on the logic circuit clock before the conditional branch. By doing so, the number of clocks consumed by the logic circuit can be reduced and the speed can be increased. [Selection diagram] Fig. 10

Description

  The present invention relates to a high-level synthesis method, a high-level synthesis program, and a high-level synthesis apparatus.

  High-level synthesis is a technology that automatically converts an operation description in a high-level language such as C language into an RTL (Register Transfer Level) description. With this technology, the designer can greatly reduce the man-hours for designing the logic circuit. However, in order to convert to high-performance RTL descriptions, memory access and computation optimization are required.

  Patent Document 1 states that “the analysis unit analyzes the reuse relationship between array accesses based on the conditions of the subscript and the conditional statement from the behavior description stored in the storage unit, and the data reuse distance between the array accesses. Calculating a difference in the reuse distance between array accesses and a condition in which the reuse of the array access occurs, wherein the first processing unit describes a circular buffer based on the difference in reuse distance and a specified value, or The description of the shift register is added, and the second processing unit replaces the array access with a temporary variable access that represents the input / output end of the shift register or the circular buffer, and adds a conditional statement to optimize the operation description. Is generated. "

JP, 2014-225200, A

In the above-mentioned patent document 1, it is disclosed that a description of a circular buffer or a shift register is added at a location where reuse occurs for the purpose of optimizing reuse of array reading.
However, the invention of Patent Document 1 is a technique that can be applied when an array read occurs again in the logic circuit, and considers optimization of timing on the clock when the array read occurs multiple times in the logic circuit. It has not been.

  For example, even if array reading is performed with a logic circuit clock before a conditional branch on the logic circuit, array reading occurs after the conditional branch is satisfied or after the conditional branch is not satisfied In this case, the array is read with a logical clock having a different timing from the logical clock for reading the array before the conditional branch. For this reason, the array reading is performed at different timings, and the clock of the logic circuit is wasted, resulting in a problem that the processing time of the logic circuit is prolonged.

  Accordingly, an object of the present invention is to reduce the number of clocks consumed by the logic circuit and increase the speed by combining the timings on the logic circuit clocks for memory reading generated at the time of array reading into the same timing.

  In order to solve the above-described problem, one of the representative high-level synthesis methods of the present invention is that, when an operation description including a plurality of read descriptions to different memories is input, the read descriptions to the memory are changed before conditional branching. This is a high-level synthesis method for outputting a behavioral description that has been changed so as to be read at the same timing on the logic circuit clock.

According to the present invention, the number of clocks of the logic circuit after high-level synthesis is reduced, and the processing time of the logic circuit is increased.
Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

It is a figure which shows an example of a structure of the high level synthesis | combination apparatus which concerns on the Example of this invention. It is a figure which shows the whole high level synthesis | combination based on the Example of this invention. It is a block diagram which shows an example of the design apparatus of the behavioral description based on the Example of this invention. It is a figure which shows an example of the operation description in a prior art. It is a figure which shows an example of the operation | movement description after the change changed by the method, program, and apparatus of the high-level synthesis which concerns on the Example of this invention. FIG. 5 is a diagram explicitly showing an example of a memory read location in the behavioral description of FIG. 4. FIG. 7 is a diagram showing an example of the timing of each instruction in the logic circuit generated by the behavioral description of FIG. 6. FIG. 6 is a diagram illustrating an example of behavioral description in which the high-level synthesis method according to the embodiment of the present invention is applied to the behavioral description of FIG. 5. FIG. 9 is a diagram illustrating an example of the timing of each instruction in the logic circuit generated by the behavioral description of FIG. 8 to which the high-level synthesis method according to the embodiment of the invention is applied. It is a flowchart which shows the method of the high level synthesis | combination which concerns on Example 1 of this invention. It is a figure which shows an example of the process description pattern in which the memory reading process in the action description which concerns on the Example of this invention is inherent. It is a flowchart which shows the method of the high level synthesis | combination which concerns on Example 2 of this invention.

  Hereinafter, a conventional example and an embodiment of the present invention will be described with reference to the drawings. In addition, this invention is not limited by this embodiment. Moreover, in description of drawing, the same code | symbol is attached | subjected and shown to the same part.

  First, an example of the configuration of a high-level synthesis apparatus according to an embodiment of the present invention will be described with reference to FIG.

  FIG. 1 is a diagram illustrating a hardware configuration of a computer 110 that operates as a high-level synthesis device (hereinafter, also referred to as “semiconductor device”) according to an embodiment of the present invention. The computer 110 includes an HDD (Hard Disk Drive) 112, a CPU (Central Processing Unit) 114, a RAM (Random Access Memory) 115, and a ROM (Read Only Memory) 116. Each of these devices 112 to 116 may be connected by a bus 111.

  The HDD 112 is a device that stores a program 113 having a processing function corresponding to the preprocessing unit 14 and the high-level synthesis 21 in FIG. 1 illustrates the HDD 112 as a storage device, the present invention is not limited to this, and may be realized by a semiconductor memory element such as a flash memory or a storage device such as an optical disk. The computer 110 reads out the program 113 stored in the HDD 112 to the CPU 114, develops it in the RAM 115, and executes analysis to execute each process of the high-level synthesis method described in the present invention.

  Note that the program 113 is not necessarily recorded in the HDD 112. The program 113 may be stored in a storage medium device that can be read by the computer 110, which is an alternative to the HDD 112. Specific examples of the storage medium device that can be read by the computer 110 include a magnetic disk device such as a hard disk, an optical disk device such as a DVD and a CD, and a flash memory device such as an SSD and a USB memory. The storage device and the computer 110 do not need to be directly connected, and the computer 110 may read the program 113 by being connected to a network (that is, indirectly connected) by a LAN cable, wireless, or the like. By using such a hardware configuration, an arbitrary computer 110 can be operated as a high-level synthesis apparatus, and the high-level synthesis method according to the embodiment of the present invention can be realized.

  Next, with reference to FIG. 2, an overall outline of the high-level synthesis method according to Example 1 of the present invention will be described.

  FIG. 2 is a diagram showing an overall outline of high-level synthesis according to Example 1 of the present invention. Specifically, FIG. 2 is an example showing the processing for the behavioral description in time series in the high-level synthesis method according to the embodiment of the present invention. As shown in FIG. 2, the preprocessing unit 14 optimizes the behavior description before performing the high-level synthesis 21 on the behavior description 11 and outputs a memory read optimization behavior description 18. Next, the high-level synthesis 21 receives the memory read optimization operation description 18 and outputs a logic circuit description 22 in which the memory read is optimized. The logic circuit description 22 may be used for logic circuit design of a semiconductor device such as an FPGA (for example, a high-level synthesis device shown in FIG. 1). Then, by using the optimized (that is, changed) behavior description, the clock of the logic circuit can be managed efficiently.

  Next, an example of a behavioral description design apparatus according to the first embodiment of the present invention will be described with reference to FIG.

  FIG. 3 shows details of the design apparatus showing the internal structure of the pre-processing unit 14 shown in FIG. The preprocessing unit 14 shown in FIG. 3 outputs the memory read optimization operation description 18 by passing the input operation description 11 through the conditional branch sentence extraction unit 15, the operation analysis unit 16, and the description change unit 17. It is a functional part.

As shown in FIG. 3, the behavioral description 11 is composed of a combination of an operation processing instruction 12 and a memory read processing instruction 13. The conditional branch sentence extraction unit 15 is a functional unit that performs a process of extracting a conditional branch sentence from the arithmetic processing instruction 12 and the memory read processing instruction 13 included in the behavior description 11. The arithmetic analysis unit 16 is a functional unit that extracts the memory to be read after determining whether or not a plurality of read descriptions to different memories exist in the extracted conditional branch sentence. The description changing unit 17 is a functional unit that, when implemented as a logic circuit for the memory, changes to a description that generates a memory reading circuit before conditional branching, and outputs a memory reading optimization operation description 18. is there. These functional units may be modules in the above-described program 113, or may be realized as independent hardware in the computer 110.
Next, specific examples of the high-level synthesis method according to the present invention will be described with reference to FIGS.

FIG. 4 is a diagram showing an example of behavioral description in conventional high-level synthesis. The operation description is a description of an operation in a processing instruction, like an ordinary software program. As described above, the behavioral description may include a conditional branch sentence. A conditional branch statement is a control structure that exists in the behavior description and defines a condition such as “If X, Y, Z otherwise”. For example, the conditional branch statement may include an if statement, then clause, else clause, and the like.
As an example, the behavioral description shown in FIG. 4 includes a conditional branching statement “if (bramA [1]> 100) {sum + = bramB [1];})”. The behavioral description shown in FIG. 4 is an example of a behavioral description written in C language. However, the behavioral description in the present invention is not limited to C language, and may be written in another computer language. Good.

FIG. 5 is a diagram illustrating an example of the behavioral description after being changed by the high-level synthesis method, program, and apparatus according to the first embodiment of the present invention.
By changing the behavioral description shown in FIG. 4 into a conditional branch statement as shown in FIG. 5, the read clock timing of the memory can be matched. Specifically, as one of the methods to change the behavioral description, for the conditional branch statement array and argument, assign the same pointer to the description that acquires the pointer before conditional branching There is a method in which a description to be inserted is inserted, and a reference description to the subsequent array or argument is changed to be performed by a pointer.

  Here, the pointer substitution process has been described as a method for changing the behavioral description, but the present invention is not limited to this, and other methods may be used as long as they have the effect of unifying the memory read clock timing.

  FIG. 6 is a diagram explicitly showing memory reading application locations in the behavioral description of FIG. The behavioral description shown in FIG. 6 does not apply the high-level synthesis method according to the embodiment of the present invention (that is, the behavioral description in the conventional high-level synthesis). As shown in FIG. 6, the behavioral description is composed of processing items 71, processing items 72, and writing processing 73.

  FIG. 7 is a diagram showing the timing of each process when the behavioral description code in the conventional high-level synthesis shown in FIG. 6 is realized as a logic circuit by high-level synthesis. As shown in FIG. 7, the logic circuit clock is engraved in order from 1 to 5, and the processing arranged at the timing is sequentially executed. For example, the bramA [1] read 81 process is performed with clocks 1 and 2, and the process 100 and comparison 82 is performed with 2 clocks. The conditional branch processing term indicated by the processing term 71 in FIG. 6 is executed at the processing timing indicated by the processing group 83 in FIG. 7 on the logic circuit clock. Also, the conditional branch processing term shown in the processing term 72 in FIG. 6 is executed at the processing timing shown in the processing group 84 in FIG. 7 on the logic circuit clock. 6 is processed as an output indicated by 85 in FIG. 7 on the logic circuit clock.

  As a result, the behavioral description shown in FIG. 6 is executed on the logic circuit while consuming 5 clocks as shown in FIG. The timing on the clocks of the processing groups 83 and 84 is shifted because the high-level synthesis converts the conditional branch code into a logic circuit so that the dependence on the processing outside the conditional branch is strictly eliminated. This is because the processing timing of the code 71 and the conditional branch code 72 is intentionally shifted.

  However, in the case of the example, since the processing group 83 is access to bramA [1] and the processing group 84 is access to bramB [1], there is no dependency between memory accesses. Therefore, the bramB [1] read 87 process can be executed simultaneously with the bramA [1] read 81 process, and the bramB [1] read 87 of the processing group 84 should be able to start from one clock. It is.

  FIG. 8 is a diagram illustrating an example of a behavior description code obtained by applying the high-level synthesis method according to the embodiment of the present invention to the behavior description of FIG. FIG. 9 is a diagram showing an example of the timing of each instruction in the logic circuit generated by the behavioral description of FIG. 8 to which the high-level synthesis method according to the embodiment of the present invention is applied. The code of the behavioral description shown in FIG. 8 is sequentially executed by the logic circuit clock shown in FIG. 9 when high-level synthesis is performed. The code group indicated by 91 in FIG. 8 is a description for bramA [1] and bramB [1] to be reliably read (that is, prefetched) before the conditional branch sentence. As in the processing groups 83 and 84 of FIG. 7, in the high-level synthesis, the memory is read not just at the time of declaration but immediately before the operation using the memory.

  Therefore, in order to prefetch the memory before the conditional branch, it is necessary to insert an operation using the memory before the conditional branch. In the code group 91, the pointers are first acquired for the memories bramA [1] and bramB [1] by the codes int * tmp1 = & bramA [1]; and int * tmp2 = & bramB [1] ;. In software, a pointer indicates an address of a memory, but in a logic circuit converted by high-level synthesis, the pointer functions as a register. Here, a process of assigning the same value to the value indicated by the pointer, * tmp1 = * tmp1, * tmp2 = * tmp2 is added. The process of assigning the same value to the memory does not make sense as a process on software, but in high-level synthesis, the assignment is handled as an operation to the memory. By arranging this substitution process, a memory reading process can also be arranged before the substitution process.

By this method, the memory read clock timing in the subsequent conditional branch can be matched by intentionally prefetching the memory. With the code 91, the bramA [1] reading process and the bramB [1] reading process are processed simultaneously with the clocks 1 and 2 on the logic circuit clock as shown in the process 101 of FIG.
The code indicated by 92 in FIG. 8 includes 100 and the comparison 82 in FIG. 7 except for the bramA [1] reading process. As shown in FIG. 9, the bramA [1] reading has already been completed. As shown in nine processing groups (102), processing can be performed with two clocks. Similarly, the process 93 in FIG. 8 can be processed with the clocks 2 and 3 as shown in the process 103 in FIG. As a result, the overall processing time can be shortened by reducing the number of clocks, resulting in higher speed.

  Next, the above-described high-level synthesis mode will be described with reference to FIG. 10 using a flowchart.

  FIG. 10 is a flowchart illustrating a high-level synthesis method according to an embodiment of the present invention. First, in step 31, the behavioral description 11 in a state where the high-level synthesis method according to the embodiment of the present invention is not applied is input to the preprocessing unit 14. This behavioral description is input by, for example, sequentially transferring information that the user (for example, a logic circuit designer or the like) partially inputs to the preprocessing unit 14 to an input device such as a keyboard. Alternatively, it may be inputted by continuously transferring it from the storage device storing the completed operation description to the preprocessing unit 14.

  Next, in step 32, the conditional branch sentence extraction unit 15 extracts a conditional branch sentence within the behavior description. Here, the expression extracting includes taking out, identifying, listing, and selecting. Specifically, the conditional branch sentence extraction unit 15 may extract the processing terms 71 and the processing terms 72 shown in FIG. 9 As described above, the conditional branch statement and its interior are composed of the operation processing instruction 12 and the memory read processing instruction 13.

  Next, in step 33, it is determined using the arithmetic analysis unit 16 whether or not there are a plurality of read processing instructions 13 for different memories in the above-described processing terms (for example, the processing terms 71 and 72 shown in FIG. 6). To do. Here, the expression “determining” includes detection, determination, determination, and determination. Also, here, the expression “different memory” means that different memory addresses in the same memory device are indicated (reading access to the same memory address is already processed at the same time. In the case where there are a plurality of read descriptions, the effect of the present invention is further exerted).

  When it is determined that there are a plurality of read processing instructions for different memories in the processing item, the process proceeds to step 34, and when it is determined that there are not a plurality of read processing instructions for different memories. Then, the process proceeds to step 38. In the behavioral description, the memory read processing instruction 13 is an instruction for reading an array element or an argument. For this reason, when the instruction is described in the operation description, a process of reading each array element and argument is executed at the timing when the instruction is called.

  Next, a specific example of this determination process will be described with reference to FIG. FIG. 11 is a diagram illustrating an example of a process description pattern including a memory read process in the behavioral description according to the embodiment of the present invention. As shown in FIG. 11, in the description of bramA [1]> 100, there are two processes of reading an array element called bramA [1] and a comparison process of bramA [1] and 100, and reading bramA [1]. After processing, a comparison process between bramA [1] and 100 is executed. For example, referring to FIG. 6, the processing item 71 is a description of bramA [1]> 100 of the determination sentence, reads the array element bramA [1], and the processing item 72 is + = bramB [1]. The array element bramB [1] is being read. Since these processing terms hold the memory read processing instruction 13 for the conditional branch statement, it is determined that there are a plurality of read processing instructions for different memories. Therefore, the process proceeds to step 34.

  Next, in step 34, the arithmetic analysis unit 16 extracts and acquires the array elements and arguments read by the memory read processing instruction 13. Specifically, with reference to FIG. 6, the operation analysis unit 16 acquires bramA [1] and bramB [1] as an array to access.

  Next, in step 35, the arithmetic analysis unit 16 determines whether there is a resource that can be used in the semiconductor device on which the behavioral description 11 is mounted. Here, the semiconductor device on which the behavioral description 11 is mounted is a semiconductor device that can generate a logic circuit such as an FPGA by performing high-level synthesis processing on the behavioral description. For example, as an example, this semiconductor device may be the computer 110 that functions as the high-level synthesis device shown in FIG. In this process, in step 36 described later, it is determined whether or not register resources (for example, CPU resources, memory resources, etc.) of the semiconductor device can be secured.

Specifically, the arithmetic analysis unit 16 may determine the presence / absence of a necessary resource by comparing with the resource amount required for the behavioral description. Alternatively, a predetermined resource usage rate is set in advance, and the processing is continued only when the resource usage rate of the semiconductor device is equal to or lower than the predetermined resource usage rate (that is, processing for changing the operation description as described later is performed). Is possible. If it is determined that the resource can be secured, the process proceeds to step 36, and if the resource cannot be secured, the process proceeds to step 38.
In this way, by changing the operation description only when the resources of the semiconductor device can be secured, it is possible to avoid overloading the semiconductor device when the resource usage rate of the semiconductor device is high. Can be used.

Next, in step 36, the description changing unit 17 changes the description so that the array elements and arguments inside the behavior description are read at the same timing before conditional branching. Here, the expression “change” includes correcting, converting, correcting, and adjusting.
Specifically, as an example of the processing, as shown in FIG. 5, for the array element and the argument, a description for acquiring the pointer before the conditional branch and a description for assigning the same pointer to the pointer Is inserted, and the reference description to the subsequent array elements and arguments is changed to be performed by the pointer.

  Note that when this method is used, resources required from the registers of the semiconductor device increase, but the array elements and arguments of the operation description can be read at the same timing on the logic circuit clock. As a result, useless clock consumption on the logic circuit clock can be suppressed, and an effect of shortening the processing time can be obtained.

  Next, in step 38, the preprocessing unit 14 outputs the operation description in which the memory read timing is changed (ie, optimized) by the description changing unit 17 as described above in step 36. In this embodiment, the behavioral description that has not been changed by the description changing unit 17 in step 36 (for example, the behavioral description that has been determined that there is no necessary resource in step 35) is the normal behavioral description that has not been changed. Is processed as

  However, in Example 2 to be described later, it is determined that there is no resource available for the semiconductor device (that is, a semiconductor device that can generate a logic circuit such as an FPGA such as the high-level synthesis device shown in FIG. 1). In this case, the behavioral description is changed, and the changed behavioral description is stored in the storage device (for example, the HDD 112 in FIG. 1). Can be used for high-level synthesis.

  As described above, the preprocessing unit 14 forcibly performs the read process in the logic circuit after the high-level synthesis by inserting the array element after the conditional branch and the description for arranging the input read before the conditional branch. By executing at the same timing, the subsequent arithmetic processing can be executed without useless logic circuit clocks.

  Next, a high-level synthesis method according to Example 2 of the present invention will be described with reference to FIG. In addition, about Example 2, about the point which is not described below, since it is common with Example 1, description is abbreviate | omitted.

  FIG. 12 is a flowchart showing a high-level synthesis method according to Embodiment 2 of the present invention. In the first embodiment described above, the operation description determined to have no memory read description and the operation description determined to have no necessary resources in the semiconductor device were processed as normal operation descriptions in an unmodified state. In this embodiment, even when it is determined that there is no available resource in the semiconductor device (that is, a semiconductor device capable of generating a logic circuit such as an FPGA such as the high-level synthesis device shown in FIG. 1). By changing the operation description and storing the changed operation description in the storage device (for example, the HDD 112 in FIG. 1), when the resource of the semiconductor device becomes available at a later timing, the changed operation description is displayed. It can be used for high level synthesis. Thereby, the resource usage load of the semiconductor device can be reduced, and the behavioral description that has been changed once can be reused.

  In FIG. 12, step 31, step 32, step 33, step 34, step 35, step 36, and step 38 are substantially the same as the steps in FIG. Omitted.

  First, in step 37a, it is determined in step 35 that there are no resources available for the semiconductor device (that is, a semiconductor device capable of generating a logic circuit such as an FPGA such as the high-level synthesis device shown in FIG. 1). The behavioral description is changed by the description changing unit 17. As described above, in this change process, the array element and the argument included in the behavioral description are changed so as to be read at the same timing before the conditional branch.

  Specifically, as an example of the processing, as shown in FIG. 5, for an array element and an argument, a description for acquiring the pointer before conditional branching and a description for assigning the same pointer to the pointer And a method of changing the reference description to the subsequent array elements and arguments to be performed by the pointer. Next, the changed operation description may be stored in a storage device (for example, the HDD 112 or the RAM 115 in FIG. 1). As described above, even when there is no available resource in the semiconductor device at the time of the change, the changed operation description can be prepared in advance for the subsequent processing.

  Next, in step 37b, it is determined whether the same behavioral description as the behavioral description changed in step 37a is generated and there is a resource available in the semiconductor device. Specifically, the arithmetic analysis unit 16 confirms whether the newly entered behavior description is the same as the state before the behavior description changed in step 37a (all contents such as conditional branch statements, array elements, arguments, etc.). Whether the items match).

  If it is determined that the newly entered behavior description is the same as the state before the behavior description changed in step 37a, the semiconductor device on which the behavior description is mounted (for example, as shown in FIG. 1). It is determined whether there are resources (CPU resources, memory resources, etc.) that can be used by a computer that functions as a high-level synthesis device. If it is determined that the newly entered behavioral description is the same as the state before the behavioral description changed in step 37a and the resources of the semiconductor device can be secured, the process proceeds to step 37c. Move on.

  On the other hand, if it is determined that the newly entered behavior description and the behavior description changed in step 37a are not the same, and / or that it is not possible to secure semiconductor resources, this processing is performed. Ends.

  Next, in step 37c, the modified behavioral description saved in step 37a is read from the storage device and output instead of the newly entered (unmodified) behavioral description.

  As described above, even when the semiconductor device does not have the necessary resources, by changing the memory reading of the operation description and storing it in the storage device, the same operation description is generated in the subsequent processing, and the semiconductor device When device resources become available, the modified behavioral descriptions can be reused multiple times by reading the modified behavioral descriptions that have been saved, and high-level synthesis processing can be performed efficiently. be able to.

11 Behavior description 14 Preprocessing unit 15 Conditional branch sentence extraction unit 16 Operation analysis unit 17 Description change unit 21 High-level synthesis 110 Computer 112 HDD
113 programs

Claims (15)

A high-level synthesis method,
When an operation description including multiple read descriptions to different memories is input,
Outputting a description of the operation in which the read description to the memory is changed so as to be read at the same timing on the logic circuit clock before the conditional branch;
High level synthesis method. The high level synthesis method of claim 1,
Extracting the conditional branch sentence from the input behavior description by a conditional branch sentence extraction unit;
A step of determining the presence or absence of a plurality of read descriptions in different memories in the extracted conditional branch sentence by an arithmetic analysis unit;
When it is determined that there are a plurality of read descriptions to the different memories, the operation is performed by the changing unit so that the plurality of read descriptions to the different memories are read at the same timing on the logic circuit clock before the conditional branch. Changing the description and generating the modified behavior description;
High-level synthesis method comprising Determining whether there is a resource that can be used in a semiconductor device that implements the behavior description;
When it is determined that the semiconductor device has available resources, the behavioral description is changed so that a plurality of read descriptions to the different memories are read at the same timing before conditional branching, and the modified behavioral description is changed to Generating step;
Performing high-level synthesis processing on the modified behavioral description;
The high level synthesis method according to claim 2, comprising: Determining whether there is an available resource in the semiconductor device in which the behavior description is mounted;
If it is determined that there are no resources available in the semiconductor device, the behavioral description is changed so that a plurality of read descriptions to the different memories are read at the same timing before conditional branching, and the modified behavioral description is changed to Generating step;
Storing the modified behavioral description in a storage device;
When the same operation description as the operation description is input and it is determined that there is a resource that can be used in the semiconductor device, the changed operation description stored in the storage device is read, and the changed operation Performing high-level synthesis processing on the description;
The high level synthesis method according to claim 2, comprising: In the step of changing the behavior description so that a plurality of read descriptions to the different memories are read at the same timing before the conditional branch, and generating the modified behavior description,
Array pointers and variable pointers that perform memory access are acquired, and the modified behavioral description in which the same pointer value is assigned to the pointer before the conditional branch description is output.
The high level synthesis method according to claim 2. A high-level synthesis program,
When an operation description including a conditional branch statement is input,
Outputting a modified behavioral description that is modified so that a plurality of read descriptions to different memories included in the conditional branch statement are read at the same timing on the logic circuit clock before the conditional branch;
High-level synthesis program. In the high-level synthesis program according to claim 6,
Extracting the conditional branch sentence from the input behavior description by a conditional branch sentence extraction unit;
A step of determining the presence or absence of a plurality of read descriptions in different memories in the extracted conditional branch sentence by an arithmetic analysis unit;
When it is determined that there are a plurality of read descriptions to the different memories, the operation is performed by the changing unit so that the plurality of read descriptions to the different memories are read at the same timing on the logic circuit clock before the conditional branch. Changing the description and generating the modified behavior description;
High-level synthesis program that executes Determining whether there is a resource that can be used in a semiconductor device that implements the behavior description;
When it is determined that the semiconductor device has available resources, the behavioral description is changed so that a plurality of read descriptions to the different memories are read at the same timing before conditional branching, and the modified behavioral description is changed to Generating step;
Performing high-level synthesis processing on the modified behavioral description;
The high-level synthesis program according to claim 7, wherein: Determining whether there is a resource that can be used in a semiconductor device that implements the behavior description;
If it is determined that there are no resources available in the semiconductor device, the behavioral description is changed so that a plurality of read descriptions to the different memories are read at the same timing before conditional branching, and the modified behavioral description is changed to Generating step;
Storing the modified behavioral description in a storage device;
When the same operation description as the operation description is input and it is determined that there is a resource that can be used in the semiconductor device, the changed operation description stored in the storage device is read, and the changed operation Performing high-level synthesis processing on the description;
The high-level synthesis program according to claim 7, wherein: In the step of changing the behavior description so that a plurality of read descriptions to the different memories are read at the same timing before the conditional branch, and generating the modified behavior description,
Array pointers and variable pointers that perform memory access are acquired, and the modified behavioral description in which the same pointer value is assigned to the pointer before the conditional branch description is output.
The high-level synthesis program according to claim 7. A high-level synthesis device,
When an operation description including a conditional branch statement is input,
Outputting a modified behavioral description that is modified so that a plurality of read descriptions to different memories included in the conditional branch statement are read at the same timing on the logic circuit clock before the conditional branch;
High-level synthesizer. The high-level synthesizer is
A conditional branch sentence extraction unit that extracts the conditional branch sentence from the input behavior description;
An operation analysis unit that determines whether or not a plurality of read descriptions exist in different memories in the extracted conditional branch statement;
If it is determined that there are a plurality of read descriptions to the different memory, the operation description is changed so that the plurality of read descriptions to the different memory are read at the same timing on the logic circuit clock before the conditional branch. , A change part that generates a behavior description after change, and
The high-level synthesis apparatus according to claim 11 having The high-level synthesizer is
Determining whether there is a resource that can be used in the semiconductor device that implements the behavior description,
When it is determined that the semiconductor device has available resources, the behavioral description is changed so that a plurality of read descriptions to the different memories are read at the same timing before conditional branching, and the modified behavioral description is changed to Generate and
A high-level synthesis process is performed on the behavior description after the change.
The high level synthesis apparatus according to claim 12. The high-level synthesizer is
Determining whether there is a resource that can be used in the semiconductor device that implements the behavior description,
If it is determined that there are no resources available in the semiconductor device, the behavioral description is changed so that a plurality of read descriptions to the different memories are read at the same timing before conditional branching, and the modified behavioral description is changed to Generate and
Save the modified behavioral description in a storage device,
When the same operation description as the operation description is input and it is determined that there is a resource that can be used in the semiconductor device, the changed operation description stored in the storage device is read, and the changed operation Perform high-level synthesis on the description,
The high level synthesis apparatus according to claim 12. The high-level synthesizer is
In the step of changing the behavior description so that a plurality of read descriptions to the different memories are read at the same timing before the conditional branch, and generating the behavior description after the change, an array and a pointer of the variable to be accessed are obtained. And output the modified behavioral description in which the same pointer value is assigned to the pointer before the conditional branch description.
The high level synthesis apparatus according to claim 12.

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