JP2020048179A - Data latch circuit and semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data latch circuit and a semiconductor storage device capable of miniaturization. A data latch circuit includes a first n-channel transistor and a first p-channel transistor. The gate of the first n-channel transistor and the gate of the first p-channel transistor are common. [Selection diagram] Fig. 4

Description

  Embodiments relate to a data latch circuit and a semiconductor memory device.

  2. Description of the Related Art In recent years, a semiconductor memory device equipped with a NAND flash memory uses a sense amplifier to read data stored in each memory cell. If an attempt is made to maintain the data transfer rate while increasing the integration of the memory cells, the number of data latch circuits connected to the sense amplifier increases, and the overall area increases.

JP 2007-266143 A

  An object of the embodiments is to provide a data latch circuit and a semiconductor memory device that can be reduced in size.

  The data latch circuit according to the embodiment includes a first n-channel transistor and a first p-channel transistor. The gate of the first n-channel transistor and the gate of the first p-channel transistor are common.

  The semiconductor memory device according to the embodiment includes a sense amplifier, the data latch circuit, a plurality of electrode films stacked apart from each other, a semiconductor member penetrating the plurality of electrode films, A charge storage member provided between the semiconductor member, a source line connected to one end of the semiconductor member, and a bit line connected between the other end of the semiconductor member and the sense amplifier. .

FIG. 2 is a cross-sectional view illustrating the semiconductor memory device according to the first embodiment. FIG. 2 is a plan view showing a sense amplifier circuit of the semiconductor memory device according to the first embodiment. FIG. 2 is a plan view illustrating the data latch circuit according to the first embodiment. (A) is a plan view showing one data latch circuit, and (b) is a circuit diagram thereof. FIG. 2 is a cross-sectional view illustrating a memory cell of the semiconductor memory device according to the first embodiment. FIG. 5 is a plan view illustrating a data latch circuit according to a second embodiment. (A) is a plan view showing one data latch circuit, and (b) is a circuit diagram thereof. FIG. 11 is a plan view illustrating a semiconductor region, a gate, and a contact in a data latch circuit according to a third embodiment. FIG. 11 is a plan view illustrating a semiconductor region, a gate, a contact, and a first wiring layer in a data latch circuit according to a third embodiment. FIG. 13 is a plan view illustrating a semiconductor region, a gate, a contact, a first wiring layer, a second wiring layer, and a third wiring layer in the data latch circuit according to the third embodiment. It is a top view showing one data latch circuit concerning a 3rd embodiment, (a) shows a semiconductor region, a gate, and a contact, (b) shows a 1st wiring layer in addition to (a), (c) shows a second wiring layer and a third wiring layer in addition to (b). FIG. 14 is a plan view illustrating four data latch circuits according to the third embodiment. (A) is a plan view showing one data latch circuit according to the third embodiment, and (b) is a circuit diagram thereof. FIG. 14 is a plan view illustrating a semiconductor region, a gate, a contact, and a first wiring layer in four data latch circuits according to the fourth embodiment. FIG. 14 is a plan view illustrating a semiconductor region, a gate, a contact, a first wiring layer, and a second wiring layer in four data latch circuits according to the fourth embodiment. FIG. 14 is a plan view illustrating a semiconductor region, a gate, a contact, a first wiring layer, a second wiring layer, and a third wiring layer in four data latch circuits according to the fourth embodiment. (A) is a plan view showing one data latch circuit according to the fourth embodiment, and (b) is a circuit diagram thereof.

(First embodiment)
Hereinafter, the first embodiment will be described.
FIG. 1 is a sectional view showing the semiconductor memory device according to the present embodiment.
FIG. 2 is a plan view showing the sense amplifier circuit of the semiconductor memory device according to the present embodiment.
FIG. 3 is a plan view showing the data latch circuit according to the present embodiment.
FIG. 4A is a plan view showing one data latch circuit, and FIG. 4B is a circuit diagram thereof.
FIG. 5 is a sectional view showing a memory cell of the semiconductor memory device according to the present embodiment.
Each drawing is a schematic diagram, and constituent elements are omitted or emphasized as appropriate. In addition, the numbers and dimensional ratios of the components do not always match between the drawings.

  As shown in FIG. 1, in the semiconductor memory device 1 according to the present embodiment, a control circuit board 10 and a memory array board 80 are provided. In the control circuit board 10, a silicon substrate 11 and an interlayer insulating film 12 are stacked, and in the memory array substrate 80, a silicon substrate 81 and an interlayer insulating film 82 are stacked. The control circuit board 10 and the memory array substrate 80 are bonded together in such a manner that the interlayer insulating film 12 and the interlayer insulating film 82 face each other.

First, the control circuit board 10 will be described.
As shown in FIG. 2, in the control circuit board 10, a control circuit is formed in an upper layer portion of a silicon substrate 11 and an interlayer insulating film 12 (see FIG. 1). A sense amplifier area 13 is set in the control circuit, and a plurality of sense amplifier circuits 14 are provided in the sense amplifier area 13. In each sense amplifier circuit 14, one sense amplifier 15 and a plurality of, for example, five data latch circuits 16 are arranged in a line. The sense amplifier 15 sequentially detects electric signals transmitted from the memory array substrate 80 as binary data. Each data latch circuit 16 temporarily holds data detected by the sense amplifier 15. In FIGS. 2, 3, and 4A, the interlayer insulating film 12 is omitted for convenience of illustration.

  Hereinafter, the control circuit board 10 employs an XYZ orthogonal coordinate system for convenience of description. The direction in which the plurality of sense amplifier circuits 14 are arranged is referred to as “X direction”, and the direction in which the sense amplifiers 15 and the data latch circuits 16 are arranged in each sense amplifier circuit 14 is referred to as “Y direction”. A direction orthogonal to both of the Y directions is referred to as a “Z direction”. In the Z direction, the direction from the silicon substrate 11 to the interlayer insulating film 12 is also referred to as “up”, and the opposite direction is also referred to as “down”, but this expression is for convenience and is independent of the direction of gravity. It is.

  As shown in FIGS. 2 and 3, in the sense amplifier region 13, a plurality of data latch circuits 16 are arranged in a matrix along the X direction and the Y direction. The plurality of data latch circuits 16 arranged along the Y direction belong to the same sense amplifier circuit 14, and the plurality of data latch circuits 16 arranged along the X direction belong to different sense amplifier circuits 14. The layout of the plurality of data latch circuits 16 arranged along the Y direction is the same. On the other hand, the layouts of the data latch circuits 16 adjacent in the X direction are mirror images of each other.

  As shown in FIG. 4A, on the silicon substrate 11, a plurality of n-wells 21 having an n-type conductivity and a plurality of p-wells 22 having a p-type conductivity are provided. The n-wells 21 and the p-wells 22 are alternately arranged along the X direction. Each n-well 21 and each p-well 22 extend in the Y direction and are arranged over all the data latch circuits 16 arranged along the Y direction. Each data latch circuit 16 is formed over one n-well 21 and one p-well 22 adjacent in the X direction. One data latch circuit 16 shares one n-well 21 with another data latch circuit 16 arranged on one side in the X direction, and another data latch circuit 16 arranged on the other side in the X direction. And the p-well 22 are shared.

Hereinafter, the configuration of each data latch circuit 16 will be described.
As shown in FIGS. 3 and 4A, in each data latch circuit 16, p-type layers 31 to 36 having a p-type conductivity are provided on the n-well 21. The p-type layers 31 to 36 are separated from each other and arranged in a line in this order along the Y direction. The p-type layer 36 and the p-type layer 31 are continuous between the data latch circuits 16 adjacent in the Y direction. Also, between the p-type layer 31 and the p-type layer 32, between the p-type layer 32 and the p-type layer 33, between the p-type layer 34 and the p-type layer 35, and between the p-type layer 35 and the p-type layer A part of the n-well 21 is interposed between each of the layers 36. On the other hand, an STI (Shallow Trench Isolation: element isolation insulating film) 23 is provided between the p-type layer 33 and the p-type layer 34.

  Thereby, of the two data latch circuits 16 adjacent in the Y direction, the p-type layers 34, 35, 36 of one data latch circuit 16 and the p-type layers 31, 32, 33 of the other data latch circuit 16 Together with the n-well 21 interposed between these p-type layers, one island-shaped semiconductor region (active area) is formed. However, p-type layers 31 to 33 or p-type layers 34 to 36 form island-shaped semiconductor regions at both ends of a column including a plurality of data latch circuits 16 constituting each sense amplifier circuit 14, respectively. I have.

  In each data latch circuit 16, n-type layers 41 to 45 having an n-type conductivity are provided on the p-well 22. The n-type layers 41 to 45 are separated from each other and arranged in a line in this order along the Y direction. In the data latch circuits 16 adjacent in the Y direction, the n-type layer 45 and the n-type layer 41 are continuous. Also, between the n-type layer 41 and the n-type layer 42, between the n-type layer 42 and the n-type layer 43, between the n-type layer 43 and the n-type layer 44, and between the n-type layer 44 and the n-type layer 45. And a part of the p-well 22 is interposed between them.

  Thereby, on each p-well 22, a plurality of sets of n-type layers 41 to 45 arranged along the Y direction form one line shape together with the p-well 22 interposed between these n-type layers. Of semiconductor regions (active areas).

  In the sense amplifier region 13, a plurality of island-shaped semiconductor regions respectively formed by p-type layers 34 to 36, p-type layers 31 to 33, and an n-well 21 interposed between these p-type layers, The STI 23 is arranged between the plurality of linear semiconductor regions formed by the layers 41 to 45 and the p-well 22 interposed between these n-type layers.

  In each data latch circuit 16, gates 51 to 56 are provided. Gates 51-56 extend generally in the X direction and traverse the semiconductor region described above. A gate insulating film (not shown) is provided between the gates 51 to 56 and the semiconductor region. Hereinafter, the positional relationship between the gates 51 to 56 and the p-type layers 31 to 36 and the n-type layers 41 to 45 will be described.

  As shown in FIG. 3, gate 51 is arranged so as to cross the region immediately above the portion between n-type layer 31 and p-type layer 32 in n-well 21. In the data latch circuits 16 adjacent in the X direction, the gate 51 is common. That is, one gate 51 extending in the X direction is adjacent to each other in the X direction, and in each of the two data latch circuits 16 whose layouts are mirror images of each other, the p-type layer 31 and the p-type layer 32 in the n-well 21 It is arranged in the area immediately above the portion between the two. Specifically, when two data latch circuits 16 adjacent to each other in the X direction and sharing the n-well 21 among the plurality of data latch circuits 16 are referred to as a “data latch circuit 16a” and a “data latch circuit 16b”, The p-type layers 31a and 32a belonging to the data latch circuit 16a and the p-type layers 31b and 32b belonging to the data latch circuit 16b share one gate 51.

  Gate 52 is arranged so as to cross the region immediately above the portion between n-type layer 41 and n-type layer 42 in p well 22. The gate 52 is common to the data latch circuits 16 adjacent in the X direction. That is, one gate 52 extending in the X direction is adjacent to each other in the X direction, and in each of the two data latch circuits 16 whose layouts are mirror images of each other, the n-type layer 41 and the n-type layer 42 in the p-well 22 are It is arranged in the area immediately above the portion between the two. Specifically, when two data latch circuits 16 adjacent to each other in the X direction and sharing the p-well 22 among the plurality of data latch circuits 16 are referred to as a “data latch circuit 16a” and a “data latch circuit 16c”, The n-type layer 41a and the n-type layer 42a belonging to the data latch circuit 16a and the n-type layer 41c and the n-type layer 42c belonging to the data latch circuit 16c share one gate 52.

  The combination of the two data latch circuits 16 sharing the gate 51 and the two data latch circuits 16 sharing the gate 52 are different. As described above, one data latch circuit 16a shares the gate 51 with the data latch circuit 16b on one side in the X direction, and shares the gate 52 with the data latch circuit 16c on the other side in the X direction. In the entire sense amplifier region 13, the gates 51 and 52 are arranged alternately and separated from each other along the X direction.

  The gate 53 has a region immediately above a portion between the p-type layer 32 and the p-type layer 33 in the n-well 21 and a region immediately above a portion between the n-type layer 42 and the n-type layer 43 in the p-well 22. It is arranged to cross. When viewed from the Z direction, the shape of the gate 53 is, for example, a crank shape.

  The gate 54 has a region immediately above a portion between the p-type layer 34 and the p-type layer 35 in the n-well 21 and a region immediately above a portion between the n-type layer 43 and the n-type layer 44 in the p-well 22. It is arranged to cross. When viewed from the Z direction, the shape of the gate 54 is, for example, a crank shape.

  Gate 55 is arranged so as to cross the area immediately above the portion between n-type layer 35 and p-type layer 36 in n-well 21. In the data latch circuits 16 adjacent in the X direction, the gate 55 is common. That is, in the above example, the gate 55 is common between the data latch circuit 16a and the data latch circuit 16b.

  Gate 56 is arranged so as to cross the region immediately above the portion between p-type layer 44 and n-type layer 45 in p-well 22. The gate 56 is common to the data latch circuits 16 adjacent in the X direction. That is, in the above example, the gate 56 is common between the data latch circuit 16a and the data latch circuit 16c.

  Similar to the relationship between the gates 51 and 52 described above, the two data latch circuits 16 sharing the gate 55 and the two data latch circuits 16 sharing the gate 56 are different in combination. As described above, one data latch circuit 16a shares the gate 55 with the data latch circuit 16b on one side in the X direction, and shares the gate 56 with the data latch circuit 16c on the other side in the X direction. In the entire sense amplifier region 13, the gates 55 and the gates 56 are arranged alternately and separated from each other along the X direction.

Thus, in each data latch circuit 16, four p-channel transistors p1 to p4 and four n-channel transistors n1 to n4 are formed.
More specifically, a p-channel transistor p3 is formed by the p-type layer 31, the p-type layer 32, the portion between the p-type layer 31 and the p-type layer 32 in the n-well 21, and the gate 51. . The p-type layer 32, the p-type layer 33, the portion between the p-type layer 32 and the p-type layer 33 in the n-well 21, and the gate 53 form a p-channel transistor p4. The p-type layer 34, the p-type layer 35, the portion between the p-type layer 34 and the p-type layer 35 in the n-well 21, and the gate 54 form a p-channel transistor p2. The p-type layer 35, the p-type layer 36, the portion between the p-type layer 35 and the p-type layer 36 in the n-well 21, and the gate 55 form a p-channel transistor p1.

  An n-channel transistor n4 is formed by the n-type layer 41, the n-type layer 42, the portion between the n-type layer 41 and the n-type layer 42 in the p-well 22, and the gate 52. An n-channel transistor n3 is formed by the n-type layer 42, the n-type layer 43, the portion between the n-type layer 42 and the n-type layer 43 in the p-well 22, and the gate 53. The n-type layer 43, the n-type layer 44, the portion between the n-type layer 43 and the n-type layer 44 in the p-well 22, and the gate 54 form an n-channel transistor n2. An n-channel transistor n1 is formed by the n-type layer 44, the n-type layer 45, the portion between the n-type layer 44 and the n-type layer 45 in the p-well 22, and the gate 56.

  Thus, the p-channel transistor p4 and the n-channel transistor n3 share one gate 53. Further, the p-channel transistor p2 and the n-channel transistor n2 share one gate 54.

Each data latch circuit 16 is provided with contacts 61 to 73.
The lower end of the contact 61 is connected to the p-type layer 31 and the p-type layer 36. The lower end of the contact 62 is connected to the n-type layers 41 and 45. The contacts 61 and 62 are shared by two data latch circuits 16 adjacent in the Y direction.

  The lower end of the contact 63 is connected to the gate 51. The contact 63, like the gate 51, is shared by two data latch circuits 16 adjacent in the X direction. The contact 64 is connected to the lower end of the gate 52. Like the gate 52, the contact 64 is shared by two data latch circuits 16 adjacent in the X direction.

  The lower end of the contact 65 is connected to the n-type layer 42. The lower end of the contact 66 is connected to the gate 53. The lower end of the contact 67 is connected to the p-type layer 33. The lower end of the contact 68 is connected to the n-type layer 43. The lower end of the contact 69 is connected to the p-type layer 34. The lower end of the contact 70 is connected to the gate 54. The lower end of the contact 71 is connected to the n-type layer 44.

  The lower end of the contact 72 is connected to the gate 55. Like the gate 55, the contact 72 is shared by two data latch circuits 16 adjacent in the X direction. The lower end of the contact 73 is connected to the gate 56. Like the gate 56, the contact 73 is shared by two data latch circuits 16 adjacent in the X direction.

Each data latch circuit 16 is provided with wirings 76 and 77.
As shown in FIG. 4A, the wiring 76 is connected to the upper end of the contact 70, the upper end of the contact 65 disposed above the contact 70, and the upper end of the contact 67. The wiring 77 is connected to the upper end of the contact 66, the upper end of the contact 71 and the upper end of the contact 69 disposed below the contact 66 in the drawing.
Each of the above contacts may include a plurality of contacts arranged in the Z direction, and the plurality of contacts may be connected via an intermediate wiring. For example, the contacts 61 to 64, 72, and 73 each include two or more stages of contacts arranged in the Z direction, and may be connected via an intermediate wiring provided in the same layer as the wirings 76 and 77. Good.

  As a result of connecting the transistors as described above, the circuit shown in FIG. 4B is configured in each data latch circuit 16.

  That is, one of the source and the drain of the p-channel transistor p1 and one of the source and the drain of the p-channel transistor p2 are connected to each other because they are the common p-type layer 35. The other of the source and the drain of the p-channel transistor p2 is connected to one of the source and the drain of the n-channel transistor n1 and one of the source and the drain of the n-channel transistor n2 via the contact 69, the wiring 77, and the contact 71. And a common gate 53 of the p-channel transistor p4 and the n-channel transistor n3 via the contact 69, the wiring 77, and the contact 66.

  On the other hand, one of the source and the drain of the p-channel transistor p3 and one of the source and the drain of the p-channel transistor p4 are connected to each other because they are the common p-type layer 32. The other of the source and the drain of the p-channel transistor p4 is connected to one of the source and the drain of the n-channel transistor n4 and one of the source and the drain of the n-channel transistor n3 via the contact 67, the wiring 76, and the contact 65. , And to the common gate 54 of the p-channel transistor p2 and the n-channel transistor n2 via a contact 67, a wiring 76, and a contact 70.

  The other of the source and drain (p-type layer 36) of the p-channel transistor p1 and the other of the source and drain (p-layer 31) of the p-channel transistor p3 are connected to the first reference via a contact 61. A power supply potential VDD which is a potential is applied. The other of the source and the drain of the n-channel transistor n2 and the other of the source and the drain of the n-channel transistor n3 are the common n-type layer 43, and are connected via the contact 68 to the ground potential which is the second reference potential. GND is applied. Note that the second reference potential is not limited to the ground potential, but is lower than the first reference potential.

  The control signal Vc is input to the gate 56 of the n-channel transistor n1 and the gate 52 of the n-channel transistor n4 via the contacts 73 and 64, respectively. The selection signals Vs1 and Vs2 are input to the gate 55 of the p-channel transistor p1 and the gate 51 of the p-channel transistor p3 via the contacts 72 and 63, respectively. The other of the source and the drain of the n-channel transistor n1 (the n-type layer 45) and the other of the source and the drain of the n-channel transistor n4 (the n-type layer 41) can be connected to the sense amplifier 15 via the contact 62. And the data signal SA output from the sense amplifier 15 is applied. In the data latch circuit 16, the n-channel transistors n1 and n4 function as transfer gates, the n-channel transistors n2 and n3 function as drivers, and the p-channel transistors p1 to p4 function as loads.

Next, the memory array substrate 80 will be described.
As shown in FIG. 5, in the memory array substrate 80, a source line 83 made of a conductive material is provided on a silicon substrate 81. On the source line 83, a stacked body 85 is provided. In the stacked body 85, insulating films 86 and electrode films 87 are alternately stacked.

  A core member 90 extending in the stacking direction of the insulating film 86 and the electrode film 87 is provided in the stacked body 85. The core member 90 is made of an insulating material such as silicon oxide. The shape of the core member 90 is columnar, for example, substantially columnar. Silicon pillars 91 are provided around the core member 90 and on the lower surface. The lower end of the silicon pillar 91 is connected to the source line 83.

  Around the silicon pillar 91, a tunnel insulating film 92, a charge storage film 93, and a block insulating film 94 are stacked in this order. The tunnel insulating film 92 is normally insulative, but is a film through which a tunnel current flows when a predetermined voltage within the range of the drive voltage of the semiconductor memory device 1 is applied. For example, a single-layer silicon oxide film Or an ONO film in which a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are stacked in this order.

  The charge storage film 93 is a film capable of storing charges, and is made of, for example, a material including an electron trap site, for example, silicon nitride. Note that a conductive floating gate electrode may be provided as the charge storage section instead of the insulating charge storage film 93. In this case, the floating gate electrode is divided for each electrode film 87. The block insulating film 94 is a film that does not substantially flow a current even when a voltage is applied within the range of the driving voltage of the semiconductor memory device 1. The block insulating film 94 includes, for example, a material having a higher dielectric constant than silicon oxide.

  On the side and above the stacked body 85, an interlayer insulating film 82 is provided. A plug 96 and a bit line 97 are provided in the interlayer insulating film 82 and on the stacked body 85. The upper end of the silicon pillar 91 is connected to a bit line 97 via a plug 96. The bit line 97 is connected to the sense amplifier 15 of the control circuit board 10 (see FIG. 2).

  With such a configuration, a memory cell transistor is formed at each intersection between the electrode film 87 and the silicon pillar 91. In the memory cell transistor, the silicon pillar 91 serves as a channel, the electrode film 87 serves as a gate, and the block insulating film 94 serves as a gate insulating film. Then, by storing charges in the charge storage film 93, the threshold value of the memory cell transistor is changed and data is stored. The threshold value of the memory cell transistor can take eight levels, for example. As a result, 3-bit data can be stored in one memory cell transistor.

Next, the operation of the semiconductor memory device according to the embodiment will be described.
As shown in FIG. 4B, in the initial state, the selection signals Vs1 and Vs2, the control signals Vc1 and Vc2, and the data signal SA are all “L” (low level). Therefore, the p-channel transistors p1 and p3 are on, and the n-channel transistors n1 and n4 are off.

  From this state, for the data latch circuit 16 that holds data, the selection signal Vs2 is set to “H” (high level), and the p-channel transistor p3 is turned off. Further, the control signal Vc2 is set to “H” to turn on the n-channel transistor n4. As a result, the potential at the connection point N2 between the p-channel transistor p4 and the n-channel transistor n3 becomes "L". As a result, the p-channel transistor p2 is turned on and the n-channel transistor n2 is turned off, so that the potential at the connection point N1 between the p-channel transistor p2 and the n-channel transistor n2 becomes "H". Thus, the p-channel transistor p4 is turned off and the n-channel transistor n3 is turned on, so that the potential of the connection point N2 is stabilized at "L". Thereafter, the selection signal Vs2 is returned to “L”, and the p-channel transistor p3 is turned on. Further, the control signal Vc2 is returned to "L", and the n-channel transistor n4 is turned off.

  As shown in FIG. 5, when data is read from the memory cell transistor, a current flows between the source line 83 and the bit line 97, and this current is input to the sense amplifier 15 of the sense amplifier circuit 14 shown in FIG. . The sense amplifier 15 detects a value based on the input current and outputs the value to the data latch circuit 16 as a data signal SA. At this time, the sense amplifier 15 outputs the original data signal SA after temporarily setting the data signal SA to “H”. Next, the control signal Vc1 is set to “H”, the n-channel transistor n1 is turned on, and the value of the data signal SA is written to the data latch circuit 16.

  When the data signal SA is “H”, the potential of the connection point N1 remains “H” because the n-channel transistor n1 is on, and the potential of the connection point N2 is “L”. It is fixed as it is.

  When the data signal SA is “L”, the potential at the connection point N1 is “L” because the n-channel transistor n1 is in the ON state. Therefore, the p-channel transistor p4 is turned on, and the n-channel transistor n3 is turned off. Therefore, the potential of the connection point N2 becomes “H”. Thus, the p-channel transistor p2 is turned off, and the n-channel transistor n2 is turned on. As a result, the potential of the connection point N1 is fixed at “L”.

  In summary, when the data signal SA is "H", the potential of the connection point N1 is fixed at "H" and the potential of the connection point N2 is fixed at "L". On the other hand, when the data signal SA is "L", the potential of the connection point N1 is fixed at "L" and the potential of the connection point N2 is fixed at "H". In this manner, the data latch circuit 16 can store the potential of the data signal SA and hold the value represented by the data signal SA. For example, binary data can be held by associating a value “0” with the potential “H” of the data signal SA and associating a value “1” with the potential “L”.

Next, effects of the present embodiment will be described.
In the present embodiment, one gate 53 realizes both the gate of the p-channel transistor p4 and the gate of the n-channel transistor n3. In addition, one gate 54 realizes both the gate of the p-channel transistor p2 and the gate of the n-channel transistor n2. Thus, the number of gates in the data latch circuit 16 can be reduced, and the size of the data latch circuit 16 can be reduced.

  In each data latch circuit 16, the p-channel transistors p1 to p4 and the n-channel transistors n1 to n4 are separately arranged in the X direction, and the layouts of the data latch circuits 16 adjacent in the X direction are mutually mirror images. I have. Thus, the gates 51, 52, 55, and 56 can be shared between the data latch circuits 16 adjacent in the X direction. Thus, the size of the data latch circuit 16 can be reduced.

  Further, in the present embodiment, a control circuit including the sense amplifier region 13 is provided on the control circuit substrate 10, and a memory cell transistor is provided on the memory array substrate 80. As described above, when the control circuit is formed on a dedicated substrate, the control circuit does not receive the heat history required for forming the memory cell transistor in the manufacturing process. Therefore, the p-channel transistors p1 to p4 and the n-channel transistors n1 to n4 are not received. n4 itself can be miniaturized. This also allows the data latch circuit 16 to be downsized.

  By reducing the size of the data latch circuit 16, the sense amplifier circuit 14 can be reduced in size, and the overall semiconductor memory device 1 can be reduced in size. Conversely, if the area of the sense amplifier circuit 14 is fixed, more data latch circuits 16 can be provided for each sense amplifier circuit 14. As a result, as the memory cell transistor is miniaturized, the channel area is reduced, and the fluctuation of the threshold value due to the increase or decrease of one electron stored in the charge storage film 93 is increased, and it takes a long time to write and read data. Even in such a case, since each sense amplifier circuit 14 can hold a large amount of data, the data transfer speed can be kept constant.

(Second embodiment)
Next, a second embodiment will be described.
FIG. 6 is a plan view showing the data latch circuit according to the present embodiment.
FIG. 7A is a plan view showing one data latch circuit, and FIG. 7B is a circuit diagram thereof.

  As shown in FIGS. 6 and 7A, the semiconductor memory device 2 according to the present embodiment is different from the semiconductor memory device 1 according to the first embodiment (see FIGS. 1 to 5) in comparison with the first embodiment. The configurations of the p-channel transistors p1 to p4 and the n-channel transistors n1 to n4 are the same, but the shapes of the wirings are different. As a result, the region where the data latch circuit 18 according to the present embodiment is formed is different from the region where the data latch circuit 16 according to the first embodiment is formed.

Hereinafter, a specific description will be given.
In the sense amplifier region 13 of the present embodiment, the shapes, positional relationships and connection relationships of the n-well 21, the p-well 22, the p-type layers 31 to 36, the n-type layers 41 to 45, the gates 51 to 56, and the contacts 61 to 73 are as follows. , And the same as in the first embodiment.

  However, in the present embodiment, wirings 78 and 79 are provided instead of the wirings 76 and 77 of the first embodiment. The wiring 78 is connected to the upper end of the contact 70, the upper end of the contact 65 and the upper end of the contact 67 disposed below the contact 70 in the drawing. The wiring 79 is connected to the upper end of the contact 66, the upper end of the contact 71 arranged above the contact 66 and the upper end of the contact 69.

  As a result, each data latch circuit 18 has one island-shaped semiconductor region surrounded by STI 23 and a part of a band-shaped semiconductor region arranged in p-well 22. Including a rectangular area. In the island-shaped semiconductor region, p-type layers 34, 35, 36, 31, 32, and 33 are arranged in this order. The p-type layer 36 and the p-type layer 31 are continuous, but the other p-type layers are separated from each other, and a part of the n-well 21 is interposed between adjacent p-type layers. . In a part of the band-shaped semiconductor region, n-type layers 43, 44, 45, 41, and 42 are arranged in this order. The n-type layer 45 and the n-type layer 41 are continuous, but the other n-type layers are separated from each other, and a part of the p-well 22 is interposed between adjacent n-type layers. .

As shown in FIG. 7B, a circuit similar to that of the first embodiment can be realized by such a configuration.
Other configurations, operations, and effects of the present embodiment are the same as those of the above-described first embodiment.

(Third embodiment)
Next, a third embodiment will be described.
FIG. 8 is a plan view showing a semiconductor region, a gate, and a contact in the data latch circuit according to the present embodiment.
FIG. 9 is a plan view showing a semiconductor region, a gate, a contact, and a first wiring layer in the data latch circuit according to the present embodiment.
FIG. 10 is a plan view showing a semiconductor region, a gate, a contact, a first wiring layer, a second wiring layer, and a third wiring layer in the data latch circuit according to the present embodiment.
FIGS. 11A to 11C are plan views showing one data latch circuit according to the present embodiment, in which FIG. 11A shows a semiconductor region, a gate and a contact, and FIG. 1C illustrates a first wiring layer, and FIG. 2C illustrates a second wiring layer and a third wiring layer in addition to FIG.
FIG. 12 is a plan view showing four data latch circuits according to the present embodiment.
FIG. 13A is a plan view showing one data latch circuit according to the present embodiment, and FIG. 13B is a circuit diagram thereof.

  FIGS. 8 to 10 are diagrams schematically showing a layout relationship between a plurality of data latch circuits, and a detailed configuration of each data latch circuit is partially omitted for easy understanding of the drawings. . On the other hand, FIGS. 11A to 11C and FIG. 13A are diagrams showing the configuration of one data latch circuit in detail, and do not show the relationship with other data latch circuits. FIG. 12 shows an intermediate concept between these, and shows four data latch circuits in two rows and two columns.

  The semiconductor memory device 3 according to the present embodiment is different from the semiconductor memory device 1 according to the first embodiment (see FIGS. 1 to 5) in the configuration of the data latch circuit. The configuration of the memory array substrate 80 is the same as in the first embodiment.

First, the well, the n-type layer, the p-type layer, and the gate provided on the silicon substrate 11 will be described.
As shown in FIG. 8, in the semiconductor memory device 3 according to the present embodiment, n-wells 21 and p-wells 22 are alternately arranged on the silicon substrate 11 along the X direction. Each n-well 21 and each p-well 22 extend in the Y direction. Each data latch circuit 116 is set over a half area of one n-well 21 and two p-wells 22 arranged on both sides thereof. The length of the data latch circuit 116 in the X direction is equal to the sum of the length of one n-well 21 and the length of one p-well 22.

  In the sense amplifier region 13 of the semiconductor memory device 3, a plurality of data latch circuits 116 are arranged in a matrix along the X and Y directions. The layout of two data latch circuits 116 adjacent in the X direction is a mirror image of each other, and the layout of two data latch circuits 116 adjacent in the Y direction is also a mirror image of each other.

  11 (a) to 11 (c) and FIG. 13 (a), for convenience of explanation, the p-well 22 included in each data latch circuit 116 will be described by dividing it into a p-well 22a and a p-well 22b. In each data latch circuit 116, the p-well 22a and the p-well 22b are separated from each other via the n-well 21. On the other hand, the p-well 22a of a certain data latch circuit 116 is continuous with the p-well 22b of the data latch circuit 116 adjacent to the data latch circuit 116 in the X direction.

  As shown in FIG. 11A, n-type layers 141 to 143 having an n-type conductivity are provided on the p-well 22a. The n-type layers 141 to 143 are separated from each other and arranged in a line in this order along the Y direction. In the data latch circuits 116 adjacent in the Y direction, the n-type layers 141 are continuous, and the n-type layers 143 are also continuous. A part of the p-well 22a is interposed between the n-type layer 141 and the n-type layer 142 and between the n-type layer 142 and the n-type layer 143, respectively.

  As a result, on each p-well 22a, a plurality of sets of n-type layers 141 to 143 arranged along the Y direction form one linear shape together with the p-well 22a interposed between these n-type layers. Semiconductor region (active area) 111 is formed. The semiconductor region 111 includes an n-type layer 141 in each data latch circuit 116, a portion between the n-type layer 141 and the n-type layer 142 in the p-well 22a, an n-type layer 142, and an n-type layer 142 and n in the p-well 22a. And a portion between the n-type layer 143 and the n-type layer 143. One semiconductor region 111 extends in the Y direction over a plurality of data latch circuits 116 arranged in the Y direction.

  On the n-well 21, p-type layers 131 and 132 having a p-type conductivity are provided. The p-type layer 131 and the p-type layer 132 are separated in the Y direction. In the data latch circuits 116 adjacent to each other in the Y direction, the p-type layers 132 are continuous. Part of the n-well 21 is interposed between the p-type layer 131 and the p-type layer 132.

  As a result, on each n-well 21, the p-type layer 131, the portion between the p-type layer 131 and the p-type layer 132 in the n-well 21, The p-type layer 132, the portion between the p-type layer 132 and the p-type layer 131 in the n-well 21, and the p-type layer 131 are continuously arranged in this order along the Y direction, so that an island-shaped semiconductor is formed. An area (active area) 112 is formed.

  Further, p-type layers 133 and 134 having a p-type conductivity are provided on the n-well 21. The p-type layer 133 and the p-type layer 134 are separated from each other in the Y direction. In the data latch circuits 116 adjacent in the Y direction, the p-type layers 133 are continuous. A part of the n-well 21 is interposed between the p-type layer 133 and the p-type layer 134.

  Thus, on each n-well 21, the p-type layer 134, the portion between the p-type layer 134 and the p-type layer 133 in the n-well 21, The p-type layer 133, the portion of the n-well 21 between the p-type layer 133 and the p-type layer 134, and the p-type layer 134 are continuously arranged in this order along the Y direction to form an island-shaped semiconductor. An area (active area) 113 is formed.

  On the p well 22b, n-type layers 144 to 146 having an n-type conductivity are provided. The n-type layers 144 to 146 are separated from each other and are arranged in a line in this order along the Y direction. In the data latch circuits 116 adjacent in the Y direction, the n-type layers 144 are continuous, and the n-type layers 146 are also continuous. A part of the p-well 22b is interposed between the n-type layer 144 and the n-type layer 145 and between the n-type layer 145 and the n-type layer 146, respectively.

  Thereby, on each p-well 22b, a plurality of sets of n-type layers 144 to 146 arranged along the Y direction form one line-like shape together with the p-well 22b interposed between these n-type layers. (Active area) 114 is formed. The semiconductor region 114 includes an n-type layer 144 in each data latch circuit 116, a portion between the n-type layer 144 and the n-type layer 145 in the p-well 22b, an n-type layer 145, and an n-type layer 145 and n in the p-well 22b. And a portion between the n-type layer 146 and the n-type layer 146. One semiconductor region 114 extends over a plurality of data latch circuits 116 arranged along the Y direction.

  In the entire sense amplifier region 13, the semiconductor region 111 continuously extends along the Y direction. The semiconductor regions 112 are intermittently arranged in a line along the Y direction. The semiconductor regions 113 are also intermittently arranged in a line along the Y direction. The semiconductor region 114 extends continuously along the Y direction.

  The semiconductor regions 111 to 114 are arranged in this order along the X direction and are separated from each other. The positions of the n-type layer 141, the p-type layer 133, and the n-type layer 144 in the Y direction are substantially the same, and the n-type layer 142, the p-type layer 131, the p-type layer 134, and the n-type layer 145 Are substantially the same in the Y direction, and the positions of the n-type layer 143, the p-type layer 132, and the n-type layer 146 in the Y direction are substantially the same.

  The STI 23 is arranged between the semiconductor regions 111 to 114. The combination of the two data latch circuits 116 sharing the semiconductor region 112 is different from the combination of the two data latch circuits 116 sharing the semiconductor region 113. That is, one data latch circuit 116 shares the semiconductor region 112 with the data latch circuit 116 on one side in the Y direction, and shares the semiconductor region 113 with the data latch circuit 116 on the other side in the Y direction.

  In each data latch circuit 116, gates 151 to 154 are provided. The gates 151 to 154 extend substantially in the X direction and cross the semiconductor regions 111 to 114 described above. When viewed from the Z direction, the gates 151 to 154 have a band shape extending in the X direction. A gate insulating film (not shown) is provided between the gates 151 to 154 and the semiconductor regions 111 to 114. Hereinafter, the positional relationship between the gates 151 to 154 and the semiconductor regions 111 to 114 will be described.

  Gate 151 traverses semiconductor region 111. Specifically, a part of the gate 151 is arranged in a region immediately above a portion between the n-type layer 141 and the n-type layer 142 in the p-well 22a. The gate 151 is common to the data latch circuits 116 adjacent in the X direction. That is, one gate 151 extending in the X direction is adjacent in the X direction, and traverses the semiconductor region 111 in each of the two data latch circuits 116 whose layouts are mirror images of each other.

  Gate 152 traverses semiconductor region 111 and semiconductor region 112. Specifically, a part of the gate 152 is disposed immediately above a part between the n-type layer 142 and the n-type layer 143 in the p-well 22a, and another part is connected to the p-type layer 131 in the n-well 21. It is arranged in a region immediately above a portion between the p-type layer 132 and the p-type layer 132. Gate 152 is arranged inside each data latch circuit 116 and does not extend between adjacent data latch circuits 116.

  Gate 153 traverses semiconductor region 113 and semiconductor region 114. Specifically, a part of the gate 153 is arranged in a region immediately above the part between the p-type layer 133 and the p-type layer 134 in the n-well 21, and the other part is connected to the n-type layer 144 in the p-well 22 b. It is arranged in a region immediately above a portion between the n-type layers 145. The gate 153 is arranged inside each data latch circuit 116 and does not extend between adjacent data latch circuits 116.

  Gate 154 traverses semiconductor region 114. Specifically, a part of the gate 154 is disposed immediately above a portion between the n-type layers 145 and 146 in the p-well 22b. The gate 154 is common to the data latch circuits 116 adjacent in the X direction. That is, one gate 154 extending in the X direction is adjacent to each other in the X direction, and traverses the semiconductor region 114 in each of the two data latch circuits 116 whose layouts are mirror images of each other.

  The combination of the two data latch circuits 116 sharing the gate 151 and the two data latch circuits 116 sharing the gate 154 are different. A certain data latch circuit 116 shares a gate 151 with the data latch circuit 116 on one side in the X direction, and shares a gate 154 with the data latch circuit 116 on the other side in the X direction. In the entire sense amplifier region 13, the gates 151 and 153 are arranged in a line along the X direction, and the gates 152 and 154 are arranged in a line along the X direction.

  As shown in FIGS. 13A and 13B, with the above-described configuration, in each data latch circuit 116, two p-channel transistors p2 and p4 and four n-channel transistors n1 to n4 are formed. .

  More specifically, an n-channel transistor n1 is formed by the n-type layer 141, the n-type layer 142, the portion of the p-well 22a between the n-type layer 141 and the n-type layer 142, and the gate 151. . The n-type layer 142, the n-type layer 143, the portion between the n-type layer 142 and the n-type layer 143 in the p-well 22a, and the gate 152 form an n-channel transistor n2. The n-type layer 144, the n-type layer 145, a portion between the n-type layer 144 and the n-type layer 145 in the p-well 22b, and the gate 153 form an n-channel transistor n3. The n-type layer 145, the n-type layer 146, the portion between the n-type layer 145 and the n-type layer 146 in the p-well 22b, and the gate 154 form an n-channel transistor n4.

  The p-type layer 131, the p-type layer 132, the portion between the p-type layer 131 and the p-type layer 132 in the n-well 21, and the gate 152 form a p-channel transistor p <b> 2. The p-type layer 133, the p-type layer 134, the portion between the p-type layer 133 and the p-type layer 134 in the n-well 21, and the gate 153 form a p-channel transistor p4.

  Thus, the n-channel transistor n2 and the p-channel transistor p2 share one gate 152. The n-channel transistor n3 and the p-channel transistor p4 share one gate 153. Further, two n-channel transistors n1 provided in two data latch circuits 116 adjacent in the X direction share one gate 151. Two n-channel transistors n4 provided in two data latch circuits 116 adjacent in the X direction share one gate 154.

Next, the contact will be described.
As shown in FIGS. 11A, 12 and 13A, each data latch circuit 116 is provided with contacts 161 to 172. When viewed from the Z direction, the shape of the contacts 165 and 168 is an oval whose length in the Y direction is longer than the length in the X direction. Other shapes of the contacts are substantially circular. However, in FIG. 13A, a contact belonging to only one data latch circuit 116 is represented by a circle or an ellipse, and a contact shared with the adjacent data latch circuit 116 is represented by a semicircle. As in the first embodiment, each contact may include a plurality of contacts arranged in the Z direction, and the plurality of contacts may be connected via an intermediate wiring. The intermediate wiring may be provided in the same layer as a first wiring layer 121 or a second wiring layer 122 described later.

  The lower end of the contact 161 is connected to the gate 151. The contact 161 is shared by two data latch circuits 116 adjacent in the X direction. The lower end of the contact 162 is connected to the n-type layer 141. The contact 162 is shared by two data latch circuits 116 adjacent in the Y direction. The lower end of the contact 163 is connected to the n-type layer 142. The lower end of the contact 164 is connected to the n-type layer 143. The contact 164 is shared by two data latch circuits 116 adjacent in the Y direction. As described above, the contacts 162, 163, and 164 are connected to the same semiconductor region 111 and are arranged along the Y direction.

  The contact 165 is connected to the gate 153 at an intermediate portion in the Z direction, and the lower end is connected to the p-type layer 131. When viewed from the Z direction, the shape of the contact 165 is an oval whose length in the Y direction is longer than the length in the X direction. The lower end of the contact 166 is connected to the p-type layer 132. The contact 166 is shared by two data latch circuits 116 adjacent in the Y direction. Thus, the contacts 165 and 166 are connected to the same semiconductor region 112 and are arranged along the Y direction.

  The lower end of the contact 167 is connected to the p-type layer 133. The contact 167 is shared by two data latch circuits 116 adjacent in the Y direction. The contact 168 is connected to the gate 152 at an intermediate portion in the Z direction, and the lower end is connected to the p-type layer 134. When viewed from the Z direction, the shape of the contact 168 is an oval whose length in the Y direction is longer than the length in the X direction. Thus, the contacts 167 and 168 are connected to the same semiconductor region 113 and are arranged along the Y direction.

  The lower end of the contact 169 is connected to the n-type layer 144. The contact 169 is shared by two data latch circuits 116 adjacent in the Y direction. The lower end of the contact 170 is connected to the n-type layer 145. The lower end of the contact 171 is connected to the n-type layer 146. The contact 171 is shared by two data latch circuits 116 adjacent in the Y direction. Thus, the contacts 169, 170, and 171 are connected to the same semiconductor region 114 and are arranged along the Y direction. The lower end of the contact 172 is connected to the gate 154. The contact 172 is shared by two data latch circuits 116 adjacent in the X direction.

  Above the silicon substrate 11 and the gate, a first wiring layer 121, a second wiring layer 122, and a third wiring layer 123 are stacked in this order. That is, the first wiring layer 121 is located above the gates 151 to 154, the second wiring layer 122 is located above the first wiring layer 121, and the third wiring layer 123 is located above the second wiring layer 122. Located in the upper layer.

Hereinafter, the first wiring layer 121 will be described.
As shown in FIGS. 9, 11B, 12 and 13A, in the first wiring layer 121, a wiring 121a, a wiring 121b, and a wiring 121c are provided. In the wiring 121a, a trunk 121d and branches 121e and 121f are provided. The trunk portion 121d of the wiring 121a extends in the X direction central portion of each data latch circuit 116, that is, between the semiconductor region 112 and the semiconductor region 113 in the Y direction.

  The trunk 121d is provided over a plurality of data latch circuits 116 arranged along the Y direction. The trunk 121d passes through a region immediately above the gate 152 and a region immediately above the gate 153. The branch 121e of the wiring 121a extends from the trunk 121d to one side in the X direction, and is connected to the upper end of the contact 162. The branch 121e is shared by two data latch circuits 116 adjacent in the Y direction. The branch 121f of the wiring 121a extends from the trunk 121d to the other side in the X direction and is connected to the upper end of the contact 171. The branch portion 121f is shared by two data latch circuits 116 adjacent in the Y direction. As described above, the wiring 121a is connected to the n-type layer 141 via the contact 162, and is also connected to the n-type layer 146 via the contact 171.

  The wiring 121b extends in the X direction and is connected to the upper ends of the contacts 163 and 165. Thus, the n-type layer 142, the p-type layer 131, and the gate 153 are connected to each other via the contact 163, the wiring 121b, and the contact 165. The wiring 121c also extends in the X direction, and is connected to the upper end of the contact 168 and the upper end of the contact 170. Thus, the n-type layer 145, the p-type layer 134, and the gate 152 are connected to each other via the contact 170, the wiring 121c, and the contact 168.

Next, the second wiring layer 122 will be described.
As shown in FIGS. 10, 12, and 13A, in the second wiring layer 122, wirings 122a and 122b are provided. The wirings 122a and 122b have a linear shape extending in the X direction, and are provided over a plurality of data latch circuits 116 arranged in the X direction.

  The wiring 122a is arranged so as to pass through a region immediately above the gate 151 and a region immediately above the gate 153, and is connected to the upper end of the contact 161. Note that the wiring 122a also passes through a region immediately above the contact 165, but is not connected to the contact 165. Thus, the wiring 122a is connected to the gate 151 via the contact 161.

  The wiring 122b is arranged so as to pass through the region directly above the gate 152 and the region immediately above the gate 154, and is connected to the upper end of the contact 172. Note that the wiring 122b also passes through a region immediately above the contact 168, but is not connected to the contact 168. Thus, the wiring 122b is connected to the gate 154 via the contact 172.

Next, the third wiring layer 123 will be described.
As shown in FIG. 10, FIG. 11C, FIG. 12, and FIG. 13A, in the third wiring layer 123, wirings 123a and 123b are provided. The wirings 123a and 123b have a line shape extending in the Y direction, and are provided over a plurality of data latch circuits 116 arranged in the Y direction. The wirings 123a and the wirings 123b are alternately arranged along the X direction.

  The wiring 123a is arranged along the boundary between the data latch circuits 116 adjacent in the X direction. For example, the wiring 123a belongs to two data latch circuits 116 adjacent in the X direction, and the semiconductor region 111 and the semiconductor region 111 adjacent via the STI 23. It is arranged immediately above the semiconductor region 114. The wiring 123a is connected to the upper end of the contact 164 and the upper end of the contact 169. Thus, the wiring 123 a is connected to the n-type layer 143 via the contact 164 and to the n-type layer 144 via the contact 169.

  The wiring 123b is disposed at the center of the data latch circuit 116 in the X direction, and is disposed, for example, in the region immediately above the semiconductor region 112 and the region immediately above the semiconductor region 113 of each data latch circuit 116. The wiring 123b is connected to the upper ends of the contacts 166 and 167. Thus, the wiring 123 b is connected to the p-type layer 132 via the contact 166 and to the p-type layer 133 via the contact 167.

  As a result of connecting the transistors as described above, the circuit shown in FIG. 13B is formed in each data latch circuit 116.

  That is, one of the source and the drain of the n-channel transistor n1 and one of the source and the drain of the n-channel transistor n2 are connected to each other because they are the common n-type layer 142. The n-type layer 142 is connected to one of the source and the drain (p-type layer 131) of the p-channel transistor p2 and the p-channel transistor p4 and the n-channel transistor n3 via the contact 163, the wiring 121b, and the contact 165. They are connected to a common gate 153.

  Similarly, one of the source and the drain of the n-channel transistor n3 and one of the source and the drain of the n-channel transistor n4 are connected to each other because they are the common n-type layer 145. The n-type layer 145 is connected to one of the source and the drain (p-type layer 134) of the p-channel transistor p4 and the p-channel transistor p2 and the n-channel transistor n2 via the contact 170, the wiring 121c, and the contact 168. They are connected to a common gate 152.

  The other of the source and the drain of the n-channel transistor n1 (the n-type layer 141) and the other of the source and the drain of the n-channel transistor n4 (the n-type layer 146) are interconnected via the contacts 162 and 171 respectively. 121a. The wiring 121a is connectable to the sense amplifier 15, and the data signal SA output from the sense amplifier 15 is applied.

  The other of the source and the drain (n-type layer 143) of the n-channel transistor n2 is connected to the wiring 123a of the third wiring layer 123 via the contact 164. The other of the source and the drain (n-type layer 144) of the n-channel transistor n3 is connected to the wiring 123a of the third wiring layer 123 via the contact 169. A ground potential GND as a second reference potential is applied to the wiring 123a.

  The other of the source and drain (p-type layer 132) of the p-channel transistor p2 is connected to the wiring 123b of the third wiring layer 123 via the contact 166. The other of the source and the drain (p-type layer 133) of the p-channel transistor p4 is connected to the wiring 123b of the third wiring layer 123 via the contact 167. The power supply potential VDD as a first reference potential is applied to the wiring 123b.

  The gate 151 of the n-channel transistor n1 is connected to the wiring 122a of the second wiring layer 122 via the contact 161. The control signal Vc1 is input to the wiring 122a. The gate 154 of the n-channel transistor n4 is connected to the wiring 122b of the second wiring layer 122 via the contact 172. The control signal Vc2 is input to the wiring 122b.

Next, the operation of the semiconductor memory device according to the embodiment will be described.
As shown in FIG. 13B, in the initial state, the control signals Vc1 and Vc2 and the data signal SA are all “L”. Therefore, the n-channel transistors n1 and n4 are off.

  From this state, for the data latch circuit 116 that holds data, the control signal Vc2 is set to “H” to turn on the n-channel transistor n4. As a result, the potential at the connection point N2 between the p-channel transistor p4 and the n-channel transistor n3 becomes "L". As a result, the p-channel transistor p2 is turned on and the n-channel transistor n2 is turned off, so that the potential at the connection point N1 between the p-channel transistor p2 and the n-channel transistor n2 becomes "H". Thus, the p-channel transistor p4 is turned off and the n-channel transistor n3 is turned on, so that the potential of the connection point N2 is stabilized at "L". Thereafter, the control signal Vc2 is returned to "L", and the n-channel transistor n4 is turned off.

  Then, the sense amplifier 15 outputs the original data signal SA after setting the data signal SA to “H” once. Next, the control signal Vc1 is set to “H”, the n-channel transistor n1 is turned on, and the value of the data signal SA is written to the data latch circuit 16.

  When the data signal SA is “H”, the potential of the connection point N1 remains “H” because the n-channel transistor n1 is on, and the potential of the connection point N2 is “L”. It is fixed as it is.

  When the data signal SA is “L”, the potential at the connection point N1 is “L” because the n-channel transistor n1 is in the ON state. Therefore, the p-channel transistor p4 is turned on, and the n-channel transistor n3 is turned off. Therefore, the potential of the connection point N2 becomes “H”. Thus, the p-channel transistor p2 is turned off and the n-channel transistor n2 is turned on, so that the potential of the connection point N1 is fixed at "L".

  Thus, when the data signal SA is “H”, the potential at the connection point N1 is fixed at “H”, the potential at the connection point N2 is fixed at “L”, and when the data signal SA is “L”. , The potential of the connection point N1 is fixed at “L”, and the potential of the connection point N2 is fixed at “H”. As a result, the data latch circuit 116 can hold the value represented by the data signal SA.

Next, effects of the present embodiment will be described.
In this embodiment, the data latch circuit 116 can be constituted by six transistors. Thus, the size of the data latch circuit 116 can be reduced as compared with the first embodiment.

  In the present embodiment, one gate 152 realizes both the gate of the n-channel transistor n2 and the gate of the p-channel transistor p2. Further, one gate 153 realizes both the gate of the n-channel transistor n3 and the gate of the p-channel transistor p4. Thus, the number of gates in the data latch circuit 116 can be reduced, and the size of the data latch circuit 116 can be reduced.

  Further, in the present embodiment, the gates 151 and 153 have a band shape extending in the X direction, and are arranged along the X direction. The gates 152 and 154 also have a band shape extending in the X direction, and are arranged along the X direction. As a result, the number of gate columns in each data latch circuit 116 becomes two, and the size of the data latch circuit 116 in the Y direction can be reduced.

Furthermore, in the present embodiment, the layouts of the data latch circuits 116 adjacent in the X direction are mirror images of each other. Accordingly, the gate 151 can be shared between the data latch circuits 116 adjacent in the X direction, and the gate 154 can be shared. The layout of the data latch circuits 116 adjacent in the Y direction is a mirror image of each other. Thus, the n-type layer 141, the n-type layer 143, the p-type layer 132, the p-type layer 133, the n-type layer 144, and the n-type layer 146 can be shared between the data latch circuits 116 adjacent in the Y direction. Thus, the size of the data latch circuit 16 can be reduced.
Other configurations, operations, and effects of the present embodiment are the same as those of the above-described first embodiment.

(Fourth embodiment)
Next, a fourth embodiment will be described.
FIG. 14 is a plan view showing a semiconductor region, a gate, a contact, and a first wiring layer in the four data latch circuits according to the present embodiment.
FIG. 15 is a plan view showing a semiconductor region, a gate, a contact, a first wiring layer, and a second wiring layer in four data latch circuits according to the present embodiment.
FIG. 16 is a plan view showing a semiconductor region, a gate, a contact, a first wiring layer, a second wiring layer, and a third wiring layer in four data latch circuits according to the present embodiment.
FIG. 17A is a plan view showing one data latch circuit according to the present embodiment, and FIG. 17B is a circuit diagram thereof.

  As shown in FIGS. 14 to 16 and FIG. 17A, a semiconductor memory device 4 according to the present embodiment is the same as the semiconductor memory device 3 according to the third embodiment described above (see FIGS. 8 to 13B). The configuration of the data latch circuit 118 is different from that of FIG.

  In the data latch circuit 118, the shape, positional relationship, and connection relationship of the n-well 21, the p-well 22, the p-type layers 131 to 134, the n-type layers 141 to 146, the gates 151 to 54, and the contacts 161 to 172 are the third. This is the same as the data latch circuit 116 according to the embodiment. On the other hand, the data latch circuit 118 is different from the data latch circuit 116 in the configuration of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123. The data latch circuit 118 has vias 181 and 182.

First, the first wiring layer 121 will be described.
As shown in FIGS. 14 and 17A, in the first wiring layer 121 of the data latch circuit 118, wirings 121b, 121c, 121g, 121h, and 121i are provided. The positions and shapes of the wiring 121b and the wiring 121c are the same as in the third embodiment. The wiring 121h is connected to the upper end of the contact 162 and the lower end of the via 181. The wiring 121i is connected to the upper end of the contact 171 and the lower end of the via 182.

  In the wiring 121g, a trunk 121j and branches 121m and 121n are provided. The trunk 121j of the wiring 121g extends in the X direction center of each data latch circuit 118, that is, between the semiconductor region 112 and the semiconductor region 113 in the Y direction. The trunk 121j is provided over a plurality of data latch circuits 118 arranged along the Y direction. The trunk 121j is arranged so as to pass through a region immediately above the gate 152 and a region immediately above the gate 153.

  The branch 121m of the wiring 121g extends from the trunk 121j to one side in the X direction, and is connected to the upper end of the contact 167. The branch portion 121m is shared by two data latch circuits 118 adjacent in the Y direction. The branch 121n of the wiring 121g extends from the trunk 121j to the other side in the X direction, and is connected to the upper end of the contact 166. The branch 121n is shared by two data latch circuits 118 adjacent in the Y direction. In this way, the wiring 121g is connected to the p-type layer 133 via the contact 167 and to the p-type layer 132 via the contact 166.

Next, the second wiring layer 122 will be described.
As shown in FIG. 15, a wiring 122c is provided in the second wiring layer 122 of the data latch circuit 118. In the wiring 122c, a trunk 122d and branches 122e and 122f are provided. The trunk 122d of the wiring 122c extends in the X direction. The trunk 122d is provided over a plurality of data latch circuits 118 arranged along the X direction. The trunk 122d is disposed so as to pass through a region immediately above the wiring 121b and a region immediately above the wiring 121c of the first wiring layer 121.

  The branch 122e of the wiring 122c extends from the trunk 122d to one side in the Y direction, and is connected to the upper end of the contact 161. The branch 122f of the wiring 122c extends from the trunk 122d to the other side in the Y direction, and is connected to the upper end of the contact 172. Thus, the wiring 122c is connected to the gate 151 via the contact 161 and to the gate 154 via the contact 172.

Next, the third wiring layer 123 will be described.
As shown in FIG. 16, in the third wiring layer 123 of the data latch circuit 118, wirings 123a, 123c and 123d are provided. The wirings 123a, 123c, and 123d have a line shape extending in the Y direction, and are provided over a plurality of data latch circuits 118 arranged in the Y direction.

  The position and shape of the wiring 123a are the same as in the third embodiment. That is, the wiring 123a is arranged along the boundary between the data latch circuits 118 adjacent in the X direction. For example, the wiring 123a belongs to two data latch circuits 118 adjacent in the X direction and is adjacent to the semiconductor region via the STI 23. 111 and the semiconductor region 114. The wiring 123a is connected to the upper end of the contact 164 and the upper end of the contact 169. Thus, the wiring 123a is connected to the n-type layer 143 via the contact 164 and to the n-type layer 144 via the contact 169.

  The wiring 123c is arranged near the region immediately above the semiconductor region 112, and is connected to the upper end of the via 181. As a result, the wiring 123c is connected to the n-type layer 141 via the via 181, the wiring 121h, and the contact 162.

  The wiring 123d is arranged near the region immediately above the portion between the semiconductor region 113 and the semiconductor region 114, and is connected to the upper end of the via 182. Thus, the wiring 123d is connected to the n-type layer 146 via the via 182, the wiring 121i, and the contact 172.

As a result of connecting the transistors as described above, each data latch circuit 118 forms the circuit shown in FIG.
The connection between the transistors in the data latch circuit 118 is similar to that of the data latch circuit 116 according to the third embodiment. The connection between the n-channel transistors n2 and n3 and the ground potential GND is the same as that of the data latch circuit 116.

  On the other hand, the data latch circuit 118 differs from the data latch circuit 116 in the manner in which the power supply potential VDD, the control signal Vc, and the data signals SA and bSA are input to each transistor. The data latch circuit 118 differs from the data latch circuit 116 in that the control signal Vc is common and that the data signals SA and bSA are complementary signals. If one of the data signals SA and bSA is “H”, the other is “L”.

  The other of the source and drain (p-type layer 132) of the p-channel transistor p2 is connected to the wiring 121g via the contact 166 and the branch 121n. The other of the source and drain (p-type layer 133) of the p-channel transistor p4 is connected to the wiring 121g via the contact 169 and the branch 121m. The power supply potential VDD as a first reference potential is applied to the wiring 121g.

  The gate 151 of the n-channel transistor n1 is connected to the wiring 122c via the contact 161. The gate 154 of the n-channel transistor n4 is connected to the wiring 122c via the contact 172. A common control signal Vc is applied to the wiring 122c.

  The other of the source and the drain (the n-type layer 141) of the n-channel transistor n1 is connected to the wiring 123b via the contact 162, the wiring 121h, and the via 181. The data signal SA is applied to the wiring 123b.

  The other of the source and the drain (the n-type layer 146) of the n-channel transistor n1 is connected to the wiring 123c via the contact 171, the wiring 121i, and the via 182. The data signal bSA is applied to the wiring 123c.

Next, the operation of the semiconductor memory device according to the embodiment will be described.
As shown in FIG. 17B, in the initial state, the control signal Vc and the data signal SA are both “L”. Therefore, the n-channel transistors n1 and n4 are off. From this state, for the data latch circuit 118 that holds data, the control signal Vc is set to “H” to turn on the n-channel transistors n1 and n4. Then, the sense amplifier 15 outputs the data signals SA and bSA to the data latch circuit 118. The data holding method by the n-channel transistors n2 and n3 and the p-channel transistors p2 and p4 is the same as in the third embodiment.
According to this embodiment, the same effect as that of the third embodiment can be obtained.

  According to the embodiment described above, a data latch circuit and a semiconductor memory device that can be reduced in size can be realized.

  Although some embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalents thereof.

1, 2, 3, 4: semiconductor memory device 10: control circuit board 11: silicon substrate 12: interlayer insulating film 13: sense amplifier area 14: sense amplifier circuit 15: sense amplifier 16, 16a, 16b, 16c: data latch circuit 18: data latch circuit 21: n-well 22, 22a, 22b: p-well 23: STI
31 to 36, 31a, 31b, 32a, 32b: p-type layer 41 to 45, 41a, 41c, 42a, 42c: n-type layer 51 to 56: gate 61 to 73: contact 76, 77, 78, 79: wiring 80 : Memory array substrate 81: silicon substrate 82: interlayer insulating film 83: source line 85: laminated body 86: insulating film 87: electrode film 90: core member 91: silicon pillar 92: tunnel insulating film 93: charge storage film 94: block Insulating film 96: Plug 97: Bit line 111-114: Semiconductor area (active area)
116: data latch circuit 118: data latch circuit 121: first wiring layer 121a, 121b, 121c: wiring 121d: trunk 121e, 121f: branch 121g, 121h, 121i: wiring 121j: trunk 121m, 121n: branch 122: Second wiring layers 122a, 122b, 122c: wiring 122d: trunks 122e, 122f: branches 123: third wiring layers 123a, 123b, 123c, 123d: wirings 131 to 134: p-type layers 141 to 146: n-type layers 151 154: gates 161 to 172: contacts 181 and 182: vias GND: ground potentials N1, N2: connection points n1 to n4: n-channel transistors p1 to p4: p-channel transistors SA, bSA: data signals VDD: power supply potential Vc, Vc1, Vc2: control signal Vs1, Vs2: selection signal

Claims (26)

A first n-channel transistor;
A first p-channel transistor;
With
A data latch circuit wherein a gate of the first n-channel transistor and a gate of the first p-channel transistor are common.   2. The data latch circuit according to claim 1, wherein said first n-channel transistor is a driver, and said first p-channel transistor is a load.   3. The data latch circuit according to claim 1, wherein said gate has a crank shape. A second n-channel transistor;
A third n-channel transistor;
A fourth n-channel transistor;
A second p-channel transistor;
Further comprising
A gate of the second n-channel transistor and a gate of the second p-channel transistor are common;
One of a source and a drain of the third n-channel transistor is a gate of the second n-channel transistor, a gate of the second p-channel transistor, and a source of the first n-channel transistor. -One of the drain and one of the source and the drain of the first p-channel transistor is connected, and the other of the source and the drain of the third n-channel transistor is connected to a sense amplifier;
One of a source and a drain of the fourth n-channel transistor is a gate of the first n-channel transistor, a gate of the first p-channel transistor, and a source of the second n-channel transistor. -One of a drain and one of a source and a drain of the second p-channel transistor is connected, and the other of a source and a drain of the fourth n-channel transistor is connected to the sense amplifier;
A first reference potential can be applied to the other of the source and drain of the first p-channel transistor and the other of the source and drain of the second p-channel transistor;
The second reference potential is applied to the other of the source and the drain of the first n-channel transistor and the other of the source and the drain of the second n-channel transistor. 3. The data latch circuit according to 1. A sense amplifier,
A data latch circuit according to any one of claims 1 to 4,
A plurality of electrode films stacked apart from each other,
A semiconductor member penetrating the plurality of electrode films;
A charge storage member provided between the electrode film and the semiconductor member,
A source line connected to the semiconductor member;
A bit line connected between the semiconductor member and the sense amplifier;
Semiconductor storage device comprising: The sense amplifier and the data latch circuit are provided on a first substrate,
The plurality of electrode films, the semiconductor member, the charge storage member, the source line, and the bit line are provided on a second substrate,
6. The semiconductor memory device according to claim 5, wherein said first substrate and said second substrate are bonded to each other. A first sense amplifier circuit;
A second sense amplifier circuit;
With
The first sense amplifier circuit and the second sense amplifier circuit each include a data latch circuit including an n-channel transistor,
A semiconductor memory device wherein a gate of the n-channel transistor of the first sense amplifier circuit and a gate of the n-channel transistor of the second sense amplifier circuit are common.   8. The semiconductor memory device according to claim 7, wherein said n-channel transistor of said first sense amplifier circuit and said n-channel transistor of said second sense amplifier circuit are transfer gates. A plurality of electrode films stacked apart from each other,
A semiconductor member penetrating the plurality of electrode films;
A charge storage member provided between the electrode film and the semiconductor member,
A source line connected to the semiconductor member;
A bit line connecting the semiconductor member to the first sense amplifier circuit and the second sense amplifier circuit;
The semiconductor memory device according to claim 7, further comprising: The first sense amplifier circuit and the second sense amplifier circuit are formed on a first substrate,
The plurality of electrode films, the semiconductor member, the charge storage member, the source line, and the bit line are formed on a second substrate,
10. The semiconductor memory device according to claim 9, wherein said first substrate and said second substrate are bonded to each other. A first semiconductor substrate;
An n-well provided on the first semiconductor substrate;
A p-well provided on the first semiconductor substrate and arranged adjacent to the n-well in a first direction;
First to sixth p-type layers provided on the n-well and arranged in a second direction intersecting the first direction;
First to fifth n-type layers provided on the p-well and arranged along the second direction;
A first gate provided immediately above a portion of the n-well between the first p-type layer and the second p-type layer;
A second gate provided immediately above a portion of the p-well between the first n-type layer and the second n-type layer;
A region immediately above a portion between the second p-type layer and the third p-type layer in the n-well, and the second n-type layer and the third n-type layer in the p-well. A third gate provided immediately above the portion between
A region immediately above a portion between the fourth p-type layer and the fifth p-type layer in the n-well, and the third n-type layer and the fourth n-type layer in the p-well. A fourth gate provided immediately above the portion between
A fifth gate provided immediately above a portion of the n-well between the fifth p-type layer and the sixth p-type layer;
A sixth gate provided immediately above a portion of the p-well between the fourth n-type layer and the fifth n-type layer;
A data latch circuit comprising:   12. The data latch circuit according to claim 11, wherein the shape of the third gate and the shape of the fourth gate are a crank shape.   13. The data latch circuit according to claim 11, further comprising an insulating layer provided between said third p-type layer and said fourth p-type layer. A first contact having a lower end connected to the third p-type layer;
A second contact having a lower end connected to the second n-type layer;
A third contact having a lower end connected to the fourth gate;
A fourth contact having a lower end connected to the third gate;
A fifth contact having a lower end connected to the fourth n-type layer;
A sixth contact having a lower end connected to the fourth p-type layer;
Further comprising
14. The data according to claim 11, wherein the first contact and the sixth contact are arranged in the second direction, and the second contact and the fifth contact are arranged in the second direction. Latch circuit. A plurality of data latch circuits according to any one of claims 11 to 14,
A sense amplifier,
A seventh contact to which a first reference potential is applied;
An eighth contact to which a second reference potential is applied and which is connected to the third n-type layer;
A ninth contact connected to the sense amplifier;
With
The plurality of data latch circuits are arranged in a matrix along the first direction and the second direction.
The data latch circuits adjacent in the first direction have layouts that are mirror images of each other,
The data latch circuits arranged in a line along the second direction have the same layout,
The first gate is common and the fifth gate is common between the data latch circuits adjacent in the first direction. The second gate is common between the data latch circuits adjacent in the first direction. Are common, and the sixth gate is common,
The first p-type layer and the sixth p-type layer are continuous between the data latches adjacent to each other in the second direction, are connected to the seventh contact, and are connected to the first n-type layer. The semiconductor memory device, wherein the shape layer and the fifth n-type layer are continuous and connected to the ninth contact. A second semiconductor substrate bonded to the first semiconductor substrate;
A source line provided on the second semiconductor substrate;
A plurality of electrode films provided on the source line and stacked apart from each other;
A semiconductor member that penetrates the plurality of electrode films and is connected to the source line;
A charge storage member provided between the electrode film and the semiconductor member,
A bit line provided on the plurality of electrode films and connected to the semiconductor member;
Further comprising
16. The semiconductor memory device according to claim 15, wherein said bit line is connectable to said sense amplifier. A first semiconductor substrate;
A first p-well provided on the first semiconductor substrate;
A second p-well provided on the first semiconductor substrate and separated from the first p-well in a first direction;
An n-well provided on the first semiconductor substrate and disposed between the first p-well and the second p-well;
First to third n-type layers provided on the first p-well and arranged along a second direction intersecting the first direction;
Fourth to sixth n-type layers provided on the second p-well and arranged along the second direction;
First and second p-type layers provided on the n-well and arranged in the second direction;
Third and fourth p-type layers provided on the n-well and arranged along the second direction;
A first gate provided immediately above a portion of the first p-well between the first n-type layer and the second n-type layer;
A region immediately above a portion between the second n-type layer and the third n-type layer in the first p-well, and the first p-type layer and the second p-type in the n-well. A second gate provided in a region immediately above a portion between the first and second layers,
A region immediately above a portion between the third p-type layer and the fourth p-type layer in the n-well, and the fourth n-type layer and the fifth n-type in the second p-well. A third gate provided in a region directly above a portion between the gate and the shape layer;
A fourth gate provided immediately above a portion of the second p-well between the fifth n-type layer and the sixth n-type layer;
A data latch circuit comprising:   The first n-type layer, a portion of the first p-well between the first n-type layer and the second n-type layer, the second n-type layer, the first p-well , A portion between the second n-type layer and the third n-type layer, a first semiconductor region including the third n-type layer, the first p-type layer, and the n-well And a portion between the first p-type layer and the second p-type layer, and a second semiconductor region including the second p-type layer, the third p-type layer, and the n-well. A portion between the third p-type layer and the fourth p-type layer, a third semiconductor region including the fourth p-type layer, and the fourth n-type layer; A portion between the fourth n-type layer and the fifth n-type layer in the second p-well, the fifth n-type layer, the fifth n-type layer in the second p-well, Sixth n Portion between the layers, and the sixth fourth semiconductor region data latch circuit according to claim 17, wherein further comprising an insulating layer provided therebetween, including n-type layer of. The second semiconductor region is disposed between the first semiconductor region and the third semiconductor region;
The second gate is connected to the fourth p-type layer and the fifth n-type layer;
19. The data latch circuit according to claim 18, wherein said third gate is connected to said second n-type layer and said first p-type layer.   20. The data latch circuit according to claim 17, wherein the shape of the second gate and the shape of the third gate are strips extending in the first direction.   21. The data latch circuit according to claim 17, wherein said first n-type layer is connected to said sixth n-type layer.   21. The data latch circuit according to claim 17, wherein the second p-type layer is connected to the third p-type layer. A plurality of data latch circuits according to any one of claims 17 to 22,
A sense amplifier,
With
The plurality of data latch circuits are arranged in a matrix along the first direction and the second direction.
The first p-well, the n-well, the second p-well, the first semiconductor region, and the fourth semiconductor region extend in the second direction;
The data latch circuits adjacent in the first direction have layouts that are mirror images of each other,
The layout of the data latch circuits adjacent to each other along the second direction is a mirror image of each other,
The first gate is common between the data latch circuits adjacent in the first direction;
The fourth gate is common between the data latch circuits adjacent in the first direction,
Between the data latches adjacent in the second direction, the first n-type layer is common, the fourth n-type layer is common, and the third p-type layer is common,
A semiconductor memory in which the third n-type layer is common, the sixth n-type layer is common, and the second p-type layer is common between the data latches adjacent in the second direction. apparatus. A first reference potential is applied to the second p-type layer and the third p-type layer;
A second reference potential lower than the first reference potential is applied to the third n-type layer and the fourth n-type layer;
24. The semiconductor memory device according to claim 23, wherein said first n-type layer and said sixth n-type layer are connected to said sense amplifier. Source lines,
A plurality of electrode films provided on the source line and stacked apart from each other;
A semiconductor member that penetrates the plurality of electrode films and is connected to the source line;
A charge storage member provided between the electrode film and the semiconductor member,
A bit line provided on the plurality of electrode films and connected to the semiconductor member;
Further comprising
25. The semiconductor memory device according to claim 23, wherein said bit line is connectable to said sense amplifier. A second semiconductor substrate bonded to the first semiconductor substrate;
26. The semiconductor memory device according to claim 25, wherein the source line, the plurality of electrode films, the semiconductor member, the charge storage member, and the bit line are provided on the second semiconductor substrate.

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