JP2021077787A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device capable of reducing both on-resistance and short-circuit current. A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate is provided between a current diffusion region having a first conductive type and a bottom surface of a gate trench and a second main surface, and has an electric field relaxation region having a second conductive type. The current diffusion region is in contact with the side surface of the gate trench, sandwiches the first region between the first region containing the first conductive type impurities at the first effective concentration and the side surface, and is the first conductive region at the second effective concentration. It has a second region containing impurities of the type, and the first effective concentration is lower than the second effective concentration. When viewed in a plan view from a direction perpendicular to the first main surface, the electric field relaxation region has a side end surface on the side away from the gate trench from the first position where the current diffusion region, the body region, and the side surface are in contact with each other. The boundary surface between the first region and the second region is located between the first position and the side end surface. [Selection diagram] Fig. 1

Description

The present disclosure relates to silicon carbide semiconductor devices.

As one of the silicon carbide semiconductor devices, a trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which a field shield region is provided below a gate trench and a current diffusion layer is provided between a base region and a drift region is disclosed. (For example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2001-267570

In the conventional silicon carbide semiconductor device provided with the current diffusion layer, the on-resistance and the short-circuit current have a trade-off relationship. That is, if the on-resistance is lowered, the short-circuit current becomes large, and if the short-circuit current is reduced, the on-resistance becomes high.

Therefore, it is an object of the present disclosure to provide a silicon carbide semiconductor device capable of reducing both on-resistance and short-circuit current.

According to one aspect of the present embodiment, the silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate is provided on a drift region having a first conductive type, a current diffusion region having the first conductive type, and a current diffusion region having the first conductive type, and is provided on the current diffusion region. It has a body region having a second conductive type different from the above, and a source region provided on the body region so as to be separated from the current diffusion region and having the first conductive type. The first main surface is provided with a gate trench defined by a side surface that penetrates the source region, the body region, and the current diffusion region to reach the drift region, and a bottom surface that is connected to the side surface. It further has a gate insulating film in contact with the side surface and the bottom surface, and the silicon carbide substrate is provided between the bottom surface and the second main surface, and further has an electric field relaxation region having the second conductive type. The current diffusion region is in contact with the side surface, the first region is sandwiched between the first region containing the first conductive type impurities at the first effective concentration and the side surface, and the first effective concentration is the same. It has a second region containing first conductive type impurities, and the first effective concentration is lower than the second effective concentration. When viewed in a plan view from a direction perpendicular to the first main surface, the electric field relaxation region is located on a side away from the gate trench from the first position where the current diffusion region, the body region, and the side surface are in contact with each other. It has a side end surface, and the boundary surface between the first region and the second region is located between the first position and the side end surface.

According to the present disclosure, both on-resistance and short-circuit current can be reduced.

FIG. 1 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to an embodiment. FIG. 2A is a cross-sectional view (No. 1) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2B is a cross-sectional view (No. 2) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2C is a cross-sectional view (No. 3) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2D is a cross-sectional view (No. 4) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2E is a cross-sectional view (No. 5) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2F is a cross-sectional view (No. 6) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2G is a cross-sectional view (No. 7) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2H is a cross-sectional view (No. 8) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2I is a cross-sectional view (No. 9) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2J is a cross-sectional view (No. 10) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2K is a cross-sectional view (No. 11) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2L is a cross-sectional view (No. 12) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2M is a cross-sectional view (No. 13) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2N is a cross-sectional view (No. 14) showing a method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 3A is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first reference example. FIG. 3B is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the second reference example. FIG. 4 is a diagram showing the characteristics of the embodiment, the first reference example, and the second reference example. FIG. 5 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the modified example of the embodiment.

The embodiment for carrying out will be described below.

[Explanation of Embodiments of the present disclosure]
First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are designated by the same reference numerals, and the same description is not repeated for them. In the crystallographic description in the present specification, the individual orientation is indicated by [], the aggregation orientation is indicated by <>, the individual plane is indicated by (), and the aggregation plane is indicated by {}. Negative crystallographic exponents are usually expressed by adding a "-" (bar) above the number, but in the present specification, the number is preceded by a negative sign. There is.

[1] The silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and the silicon carbide substrate is A second conductive type provided on the drift region having the first conductive type, a current diffusion region having the first conductive type, and a second conductive type provided on the current diffusion region and different from the first conductive type. A body region having the above, and a source region provided on the body region so as to be separated from the current diffusion region and having the first conductive type, and the first main surface has the source region. A gate trench defined by a side surface that penetrates the body region and the current diffusion region to reach the drift region and a bottom surface that is connected to the side surface is provided, and a gate insulating film that is in contact with the side surface and the bottom surface is provided. Further, the silicon carbide substrate is provided between the bottom surface and the second main surface, further has an electric field relaxation region having the second conductive type, and the current diffusion region is in contact with the side surface. The first region is sandwiched between the first region containing the first conductive type impurities at the first effective concentration and the side surface, and the first conductive type impurities are contained at the second effective concentration. The first effective concentration is lower than the second effective concentration, and when viewed in a plan view from a direction perpendicular to the first main surface, the electric field relaxation region is the current diffusion region. Has a side end surface on the side away from the gate trench from the first position where the body region and the side surface are in contact with each other, and the boundary surface between the first region and the second region is the first position. It is located between the side end faces.

An electric field relaxation region is provided between the bottom surface of the gate trench and the second main surface, and the electric field relaxation region is separated from the gate trench from the first position when viewed in a plan view from a direction perpendicular to the first main surface. It has a side end face on the side. Therefore, it is possible to relax the electric field concentration in the vicinity of the bottom surface and suppress the dielectric breakdown of the gate insulating film. Further, between the source electrode and the drain electrode, between the depletion layer formed by the pn junction between the body region and the current diffusion region and the depletion layer formed by the pn junction between the electric field relaxation region and the third region. Current flows through the constricted area of. Since the current diffusion region is provided, the on-resistance in the narrowed region can be reduced. Further, the first effective concentration is lower than the second effective concentration, and when viewed in a plane from a direction perpendicular to the first main surface, the boundary surface between the first region and the second region is the first position and the side end surface. It is located between and. Therefore, the short-circuit current can be reduced.

[2] In [1], the drift region is provided between the current diffusion region and the electric field relaxation region, and has a third region containing the first conductive type impurities at a third effective concentration. , The second effective concentration may be higher than the third effective concentration. Since the second effective concentration is higher than the third effective concentration, the on-resistance can be reduced more reliably.

[3] In [1], the drift region is provided between the current diffusion region and the electric field relaxation region, and has a third region containing the first conductive type impurities at a third effective concentration. The first effective concentration may be higher than the third effective concentration. Since the first effective concentration is higher than the third effective concentration, the on-resistance can be reduced more reliably.

[4] In [2] or [3], the first effective concentration is n1 (cm ^-3 ), the second effective concentration is n2 (cm ^-3 ), and the third effective concentration is n3 (cm ^-3 ). In the direction perpendicular to the second main surface, the distance between the lower end surface of the current diffusion region and the upper end surface of the electric field relaxation region is H1 (μm), and the relative permittivity of silicon carbide is ε _sic (. When F / m), the vacuum permittivity is ε ₀ (F / m), the diffusion potential of silicon carbide is V _d (V), and the amount of electric field is q (C), the relationship of the following equation (1) is as follows. It may hold. When the relationship of the equation (1) is established, stable and excellent on-resistance and short-circuit current can be obtained.

8 (ε _sic ε ₀ V _d / qH1 ² ) <n3 <n1 <n2 equation (1)

[5] In [1] to [4], the second effective concentration may be 5 times or more and 20 times or less the first effective concentration. When the second effective concentration is 5 times or more and 20 times or less the first effective concentration, stable and excellent on-resistance and short-circuit current can be obtained.

[6] In [1] to [5], the upper end surface of the electric field relaxation region may include the bottom surface of the gate trench. Since the upper end surface of the electric field relaxation region includes the bottom surface of the gate trench, more excellent withstand voltage can be obtained.

[7] In [1] to [6], the side surface of the gate trench may include a {0-33-8} surface. Since the side surface includes the {0-33-8} surface, good mobility can be obtained on the side surface of the gate trench, and the channel resistance can be reduced.

[Embodiments of the present disclosure]
The embodiments of the present disclosure relate to so-called vertical MOSFETs (silicon carbide semiconductor devices). FIG. 1 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to an embodiment.

As shown in FIG. 1, the MOSFET 100 according to the present embodiment includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier. It mainly has a metal film 84 and a passivation film 85. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are composed of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has an n-type (first conductive type). The maximum diameter of the first main surface 1 of the silicon carbide substrate 10 is, for example, 100 mm or more, preferably 150 mm or more.

The first main surface 1 is a surface on which the {0001} surface or the {0001} surface is inclined by an off angle of 8 ° or less in the off direction. Preferably, the first main surface 1 is a surface on which the (000-1) surface or the (000-1) surface is inclined by an off angle of 8 ° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1 ° or more, or 2 ° or more. The off angle may be 6 ° or less, or 4 ° or less.

The silicon carbide epitaxial layer 40 mainly has a drift region 11, a current diffusion region 14, a body region 12, a source region 13, an electric field relaxation region 16, and a contact region 18.

The drift region 11 contains an n-type impurity such as nitrogen or phosphorus (P) and has an n-type conductive type. The drift region 11 mainly has, for example, a third region 11C, a fourth region 11D, and a fifth region 11E.

The current diffusion region 14 is provided on the drift region 11. The current diffusion region 14 contains an n-type impurity such as phosphorus and has an n-type conductive type. The current diffusion region 14 mainly includes, for example, a first region 14A and a second region 14B.

The body region 12 is provided on the current diffusion region 14. The body region 12 contains a p-type impurity such as aluminum (Al) and has a p-type (second conductive type) conductive type. The effective concentration of p-type impurities in the body region 12 is 5 × 10 ¹⁷ cm ^-3 or more. The short-channel effect (punch-through) can occur when the depletion layer spreads from the pn junction region into the channel region and the entire channel region becomes a depletion layer. By increasing the effective concentration of p-type impurities in the body region 12, the spread of the depletion layer formed in the channel region can be reduced. The thickness of the body region 12 may be smaller than, for example, 0.7 μm. The effective concentration of p-type impurities in the body region 12 is, for example, about ^{1 × 10 18} cm ^-3.

The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 contains an n-type impurity such as nitrogen or phosphorus and has an n-type conductive type. The source region 13 constitutes the first main surface 1. The effective concentration of n-type impurities in the source region 13 may be higher than the effective concentration of p-type impurities in the body region 12. The effective concentration of n-type impurities in the source region 13 is, for example, about ^{1 × 10 19} cm ^-3.

The contact region 18 contains a p-type impurity such as aluminum and has a p-type conductive type. The effective concentration of p-type impurities in the contact region 18 is higher than, for example, the effective concentration of p-type impurities in the body region 12. The contact region 18 penetrates the source region 13 and contacts the body region 12. The contact area 18 constitutes the first main surface 1. The effective concentration of the p-type impurity in the contact region 18 is, for example, 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less.

The first main surface 1 is provided with a gate trench 5 defined by a side surface 3 and a bottom surface 4. The side surface 3 penetrates the source region 13, the body region 12, the current diffusion region 14, and the drift region 11 to reach the electric field relaxation region 16. The bottom surface 4 is connected to the side surface 3. The bottom surface 4 is located in the electric field relaxation region 16. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle θ1 of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 45 ° or more and 65 ° or less. The angle θ1 may be, for example, 50 ° or more. The angle θ1 may be, for example, 60 ° or less. The side surface 3 preferably has a {0-33-8} surface. The {0-33-8} plane is a crystal plane from which excellent mobility can be obtained. The gate trench 5 extends in a striped manner along a direction parallel to, for example, the first main surface 1. The gate trench 5 may extend in a honeycomb shape or may be scattered in an island shape.

The electric field relaxation region 16 contains a p-type impurity such as Al and has a p-type conductive type. The electric field relaxation region 16 is located between the bottom surface 4 of the gate trench 5 and the second main surface 2. The upper end surface of the electric field relaxation region 16 includes, for example, the bottom surface 4 of the gate trench 5. A part of the upper end surface of the electric field relaxation region 16 faces a part of the lower end surface of the current diffusion region 14. The electric field relaxation region 16 may be electrically connected to the source electrode 60. The effective concentration p1 of the p-type impurity in the electric field relaxation region 16 is, for example, 5 × 10 ¹⁷ cm ^-3 or more and 5 × 10 ¹⁸ cm ^-3 or less.

The third region 11C of the drift region 11 is sandwiched between the current diffusion region 14 and the electric field relaxation region 16. The third region 11C is in contact with each of the current diffusion region 14 and the electric field relaxation region 16. The third region 11C is on the second main surface 2 side of the current diffusion region 14. The third region 11C is on the first main surface 1 side of the electric field relaxation region 16. The third effective concentration n3 of the n-type impurity in the third region 11C is, for example, 5 × 10 ¹⁵ cm ^-3 or more and 5 × 10 ¹⁶ cm ^-3 or less.

The fourth region 11D is on the second main surface 2 side of the third region 11C. The fourth region 11D is connected to the third region 11C. The fourth region 11D is in contact with the electric field relaxation region 16 in a direction parallel to the second main surface 2. The fourth region 11D and the electric field relaxation region 16 may be located on the same plane parallel to the second main surface 2. The effective concentration of the n-type impurity in the fourth region 11D may be higher than the third effective concentration n3. The effective concentration of the n-type impurity in the fourth region 11D is, for example, 5 × 10 ¹⁶ cm ^-3 or more and 5 × 10 ¹⁷ cm ^-3 or less.

The fifth region 11E is on the second main surface 2 side of the fourth region 11D. The fifth region 11E is connected to the fourth region 11D. The fifth region 11E is in contact with the electric field relaxation region 16. The fifth region 11E is on the second main surface 2 side of the electric field relaxation region 16. The fifth region 11E may be sandwiched between the fourth region 11D and the silicon carbide single crystal substrate 50. The fifth region 11E may be connected to the silicon carbide single crystal substrate 50. The effective concentration of the n-type impurity in the fifth region 11E may be lower than the effective concentration of the n-type impurity in the fourth region 11D. The effective concentration of the n-type impurity in the fifth region 11E is, for example, 5 × 10 ¹⁵ cm ^-3 or more and 5 × 10 ¹⁶ cm ^-3 or less.

The first region 14A of the current diffusion region 14 is sandwiched between the body region 12 and the third region 11C in a direction perpendicular to the second main surface 2. The first region 14A is in contact with each of the body region 12 and the third region 11C. The first region 14A is on the second main surface 2 side with respect to the body region 12. The first region 14A is on the first main surface 1 side with respect to the third region 11C. The first region 14A is also in contact with the side surface 3. The first effective concentration n1 of the n-type impurity in the first region 14A is, for example, 5 × 10 ¹⁵ cm ^-3 or more and 5 × 10 ¹⁶ cm ^-3 or less. The first effective concentration n1 may be higher than the third effective concentration n3 and may be equal to the third effective concentration n3.

The second region 14B sandwiches the first region 14A with the side surface 3. That is, the first region 14A is sandwiched between the side surface 3 and the second region 14B in a direction parallel to the first main surface 1. The second region 14B is on the side away from the gate trench 5 with respect to the first region 14A. The second region 14B is in contact with each of the body region 12, the third region 11C and the first region 14A. The second region 14B is on the second main surface 2 side with respect to the body region 12. The second region 14B is on the first main surface 1 side with respect to the third region 11C. The second effective concentration n2 of the n-type impurity in the second region 14B is, for example, 5 × 10 ¹⁶ cm ^-3 or more and 5 × 10 ¹⁷ cm ^-3 or less. The first effective concentration n1 is lower than the second effective concentration n2. Further, the second effective concentration n2 may be higher than the third effective concentration n3.

As shown in FIG. 1, the electric field relaxation region 16 is viewed from the first position 91 where the current diffusion region 14, the body region 12, and the side surface 3 are in contact with each other when viewed in a plan view from a direction perpendicular to the first main surface 1. Also has a side end face 92 on the side away from the gate trench 5. Further, when viewed in a plane from a direction perpendicular to the first main surface 1, the boundary surface 93 between the first region 14A and the second region 14B is located between the first position 91 and the side end surface 92. From another point of view, when viewed in a plan view from the direction perpendicular to the first main surface 1, the boundary surface 93 is located on the side separated from the gate trench 5 from the first position 91, and the side end surface 92 is It is located on the side away from the gate trench 5 with respect to the boundary surface 93. For example, when viewed in a plan view from a direction perpendicular to the first main surface 1, the distance W1 between the two first positions 91 on the two side surfaces 3 is smaller than the distance W2 between the two boundary surfaces 93. The distance W2 may be smaller than the width W3 between the two side end faces 92. The first position A is a contact point between the boundary surface 54 between the body region 12 and the current diffusion region 14 and the side surface 3 of the gate trench 5.

The distance H1 (μm) between the lower end surface of the current diffusion region 14 and the upper end surface of the electric field relaxation region 16 in the direction perpendicular to the second main surface 2 satisfies the relationship represented by the equation (1). Is preferable. By satisfying this relationship, stable and excellent on-resistance and short-circuit current can be obtained. Here, ε _sic is the relative permittivity (F / m) of silicon carbide, ε ₀ is the vacuum permittivity (F / m), V _d is the diffusion potential (V) of silicon carbide, and q is. It is an elementary charge (C).

8 (ε _sic ε ₀ V _d / qH1 ² ) <n3 <n1 <n2 equation (1)

The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the electric field relaxation region 16 on the bottom surface 4. The gate insulating film 81 is in contact with each of the source region 13, the body region 12, the first region 14A, and the third region 11C on the side surface 3. The gate insulating film 81 may be in contact with the source region 13 on the first main surface 1.

The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of polysilicon (polySi) containing, for example, conductive impurities. The gate electrode 82 is arranged inside the gate trench 5. A part of the gate electrode 82 may be arranged on the first main surface 1.

The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

The barrier metal film 84 covers the upper surface and the side surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. The barrier metal film 84 is in contact with each of the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 may be in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), Al, and Si. The contact electrode 61 is ohmic contacted with the source region 13. The contact electrode 61 may be ohmic-bonded to the contact region 18. The source wiring 62 covers the upper surface and the side surface of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with each of the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of, for example, a material containing Al.

The passivation film 85 covers the upper surface of the source wiring 62. The passivation film 85 is in contact with the source wiring 62. The passivation film 85 is made of a material containing, for example, polyimide.

The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of, for example, a material containing NiSi. The drain electrode 70 may be made of a material containing Ti, Al, and Si. The drain electrode 70 is ohmic-bonded to the silicon carbide single crystal substrate 50.

The upper end surface of the electric field relaxation region 16 may be separated from the bottom surface 4 in the direction perpendicular to the second main surface 2. In this case, for example, the bottom surface 4 may be located in the drift region 11, and the side surface 3 may penetrate the source region 13, the body region 12, and the current diffusion region 14 to reach the drift region 11. For example, there may be a third region 11C between the upper end surface of the electric field relaxation region 16 and the bottom surface 4.

A buffer layer containing an n-type impurity such as nitrogen and having an n-type conductive type may be provided between the silicon carbide single crystal substrate 50 and the fifth region 11E. The effective concentration of the n-type impurities in the buffer layer may be higher than the effective concentration of the n-type impurities in the fifth region 11E.

Next, a method of manufacturing the MOSFET 100 according to the embodiment will be described. 2A to 2N are cross-sectional views showing a method of manufacturing the MOSFET 100 according to the embodiment.

First, as shown in FIG. 2A, a step of preparing the silicon carbide single crystal substrate 50 is carried out. For example, a silicon carbide single crystal substrate 50 is prepared by slicing a silicon carbide ingot (not shown) produced by a sublimation method. A buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50. The buffer layer uses, for example _{, a mixed gas of silane (SiH 4} ) and propane (C ₃ H ₈ ) as a raw material gas, and chemical vapor deposition (CVD) using, for example, hydrogen (H _{2) as a carrier gas.} ) Can be formed by the method. During the epitaxial growth of the buffer layer, n-type impurities such as nitrogen may be introduced into the buffer layer.

Next, as also shown in FIG. 2A, a step of forming the first epitaxial layer 21 is carried out. For example, the first epitaxial layer 21 is formed on the silicon carbide single crystal substrate 50 by a CVD method using a mixed gas of silane and propane as a raw material gas and hydrogen as a carrier gas, for example. During epitaxial growth, n-type impurities such as nitrogen are introduced into the first epitaxial layer 21. The first epitaxial layer 21 has an n-type conductive type. The effective concentration of the n-type impurities in the first epitaxial layer 21 may be lower than the effective concentration of the n-type impurities in the buffer layer.

Next, as shown in FIG. 2B, a step of forming the electric field relaxation region 16 is performed. For example, a mask layer (not shown) having an opening is formed on the region where the electric field relaxation region 16 is formed. Next, p-type impurity ions that can impart p-type, such as aluminum ions, are injected into the first epitaxial layer 21. As a result, the electric field relaxation region 16 is formed.

Next, as shown in FIG. 2C, a step of forming the fourth region 11D is performed. For example, a mask layer (not shown) having an opening is formed on a region where the fourth region 11D is formed, that is, a region on the side of the electric field relaxation region 16 in a direction parallel to the second main surface 2. Next, an n-type impurity ion capable of imparting an n-type such as nitrogen is injected into the first epitaxial layer 21. As a result, the fourth region 11D is formed. Of the first epitaxial layer 21, a portion of the silicon carbide single crystal substrate 50 side of the electric field relaxation region 16 and a portion of the silicon carbide single crystal substrate 50 side of the fourth region 11D are the fifth region 11E. The effective concentration of the n-type impurity in the fourth region 11D is higher than the effective concentration of the n-type impurity in the fifth region 11E.

Next, as shown in FIG. 2D, a step of forming the second epitaxial layer 22 is carried out. For example, the second epitaxial layer 22 is formed on the first epitaxial layer 21 by a CVD method using a mixed gas of silane and propane as a raw material gas and, for example, hydrogen as a carrier gas. During epitaxial growth, n-type impurities such as nitrogen are introduced into the second epitaxial layer 22. The second epitaxial layer 22 has an n-type conductive type. The thickness of the second epitaxial layer 22 is, for example, 0.8 μm or more and 1.2 μm or less. For example, the effective concentration of the n-type impurities in the second epitaxial layer 22 is lower than the effective concentration of the n-type impurities in the fourth region 11D.

Next, as shown in FIG. 2E, a step of forming the body region 12 is performed. For example, p-type impurity ions that can impart p-type such as aluminum ions are injected into the entire surface of the second epitaxial layer 22. As a result, the body region 12 is formed.

Next, as also shown in FIG. 2E, a step of forming the source region 13 is performed. For example, an n-type impurity ion capable of imparting an n-type such as phosphorus is injected into the entire surface of the second epitaxial layer 22. As a result, the source region 13 is formed.

Next, as shown in FIG. 2F, a step of forming the current diffusion region 14 is performed. For example, an n-type impurity ion capable of imparting an n-type such as phosphorus is injected deeper than the body region 12 into the entire surface of the second epitaxial layer 22. Next, a mask layer (not shown) having an opening is formed on the region where the second region 14B is formed. Next, an n-type impurity ion capable of imparting an n-type such as phosphorus is injected deeper than the body region 12 into the second epitaxial layer 22. As a result, the second region 14B is formed. Of the regions in which the n-type impurity ions are injected deeper than the body region 12, the remainder of the second region 14B becomes the first region 14A. The first region 14A and the second region 14B are formed so as to be in contact with the body region 12.

Of the second epitaxial layer 22, the portion closer to the first epitaxial layer 21 than the current diffusion region 14 becomes the third region 11C. For example, the third effective concentration n3 of the n-type impurity in the third region 11C is lower than the effective concentration of the n-type impurity in the fourth region 11D.

Next, as shown in FIG. 2G, a step of forming the contact region 18 is performed. For example, a mask layer (not shown) having an opening is formed on the region where the contact region 18 is formed. Next, p-type impurity ions that can impart p-type, such as aluminum ions, are injected into the source region 13 and the body region 12. As a result, the contact region 18 in contact with the body region 12 is formed.

Next, activation annealing is performed to activate the impurity ions injected into the silicon carbide substrate 10. The temperature of activation annealing is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activated annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

Next, as shown in FIG. 2H, a step of forming the gate trench 5 is carried out. For example, a mask layer (not shown) having an opening at a position where the gate trench 5 is formed is formed on the first main surface 1 composed of the source region 13 and the contact region 18. Using the mask layer, a part of the source region 13, a part of the body region 12, a part of the current diffusion region 14, and a part of the drift region 11 are removed by etching. As the etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching can be used. Specifically, for example _{, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF 6} ) or _{a mixed gas of SF 6} and oxygen (O ₂ ) as the reaction gas can be used. A side portion substantially perpendicular to the first main surface 1 and a bottom portion provided continuously with the side portion and substantially parallel to the first main surface 1 in the region where the gate trench 5 should be formed by etching. A recess (not shown) is formed.

Next, thermal etching is performed in the recess. Thermal etching can be performed by heating with the mask layer formed on the first main surface 1, for example, in an atmosphere containing a reactive gas having at least one kind of halogen atom. At least one or more halogen atoms contain at least one of a chlorine (Cl) atom and a fluorine (F) atom. The atmosphere contains, for example, chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), SF ₆ or carbon tetrafluoride (CF ₄ ). For example, a mixed gas of chlorine gas and oxygen gas is used as a reaction gas, and the heat treatment temperature is set to, for example, 800 ° C. or higher and 900 ° C. or lower, and thermal etching is performed. The reaction gas may contain a carrier gas in addition to the chlorine gas and oxygen gas described above. As the carrier gas, for example, nitrogen gas, argon gas, helium gas, or the like can be used.

By the above thermal etching, a gate trench 5 is formed on the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is composed of a source region 13, a body region 12, a current diffusion region 14, and a drift region 11. The bottom surface 4 is composed of an electric field relaxation region 16. The angle θ1 between the side surface 3 and the plane including the bottom surface 4 is, for example, 45 ° or more and 65 ° or less. Next, the mask layer is removed from the first main surface 1.

Next, as shown in FIG. 2I, a step of forming the gate insulating film 81 is performed. For example, by thermally oxidizing the silicon carbide substrate 10, the gate insulating film 81 in contact with the source region 13, the body region 12, the current diffusion region 14, the drift region 11, the electric field relaxation region 16, and the contact region 18 is formed. It is formed. Specifically, the silicon carbide substrate 10 is heated in an atmosphere containing oxygen, for example, at a temperature of 1300 ° C. or higher and 1400 ° C. or lower. As a result, the first main surface 1 and the gate insulating film 81 in contact with the side surface 3 and the bottom surface 4 are formed.

Next, heat treatment (NO annealing) may be performed on the silicon carbide substrate 10 in a nitric oxide (NO) gas atmosphere. In NO annealing, the silicon carbide substrate 10 is held for about 1 hour under the conditions of, for example, 1100 ° C. or higher and 1400 ° C. or lower. As a result, nitrogen atoms are introduced into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of the interface state in the interface region is suppressed, so that the channel mobility can be improved.

After NO annealing, Ar annealing using argon (Ar) as the atmosphere gas may be performed. The heating temperature of Ar annealing is, for example, higher than the heating temperature of NO annealing. The Ar annealing time is, for example, about 1 hour. As a result, the formation of an interface state in the interface region between the gate insulating film 81 and the body region 12 is further suppressed. As the atmosphere gas, another inert gas such as nitrogen gas may be used instead of Ar gas.

Next, as shown in FIG. 2J, a step of forming the gate electrode 82 is carried out. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a reduced pressure CVD (Low Pressure-Chemical Vapor Deposition: LP-CVD) method. The gate electrode 82 is formed so as to face each of the source region 13, the body region 12, the current diffusion region 14, and the drift region 11.

Next, as shown in FIG. 2K, a step of forming the interlayer insulating film 83 is carried out. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and contact the gate insulating film 81. The interlayer insulating film 83 is formed by, for example, a CVD method. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

Next, as shown in FIG. 2L, a step of forming the barrier metal film 84, the contact electrode 61, and the drain electrode 70 is performed. For example, by etching so that an opening is formed in the interlayer insulating film 83 and the gate insulating film 81, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81 in the opening. To do. Next, the barrier metal film 84 that covers the upper surface and the side surface of the interlayer insulating film and the side surface of the gate insulating film 81 is formed. The barrier metal film 84 is made of, for example, a material containing TiN. The barrier metal film 84 is formed by, for example, film formation by a sputtering method and reactive ion etching (RIE). Next, a metal film (not shown) for the contact electrode 61 in contact with the source region 13 and the contact region 18 is formed on the first main surface 1. The metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is made of, for example, a material containing Ni. Next, a metal film (not shown) for the drain electrode 70 in contact with the silicon carbide single crystal substrate 50 is formed on the second main surface 2. The metal film for the drain electrode 70 is formed by, for example, a sputtering method. The metal film for the drain electrode 70 is made of, for example, a material containing Ni.

Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are held at a temperature of, for example, 900 ° C. or higher and 1100 ° C. or lower for about 5 minutes. As a result, at least a part of the metal film for the contact electrode 61 and at least a part of the metal film for the drain electrode 70 react with the silicon contained in the silicon carbide substrate 10 to silicide. As a result, the contact electrode 61 that ohmic-bonds the source region 13 and the drain electrode 70 that ohmic-bonds the silicon carbide single crystal substrate 50 are formed. The contact electrode 61 may be ohmic contacted with the contact region 18. The contact electrode 61 may be made of a material containing Ti, Al, and Si. The drain electrode 70 may be made of a material containing Ti, Al, and Si.

Next, as shown in FIG. 2M, a step of forming the source wiring 62 is performed. Specifically, the source wiring 62 that covers the contact electrode 61 and the barrier metal film 84 is formed. The source wiring 62 is formed by, for example, film formation by a sputtering method and RIE. The source wiring 62 is made of a material containing, for example, aluminum. In this way, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

Next, as shown in FIG. 2N, a step of forming the passivation film 85 is carried out. Specifically, a passivation film 85 that covers the source wiring 62 is formed. The passivation film 85 is made of a material containing, for example, polyimide. The passivation film 85 is formed by, for example, a coating method.

In this way, the MOSFET 100 according to the embodiment is completed.

Next, the action and effect of the MOSFET according to the present embodiment will be described.

In the MOSFET 100 according to the present embodiment, an electric field relaxation region 16 is provided between the bottom surface 4 and the second main surface 2, and the electric field relaxation region 16 is viewed in a plan view from a direction perpendicular to the first main surface 1. The side end surface 92 is provided on the side away from the gate trench 5 from the first position 91. Therefore, the electric field concentration in the vicinity of the bottom surface 4 can be relaxed, and the dielectric breakdown of the gate insulating film 81 can be suppressed.

Between the source electrode 60 and the drain electrode 70, the depletion layer created by the pn junction between the body region 12 and the current diffusion region 14 and the depletion created by the pn junction between the electric field relaxation region 16 and the third region 11C. Current flows through the constricted area between the layers. In the present embodiment, since the current diffusion region 14 is provided, the on-resistance in the narrowed region can be reduced. Further, the first effective concentration n1 of the n-type impurities contained in the first region 14A is lower than the second effective concentration n2 of the n-type impurities contained in the second region 14B, and is from the direction perpendicular to the first main surface 1. When viewed in a plan view, the boundary surface 93 between the first region 14A and the second region 14B is located between the first position 91 and the side end surface 92. Therefore, the short-circuit current can be reduced.

Thus, according to the present embodiment, both the on-resistance and the short-circuit current can be reduced. That is, according to the present embodiment, it is possible to reduce the on-resistance and the short-circuit current at the same time. Then, an excellent short-circuit withstand capability can be obtained by reducing the short-circuit current.

Since the second effective concentration n2 is higher than the third effective concentration n3, the on-resistance can be reduced more reliably. Further, since the first effective concentration n1 is higher than the third effective concentration n3, the on-resistance can be reduced more reliably.

The second effective concentration n2 is preferably 5 times or more and 20 times or less the first effective concentration n1. If the second effective concentration n2 is less than five times the first effective concentration n1, the second effective concentration n2 may be too high or the first effective concentration n1 may be too low. When the second effective concentration n2 is too high, it is difficult to obtain an excellent short-circuit current, and when the first effective concentration n1 is too low, it is difficult to obtain an excellent on-resistance. If the second effective concentration n2 is more than 20 times the first effective concentration n1, the second effective concentration n2 may be too low or the first effective concentration n1 may be too high. When the second effective concentration n2 is too low, it is difficult to obtain an excellent on-resistance, and when the first effective concentration n1 is too high, it is difficult to obtain an excellent short-circuit current. Therefore, the second effective concentration n2 is preferably 5 times or more and 20 times or less of the first effective concentration n1, and more preferably 10 times or more and 15 times or less of the first effective concentration n1.

Since the upper end surface of the electric field relaxation region 16 includes the bottom surface 4 of the gate trench 5, the dielectric breakdown of the gate insulating film 81 can be further suppressed, and a more excellent withstand voltage can be obtained.

Since the side surface 3 of the gate trench 5 includes the {0-33-8} surface, excellent mobility can be obtained for the channel, and the channel resistance can be reduced.

Here, the effect of the present embodiment will be further described in comparison with the reference example. FIG. 3A is a cross-sectional view showing the configuration of a MOSFET (silicon carbide semiconductor device) according to the first reference example. FIG. 3B is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the second reference example.

As shown in FIG. 3A, the MOSFET 201 according to the first reference example is different from the MOSFET 100 according to the embodiment in that the current diffusion region 14 is not provided. In the MOSFET 201, the third region 11C of the drift region 11 is sandwiched between the body region 12 and the electric field relaxation region 16. The third region 11C is in contact with each of the body region 12 and the electric field relaxation region 16. The thickness of the third region 11C of the MOSFET 201 is equal to the sum of the thickness of the third region 11C of the MOSFET 100 and the thickness of the current diffusion region 14. Other configurations are the same as the configuration of MOSFET 100.

As shown in FIG. 3B, the MOSFET 202 according to the second reference example is different from the MOSFET 100 according to the embodiment in that the current diffusion region 14 is composed of only the second region 14B. In the MOSFET 202, the second region 14B of the current diffusion region 14 is also in contact with the side surface 3. Other configurations are the same as the configuration of MOSFET 100.

FIG. 4 is a diagram showing the characteristics of the embodiment, the first reference example, and the second reference example. The horizontal axis of FIG. 4 indicates the on-resistance, and the vertical axis of FIG. 4 indicates the short-circuit current. As shown in FIG. 4, in the first reference example, the short-circuit current is about 18 A / mm, but the on-resistance is as high as about ^{4.8 mΩ · cm 2.} Further, in the second reference example, the on-resistance is ^{about 1.8 mΩ · cm 2} , but the short-circuit current is as high as about 53 A / mm. On the other hand, the on-resistance of the embodiment is ^{about 2.2 mΩ · cm 2} , and the short-circuit current is about 32 A / mm. That is, the on-resistance of the embodiment is 1/2 or less of the on-resistance of the first reference example, and the short-circuit current of the embodiment is 2/3 or less of the short-circuit current of the second reference example. As described above, according to the embodiment, both the reduction of the on-resistance and the reduction of the short-circuit current can be achieved at the same time.

The electric field relaxation region 16 may be formed after the gate trench 5 is formed. For example, after the gate trench 5 is formed, p-type impurity ions may be injected into the first epitaxial layer 21 near the bottom of the gate trench 5. Further, the current diffusion region 14 may be formed before the body region 12 is formed. For example, the first region 14A and the second region 14B may be formed by injecting n-type impurity ions into the second epitaxial layer 22 before the body region 12 is formed.

[Modification example]
Next, a modified example of the embodiment will be described. The modified example differs from the embodiment mainly in the shape of the gate trench. FIG. 5 is a cross-sectional view showing the configuration of a MOSFET (silicon carbide semiconductor device) according to a modified example of the embodiment.

As shown in FIG. 5, in the MOSFET 300 according to the modified example, the gate trench 5 is a vertical trench. That is, the angle θ1 of the side surface 3 with respect to the plane including the bottom surface 4 may be 90 °. In this case, the distance W1 between the two first positions 91 on the two side surfaces 3 is the width of the bottom surface 4 of the gate trench 5 and the opening of the gate trench 5 in the direction parallel to the second main surface 2. It is almost the same as the width. Other configurations are the same as in the embodiment.

The same effect as that of the embodiment can be obtained by such a modification.

In the above-described embodiment and reference example, the n-type is the first conductive type and the p-type is the second conductive type. However, the p-type may be the first conductive type and the n-type may be the second conductive type. Good. In the above-described embodiment and reference example, the MOSFET has been described as an example of the silicon carbide semiconductor device, but the silicon carbide semiconductor device may be, for example, an insulated gate bipolar transistor (IGBT) or the like. The effective concentration of p-type impurities and the effective concentration of n-type impurities in each of the above impurity regions are determined by, for example, the scanning capacitance microscope (SCM) method or the secondary ion mass spectrometry (SIMS) method. It can be measured by such means. The position of the interface between the p-type region and the n-type region (that is, the pn junction interface) can be specified by, for example, the SCM method or the SIMS method. The distribution of the effective concentration of multiple carriers in the current diffusion region should be specified based on the distribution of the thickness of the depletion layer generated by, for example, the pn junction between the current diffusion region and the body region, without measuring the effective concentration. Can be done. The thickness of the depletion layer can be specified by, for example, the SCM method or the SIMS method.

Although the embodiments have been described in detail above, the embodiments are not limited to the specific embodiments, and various modifications and changes can be made within the scope of the claims.

1 1st main surface 2 2nd main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift area 11C 3rd area 11D 4th area 11E 5th area 12 Body area 13 Source area 14 Current diffusion area 14A 1st area 14B 2nd region 16 Electric field relaxation region 18 Contact region 21 1st epitaxial layer 22 2nd epitaxial layer 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 54 Boundary surface 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulation Film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Passion film 91 First position 92 Side end face 93 Boundary surface 100, 201, 202, 300 Silicon carbide semiconductor device (MOSFET)
H1, W1, W2, W3 Distance θ1 Angle

Claims (7)

A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface is provided.
The silicon carbide substrate is
The drift region having the first conductive type and
A current diffusion region provided on the drift region and having the first conductive type,
A body region provided on the current diffusion region and having a second conductive type different from the first conductive type,
A source region provided on the body region so as to be separated from the current diffusion region and having the first conductive type, and a source region.
Have,
The first main surface is provided with a gate trench defined by a side surface that penetrates the source region, the body region, and the current diffusion region to reach the drift region, and a bottom surface that is connected to the side surface.
Further having a gate insulating film in contact with the side surface and the bottom surface,
The silicon carbide substrate is provided between the bottom surface and the second main surface, and further has an electric field relaxation region having the second conductive type.
The current diffusion region is
A first region that is in contact with the side surface and contains the first conductive type impurities at the first effective concentration, and
The first region is sandwiched between the side surface and the second region containing the first conductive type impurity at the second effective concentration.
Have,
The first effective concentration is lower than the second effective concentration,
When viewed in a plane from the direction perpendicular to the first main surface,
The electric field relaxation region has a side end surface on a side away from the gate trench from the first position where the current diffusion region, the body region, and the side surface are in contact with each other.
A silicon carbide semiconductor device in which the boundary surface between the first region and the second region is located between the first position and the side end surface. The drift region is provided between the current diffusion region and the electric field relaxation region, and has a third region containing the first conductive type impurities at a third effective concentration.
The silicon carbide semiconductor device according to claim 1, wherein the second effective concentration is higher than the third effective concentration. The drift region is provided between the current diffusion region and the electric field relaxation region, and has a third region containing the first conductive type impurities at a third effective concentration.
The silicon carbide semiconductor device according to claim 1, wherein the first effective concentration is higher than the third effective concentration. The first effective concentration is n1 (cm ^-3 ), the second effective concentration is n2 (cm ^-3 ), the third effective concentration is n3 (cm ^-3 ), and the direction perpendicular to the second main surface. The distance between the lower end surface of the current diffusion region and the upper end surface of the electric field relaxation region is H1 (μm), the relative permittivity of silicon carbide is ε _sic (F / m), and the vacuum permittivity is ε ₀ (. The silicon carbide semiconductor device according to claim 2 or 3, wherein the following relationship holds when F / m), the diffusion potential of silicon carbide is V _{d (V), and the amount of electric element is q (C).}
8 (ε _sic ε ₀ V _d / qH1 ² ) <n3 <n1 <n2 equation (1) The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the second effective concentration is 5 times or more and 20 times or less the first effective concentration. The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the upper end surface of the electric field relaxation region includes the bottom surface of the gate trench. The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the side surface of the gate trench includes a {0-33-8} surface.

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