JP2021528940A - Devices, methods and systems for mitigating voltage overshoot events - Google Patents

Abstract

Technology and mechanism to mitigate supply voltage overshoot with a voltage regulator (VR). In one embodiment, the VR back converter function comprises a first circuit comprising a first inductor and a first switch circuit variously coupled thereto. The second circuit of VR includes a second inductor and a second switch circuit variously coupled to it. In response to the voltage overshoot condition indication, the respective states of the first switch circuit and the second switch circuit are the first inductor, the second inductor, and various ones of the first switch circuit and the second switch circuit. It is configured to allow a conductive path for dissipating energy. In another embodiment, mitigating the voltage overshoot condition involves toggling alternately between two different configurations of the second switch circuit.

Description

The present invention generally relates to the adjustment of the supply voltage, and more specifically to the circuit for alleviating the voltage overshoot state, but is not limited thereto.

DC-DC voltage regulators are typically used to convert a DC input voltage to either a higher or lower DC output voltage. Various types of switching voltage regulators are often used in integrated circuit (IC) applications due to their small size and efficiency. A switching regulator is typically one that is rapidly opened and closed to transfer energy between an inductor (eg, a stand-alone inductor or transformer) and an input voltage source to regulate the output voltage. Including the above switches.

Next-generation IC architectures continue to tend towards better power efficiency at lower operating voltages. Unfortunately, these architectures overshoot to levels much higher than those that allow acceptable reliability and lifetime of circuit components (eg, in the range of 1.5V to 2.0V). Tends to supply voltage. As semiconductor manufacturing processes continue to enable more power density solutions, voltage overshoot events are expected to have an increased impact on IC performance.

The embodiments described herein provide a variety of techniques and mechanisms for configuring switch circuits of voltage regulators to mitigate the duration or magnitude of voltage overshoot conditions. In one embodiment, the first circuit of VR can operate to provide a back converter function for outputting a constant voltage power supply. In response to the detection of the overshoot state of the output voltage, the VR control circuit can generate a signal for configuring the respective switch states of both the first circuit and the second circuit of the VR. Such a switch state allows a conductive path to dissipate energy using the inductors of the first and second circuits respectively. In some embodiments, mitigating voltage overshoot involves the VR being alternately toggled between the two configurations to allow for each different conductive path.

In the following description, a number of details will be discussed to provide a more detailed description of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be implemented without these specific details. In other examples, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present disclosure.

Various embodiments of the present invention are shown by way of illustration in the accompanying drawings without limitation.

FIG. 5 is a hybrid circuit and functional block diagram showing elements of the device for providing voltage overshoot mitigation according to an embodiment. It is a flow diagram which shows the element of the method of mitigating the voltage overshoot according to one Embodiment. It is a timing diagram which shows various states of a circuit during relaxation of a voltage overshoot event according to one Embodiment. FIG. 5 is a hybrid circuit and functional block diagram showing elements of a packaged device for providing voltage overshoot mitigation according to an embodiment. FIG. 5 is a hybrid circuit and functional block diagram showing elements of a control circuit for facilitating voltage overshoot mitigation according to one embodiment. It is a hybrid circuit and a functional block diagram which shows the element of the control circuit for facilitating the relaxation of the voltage overshoot according to one Embodiment. FIG. 6 is a functional block diagram showing elements of a packaged device for selecting a circuit for voltage overshoot mitigation according to an embodiment. It is a functional block diagram which shows the arithmetic unit according to one Embodiment. FIG. 6 is a functional block diagram showing an exemplary computer system according to an embodiment.

In the corresponding drawings of the embodiments, the signals are represented by solid lines. Some lines can be thickened to indicate more component signal paths and / or have arrows at one or more ends to indicate the direction of the information flow. Such instructions are not intended to be limiting. Rather, lines are used in connection with one or more exemplary embodiments to facilitate understanding of the circuit or logic unit. Arbitrarily represented signals, defined by design needs or preferences, may actually include one or more signals that can travel in either direction, in any suitable type of signaling scheme. Can be implemented.

Throughout the specification and claims, the term "connected" means a direct connection between objects connected without an intermediate device, such as an electrical, mechanical or magnetic connection. The term "combined" refers to a direct electrical, mechanical, magnetic connection between connected objects, or an indirect connection via one or more passive or active intermediate devices. means. The term "circuit" or "module" refers to one or more passive and / or active components arranged to cooperate with each other to provide the desired function. The term "signal" refers to at least one current signal, voltage signal, magnetic signal or data clock signal. The meanings of "a", "an" and "the" include multiple references. The meaning of "in" includes "in" and "on".

The term "device" or "device" can generally refer to a device according to the context of its usage. For example, the device can refer to a stack of layers or structures, a single structure or layer, a connection of various structures with active and / or passive elements, and the like. In general, a device is a three-dimensional structure having a plane along the x-y direction and a height along the z direction of the x-y-z Cartesian coordinate system. The plane of the device may also be the plane of the devices that make up the device.

The term "scaling" generally means converting a design (schematic diagram and layout) from one process technique to another and then reducing the layout area. Also, the term "scaling" generally means shrinking layouts and devices within the same technology node. Also, the term "scaling" means, for example, adjusting the signal frequency for other parameters such as power level (eg, decelerating or speeding up, i.e. reducing or expanding, respectively).

The terms "substantially", "close", "nearly", "near", and "roughly" generally mean within +/- 10% of the target value. For example, unless otherwise specified in the explicit context of their use, the terms "substantially equal," "roughly equal," and "nearly equal" are among those described as such. It simply means that there are only accidental fluctuations. In the art, such fluctuations are typically less than +/- 10% of a given target value.

The terms used in this way allow the embodiments of the invention described herein to operate in a different orientation than those illustrated herein or otherwise described, for example. It should be understood that they can be exchanged under such appropriate circumstances.

The use of ordinal adjectives "first", "second", "third", etc. to describe a common object simply refers to different instances of similar objects, unless otherwise specified. It only indicates that, and does not mean that the objects so described must be in a given sequence in time, space, ranking, or otherwise.

For the purposes of this disclosure, the terms "A and / or B" and "A or B" mean (A), (B) or (A and B). For the purposes of this disclosure, the terms "A, B and / or C" are used as (A), (B), (C), (A and B), (A and C), (B and C). Or (A, B and C).

The terms "left", "right", "front", "rear", "top", "bottom", "upper", "lower" and other terms within the specification and claims are for illustration purposes. And not necessarily used to describe a permanent relative position. For example, the terms "upper", "lower", "front", "rear", "top", "bottom", "upper", "lower" and "about" as used herein are It refers to the relative position of one component, structure, or material with respect to other referenced components, structures, or materials within the device, and such physical relationships are noteworthy. These terms are used herein for explanatory purposes and primarily within the context of the device z-axis, and are therefore used in connection with device orientation. Therefore, the first material "above" the second material in the context of the figures provided herein is if the device is oriented in the opposite direction to the context of the figures provided. It can also be "below" the second material. In the context of the material, one material placed above or below the other material may be in direct contact or may have one or more intervening materials. Further, one material disposed between the two materials may be in direct contact with the two layers or may have one or more intervening layers. In contrast, the first material "attached" to the second material is in direct contact with the second material. Similar distinctions are made in component assemblies.

The term "between (and)" may be used in the context of the device's z-axis, x-axis, or y-axis. One material between the other two materials may be in contact with one or both of these other materials, or is separated from both of the other two materials by one or more intervening materials. You may. Thus, one material "between" the other two materials may be in contact with either of the other two materials, or may be bonded to the other two materials via an intervening material. good. One device between the other two devices may be directly connected to one or both of those other devices, or separated from both of the other two devices by one or more intervening devices. May be done.

As used throughout the specification and in the claims, the list of items joined by the terms "at least one" or "one or more" includes any combination of the listed terms. Can mean. For example, the term "at least one of A, B or C" can mean A, B, C, A and B, A and C, B and C, or A, B and C. It is pointed out that the elements of the figure having the same reference number (or name) as the elements of the other figures can operate or function in the same manner as those described in the other figures, but are not limited thereto. do.

In addition, the various elements of combined and ordinal logic discussed in this disclosure include physical structures (such as AND gates, OR gates, or XOR gates) and logic structures that are Boolean equivalents of the logic under discussion. It can be associated with both synthetic or otherwise optimized collections of running devices.

It is pointed out that the elements of the figure having the same reference number (or name) as the elements of the other figures can operate or function in the same manner as those described in the other figures, but are not limited thereto. do.

FIG. 1 shows each feature of the apparatus 100 for mitigating or mitigating a voltage overshoot condition according to one embodiment. The device 100 is an example of an embodiment in which the switch circuit conducive to the voltage regulator in response to an overshoot of the output voltage.
path) can be provided operation-selectively. Such conductive paths are overvoltage by allowing energy to be dissipated or otherwise transferred from one or more circuit elements used to provide a regulated output voltage. It can help alleviate or reduce the duration or size of the shoot.

As shown in FIG. 1, device 100 includes a load circuit 120 and a voltage regulator (VR) 110 coupled to supply voltage to the load circuit 120 via a node 112. For example, the circuit 130 of the VR 110 can be configured to supply a _{regulated output voltage V O} to the node 112 based on the _{input voltage V IN supplied to the VR 110.} The circuit 130 includes an inductor L1 and switch circuits S1 and S2 variously coupled to the inductor L1. In one embodiment, the switch circuit S1 is coupled between the inductor L1 and the first node. The first node causes the VR 110 to receive, for example, an input voltage V _IN. The switch circuit S2 is coupled between the inductor L1 and another node. Other nodes provide a reference potential (eg, ground voltage). In some embodiments, one or more other circuit elements (not shown) of circuit 130 may be coupled to inductor L1 using nodes 112. The inclusion of one or more other circuit elements such as capacitors, resistors, current sources, and / or similar can facilitate the buck circuit function of circuit 130.

During the normal operation of the VR 110, the control circuit 150 controls when the switch circuits S1 and S2 are selectively turned on and / or turned off. One or more control signals, such as the illustrated exemplary control signal 152, are used to control when to turn on and / or off. As used herein, the term "normal operation" refers to the stable voltage and current draw by the load circuit 120, that is, the _{case where the output voltage V O} does not overshoot. Normal operation is different from the voltage overshoot state when the load circuit 120 suddenly draws less current and _{overshoots the voltage V out.}

The regulation of the output voltage V _O by the circuit 130 may include a control circuit 150 that supplies a signal 152 that selectively turns on / off the switch circuits S1 and S2 at various times. For example, switching the current through the main inductor L1 and charging / discharging the capacitor (not shown) by the circuit 130 can facilitate the stability of the _{output voltage V O.} Such control of the switch circuits S1 and S2 by the control circuit 150 for adjusting the output voltage V _O avoids, for example, obscuring the conventional back circuit technology (specific features of various embodiments). Therefore, it can include one or more operations adapted from (not detailed herein).

To enable mitigation of voltage overshoot events, the VR110 further comprises a circuit 140 including another inductor L2 and switch circuits S3, S4 variously coupled to the inductor L2. In one embodiment, the switch circuit S3 is coupled between the inductor L2 and the first node. The first node provides, for example, an input voltage V _IN . The switch circuit S4 is coupled between the inductor L2 and a reference potential (eg, ground). Therefore, the inductors L1 and L2 can be coupled to the first node via the switch circuits S1 and S3, respectively. For example, the second node 112 is connected to the switch circuits S1 and S3 via the inductors L1 and L2, respectively. Can be combined. In one such embodiment, the inductors L1 and L2 are further coupled to the reference potential node via the switch circuits S2 and S4, respectively. Some embodiments are not limited in this regard, but the circuit 140 may further include one or more other circuit elements (not shown) coupled between the inductor L2 and the node 112.

The control circuit 150 detects a voltage overshoot condition and, in response, operates one or both of the circuits 130 and 140 to help alleviate one or both of the duration or magnitude of the voltage overshoot condition. It is possible to provide a function to do. In one embodiment, the control circuit 150 is coupled to the _{sample output voltage V O} or otherwise receives feedback based on the _{output voltage V O.} The mitigation or mitigation of voltage overshoot using circuit 140 can be based on such feedback. For example, the control circuit 150 may include or have access to a comparator circuit that makes a comparison based on a _{voltage V O} and a threshold voltage V _{TH (indicating a voltage overshoot condition).} At some point, the results of such a comparison may indicate an overshoot of the _{output voltage V O.} In response, the control circuit 150 may signal whether to selectively turn on / off the various switches of the switch circuits S1, S2, S3, S4 and / or when to turn them on / off. can. The operation of the switch circuits S3, S4 can be provided using one or more control signals such as the illustrated control signal 154.

In one embodiment, mitigation of voltage overshoot using control signals 152, 154 comprises transmitting signals to one or more configurations of circuit 130 and circuit 140 at each time point. In each such configuration, each conductive path dissipates energy from circuit 130 by conducting current between circuit 130 and circuit 140 via a node 112, or the other. It may be possible to transfer energy in this way.

For example, the first configuration can enable a conductive path 160 through each of the inductor L1, the node 112, the inductor L2 and the switch circuit S4 to a node that provides a reference potential (eg, ground). This first configuration may include an off state of the switch circuit S3 during each of the on states of the switch circuits S2 and S4. For example, the on state of the switch circuit S2 enables a return current path between the ground potential and the inductor L1. In one embodiment, such a first configuration may further include an off state of the switch circuit S1 in order to separate the _{inductor L1 from the input voltage VIN at least partially.}

Alternatively, or in addition, the second configuration can allow a conductive path 162 through each of the inductor L1, the node 112, the inductor L2 and the switch circuit S3 _{to the node providing the input voltage V IN.} .. This second configuration may include an off state of the switch circuit S4 during each of the on states of the switch circuits S2 and S3. In one embodiment, such a second configuration may further include an off state of the switch circuit S1 in order to separate the _{inductor L1 from the input voltage VIN at least partially.} In one such embodiment, the relaxation of the voltage overshoot may include a control circuit 150 that alternates between the first configuration and the second configuration described above a plurality of times. Alternating configurations between these configurations dissipate energy with the inductor L1 or otherwise transfer it (eg, dissipate energy from the capacitors in circuit 130) to facilitate the reduction of the _{output voltage V O.} Or, including communicating in other ways).

In various embodiments, the load circuit 120 operates using a regulated supply voltage, eg, various integrated circuits including one or more processor cores, memory, graphics processors, and / or the like. Including any of. Some embodiments are not limited to the particular functionality provided by the load circuit 120. The load circuit 120, the control circuit 150, or some or all of the switch circuits S1, S2, S3 and S4 may be mounted using the integrated circuit (IC) chip of the device 100. In such an integrated circuit (IC) chip, for example, the inductor L1 and / or the inductor L2 are coupled (but different) to the IC chip. For example, such an IC chip may be placed in the packaging material of device 100, and inductors L1 and / or inductor L2 are variously placed in or on the packaging material. In various alternative embodiments, the device 100 omits the load circuit 120, but should be coupled to the load circuit 120.

FIG. 2 shows the features of Method 200 for mitigating the duration or magnitude of a voltage overshoot event according to one embodiment. Method 200 may include operations performed by a circuit such as device 100. To illustrate the particular features of the various embodiments, the method 200 is described herein with reference to the circuit states shown by timing diagram 300 in FIG. However, the operation of method 200 may, in other embodiments, result in any of a variety of additional or alternative circuit conditions.

As shown in FIG. 2, method 200 includes the step of supplying a first voltage to a voltage regulator (VR) via a first node (at 210), which voltage regulators pass through switch circuits S1 and S3, respectively. The inductors L1 and L2 coupled to the first node are included. In such an embodiment, the second node is coupled to the switch circuits S1 and S3 via the inductors L1 and L2, respectively, and the inductors L1 and L2 are coupled to the third node via the switch circuits S2 and S4, respectively. Will be done. The third node provides a reference potential, such as a ground voltage. With reference to the embodiment shown by device 100, the provision at 210 _{can include providing an input voltage V IN} to the VR 110.

Method 200 can further (at 220) include the VR supplying a second voltage to the load circuit via a second node, the second voltage being based on the first voltage. Supplying the second voltage at 220 can include passing current through the inductor L1 during the off states of the switch circuits S2, S3 and S4, respectively, for at least a period of time. In one embodiment, the integrated circuit (IC) chip comprises switch circuits S1, S2, S3 and S4 and a load circuit. For example, the IC chip is in the package mold, and the inductors L1 and L2 are in or on the package mold, respectively, and are electrically coupled to the IC chip. The provision at 220 may include the VR 110 providing an output voltage V _OUT to the node 112. Next, with reference to FIG. 3, timing diagram 300 shows various circuit conditions during the voltage relaxation process according to one embodiment. The conditions shown by the timing diagram 300 may include, for example, a part of the conditions in the device 100. As shown in FIG. 3, timing diagram 300 _{shows a plot 320 over time domain 302 of the output voltage V O} (eg, the second voltage supplied at 220) supplied by VR to the load circuit.

According to one embodiment, the method 200 further includes (at 230) detecting an indication of a voltage overshoot condition. The detection at 230 can be based on sampling any of the second voltage, or various other feedback signals based on the second voltage. In one embodiment, the detection at 230 may include the control circuit 150 performing a comparison to determine if the second voltage exceeds a predetermined threshold voltage level in the overshoot state.

For example, referring again to FIG. 3, the output voltage V _O may begin to exceed a voltage level defined in advance as the threshold for the voltage overshoot condition to be relaxed (such as the exemplary level V _THH). The timing diagram 300 further controls, at a given time, one of the high or low current modes of the load circuit that receives the _{output voltage V O from the VR, or otherwise directs a signal.} shows a plot 310 of the S _L. In the illustrated exemplary embodiment, the transition of the signal S _L from the high logic state "1" to a low logic state "0" at time ta indicates the transition of the load circuit from the high current mode to a low current mode be able to. In such embodiments, the output voltage V _O may be in response to a transition at time ta of the signal S _L, it begins to rise at time tb with a certain baseline voltage V _BL. The detection at 230 indicates that the control circuit 150 or other such logic receives an indication that _{the output voltage V O} has transitioned to a past level V _{THH, eg, at the indicated exemplary time tc.} It may be included.

Method 200 further allows a conductive path between the inductor L1 and one of the first or third nodes via the second node and the inductor L2 in response to the instructions detected at 230 ( May include enabling (at 240). According to one embodiment, the enable in 240 comprises providing the on state of each of the switch circuit S2 and one of the switch circuits S3 or S4. The enable at 240 may include configuring the circuit 130 (in some embodiments, the circuit 140) such that the control circuit 150 enables one of the conductive paths 160, 162.

With reference to FIG. 3 again, timing diagram 300 further shows plots 330, 340, 350 of the _{control signals MN} , M _BN, and M _BP that (respectively) operate the switch circuits S2, S3, and S4. In response to an output voltage V _{O transition through V THH} , the switch circuit is configured to allow the conductive path to dissipate energy from one or more circuit elements using the inductor L1. You may. By way of example, but not by limitation, enabling a circuit path constitutes an on-state of switch S2 by asserting _MN , for example, for at least time 304, to reduce the level of _{output voltage V O.} Can include that. Enabling the circuit path may further include configuring the on state of _{switch S3 by asserting M BP} , or configuring the on state of _{switch S4 by asserting M BN.}

In some embodiments, responding to detection at 230 comprises transitioning between first and second configurations, where each conductive path dissipates energy at the inductor L1. Make it possible. For example, the first configuration may include an off state of the switch circuit S3 that occurs at the same time as the on state of each of the switch circuits S2 and S4. Such a first configuration can enable, for example, the conductive path 160. The second configuration may include an off state of the switch circuit S4 during each of the on states of the switch circuits S2 and S3 (eg, to enable the conductive path 162). The transition between the first configuration and the second configuration can be based, for example, on a threshold parameter indicating the longest duration of the on state of one of the switch circuits S3 and S4. Alternatively, or in addition, the transition between the first configuration and the second configuration is the minimum time between the state transition by one of the switch circuits S3 and S4 and the state transition by the other of the switch circuits S3 and S4. It may be based on the threshold parameters shown. In some embodiments, the method 200 toggles between the first configuration and the second configuration multiple times in response to detection at 230.

With reference to FIG. 3 again, the timing diagram 300 further shows both the plot 360 of the _{current IL2} through the inductor L2 and the plot 370 of the _{current IL1 through the inductor L1.} During time period 304, M _BN and M _BP includes, as passing a direct I _L2 alternately through the switch circuit S3 or switch circuit S4, it may be variously asserted different respective times. In such an embodiment, the current I _L2 may increase during the on-state period of S4, for example, the current I _L2 is directed through the switch circuit S4 towards the ground potential node and the switch circuit S3. The on state of may decrease during the other periods in which it is configured. As a result, the current I _L2 can vary between the two current levels I _2a , I _2b during the time period 304, during which the energy is supplied to one or more capacitors (and / or load circuits) of the VR. Can be dissipated from one or more capacitors). As a result, the current I _L1 can decrease from some level I _1b towards some lower level I _1a.

In some embodiments, the method 200 further comprises another operation (not shown) for transitioning the VR from one mode to another to mitigate the voltage overshoot, whereby the VR is a load circuit. Will again provide a stable second voltage. Such other actions may include detecting the post-enable state of the conductive path at 240 (referred to herein as the "voltage overshoot relaxation state"). The voltage overshoot relaxation state may include, for example, a second voltage below a predetermined threshold voltage that is the same as (or different from) the threshold voltage of the voltage overshoot state detected in 230. In one such embodiment, the voltage overshoot state includes a second voltage greater than the first voltage threshold, and the voltage overshoot relaxation state is smaller than the second voltage threshold less than the first voltage threshold. Including voltage. In response to the detection of the voltage overshoot relaxation state, the VR control circuit (eg, control circuit 150) configures the off states of the switch circuits S2, S3 and S4, respectively, and enables the on state of the switch circuit S1. can do.

With reference to FIG. 3 again, the output voltage V _O can be reduced to _{a pre-defined second level V THL} as the threshold corresponding to the relaxation of the voltage overshoot condition. In response to the output voltage V _O to drop below V _THL (for example, shown in the exemplary time td), each of the off state of the switch circuits S2, S3 and S4, using M _N, M _BN and M _BP May be configured. In such an embodiment, the on state of the switch circuit S1 may be configured to resume the normal operating mode of VR during period 306.

FIG. 4 shows the features of the packaged device 400 for providing a regulated supply voltage according to one embodiment. The packaged device 400 is an example of an embodiment in which the circuit is configured to mitigate voltage overshoot by allowing a conductive path to dissipate energy from the capacitor of the voltage regulator. The packaged device 400 may include, for example, some or all of the features of the device 100 and may perform operations such as those of the method 200.

As shown in FIG. 4, the packaged device 400 includes a load circuit 420 and a voltage regulator 410 coupled to supply voltage to the load circuit 420 via a node 412. For example, the buck converter circuit of the VR 400 (eg, the back converter circuit having the characteristics of the circuit 130) may include an inductor 432, a MOSFET transistor 434 and an NMOS transistor 436, which are supplied to the VR 410. The adjustment voltage V _O is supplied based on the input voltage V _IN. In one embodiment, the inductor 432, the transistor 434 and the transistor 436 functionally correspond to the inductor L1, the switch circuit S1 and the switch circuit S2 (each) of the apparatus 100. Such a back converter circuit can further include a resistor 438, a capacitor 460 and a current source 462 that facilitates the stability of the _{voltage V O.} However, in other embodiments, any of the various additional or alternative back converter circuit architectures can be adapted to VR 410.

To allow mitigation of voltage overshoot events at node 412, the VR may further include a boost converter circuit (eg, having the characteristics of circuit 140) including an inductor 442, a MOSFET transistor 444 and an NMOS transistor 446. .. In such an embodiment, the inductor 442, the transistor 444, and the transistor 446 functionally correspond to the inductor L2, the switch circuit S3, and the switch circuit S4 (each) of the device 100.

The control circuit of the VR 410 (eg, having the characteristics of the control circuit 150) may include a detector circuit 450 for making an evaluation of the _{voltage V O based on one or more threshold voltage levels.} For example, the detector circuit 450 describes _{a sample of voltage V O} with one or each of the threshold voltage level V _THH or the threshold voltage level V _THL (eg, with reference to timing diagram 300). They may be combined to compare. Such a control circuit of the VR410 may further include a back control circuit 452 and a boost control circuit 454, which are each of transistors 434, 436, 444, 446 based on evaluation by the detector circuit 450. Various on / off states are configured.

In one embodiment, the signal transmission by the back control circuit 452, which controls the respective states of the transistors 434 and 436, further comprises a periodic signal (exemplary periodic ramp signal V _{ramp in the} figure) and a control voltage signal V _c (! For example, _{it shows the difference between the voltage V O} and a given reference voltage). By way of example, but not by limitation, the back control circuit 452 can provide, for example, a pulse width modulation function adapted from conventional power management techniques, based on the _{signals V ramp} and V _c.

FIG. 5 shows the features of the control circuit 500 for configuring the switch circuit of the voltage regulator according to one embodiment. The control circuit 500 is an example of an embodiment in which the switch circuit is configured to dissipate energy from the back circuit in response to a voltage overshoot condition. The control circuit 500 may include, for example, some or all of the features of the control circuit 150.

As shown in FIG. 5, the control circuit 500 includes a detector circuit 510, a boost control circuit 540, a pulse width modulator circuit 520, and a combination logic 530. The functionality of the detector circuit 510 and the boost control circuit 540 may correspond to, for example, the functionality of the detector circuit 450 and the boost control circuit 454 (respectively), for example, the functionality of the back control circuit 452 is a pulse. It is provided in the width modulator circuit 520 and the combination logic 530.

VR buck converter circuit (not shown), for example, operation by the buck converter circuit having the features of the circuit 130, the switch control signals M _P generated by the pulse width modulator circuit 520 and the combinatorial logic 530, and in response to M _N can do. For example, the control signal M _P, M _N may be provided a switch S1 of the device 100, S2, or (in another embodiment) the transistors 434, 436 of the package 400 in order to control respectively. _{In one such embodiment, the control signals MP} , _MN are generated by the combination logic 530 based on one or both of the signals 522 and 524 generated by the pulse width modulator circuit 520. The pulse width modulation circuit 520 can then generate signals 522 and 524 based on _{the periodic ramp signal V ramp} and the _{control voltage signal V c indicating the difference between the voltage V O} and the predetermined reference voltage. .. The generation of signals 522, 524 has, for example, an operation adapted from conventional pulse width modulation techniques, which are not detailed herein to avoid obscuring certain features of various embodiments. It may be included.

The detector circuit 450 or 510 is any of a variety of circuits that can operate to indicate whether the _{tuned supply voltage V O output by the VR is above (or below) a certain threshold voltage level.} It may be included. In an exemplary embodiment, the first differential amplifier of the detector circuit 510 is to assert the signal in response to _{the voltage V O} exceeding the threshold level V _{THH, eg, the first differential amplifier of the detector circuit 510.} A two-differential amplifier is to assert a signal when _{the voltage V O} falls below another threshold level V _THL. In one such embodiment, the SR latches of the detector circuit 510 are variously set or reset based on their respective outputs from these differential amplifiers. For example, the SR latch may set the signal 512 to a Boolean high value (“1”) if _{the voltage V O} exceeds the level V _THH. If the voltage V _O is below the level V _THL , the signal 512 may be reset to a low Boolean value (“0”). Another signal 514 output by the SR latch can represent a Boolean logic state opposite that of signal 512.

The boost control circuit 540 may be coupled to provide the _{switch signals M BP} , M _BN based on the signals 512, 514 from the detector circuit. For example, the control signals M _BP , M _BN may be provided to control switches S3, S4 of device 100, or (in another embodiment) transistors 444, 446 of packaged device 400, respectively. In one such embodiment, _{one or both of the control signals M BP} , M _BN are generated based on, for example, a threshold timing parameter indicating the maximum permissible duration of one of the switch circuits S3 and S4 in the on state. Alternatively, or in addition to this, _{one or both of the control signals M BP} , M _BN is the minimum time required between the state transition by one of the switch circuits S3 and S4 and the state transition by the other of the switch circuits S3 and S4. It may be generated based on the threshold parameter indicating. Thus, the transition between the first configuration of the switch and the second configuration of the switch (eg, each of the configurations allowing a different one of the conductive paths 160, 162) is 1 in various embodiments. It can be based on one or both such threshold timing parameters. In other embodiments, the boost control circuit 540 may be just a pass-through circuit, a buffer, or is completely omitted from the control circuit 500 _{, for example, if the signals 512 and 514 are the switch signals M BN} and M _{BP, respectively.} Will be done.

In some embodiments, one or both of the signals 512 and 514 are fed to the combination logic 530, for example, the combination logic 530 asserts (or deasserts) a given one of _{the switch control signals MP} , _MN. (Unassert)) Selectively enable / disable the enable / disable assert / deassertion of whether to assert and / or when to assert. For example, the assertion of signal 512 (in response to the indication of a voltage overshoot event) can result in the combination logic 530 _{deasserting the switch control signal M P} and asserting the switch control signal M _N. While the switch control signal M _P is deasserted switch control signal M _N is asserted, the boost control circuit 540, the switch signal M _BP, by toggling various logic states of the M _BN, energy from the back circuit of VR A switch state can be provided that facilitates dissipation.

FIG. 6 shows some features of the control circuit 600 for configuring the switch circuit of the voltage regulator according to one embodiment. The control circuit 600 may include, for example, some or all of the features of the control circuit 150. As shown in FIG. 6, the control circuit 600 is coupled so as to receive each of the _{voltage V O} , the first threshold value V _TH, and the second threshold _{value V TH L output by the voltage regulator.} The received first threshold V _THH may be predefined as a reference level for determining whether an overshoot state of voltage V _{O exists, and the second threshold V THL} is such an overshoot state. May be predefined as a reference level to determine if is sufficiently relaxed. Some embodiments are not limited in this regard, but the thresholds V _THH and V _THL may differ from each other, for example if the threshold V _THL is less than the threshold V _THH.

In an exemplary embodiment, the first differential amplifier of the control circuit 600 _{asserts the signal 612 in response that the voltage V O} is higher than, for example, the threshold V _THH , the second difference of the control circuit 600. The dynamic amplifier is to assert the signal 614 when the _{voltage V O} is below the threshold V _THL. Based on the assertion of the signal 612, the SR latch 620 of the control circuit 600 can assert, for example, the output signal 622 functionally corresponding to the signal 512. The signal 622 may be supplied to a switch circuit (not shown) such as the switch circuit S4, or optionally, for example, a transistor 446, and the signal 622 functions as a _{control signal M BN in the plot 340.} In one such embodiment, the SR latch 620 further functions as a _{control signal M BP} in another signal (not shown) representing a Boolean logic state opposite to the logic state of signal 622, eg, in plot 350. Output other signals.

Further, the signal 622 is added to the feedback path back to the SR latch 620 to provide continuous toggling between different switch configurations, eg, to provide toggling as shown during time 304 in timing diagram 300. The feedback path can be provided and includes a delay circuit 630. In one embodiment, the delay circuit 630 provides, as the output 632, a version of the signal 622 that is delayed by some predetermined timing parameter. The timing parameter can represent the maximum permissible duration of the on state of a particular switch (eg, one of the switch circuits S3 and S4 of circuit 140). As a result, the signal 616 generated based on the output 632 and the signal 614 can reset the SR latch 620 (and thus the deassertion signal 612) after the time delay has ended. _{However, if the signal 612 continues to overshoot the voltage V O} after another period of time delay has expired, the signal 622 may be asserted again.

FIG. 7 shows the characteristics of the circuit device 700 that operates so as to mitigate the voltage overshoot by the voltage regulator according to one embodiment. The circuit device 700 may include some or all of the features of the device 100 and / or may be operated according to, for example, method 200. The circuit device 700 is an example of an embodiment in which the (re) configuration of one converter circuit is selected beyond the (re) configuration of another converter circuit to facilitate mitigation of voltage overshoot. Such a selective configuration is based on the proximity of one converter circuit to a given reference position, eg, the proximity relative to the proximity of the other converter circuit.

As shown in FIG. 7, the circuit device 700 includes a load circuit 710 and a plurality of voltage regulator circuits (exemplary VR720a, 720b, ..., 720n, etc.) coupled thereto. The VR720a, 720b, ..., 720n may be arranged along a given dimension, such as the x-dimension of the illustrated exemplary x-y coordinate system. For example, the respective output interconnects 712a, 712b, ..., 712n from VR720a, 720b, ..., 720n may be arranged in a line along the side surface of the IC chip further comprising the load circuit 710. .. Collectively, the VR720a, 720b, ..., 720n may be operated to provide a stable output voltage to the voltage supply nodes of the load circuit 710, eg, interconnects 712a, 712b, ..., 712n. Either form a voltage supply node or are each directly connected to a voltage supply node.

Two or more VR 720a, 720b, ..., 720n can each include their respective architectures with the characteristics of VR 110. For example, each of such VRs has a first circuit and a second circuit that functionally correspond to circuits 130 and 140, respectively. In FIG. 7, the circuit providing the function of the circuit 130 is represented by the symbol “Bk”, and the circuit providing the function of the circuit 140 is represented by the symbol “Bt”. In one such embodiment, the control circuit 730 is coupled to selectively operate the respective switch circuits (not shown) of the various Bt and Bk circuits. For a given one of VR720a, 720b, ..., 720n, such selective operation allows the conductive path to facilitate energy dissipation from the capacitor (eg) of the respective Bk circuit. Can make it possible.

Further, in order to further facilitate voltage overshoot mitigation, the control circuit 730 uses one of VR720a, 720b, ..., 720n for use in mitigating the voltage overshoot condition, VR720a, You can choose beyond the others of 720b, ..., 720n. Such a selection may be made based on a first distance between a given VR position and a position within the load circuit 710 of the source (actual or expected) of the voltage overshoot. Transformatively or additionally, such selection may be made based on a second distance between a given VR relative position and the position of control circuit 730. In some embodiments, one or both of these distances can be a delay source in voltage overshoot mitigation, and by selecting an alternative VR to use when dissipating energy to reduce the output voltage. It is based in part on our understanding that such delays can be avoided.

In the illustrated exemplary embodiment, the control circuit 730 includes or is otherwise connected to access to a memory resource or other logic that provides reference information 734. The reference information 734 can correspond to VR720a, 720b, ..., 720n by one or more distances, respectively. For example, the reference information 734 is deductively preliminarily used as a part of the initial configuration of the circuit device 700. Defined. For example, the reference information 734 may include a table 750 of identifiers BB1, BB2, ..., BBN, respectively, of VR720a, 720b, ..., 720n. For each of the identifiers BB1, BB2, ..., BBN, the table 750 can identify the corresponding distance value ΔXa and / or the corresponding distance value ΔXb. The distance value ΔXa may be equal to or based on the offset distance (along the x-dimensional) between the position of a given VR and the position of control circuit 730. The distance value ΔXb may be equal to or based on the offset distance (along the x-dimensional) between the position of a given VR and the position of a potential source of voltage overshoot. As used herein, the "potential source of voltage overshoot" is a transition between a relatively high load current operating mode and a relatively low load current operating mode (such a transition can contribute to voltage overshoot). ) Refers to a specific component of the load circuit 710 that can be.

In such an embodiment, the detector circuit 732 can receive a signal 736 indicating the location of the source in the actual (or alternative, expected upcoming) voltage overshoot condition. The signal 736 may be generated, for example, based on an operation adapted from any of a variety of conventional power management techniques. In response to signal 736, control circuit 730 accesses reference information 734 and sets the relative priority of one of VR720a, 720b, ..., 720n to VR720a, 720b, ..., 720n. It can be identified against one or more other priorities. Based on this priority, the control circuit 730 can generate a control signal to reconfigure the switch of the selected VR, for example according to the enablement at 240 in Method 200.

FIG. 8 shows the arithmetic unit 800 according to one embodiment. The arithmetic unit 800 accommodates the board 802. Board 802 may include a number of components, including but not limited to processor 804 and at least one communication chip 806. Processor 804 is physically and electrically coupled to board 802. In some embodiments, the at least one communication chip 806 is also physically and electrically coupled to the board 802. In a further implementation, the communication chip 806 is part of the processor 804.

Depending on its application, the arithmetic unit 800 may include other components that may or may not be physically and electrically coupled to the board 802. These other components include volatile memory (eg DRAM), non-volatile memory (eg ROM), flash memory, graphics processor (CPU), digital signal processor, crypto processor, chipset, antenna, display, touch. Screen display, touch screen controller, battery, audio codec, video codec, power amplifier (AMP), global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera and mass storage (hard disk drive, compact) Discs (CDs), digital general purpose discs (DVDs), etc.), but are not limited to these.

The communication chip 806 enables wireless communication for transferring data to and from the computer device 800. The term "radio" and its derivatives are used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through the use of modulated electromagnetic radiation through non-solid media. Can be used. The term does not mean that the associated device does not contain a wire, even though in some embodiments the associated device may not contain a wire. Communication chips 806 include Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long-term evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, Any radio standard or protocol that includes, but is not limited to, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other radio protocol designated as 3G, 4G, 5G and beyond. Can be implemented. The arithmetic unit 800 may include a plurality of communication chips 806. For example, the first communication chip 806 can be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 806 can be GPS, EDGE, GPRS, CDMA, WiMAX, LTE, It can be dedicated to longer range wireless communications such as Ev-DO and others.

The processor 804 of the arithmetic unit 800 includes an integrated circuit die packaged within the processor 804. The term "processor" is one of any devices or devices that process electronic data in order to convert electronic data from registers and / or memory into other electronic data that can be stored in registers and / or memory. Can point to a department. The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806.

In various implementations, the computer 800 includes laptops, netbooks, notebooks, ultrabooks, smartphones, tablets, personal digital assistants (PDAs), ultramobile PCs, mobile phones, desktop computers, servers, printers, It can be a scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In a further implementation, the computing device 800 may be any other electronic device that processes the data.

Some embodiments may be provided as computer program products or software, which software may include a machine-readable medium that stores instructions, which medium is a computer to perform a process according to one embodiment. It can be used to program a system (or other electronic device). Machine-readable media include any mechanism for storing or transmitting information in a form readable by a machine (eg, a computer). For example, a machine-readable (eg, computer-readable) medium is a machine (eg, computer) readable storage medium (eg, read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage medium. , Optical storage media, flash memory devices, etc.), machine (eg, computers) readable transmission media (eg, electrical, optical, acoustic, or other forms of propagation signals (eg, infrared signals, digital signals, etc.)) and the like.

FIG. 9 shows a schematic representation of a machine of exemplary form of computer system 900, wherein the machine is to perform any one or more of the methods described herein. A set of instructions can be executed. In another embodiment, the machine may be connected (eg, networked) to a local area network (LAN), an intranet, an extranet, or another machine within the Internet. This machine may operate at the capacity of a server or client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. This machine is a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, web appliance, server, network router, switch or bridge, or the action that the machine should take. It may be any machine capable of executing the specified set of instructions (sequentially or otherwise). Further, although only a single machine is illustrated, the term "machine" individually sets (or sets) instructions for performing any one or more of the methods described herein. It is interpreted to include a set of arbitrary machines (eg, computers) that run in or jointly.

An exemplary computer system 900 is a dynamic such as processor 902, main memory 904 (eg, read-only memory (ROM), flash memory, synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)" that communicate with each other via bus 930. Includes random access memory (DRAM), static memory 906 (eg, flash memory, static random access memory (SRAM), etc.), and secondary memory 918.

The processor 902 represents one or more general-purpose processing devices such as a microprocessor and a central processing unit. More specifically, the processor 902 is a complex instruction set computer (CISC) microprocessor, a reduced instruction set computer (RISC) microprocessor, an ultralong instruction word (VLIM) microprocessor, a processor that implements another instruction set, or a processor. It may be a processor that implements a combination of instruction sets. Processor 902 may also be one or more special purpose processing devices such as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), and network processors. Processor 902 is configured to execute processing logic 926 to perform the operations described herein.

The computer system 900 may further include a network interface device 908. The computer system 900 also includes a video display unit 910 (eg, a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 912 (eg, a keyboard), a cursor control device 914. (For example, a mouse) and a signal generator 916 (for example, a speaker) may be included.

The secondary memory 918 may include a machine-accessible storage medium (or, more specifically, a computer-readable storage medium) 932, on which the methods described herein or A set of instructions (eg, software 922) that embodies any one or more of the functions is stored. Software 922 may also be present entirely or at least partially inside main memory 904 and / or processor 902 while being executed by computer system 900. The main memory 904 and / or the processor 902 also constitute a machine-readable storage medium. Software 922 may also be transmitted and received over network 920 via network interface device 908.

Although machine-accessible storage medium 932 is shown as a single medium in exemplary embodiments, the term "machine-readable storage medium" is a single medium that stores one or more instruction sets. Or it should be construed to include multiple media (eg, centralized or distributed databases and / or associated caches and servers). The term "machine readable storage medium" is also interpreted to include a medium capable of storing or encoding an instruction set for execution by a machine and causing the machine to perform any one or more embodiments. It should be. The term "machine readable storage medium" should be construed to include, but is not limited to, solid-state memory, optical and magnetic media.

Techniques and architectures for providing voltage to integrated circuits are described herein. In the above description, for the purposes of explanation, a number of specific details are provided to provide a complete understanding of the particular embodiment. However, it will be apparent to those skilled in the art that certain embodiments may be implemented without these particular details. In other examples, structures and devices are shown in the form of block diagrams to avoid obscuring the description.

References to "one embodiment" or "embodiment" herein include, in at least one embodiment of the invention, specific features, structures, or features described in connection with such embodiments. It means that it is. The appearance of the phrase "in one embodiment" in various places herein does not necessarily refer to the same embodiment.

A portion of the detailed description herein is given in algorithms and symbolic representations of operations on data bits in computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of computer technology to most effectively convey the content of their research to them. The algorithm is considered herein and generally as a coherent sequence of steps leading to the desired result. A step is a step that requires a physical manipulation of a physical quantity. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transferred, combined, compared and otherwise processed. It is known that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, letters, terms, numbers, etc., mainly because they are used for common purposes.

However, it should be noted that all the above terms as well as similar terms are related to the appropriate physical quantity and are only simple labels applied to this physical quantity. Unless otherwise specified in the description of this specification, discussions using terms such as "processing" or "computing" or "calculation" or "decision" or "display" throughout this specification are made. , Is understood to mean the operation and process of a computer system or similar electronic computing device. Such a computer system or similar electronic computing device manipulates and transforms data represented as physical (electronic) quantities in the computer system's registers and memory to the computer system's memory or registers. Or convert to other data similarly represented as physical quantities in such information storage, transmission or display devices.

Also, certain embodiments relate to devices for performing the operations herein. The device may include a general purpose computer that may be specially configured for the required purpose, or selectively actuated or reconfigured by a computer program stored in the computer. Such computer programs include floppy disks, optical disks, CD-ROMs and any type of disk including magnetic optical disks, read-only memory (ROM), such as random access memory (RAM) such as dynamic RAM, EPROM, EEPROM, magnetic or It is stored on a computer-readable storage medium, including, but not limited to, an optical card, or any type of medium suitable for storing electronic instructions, and is coupled to a computer system bus.

The algorithms and indications presented herein are not inherently relevant to any particular computer or other device. Various general purpose systems can be used with programs that follow the teachings herein, or it has proved convenient to configure more specialized equipment to perform the required method steps. obtain. The structures required for various of these systems will become apparent from the description herein. In addition, certain embodiments are not described with reference to any particular programming language. It will be appreciated that various programming languages can be used to carry out the teachings of embodiments as described herein.

In addition to those described herein, various modifications can be made to the disclosed embodiments and implementations thereof without departing from their scope. Therefore, the explanations and examples herein should be construed in an exemplary sense rather than in a limiting sense. The scope of the invention should only be evaluated by reference to the claims below.

Claims (25)

A device for providing supply voltage:
It is a voltage regulator circuit for receiving the first voltage via the first node and supplying the second voltage to the load circuit via the second node based on the first voltage. Inductors L1 and L2, and a switch. The circuits S1, S2, S3 and S4 are included, the inductors L1 and L2 are coupled to the first node via the switch circuits S1 and S3, respectively, and the second node is coupled to the first node via the inductors L1 and L2, respectively. A voltage regulator coupled to circuits S1 and S3, the inductors L1 and L2 further coupled to a third node via the switch circuits S2 and S4, respectively, and the third node coupled to provide a reference potential. Circuit; and in response to a voltage overshoot condition indication, a current path between the inductor L1 and the first node or one of the third nodes is possible via the second node and the inductor L2. A control circuit that sends a signal to the voltage regulator circuit to provide an on state for each of the switch circuit S2 and one of the switch circuits S3 or S4;
Equipment including. In response to the instruction, the control circuit further signals the voltage regulator circuit.
During the on state of each of the switch circuits S2 and S4, the first configuration including the off state of the switch circuit S3;
With the second configuration including the off state of the switch circuit S4 during each on state of the switch circuits S2 and S3;
The device of claim 1, wherein the device is transitioned between. The device according to claim 2, wherein in response to the instruction, the control circuit further sends a signal to the voltage regulator circuit to make a plurality of transitions between the first configuration and the second configuration. A signal is sent to the voltage regulator circuit to make a transition between the first configuration and the second configuration based on a threshold parameter indicating the maximum duration of one of the switch circuits S3 and S4 in the on state. The device according to claim 2. The control circuit sends a signal to the voltage regulator circuit based on a threshold parameter indicating the minimum time between the state transition by one of the switch circuits S3 and S4 and the state transition by the other of the switch circuits S3 and S4. The device according to claim 2, wherein the device is fed and transitioned between the first configuration and the second configuration. The control circuit
The voltage overshoot relaxation state is detected; and in response to the voltage overshoot relaxation state, a signal is sent to the voltage regulator circuit to set the on state of the switch circuit S1 and the off states of the switch circuits S2, S3 and S4, respectively. The device according to claim 1 or 2, which is provided. The voltage overshoot state includes the second voltage that is greater than the first voltage threshold, and the voltage overshoot relaxation state includes a second voltage that is smaller than the second voltage threshold that is smaller than the first voltage threshold. Item 6. The apparatus according to item 6. In response to the instruction, the control circuit
The first control signal and the second control signal are generated based on the second voltage, the threshold maximum voltage parameter, and the output of the pulse width modulation circuit; and the first control signal and the first control signal are generated in the switch circuits S1 and S2. 2. The device according to any one of claims 1 or 2, which supplies control signals, respectively. The voltage regulator circuit is a first voltage regulator circuit located at a first position offset by a first distance from a reference position along a certain dimension.
The device further comprises a second voltage regulator circuit coupled to the load circuit.
The second voltage regulator circuit is located at a second position along the dimension, offset by a second distance from the reference position.
In response to the instruction, the control circuit selects the first voltage regulator circuit in preference to the second voltage regulator circuit to alleviate the duration or magnitude of the voltage overshoot state and to control the control. The circuit selects the first voltage regulator circuit based on the first distance and the second distance.
The device according to any one of claims 1 or 2. The device according to claim 9, wherein the reference position is a position along the dimension of a part of the load circuit in which a voltage overshoot event is indicated. The device according to claim 9, wherein the reference position is a position along the dimension of the control circuit. The device according to any one of claims 1 or 2, wherein the integrated circuit chip includes the switch circuits S1, S2, S3 and S4, and the load circuit. 12. The integrated circuit chip is in the package mold, and the inductors L1 and L2 are in the package mold or on the package mold, respectively, and are electrically coupled to the integrated circuit chip. Device. A system for supplying power supply voltage, including packaged devices and display devices:
The packaged device
It is a voltage regulator circuit for receiving the first voltage via the first node and supplying the second voltage to the load circuit via the second node based on the first voltage. Inductors L1 and L2, and a switch. The circuits S1, S2, S3 and S4 are included, the inductors L1 and L2 are coupled to the first node via the switch circuits S1 and S3, respectively, and the second node is coupled to the first node via the inductors L1 and L2, respectively. A voltage regulator coupled to circuits S1 and S3, the inductors L1 and L2 further coupled to a third node via the switch circuits S2 and S4, respectively, and the third node coupled to provide a reference potential. Circuit; and in response to a voltage overshoot condition indication, a current path between the inductor L1 and the first node or one of the third nodes is possible via the second node and the inductor L2. A control circuit that sends a signal to the voltage regulator circuit to provide an on state for each of the switch circuit S2 and one of the switch circuits S3 or S4;
Including
The display device is coupled to the packaged device and displays an image based on a signal communicated to the load circuit.
system. In response to the instruction, the control circuit further signals the voltage regulator circuit.
During the on state of each of the switch circuits S2 and S4, the first configuration including the off state of the switch circuit S3;
With the second configuration including the off state of the switch circuit S4 during each on state of the switch circuits S2 and S3;
The system according to claim 14, wherein the transition is made between. The control circuit
The voltage overshoot relaxation state is detected; and in response to the voltage overshoot relaxation state, a signal is sent to the voltage regulator circuit to set the on state of the switch circuit S1 and the off states of the switch circuits S2, S3 and S4, respectively. The system according to claim 14 or 15, provided. In response to the instruction, the control circuit
The first control signal and the second control signal are generated based on the second voltage, the threshold maximum voltage parameter, and the output of the pulse width modulation circuit; and the first control signal and the first control signal are generated in the switch circuits S1 and S2. 2. The system according to claim 14 or 15, which supplies control signals, respectively. The voltage regulator circuit is a first voltage regulator circuit located at a first position offset by a first distance from a reference position along a certain dimension.
The packaged device further comprises a second voltage regulator circuit coupled to the load circuit.
The second voltage regulator circuit is located at a second position along the dimension, offset by a second distance from the reference position.
In response to the instruction, the control circuit selects the first voltage regulator circuit in preference to the second voltage regulator circuit to alleviate the duration or magnitude of the voltage overshoot state and to control the control. The circuit selects the first voltage regulator circuit based on the first distance and the second distance.
The system according to claim 14 or 15. The system according to claim 14 or 15, wherein the integrated circuit (IC) chip comprises the switch circuits S1, S2, S3 and S4 and the load circuit. A way to provide a supply voltage:
It is a step of supplying the first voltage to the voltage regulator via the first node, and the voltage regulator circuit is sent to the first node via the switch circuits S1, S2, S3 and S4, and the switch circuits S1 and S3, respectively. Coupled, the second node is coupled to the switch circuits S1 and S3 via the inductors L1 and L2, respectively, and the inductors L1 and L2 are further coupled to the third node via the switch circuits S2 and S4, respectively. , Step;
It is a step of supplying a second voltage based on the first voltage to the load circuit via the second node by using the voltage regulator, and the switch circuits S2, S3 and S4 are said to be in the off state during the off state. A step involving conducting a current through the inductor L1;
The step of detecting the instruction of the voltage overshoot state; and in response to the instruction, a conductive path is provided between the inductor L1 and the first node or the second node via the second node and the inductor L2. A step that enables the step to bring about the on state of each of the switch circuit S2 and the switch circuit S3 or S4;
How to include. In response to the instruction, further signals are sent to the voltage regulator circuit.
During the on state of each of the switch circuits S2 and S4, the first configuration including the off state of the switch circuit S3;
With the second configuration including the off state of the switch circuit S4 during each on state of the switch circuits S2 and S3;
The method of claim 20, wherein the transition is made between. 21. The method of claim 21, wherein in response to the instructions, the voltage regulator circuit transitions between the first configuration and the second configuration multiple times. A control circuit signals the voltage regulator circuit between the first configuration and the second configuration based on a threshold parameter indicating the maximum duration of one of the switch circuits S3 and S4 in the on state. The method of claim 21, wherein the transition is made. A signal is sent to the voltage regulator circuit based on a threshold parameter indicating the minimum time between the state transition by one of the switch circuits S3 and S4 and the state transition by the other of the switch circuits S3 and S4. 21. The method of claim 21, wherein the transition is made between one configuration and the second configuration. The step of detecting the voltage overshoot relaxation state; and in response to the voltage overshoot relaxation state, a signal is sent to the voltage regulator circuit to turn on the switch circuit S1 and turn off the switch circuits S2, S3 and S4, respectively. Steps to provide;
The method according to claim 20 or 21, further comprising.

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