JP2022138011A - Power conversion device - Google Patents

Abstract

To suppress reduction in an output current.SOLUTION: A power conversion device has a PWM control mode as a control mode of controlling respective switching elements periodically. In the PWM control mode, at least one of a primary side voltage and a secondary side voltage changes to be positive, negative, or zero. The PWM control mode consists of an inversion period Φ in which polarities of the primary and secondary side voltages are inverted, and a transmission period. A control circuit controls the respective switching elements so that the inversion period Φ becomes equal to or less than a predetermined upper limit inversion period Φ1, in the PWM control mode.SELECTED DRAWING: Figure 5

Description

The present invention relates to power converters.

2. Description of the Related Art Conventionally, a power conversion device including a transformer having primary windings and secondary windings is known (see, for example, Patent Document 1). The power conversion device described in Patent Document 1 includes a primary side full bridge circuit having a plurality of primary side switching elements, a secondary side full bridge circuit having a plurality of secondary side switching elements, and a primary side switching element and a control circuit that controls the secondary side switching element.

The power converter described in Patent Document 1 includes an inversion period in which the polarities of the primary voltage input to the primary winding and the secondary voltage input to the secondary winding are inverted. It includes a control mode that periodically controls the primary side switching element and the secondary side switching element. The power conversion device adjusts the output current output from the secondary side full bridge circuit by adjusting the length of the inversion period in the control mode. Specifically, the power converter outputs a larger output current by lengthening the inversion period.

Patent No. 2018-26961

However, the longer the inversion period, the shorter the period during which the secondary side full bridge circuit can output the output current. Therefore, if the inversion period is longer than a certain value, the average output current within one cycle may decrease. As a result, lengthening the inversion period in order to increase the output current may rather decrease the output current.

A power conversion device for solving the above problems includes a transformer having a primary winding and a secondary winding, and a circuit connected to the primary winding, having a plurality of primary switching elements. a primary side full bridge circuit, a secondary side full bridge circuit connected to the secondary winding and having a plurality of secondary side switching elements, the plurality of primary side switching elements and the a control circuit that converts an input voltage input to the primary side full bridge circuit into an output voltage output from the secondary side full bridge circuit by controlling a plurality of secondary side switching elements; The control circuit controls the primary-side voltage input to the primary-side winding or the secondary-side switching element as a control mode for periodically controlling the plurality of primary-side switching elements and the plurality of secondary-side switching elements. A PWM control mode is provided in which at least one of the secondary voltages input to the side windings is switched to be positive, negative, or zero, and the half cycle of the PWM control mode is the difference between the primary voltage and the secondary voltage. When the inversion period in which the polarity is reversed and the transmission period include an output period in which the secondary voltage is positive or negative, and the control circuit is in the PWM control mode , the primary side switching element and the secondary side switching element are controlled so that the inversion period is equal to or less than a predetermined upper limit inversion period, and the primary side switching element and the secondary side switching element is set to T, the upper limit inversion period is shorter than T/4.

According to this, in the PWM control mode, the output current is not maximized when the inversion period is T/4, but is maximized during a maximum output period shorter than T/4. Therefore, if the inversion period becomes longer than the maximum output period, the output current will rather decrease. Therefore, each switching element is controlled so that the inversion period is equal to or less than the upper limit inversion period which is less than T/4. Thereby, it is possible to suppress the decrease in the output current.

For the power converter, the PWM control mode may be a double-sided PWM control mode in which the primary side voltage switches to positive, negative or zero and the secondary side voltage switches to positive, negative or zero.

For example, the magnitude relationship between the input voltage input to the primary side full bridge circuit and the output voltage output from the secondary side full bridge circuit may change depending on the target or situation to which the power converter is applied. be. In this case, if the control mode for controlling each switching element is changed according to the magnitude relationship, the control may become complicated. Therefore, the double-sided PWM control mode in which both the primary side voltage and the secondary side voltage are switched to positive, negative or zero is a control mode that can be similarly applied even if the magnitude relationship between the input voltage and the output voltage changes. be. This makes it possible to reduce the complexity of control associated with changes in the magnitude relationship between the input voltage and the output voltage.

Here, in the double-sided PWM control mode, since a period during which the output current is zero may occur, the maximum output period during which the output current is maximum may be shorter than T/4. For this reason, if the inversion period is brought close to T/4, there may be a problem that the output current decreases. In this regard, according to this configuration, the control circuit performs control so that the inversion period is equal to or less than the upper limit inversion period, so the above inconvenience can be suppressed.

In the power conversion device, the upper limit inversion period may be equal to or less than the maximum output period during which the output current from the secondary side full bridge circuit is maximized.
According to this, since the upper limit inversion period is equal to or shorter than the maximum output period, the output current increases while the derived inversion period increases to the maximum output period. On the other hand, when the derived inversion period is longer than the maximum output period, the output current becomes constant. Therefore, it is possible to prevent the output current from decreasing from the state of the maximum output period due to an increase in the inversion period.

The power conversion device may include a plurality of capacitors connected in parallel to the plurality of primary side switching elements and the plurality of secondary side switching elements.

According to this, the capacitor is charged/discharged with the switching of the switching pattern, so that the switching loss when each switching element performs soft switching can be reduced.

According to the present invention, reduction in output current can be suppressed.

FIG. 2 is a circuit diagram showing electrical configurations of a power conversion device and a power supply system; (a) Waveform diagram showing primary side voltage, (b) Waveform diagram showing secondary side voltage. FIG. 4 is a diagram showing a switching pattern of each switching element in a double-sided PWM control mode; (a) Graph showing primary side voltage, (b) Graph showing secondary side voltage, (c) Graph showing primary side current and secondary side current, (d) Graph showing output current. 4 is a flowchart showing a double-sided PWM control mode process; (a) Graph showing inversion period dependence of output current, (b) Graph showing inversion period dependence of transmission period, input period, output period, and overlapping period.

<Configuration>
An embodiment of a power conversion device will be described below with reference to the drawings.
As shown in FIG. 1 , the power supply system 100 includes a DC power supply 110, a load 120, and a power converter 10. DC power supply 110 is a voltage source that outputs a DC voltage. The load 120 is, for example, a power storage device capable of charging and discharging DC power, such as a secondary battery. A secondary battery is, for example, a lithium ion storage battery or a lead storage battery.

The power converter 10 is a so-called dual active bridge DC/DC converter. Power converter 10 is provided between DC power supply 110 and load 120 . The power converter 10 can convert the power of the DC power supply 110 and output it to the load 120 . Also, the power converter 10 can convert the power of the load 120 and output it to the DC power supply 110 . In the following description, the primary side will be treated as an input and the secondary side as an output. That is, the power converter 10 converts the DC voltage input from the DC power supply 110 and outputs it to the load 120 . The power conversion device 10 includes a transformer 20 , a primary side full bridge circuit 30 , a secondary side full bridge circuit 40 and a control circuit 50 .

The transformer 20 has a magnetic core 21 , and a primary winding 22 and a secondary winding 23 wound around the core 21 . That is, the transformer 20 is a so-called insulation type. Transformer 20 has a reactor L. Reactor L may be an element such as a choke coil, or may be leakage inductance of primary winding 22 and secondary winding 23 .

The primary side full bridge circuit 30 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4 as a plurality of primary side switching elements. Further, the primary side full bridge circuit 30 has a plurality of primary side diodes D1 to D4 and a plurality of primary side capacitors C1 to C4.

In this embodiment, n-type MOSFETs: Metal Oxide Semiconductor Field Effect Transistors are used as the primary side switching elements Q1 to Q4, but other switching elements such as p-type MOSFETs and IGBTs: Insulated Gate Bipolar Transistors are used. may be used. The four primary side switching elements Q1-Q4 constitute a first leg 31 and a second leg 32. As shown in FIG. The first leg 31 is a serially connected body in which the source of the first switching element Q1 and the drain of the second switching element Q2 are connected by a first connection line 33 . The second leg 32 is a serially connected body in which the source of the third switching element Q3 and the drain of the fourth switching element Q4 are connected by a second connection line 34 . The first leg 31 and the second leg 32 are connected to primary terminals 35 and 36 so as to be connected in parallel with each other. At this time, the first switching element Q1 and the third switching element Q3 constitute an upper arm, and the second switching element Q2 and the fourth switching element Q4 constitute a lower arm. That is, it can be said that the primary side full bridge circuit 30 is connected to the primary side terminals 35 and 36 .

Primary-side diodes D1-D4 and primary-side capacitors C1-C4 are connected in parallel to primary-side switching elements Q1-Q4, respectively. The primary side diodes D1 to D4 may be parasitic diodes or elements. Primary-side diodes D1-D4 are reverse-connected to primary-side switching elements Q1-Q4. The primary capacitors C1-C4 may be parasitic capacitances, elements, or a combination of parasitic capacitances and elements.

A first connection line 33 and a second connection line 34 of the primary side full bridge circuit 30 are connected to the primary side winding 22 respectively. Therefore, a voltage V1 equal to the potential difference between the second connection line 34 and the first connection line 33 is applied to the primary winding 22 . In the following description, the voltage V1 applied to the primary winding 22 may be referred to as "primary side voltage V1". The primary side voltage V1 is positive when the potential of the first connection line 33 is higher than the potential of the second connection line 34 .

In addition, the DC power supply 110 is connected to the primary side terminals 35 and 36 . Therefore, the primary side full bridge circuit 30 is connected to the DC power supply 110 via the primary side terminals 35 and 36 .

The primary side voltage sensor 37 is a voltmeter for measuring the input voltage Vin input to the primary side full bridge circuit 30 . The primary side voltage sensor 37 is connected to the primary side terminals 35 and 36 so as to be parallel to the primary side full bridge circuit 30 . Although the value of the input voltage Vin is arbitrary, it is, for example, 250 to 450 [V].

Primary side current sensor 38 is an ammeter for measuring input current Iin from DC power supply 110 to primary side full bridge circuit 30 . As the primary side current sensor 38, any form such as a shunt resistor or a hall element can be adopted.

The secondary side full bridge circuit 40 has a fifth switching element Q5, a sixth switching element Q6, a seventh switching element Q7, and an eighth switching element Q8 as a plurality of secondary side switching elements. Further, the secondary side full bridge circuit 40 has a plurality of secondary side diodes D5 to D8 and a plurality of secondary side capacitors C5 to C8.

Although n-type MOSFETs are used as the secondary side switching elements Q5 to Q8 in this embodiment, other switching elements such as p-type MOSFETs and IGBTs may be used. Four secondary side switching elements Q5 to Q8 constitute a third leg 41 and a fourth leg . The third leg 41 is a series connection body in which the source of the fifth switching element Q5 and the drain of the sixth switching element Q6 are connected by a third connection line 43. As shown in FIG. The fourth leg 42 is a serially connected body in which the source of the seventh switching element Q7 and the drain of the eighth switching element Q8 are connected by a fourth connection line 44. As shown in FIG. The third leg 41 and the fourth leg 42 are connected to secondary terminals 45 and 46 so as to be connected in parallel with each other. At this time, the fifth switching element Q5 and the seventh switching element Q7 constitute an upper arm, and the sixth switching element Q6 and the eighth switching element Q8 constitute a lower arm. That is, it can be said that the secondary side full bridge circuit 40 is connected to the secondary side terminals 45 and 46 .

Secondary diodes D5 to D8 and secondary capacitors C5 to C8 are connected in parallel to secondary switching elements Q5 to Q8, respectively. The secondary diodes D5 to D8 may be parasitic diodes or elements. Secondary diodes D5-D8 are reversely connected to secondary switching elements Q5-Q8. Secondary capacitors C5-C8 may be parasitic capacitances, elements, or a combination of parasitic capacitances and elements. Therefore, the plurality of capacitors C1-C8 are connected in parallel to the plurality of primary side switching elements Q1-Q4 and the plurality of secondary side switching elements Q5-Q8, respectively.

A third connection line 43 and a fourth connection line 44 of the secondary side full bridge circuit 40 are connected to the secondary side winding 23 respectively. Therefore, a voltage V2 equal to the potential difference between the third connection line 43 and the fourth connection line 44 is applied to the secondary winding 23 . In the following description, the voltage V2 applied to the secondary winding 23 may be referred to as "secondary voltage V2". Note that the secondary voltage V2 is positive when the potential of the third connection line 43 is higher than the potential of the fourth connection line 44 . A load 120 is connected to the secondary terminals 45 and 46 . Therefore, the secondary side full bridge circuit 40 is connected to the load 120 via the secondary side terminals 45 and 46 .

The secondary side voltage sensor 47 is a voltmeter for measuring the output voltage Vout output from the secondary side full bridge circuit 40 . The secondary side voltage sensor 47 is connected to the secondary side terminals 45 and 46 so as to be parallel to the secondary side full bridge circuit 40 . Although the value of the output voltage Vout is arbitrary, it is, for example, 250 to 450 [V].

When load 120 is a power storage device, when load 120 is connected to secondary terminals 45 and 46, secondary voltage sensor 47 detects the voltage of load 120 as output voltage Vout.

The secondary current sensor 48 is an ammeter for measuring the output current Iout output from the secondary full bridge circuit 40 . As the secondary side current sensor 48, any form such as a shunt resistor or a hall element can be adopted.

Control circuit 50 is connected to both voltage sensors 37 and 47 and to both current sensors 38 and 48 . The control circuit 50 acquires the input voltage Vin from the primary side voltage sensor 37 and the output voltage Vout from the secondary side voltage sensor 47, respectively. The control circuit 50 acquires the input current Iin from the primary side current sensor 38 and the output current Iout from the secondary side current sensor 48, respectively.

The control circuit 50 converts the input voltage Vin into the output voltage Vout by periodically controlling the plurality of primary side switching elements Q1-Q4 and the plurality of secondary side switching elements Q5-Q8. In this embodiment, the switching of the primary side switching elements Q1-Q4 and the secondary side switching elements Q5-Q8 is controlled at a predetermined cycle T.

Note that the specific hardware configuration of the control circuit 50 is arbitrary. For example, the control circuit 50 may be configured to have a dedicated hardware circuit for acquiring voltage and controlling switching, or may be a memory storing a control program and necessary information for acquiring voltage and controlling switching. , and a CPU that performs voltage acquisition and switching control based on a control program.

<About control mode>
Next, a control mode for controlling the primary side switching elements Q1-Q4 and the secondary side switching elements Q5-Q8 will be described. In the following description, each diode D1-D8 may be called "nth diode Dn", and each capacitor C1-C8 may be called "nth capacitor Cn". Note that n is a natural number from 1 to 8.

The control circuit 50 has a PWM control mode as a control mode for periodically controlling the plurality of primary side switching elements Q1-Q4 and the plurality of secondary side switching elements Q5-Q8.
The PWM control mode is a control mode in which at least one of the primary side voltage V1 or the secondary side voltage V2 is switched to positive, negative, or zero. The PWM control mode of this embodiment is a double-sided PWM control mode.

As shown in FIGS. 2(a) and 2(b), the two-sided PWM control mode switches the primary voltage V1 to positive, negative or zero, and the secondary voltage V2 to positive, negative or zero. This is the control mode that switches to Note that when the secondary voltage V2 is zero, the output current Iout is zero. Therefore, it can be said that the double-sided PWM control mode is a type of control mode having a period during which the output current Iout is zero within one cycle.

As shown in FIG. 3, in the both-side PWM control mode, the switching patterns of the switching elements Q1 to Q8 include, for example, a first pattern P1, a second pattern P2, a third pattern P3, a fourth pattern P4, and a fifth pattern P5. , a sixth pattern P6, a seventh pattern P7, and an eighth pattern P8 are set. In the following description, the switching pattern of each switching element Q1-Q8 may be simply referred to as "switching pattern".

As shown in FIG. 3, the first pattern P1 is a switching pattern in which the switching elements Q1, Q4, Q6 and Q7 are ON and the switching elements Q2, Q3, Q5 and Q8 are OFF. In this case, as shown in FIG. 2, the primary side voltage V1 becomes positive and the secondary side voltage V2 becomes negative.

As shown in FIG. 3, the second pattern P2 is a switching pattern in which the switching elements Q1, Q4, Q6 and Q8 are in the ON state and the switching elements Q2, Q3, Q5 and Q7 are in the OFF state. In this case, as shown in FIG. 2, the primary side voltage V1 becomes positive and the secondary side voltage V2 becomes zero.

As shown in FIG. 3, the third pattern P3 is a switching pattern in which the switching elements Q1, Q4, Q5 and Q8 are in the ON state and the switching elements Q2, Q3, Q6 and Q7 are in the OFF state. In this case, as shown in FIG. 2, the primary side voltage V1 becomes positive and the secondary side voltage V2 becomes positive.

As shown in FIG. 3, the fourth pattern P4 is a switching pattern in which the switching elements Q1, Q3, Q5 and Q8 are in the ON state and the switching elements Q2, Q4, Q6 and Q7 are in the OFF state. In this case, as shown in FIG. 2, the primary side voltage V1 becomes zero and the secondary side voltage V2 becomes negative.

As shown in FIG. 3, the fifth pattern P5 is a switching pattern in which the switching elements Q2, Q3, Q5 and Q8 are ON and the switching elements Q1, Q4, Q6 and Q7 are OFF. In this case, as shown in FIG. 2, the primary side voltage V1 becomes negative and the secondary side voltage V2 becomes positive.

As shown in FIG. 3, the sixth pattern P6 is a switching pattern in which the switching elements Q2, Q3, Q5 and Q7 are in the ON state and the switching elements Q1, Q4, Q5 and Q7 are in the OFF state. In this case, as shown in FIG. 2, the primary side voltage V1 becomes negative and the secondary side voltage V2 becomes zero.

As shown in FIG. 3, the seventh pattern P7 is a switching pattern in which the switching elements Q2, Q3, Q6 and Q7 are in the ON state and the switching elements Q1, Q4, Q5 and Q8 are in the OFF state. In this case, as shown in FIG. 2, the primary side voltage V1 becomes negative and the secondary side voltage V2 becomes negative.

As shown in FIG. 3, the eighth pattern P8 is a switching pattern in which the switching elements Q2, Q4, Q6 and Q7 are in the ON state and the switching elements Q1, Q3, Q5 and Q8 are in the OFF state. In this case, as shown in FIG. 2, the primary side voltage V1 becomes zero and the secondary side voltage V2 becomes negative.

In this embodiment, if the primary side voltage V1 is positive or negative, the magnitude of the primary side voltage V1 is equal to the magnitude of the input voltage Vin. Similarly, if the secondary voltage V2 is positive or negative, the magnitude of the secondary voltage V2 is assumed to be equal to the magnitude of the output voltage Vout.

In the double-side PWM control mode, the control circuit 50 repeats the unit operation with a period T, with the operation of sequentially switching the switching pattern in the order of P1→P2→P3→P4→P5→P6→P7→P8 as one unit. . As a result, the primary side voltage V1 and the secondary side voltage V2 sequentially change with a predetermined phase difference, and voltage conversion (in other words, power conversion) is performed. In this case, the control circuit 50 can be said to control the primary side full bridge circuit 30 and the secondary side full bridge circuit 40 with a phase difference.

In particular, in the double-sided PWM control mode, voltage conversion can be performed regardless of the magnitude relationship between the input voltage Vin and the output voltage Vout by controlling the switching elements Q1 to Q8. That is, the double-sided PWM control mode is a control mode in which step-up and step-down are possible.

Here, in the double-sided PWM control mode, the patterns P1 to P4 are half cycles (T/2), and the fifth patterns P5 to P8 are half cycles (T/2). The patterns P1 to P4 and the patterns P5 to P8 have the same aspect except that the polarities are reversed. Therefore, the patterns P1 to P4 will be described in detail below, and the specific control modes of the patterns P5 to P8 will be omitted.

As shown in FIG. 2, the two-sided PWM control mode is composed of an inversion period Φ and a transmission period W. As shown in FIG.
The inversion period Φ is a period in which the polarities of the primary side voltage V1 and the secondary side voltage V2 are inverted in a half cycle. The transmission period W is a period other than the inversion period Φ in the half cycle. In this embodiment, the inversion period Φ is the period in which the first pattern P1 is set, and the transmission period W is the period in which the patterns P2 to P4 are set.

The transmission period W includes an input period T1 and an output period T2.
The input period T1 is a period during which the primary voltage V1 is positive. In this embodiment, the input period T1 is the period in which the patterns P2 and P3 are set.

The output period T2 is a period during which the secondary voltage V2 is positive. In this embodiment, the output period T2 is the period in which the patterns P3 and P4 are set. That is, the period in which the third pattern P3 is set is included in both the input period T1 and the output period T2. That is, the period in which the third pattern P3 is set is the period in which both the primary side voltage V1 and the secondary side voltage V2 are positive. In the following description, the period in which the third pattern P3 is set may be referred to as "overlapping period X".

To make sure, the polarities of the patterns P1 to P4 and the patterns P5 to P8 are reversed as described above. Therefore, the input period T1 in the period of patterns P5 to P8 is a period during which the primary voltage V1 is negative, and the output period T2 is a period during which the secondary voltage V2 is negative. The overlapping period X is a period during which both the primary side voltage V1 and the secondary side voltage V2 are negative.

In the two-sided PWM control mode, the output current Iout depends on the inversion period Φ and both periods T1, T2. Specifically, the output current Iout is represented by the following formula (1).

なお、ＬはリアクトルＬのインダクタンス値である。また、重複期間Ｘは、Ｔ１＋Ｔ２＋Φ－Ｔ／２と表すことができる。重複期間Ｘはゼロ以上である。したがって、制御回路５０は、反転期間Φ及び両期間Ｔ１，Ｔ２を制御することにより、出力電流Ｉｏｕｔを制御することができる。

Note that L is the inductance value of the reactor L. Also, the overlap period X can be expressed as T1+T2+Φ-T/2. Overlap period X is greater than or equal to zero. Therefore, the control circuit 50 can control the output current Iout by controlling the inversion period Φ and both periods T1 and T2.

In particular, when the secondary current IS at the start timing of the transmission period W matches the secondary current IS at the end timing, the input period T1 and the output period T2 satisfy the following equation (2).

したがって、制御回路５０は、反転期間Φ及び出力期間Ｔ２を制御することにより、出力電流Ｉｏｕｔを制御することができる。

Therefore, the control circuit 50 can control the output current Iout by controlling the inversion period Φ and the output period T2.

In the double-sided PWM control mode, the control circuit 50 establishes a correspondence relationship between the inversion period Φ and the output period T2 by regarding the inversion period Φ as a linear function of the output period T2. The linear function of this embodiment is represented by the following equation (3) using a linear coefficient K, for example.

なお、１次係数Ｋは、少なくとも入力電圧Ｖｉｎ及び出力電圧Ｖｏｕｔに依存する。

Note that the first-order coefficient K depends at least on the input voltage Vin and the output voltage Vout.

The input period T1 and the output period T2 are uniquely determined from equations (2) and (3) by determining the inversion period Φ. The inversion period Φ and both periods T1 and T2 are, for example, the phase difference between the primary side full bridge circuit 30 and the secondary side full bridge circuit 40 (in other words, the phase between the primary side voltage V1 and the secondary side voltage V2). phase difference), the duty ratio of the primary side switching elements Q1-Q4, or the duty ratio of the secondary side switching elements Q5-Q8. Therefore, the control circuit 50 may control the output current Iout, for example, by controlling the inversion period Φ and both periods T1 and T2 based on the above parameters. Note that the parameters for controlling the inversion period Φ and both periods T1 and T2 are not limited to the above. For example, the phase difference between the first leg 31 and the second leg 32, A phase difference may be used.

In the patterns P5 to P8, the inversion period Φ is the period in which the fifth pattern P5 is set, and the transmission period W is the period in which the patterns P6 to P8 are set. Since the polarities of the patterns P1 to P4 and the patterns P5 to P8 are reversed, in the patterns P5 to P8, the input period T1 is a period in which the primary side voltage V1 is negative, and the output period T2 is a period during which the secondary voltage V2 is negative. The control circuit 50 sequentially switches the patterns P1 to P8 so that the inversion period Φ and both periods T1 and T2 satisfy the soft switching condition.

Here, soft switching conditions will be described with reference to FIG. 4(a) shows the waveform of the primary side voltage V1, FIG. 4(b) shows the waveform of the secondary side voltage V2, and FIG. 4(c) shows the primary side current IL and the secondary side current IS. 4(d) shows the waveform of the output current Iout. A primary current IL is a current flowing through the primary winding 22 and a secondary current IS is a current flowing through the secondary winding 23 . In this embodiment, for convenience of explanation, it is assumed that the primary side current IL and the secondary side current IS are the same.

As shown in FIG. 4, the soft switching condition in the both-side PWM control mode includes (A) the magnitude of the primary-side current IL becoming equal to or greater than the primary-side threshold value ILmin at the start timing of the inversion period Φ. In other words, the soft switching condition includes switching the switching pattern from the eighth pattern P8 to the first pattern P1 while the magnitude of the primary current IL is equal to or greater than the primary threshold ILmin. The primary side threshold ILmin is, for example, the magnitude of the current required to charge and discharge the primary side capacitors C1 to C4 using the primary side current IL. The primary side threshold ILmin is set, for example, based on the capacities of the primary side capacitors C1 to C4. Since the primary side current IL is negative at the start timing of the inversion period Φ, the condition (A) is that the primary side current IL is -ILmin or less.

The soft switching condition in the both-side PWM control mode includes (B) that the magnitude of the secondary-side current IS becomes equal to or greater than the secondary-side threshold value ISmin at the end timing of the inversion period Φ. In other words, the soft switching condition includes switching the switching pattern from the first pattern P1 to the second pattern P2 while the magnitude of the secondary current IS is greater than or equal to the secondary threshold ISmin. The secondary side threshold value ISmin is, for example, the magnitude of the current required to charge and discharge the secondary side capacitors C5 to C8 using the secondary side current IS. The secondary side threshold ISmin is set, for example, based on the capacitance of the secondary side capacitors C5 to C8. Since the secondary current IS is positive at the start timing of the inversion period Φ, the condition (B) is that the secondary current IS is equal to or greater than the secondary threshold ISmin. In the following explanation, it is assumed that the primary side threshold ILmin and the secondary side threshold ISmin are equal. The case where the primary side threshold ILmin and the secondary side threshold ISmin are equal is, for example, the case where the capacitance of the primary side capacitors C1 to C4 and the capacitance of the secondary side capacitors C5 to C8 are equal.

As shown in FIG. 4(d), the output current Iout becomes a predetermined offset current Ioff at the end timing of the output period T2. As the offset current Ioff increases, the ripple current of the output current Iout increases. The offset current Ioff increases as the inversion period Φ lengthens.

The control circuit 50 is configured to be able to communicate with a load control device 121 that controls the load 120 . When the control circuit 50 receives the requested electric power Pr from the load control device 121, the control circuit 50 executes the double-sided PWM control mode process so as to supply the requested electric power Pr to the load 120 in the double-sided PWM control mode.

<Regarding both sides PWM control mode processing>
The two-sided PWM control mode processing will be described below with reference to FIG.
As shown in FIG. 5, in step S100, the control circuit 50 receives the input voltage Vin from the primary side voltage sensor 37, the output voltage Vout from the secondary side voltage sensor 47, and the required power Pr from the load control device 121. Get each.

After that, the control circuit 50 proceeds to step S101 and derives the target current It from the output voltage Vout and the required power Pr.
After that, the control circuit 50 proceeds to step S102 to derive the inversion period Φ, the input period T1, and the output period T2 during which the output current Iout becomes the target current It. An example of the derivation method is to replace the left side (output current Iout) of Equation (1) with the target current It and then apply Equations (2) and (3) to the right side of Equation (1). . As a result, the target current It is represented by the inversion period Φ. Using this, the inversion period Φ can be derived from the target current It. Also, the input period T1 and the output period T2 may be derived by substituting the inversion period Φ into the equations (2) and (3), respectively.

Here, the relationship between the inversion period Φ and the output current Iout derived in the process of step S102 will be described with reference to FIG.
FIG. 6(a) shows the dependence of the output current Iout on the inversion period Φ. FIG. 6(b) shows the inversion period Φ dependence of the transmission period W, the input period T1, the output period T2, and the overlap period X based on equations (1), (2), and (3). is.

As shown in FIG. 6(b), the transmission period W is defined as T−Φ, and therefore decreases as the inversion period Φ increases. The input period T1 increases linearly as the output period T2 increases from the relationship of Equation (2). The output period T2 increases linearly with an increase in the inversion period Φ from the relationship of Equation (3).

However, since the output period T2 is included in the transmission period W, the transmission period W is the upper limit of the output period T2. Therefore, when the inversion period Φ increases by a certain amount or more, the output period T2 decreases together with the transmission period W while matching the transmission period W. FIG. Since the offset current Ioff increases as the inversion period Φ increases, the instantaneous output current Iout increases. However, as the output period T2 decreases, the period during which the output current Iout can be output becomes shorter, so the average output current Iout in the period T decreases. Therefore, as shown in FIG. 6A, after the inversion period Φ exceeds the maximum output period Φs, the output current Iout tends to decrease. In this case, a divergence occurs between the output current Iout derived from Equation (1) and the output current Iout that is actually output. That is, when the inversion period Φ becomes longer than the maximum output period Φs, the output current Iout corresponding to the inversion period Φ derived in step S102 is the output current Iout corresponding to the predetermined upper limit inversion period Φ1. smaller than Iout.

In other words, when the output period T2 is derived based on the inversion period Φ derived from the target current It, the derived output period T2 may exceed the transmission period W. Therefore, the relationship between the inversion period Φ and the output period T2 based on Equation (3) may not be satisfied.

The maximum output period Φs is the inversion period Φ during which the output current Iout is maximized. Specifically, the maximum output period Φs is the inversion period Φ during which the output current Iout represented by Equation (1) is maximized. Specifically, the maximum output period Φs is represented by the following equation (4).

入力電圧Ｖｉｎ及び出力電圧Ｖｏｕｔは正であるため、最大出力期間Φｓは、Ｔ／４より小さい。したがって、反転期間Φが最大出力期間Φｓより大きくなると、出力電流Ｉｏｕｔが減少する。

Since the input voltage Vin and the output voltage Vout are positive, the maximum output period Φs is less than T/4. Therefore, when the inversion period Φ becomes longer than the maximum output period Φs, the output current Iout decreases.

The upper limit inversion period Φ1 in this embodiment is equal to the maximum output period Φs. Therefore, the upper limit inversion period Φ1 is smaller than T/4.
Therefore, as shown in FIG. 5, the control circuit 50 of the present embodiment determines whether or not the inversion period Φ is less than the upper limit inversion period Φ1 in step S103 after executing the process of step S102. If the determination result of step S103 is negative, the control circuit 50 proceeds to step S104. In step S104, the control circuit 50 changes the inversion period Φ to the upper limit inversion period Φ1, and proceeds to step S107.

On the other hand, if the determination result of step S103 is affirmative, the control circuit 50 proceeds to step S105. In step S105, the control circuit 50 determines whether or not the inversion period Φ derived in step S102 is greater than a predetermined threshold Φ0. If the determination result is affirmative, the control circuit 50 proceeds to step S107. On the other hand, if the determination result is negative, the control circuit 50 proceeds to step S106.

In step S106, the control circuit 50 changes the inversion period Φ derived in step S102 to the threshold Φ0, and proceeds to step S107. The threshold Φ0 can be arbitrarily determined as long as it is smaller than the upper limit of the inversion period Φ1. For example, it is the minimum inversion period Φ that satisfies the soft switching conditions (A) and (B).

When the inversion period Φ is changed in step S104 or step S106, the control circuit 50 changes the input period T1 and the output period T2 derived in step S102 to correspond to the changed inversion period Φ. change.

In step S107, the control circuit 50 determines the switching mode of each of the switching elements Q1 to Q8 based on the inversion period Φ and both periods T1 and T2 derived in step S102, step S104, or step S106. Specifically, the control circuit 50 controls the phase difference between the full bridge circuits 30 and 40 and the switching elements Q1 to Q4 and Q5 to Q8 so that the derived inversion period Φ and both periods T1 and T2 are obtained. Determine the duty ratio. It can be said that the control circuit 50 determines the setting periods of the switching patterns P1 to P8 so that the inversion period Φ and both periods T1 and T2 derived in step S102 are obtained. When the inversion period Φ is changed in step S104 or step S106, the inversion period Φ and both periods T1 and T2 after the change are used as the derived inversion period Φ and both periods T1 and T2.

After that, the control circuit 50 proceeds to step S108, and performs switching control of the switching elements Q1 to Q8 in the switching mode determined in step S107. At this time, since the inversion period Φ is limited to the upper limit inversion period Φ1, the control circuit 50 controls the primary side switching elements Q1 to Q4 so that the inversion period Φ is equal to or less than the predetermined upper limit inversion period Φ1. and the secondary side switching elements Q5 to Q8.

<Action>
Next, the operation of this embodiment will be described.
As shown in FIG. 6, the inversion period Φ is limited to the upper limit inversion period Φ1. The upper limit inversion period Φ1 is less than T/4. This avoids a situation in which the inversion period Φ becomes longer than the upper-limit inversion period Φ1 in an attempt to increase the output current Iout, thereby reducing the output current Iout.

<effect>
Next, the effects of this embodiment will be described.
(1) The power conversion device 10 includes a transformer 20 having a primary winding 22 and a secondary winding 23, a primary side full bridge circuit 30, a secondary side full bridge circuit 40, and a control circuit 50. , is equipped with

The primary side full bridge circuit 30 is connected to the primary side winding 22 . The primary side full bridge circuit 30 includes a plurality of primary side switching elements Q1 to Q4.
The secondary side full bridge circuit 40 is connected to the secondary side winding 23 . The secondary side full bridge circuit 40 includes a plurality of secondary side switching elements Q5-Q8.

The control circuit 50 has a PWM control mode as a control mode for periodically controlling the switching elements Q1-Q8. The PWM control mode is a control mode in which at least one of the primary side voltage V1 input to the primary side winding 22 and the secondary side voltage V2 input to the secondary side winding 23 is switched to positive, negative, or zero. is. The PWM control mode is composed of an inversion period Φ during which the polarities of the primary side voltage V1 and the secondary side voltage V2 are reversed, and a transmission period W. FIG.

The transmission period W includes an output period T2 during which the secondary voltage V2 is positive or negative.
In the PWM control mode, the control circuit 50 controls the primary side switching elements Q1 to Q4 and the secondary side switching elements Q5 to Q8 so that the inversion period Φ is equal to or less than a predetermined upper limit inversion period Φ1.

In such a configuration, the upper limit inversion period Φ1 is smaller than T/4, where T is the period for controlling the primary side switching elements Q1 to Q4 and the secondary side switching elements Q5 to Q8.
According to such a configuration, in the PWM control mode, the output current Iout is not maximized when the inversion period Φ is T/4, but is maximized during the maximum output period Φs smaller than T/4. Therefore, when the inversion period Φ becomes longer than the maximum output period Φs, the output current Iout decreases.

In this regard, in the present embodiment, the switching elements Q1 to Q8 are controlled so that the inversion period Φ is equal to or less than the upper limit inversion period Φ1, which is smaller than T/4. As a result, it is possible to prevent the output current Iout from decreasing by lengthening the inversion period Φ in order to increase the output current Iout.

(2) PWM control mode is a two-sided PWM control mode in which the primary side voltage V1 switches to positive, negative, or zero, and the secondary side voltage V2 switches to positive, negative, or zero.
According to this configuration, voltage conversion can be performed regardless of the magnitude relationship between the input voltage Vin and the output voltage Vout by adopting the double-sided PWM control mode as the control mode. This eliminates the need to switch between different control modes according to the magnitude relationship between the input voltage Vin and the output voltage Vout, thereby reducing the complexity of control associated with changes in the magnitude relationship between the input voltage Vin and the output voltage Vout.

(3) The upper limit inversion period Φ1 is equal to or less than the maximum output period Φs during which the output current Iout output from the secondary side full bridge circuit 40 is maximized.
According to such a configuration, since the upper limit inversion period Φ1 is equal to or less than the maximum output period Φs, the output current Iout increases while the derived inversion period Φ increases to the upper limit inversion period Φ1. On the other hand, when the derived inversion period Φ becomes longer than the upper limit inversion period Φ1, the inversion period Φ is limited to the upper limit inversion period Φ1 that is equal to or less than the maximum output period Φs. Therefore, it is possible to suppress a decrease in the output current Iout due to an increase in the inversion period Φ from the maximum output period Φs.

In particular, in this embodiment, since the upper limit inversion period Φ1 is the maximum output period Φs, the output current Iout can be brought as close as possible to the target current It.
(4) The power converter 10 includes a plurality of capacitors C1 to C8 connected in parallel to the plurality of primary side switching elements Q1 to Q4 and the plurality of secondary side switching elements Q5 to Q8.

According to such a configuration, the capacitors C1 to C8 are charged and discharged in accordance with the switching of the switching pattern, thereby reducing the switching loss when the switching elements Q1 to Q8 perform soft switching.

<Modification>
The above embodiment can be implemented with the following modifications. The embodiments and the following modifications can be implemented in combination with each other within a technically consistent range.

○ The control circuit 50 may include a correspondence table in which the target current It and the inversion period Φ are associated. In this case, the control circuit 50 may derive the inversion period Φ corresponding to the target current It by referring to the correspondence table.

In the correspondence table, the inversion period Φ is defined within a range from zero to the upper limit inversion period Φ1 or less, and the target current It is defined within a range from zero to the maximum value of the output current Iout or less.

When the target current It is greater than the maximum value of the target current It in the correspondence table, the control circuit 50 sets the inversion period Φ to the upper limit inversion period Φ1 (for example, the maximum value of the inversion period Φ set in the correspondence table). An output period Φs) may be set to perform switching control. Even in this case, it can be said that the inversion period Φ is controlled to be equal to or less than the upper limit inversion period Φ1. In short, if the derived inversion period Φ is set in advance to be equal to or less than the upper limit inversion period Φ1, the control circuit 50 does not need to change the inversion period Φ to the upper limit inversion period Φ1.

(circle) the process which the control circuit 50 performs is an example to the last, and is not restricted to the thing in embodiment. For example, the control circuit 50 may obtain the target current It directly from the load control device 121 without deriving the target current It from the required power Pr. Further, for example, the control circuit 50 may perform the determination of step S103 after performing the determination of step S105.

○ The primary side full bridge circuit 30 and the secondary side full bridge circuit 40 do not have to have the capacitors C1 to C8, respectively. Also, the capacitance of each capacitor C1 to C8 may be different.

O The upper limit inversion period Φ1 may be a value smaller than the maximum output period Φs. For example, the upper limit inversion period Φ1 may be a value smaller than the maximum output period Φs by the threshold Φ0. In other words, the upper limit inversion period Φ1 may have a value corresponding to the maximum output period Φs.

O The operation mode of the control circuit 50 is not limited to the double-sided PWM control mode. For example, the operation mode of the control circuit 50 is such that either one of the primary side voltage V1 or the secondary side voltage V2 is switched to positive or negative, and the other of the primary side voltage V1 or the secondary side voltage V2 is positive, It may also switch to negative or zero. For example, in the PWM control mode in which the primary side voltage V1 switches between positive and negative, the periods of the fourth pattern P4 and the eighth pattern P8 are zero. Also, in the case of the PWM control mode in which the secondary voltage V2 is switched between positive and negative, the periods of the second pattern P2 and the sixth pattern P6 are zero. In short, the operation mode of the control circuit 50 should be a PWM control mode in which at least one of the primary side voltage V1 and the secondary side voltage V2 is switched to positive, negative or zero.

(circle) the power converter 10 may perform a bidirectional voltage conversion. In this case, the voltage input to the secondary side full bridge circuit 40 may be the input voltage Vin, and the voltage output from the primary side full bridge circuit 30 may be the output voltage Vout. At this time, for example, the switching patterns P1 to P8 may be obtained by replacing the primary side switching elements Q1 to Q4 with the secondary side switching elements Q5 to Q8.

○ The load 120 is not limited to a power storage device, and may be a drive device driven at a target voltage, for example. In this case, the load controller 121 transmits the requested current and the requested voltage to the control circuit 50 . The control circuit 50 preferably controls the switching elements Q1 to Q8 so that the soft switching conditions are satisfied within a range in which the output voltage Vout is the required voltage and the output current Iout is the required current.

DESCRIPTION OF SYMBOLS 10... Power converter, 20... Transformer, 22... Primary side winding, 23... Secondary side winding, 30... Primary side full bridge circuit, 40... Secondary side full bridge circuit, 50... Control circuit, C1 ~ C8 ... capacitor, Iout ... output current, Q1 to Q4 ... primary side switching element, Q5 to Q8 ... secondary side switching element, T ... period, T2 ... output period, V1 ... primary side voltage, V2 ... secondary side voltage, Vin... input voltage, Vout... output voltage, W... transmission period, Φ... inversion period, Φ1... upper limit inversion period, Φs... maximum output period.

Claims (4)

a transformer having a primary winding and a secondary winding;
a primary side full bridge circuit connected to the primary side winding and having a plurality of primary side switching elements;
a secondary side full bridge circuit connected to the secondary side winding and having a plurality of secondary side switching elements;
By controlling the plurality of primary side switching elements and the plurality of secondary side switching elements, an input voltage input to the primary side full bridge circuit is an output voltage output from the secondary side full bridge circuit. a control circuit that converts to
The control circuit is
As a control mode for periodically controlling the plurality of primary-side switching elements and the plurality of secondary-side switching elements, a primary-side voltage input to the primary-side winding or input to the secondary-side winding with a PWM control mode in which at least one of the secondary voltages applied is switched to positive, negative or zero,
A half cycle of the PWM control mode is composed of an inversion period in which the polarities of the primary voltage and the secondary voltage are inverted, and a transmission period,
the transmission period includes an output period in which the secondary voltage is positive or negative;
wherein, in the PWM control mode, the control circuit controls the primary side switching element and the secondary side switching element so that the inversion period is equal to or less than a predetermined upper limit inversion period;
The power conversion device, wherein the upper limit inversion period is shorter than T/4, where T is a period for controlling the primary side switching element and the secondary side switching element. 2. The power conversion of claim 1, wherein the PWM control mode is a double-sided PWM control mode in which the primary side voltage switches to positive, negative or zero and the secondary side voltage switches to positive, negative or zero. Device. 3. The power converter according to claim 1, wherein said upper limit inversion period is equal to or less than a maximum output period during which an output current output from said secondary side full bridge circuit is maximized. 4. The power converter according to claim 1, comprising a plurality of capacitors connected in parallel to said plurality of primary side switching elements and said plurality of secondary side switching elements.

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