[go: up one dir, main page]

JP2023015669A - semiconductor equipment - Google Patents

semiconductor equipment Download PDF

Info

Publication number
JP2023015669A
JP2023015669A JP2021119587A JP2021119587A JP2023015669A JP 2023015669 A JP2023015669 A JP 2023015669A JP 2021119587 A JP2021119587 A JP 2021119587A JP 2021119587 A JP2021119587 A JP 2021119587A JP 2023015669 A JP2023015669 A JP 2023015669A
Authority
JP
Japan
Prior art keywords
electrode
main
main portion
semiconductor substrate
main electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2021119587A
Other languages
Japanese (ja)
Other versions
JP7656258B2 (en
Inventor
裕規 伊藤
Hironori Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP2021119587A priority Critical patent/JP7656258B2/en
Publication of JP2023015669A publication Critical patent/JP2023015669A/en
Application granted granted Critical
Publication of JP7656258B2 publication Critical patent/JP7656258B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Figure 2023015669000001

【課題】電界集中を抑制しつつチップサイズを小型にした半導体装置を提供する。
【解決手段】半導体装置は、ソース電極の主部11aを挟むように互いに隣り合う制御電極(ゲート電極)の主部13aを接続する第1の接続部13bの外側において、主部11a上・ドレイン電極の主部12a上並びに主部13aを覆う絶縁膜下で主部12a同志を接続する接続部を有さず、絶縁膜上に設けられた接続配線を介して隣り合う主部12a同士を電気的に接続する。
【選択図】図1

Figure 2023015669000001

A semiconductor device having a reduced chip size while suppressing electric field concentration is provided.
Kind Code: A1 In a semiconductor device, a main portion 11a on the main portion 11a of the main portion 11a of the main portion 11a of the main portion 11a of the main portion 11a of the main portion 11a of the main portion 11a of the main portion 11a of the main portion 11a of the main portion 11a of the main portion 11a of the control electrode (gate electrode). There is no connecting portion for connecting the main portions 12a on the main portion 12a of the electrode and under the insulating film covering the main portion 13a, and the main portions 12a adjacent to each other are electrically connected via the connection wiring provided on the insulating film. connect effectively.
[Selection drawing] Fig. 1

Description

本発明は、半導体装置に関し、特に、半導体基板上に複数の主電極と複数の主電極間に制御電極を有する​半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of main electrodes on a semiconductor substrate and control electrodes between the plurality of main electrodes.

ソース電極とドレイン電極が半導体基板上に互いに入り組んだ櫛型構造が、トランジスタの電極構造に採用されている。このトランジスタの電極構造では、櫛型形状のソース電極と、櫛型形状のドレイン電極と、それらの間を流れる電流を制御する制御電極とが配置されている。このような交差指状に配置された電極構造を有する横型半導体装置の耐圧を向上するために、種々の構造が提案されている。例えば、櫛型電極の直線部分の電極間の距離よりも先端部分の電極間の距離を広くすることで、電極の先端部分での電界集中を緩和する構造が提示されている(例えば、特許文献1参照。)。
また櫛型形状のソース電極と、ソース電極と交差指状に配置された櫛型形状のドレイン電極と、ソース電極とドレイン電極20との間に配置されたゲート電極とを備え、ソース電極の先端部分に沿って延伸するゲート電極の湾曲部分の曲率半径が、ソース電極の他の先端部分においてよりも、ソース電極の最外部の 先端部分において大きい構造が提示されている(例えば、特許文献2参照。)。
A comb-shaped structure in which a source electrode and a drain electrode are intertwined on a semiconductor substrate is adopted as an electrode structure of a transistor. In the electrode structure of this transistor, a comb-shaped source electrode, a comb-shaped drain electrode, and a control electrode for controlling current flowing therebetween are arranged. Various structures have been proposed in order to improve the withstand voltage of a lateral semiconductor device having such an interdigitated electrode structure. For example, a structure has been proposed in which the electric field concentration at the tips of the comb-shaped electrodes is alleviated by making the distance between the electrodes at the tips wider than the distance between the electrodes in the straight parts (see, for example, Patent Document 1.).
It also has a comb-shaped source electrode, a comb-shaped drain electrode arranged in a crossing finger shape with respect to the source electrode, and a gate electrode arranged between the source electrode and the drain electrode 20 . A structure has been proposed in which the curvature radius of the curved portion of the gate electrode extending along the portion is larger at the outermost tip portion of the source electrode than at other tip portions of the source electrode (see, for example, Patent Document 2). .).

特開2013-98222号公報JP 2013-98222 A 特開2017-147264号公報JP 2017-147264 A

しかしながら、ゲート電極の曲率半径を大きくすることで、半導体装置が大きくなってしまう。 However, increasing the radius of curvature of the gate electrode increases the size of the semiconductor device.

本発明は上記事情に鑑みてなされたものであり、その目的とするところは、電界集中を抑制しつつチップサイズを小型にした半導体装置を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which electric field concentration is suppressed and the chip size is reduced.

上記課題を解決するため、1または複数の実施形態に係る半導体装置は、半導体基板と、半導体基板上に設けられ、第1の方向に延伸する第1の主電極と、半導体基板上に設けられ、第1の方向と異なる第2の方向に延伸し、隣り合う第1の主電極の互いの一方の端を接続する第1の主電極の接続部と、半導体基板上に設けられ、前記第1の主電極から離間して第1の方向に延伸する第2の主電極と、半導体基板上に設けられ、前記第1の主電極と第2の主電極との間に形成された制御電極と、半導体基板上に設けられ、第1の主電極の他方の端よりも外側であって隣り合う制御電極の互いの一方の端を接続する制御電極の第1の接続部と、半導体基板上に設けられ、第1の主電極の接続部と第2の主電極との間において隣り合う制御電極の互いの他端を接続する制御電極の第2の接続部と、第1の主電極上、第2の主電極上、並びに制御電極上に設けられた絶縁膜と、第1の接続部の外側に隣り合う第2の主電極同志を接続する接続部を絶縁膜下に有さず、絶縁膜上に設けられた接続配線を介して隣り合う第2の主電極を電気的に接続することを特徴とする。 In order to solve the above problems, a semiconductor device according to one or more embodiments includes a semiconductor substrate, a first main electrode provided on the semiconductor substrate and extending in a first direction, and a main electrode provided on the semiconductor substrate. , a first main electrode connection portion extending in a second direction different from the first direction and connecting one ends of adjacent first main electrodes to each other; a second main electrode spaced from one main electrode and extending in a first direction; and a control electrode provided on a semiconductor substrate and formed between the first main electrode and the second main electrode. a first connecting portion of the control electrode provided on the semiconductor substrate and connecting one ends of adjacent control electrodes outside the other end of the first main electrode to each other; a second connection portion of the control electrode provided between the connection portion of the first main electrode and the second main electrode to connect the other ends of the adjacent control electrodes; , the insulating film provided on the second main electrode and on the control electrode does not have a connecting part under the insulating film for connecting the second main electrodes adjacent to each other outside the first connecting part, Adjacent second main electrodes are electrically connected via a connection wiring provided on the insulating film.

上記構成によれば、電界集中を抑制しつつチップサイズを小型にした半導体装置を提供することできる。 According to the above configuration, it is possible to provide a semiconductor device with a reduced chip size while suppressing electric field concentration.

図1は、1または複数の実施形態に係る半導体装置の平面図である。FIG. 1 is a plan view of a semiconductor device according to one or more embodiments. 図2は、1または複数の実施形態に係る半導体装置の平面図の変形例である。FIG. 2 is a modified plan view of a semiconductor device according to one or more embodiments. 図3は、1または複数の実施形態に係る半導体装置の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device according to one or more embodiments.

図面を参照しながら、1または複数の実施形態について詳細に説明する。以下の図面の記載において、同一または類似の部分には同一または類似の符号を付す場合がある。図面の記載は模式的なものであり、厚みと寸法の関係、各層の厚みの比率等は一例であり、発明の技術思想を限定するものではない。また、図面相互間においても互いの寸法の関係や比率が異なる場合がある。以下の実施形態では、第1導電型がn型、第2導電型がp型の場合について例示的に説明するが、導電型を逆の関係に選択して、第1導電型がp型、第2導電型がn型の場合としてもよい場合がある。以下の説明で、部材の位置関係を説明する際に、「上部」、「下部」、「右側」、「左側」等は参照する図面の向きに基づいて必要に応じて使用されるが、発明の技術思想を限定するものではない。また、「上部」、「下部」、「右側」、「左側」等の説明は部材が接していなくて用いられる場合がある。 The details of one or more embodiments are described with reference to the drawings. In the following description of the drawings, the same or similar parts may be given the same or similar reference numerals. The descriptions in the drawings are schematic, and the relationship between thickness and dimensions, the thickness ratio of each layer, and the like are examples, and do not limit the technical idea of the invention. In addition, there are cases where mutual dimensional relationships and ratios are different between drawings. In the following embodiments, a case where the first conductivity type is n-type and the second conductivity type is p-type will be exemplified. In some cases, the second conductivity type may be n-type. In the following description, when describing the positional relationship of members, "upper", "lower", "right", "left", etc. will be used as necessary based on the orientation of the drawing to which reference is made. It does not limit the technical idea of Also, descriptions such as "upper", "lower", "right", and "left" may be used when the members are not in contact with each other.

図1は半導体装置1の平面図である。半導体装置1は半導体基板10上に、第1の主電極として例えばソース電極11,第2の主電極として例えばドレイン電極12が形成されている。更に、ソース電極11とドレイン電極12との間を流れる電流を制御する制御電極13が半導体基板10上に形成されている。 FIG. 1 is a plan view of a semiconductor device 1. FIG. The semiconductor device 1 has a first main electrode such as a source electrode 11 and a second main electrode such as a drain electrode 12 formed on a semiconductor substrate 10 . Further, a control electrode 13 for controlling current flowing between the source electrode 11 and the drain electrode 12 is formed on the semiconductor substrate 10 .

半導体基板10は例えば窒化物系半導体からなり、半導体基板10内に周知の2次元電子ガス層が生じている。ソース電極11並びにドレイン電極12は2次元電子ガス層と低抵抗接続し、2次元電子ガス層を制御電極13で制御することで、半導体装置をオン/オフさせている。 The semiconductor substrate 10 is made of, for example, a nitride-based semiconductor, and a well-known two-dimensional electron gas layer is generated within the semiconductor substrate 10 . The source electrode 11 and the drain electrode 12 are connected to the two-dimensional electron gas layer with low resistance, and the control electrode 13 controls the two-dimensional electron gas layer to turn on/off the semiconductor device.

ソース電極11は主部11aと接続部11bを備える。ソース電極11の主部11aは一方の方向に延伸し、隣り合うソース電極11の主部11aの一方の端は一方の方向と交差する方向である他方の方向に延伸する接続部11bを介して互いに接続している。ソース電極11の主部11aの他方の端は接続部が設けられておらず、ソース電極11の端となっている。 The source electrode 11 has a main portion 11a and a connecting portion 11b. The main portion 11a of the source electrode 11 extends in one direction, and one end of the main portion 11a of the adjacent source electrode 11 extends in the other direction intersecting the one direction via the connection portion 11b. connected to each other. The other end of the main portion 11 a of the source electrode 11 is not provided with a connecting portion and serves as the end of the source electrode 11 .

ドレイン電極12は一方の方向に延伸する主部12aを備える。ドレイン電極12の主部12aの幅(図1の幅y)はソース電極11の主部11aの幅(図1の幅x)よりも広い。ドレイン電極12の主部12aの両端には、隣り合うドレイン電極12の主部12aを接続する接続部が半導体基板上に形成されておらず、ドレイン電極12の上方に形成された絶縁膜内の貫通孔内並びに絶縁膜上に形成された配線を通じて、隣り合うドレイン電極12を接続している。 The drain electrode 12 has a main portion 12a extending in one direction. The width of the main portion 12a of the drain electrode 12 (width y in FIG. 1) is wider than the width of the main portion 11a of the source electrode 11 (width x in FIG. 1). At both ends of the main portion 12a of the drain electrode 12, a connection portion for connecting the main portion 12a of the adjacent drain electrode 12 is not formed on the semiconductor substrate, and the insulating film formed above the drain electrode 12 has a connection portion. Adjacent drain electrodes 12 are connected through wiring formed in the through holes and on the insulating film.

制御電極(ゲート電極)13の主部13aは一方の方向に延伸している。ソース電極11の主部11aを挟むように隣り合う制御電極(ゲート電極)13の主部13aは、ソース電極11の主部11aの他方の端よりも外側から、第1の接続部13bで接続する。第1の接続部13bは半導体基板1上に備える。また、ドレイン電極12の主部12aを挟むように隣り合う制御電極(ゲート電極)13の主部13aは、ソース電極11の接続部11bとドレイン電極12との間を第2の接続部13cで接続する。第2の接続部13cは半導体基板1上に備える。 A main portion 13a of the control electrode (gate electrode) 13 extends in one direction. The main portions 13a of the control electrodes (gate electrodes) 13 adjacent to each other with the main portion 11a of the source electrode 11 interposed therebetween are connected by a first connecting portion 13b from the outside of the other end of the main portion 11a of the source electrode 11. do. A first connection portion 13 b is provided on the semiconductor substrate 1 . In addition, the main portion 13a of the control electrode (gate electrode) 13, which is adjacent to the main portion 12a of the drain electrode 12, is connected to the connection portion 11b of the source electrode 11 and the drain electrode 12 by the second connection portion 13c. Connecting. A second connection portion 13 c is provided on the semiconductor substrate 1 .

半導体装置1によれば、半導体基板2上にドレイン電極12の接続部を設けていないので、半導体基板2のチップサイズが大きくなることを抑制することができる。また、制御電極(ゲート電極)13の第1の接続部13bの曲率は大きくなってしまうが、接続部13bと対向するようにドレイン電極12の接続部を設けていないので、制御電極(ゲート電極)13とドレイン電極12の距離を確保しやすくなり、電界集中を抑制することができる。 According to the semiconductor device 1, since the connecting portion of the drain electrode 12 is not provided on the semiconductor substrate 2, it is possible to suppress the chip size of the semiconductor substrate 2 from increasing. In addition, although the curvature of the first connection portion 13b of the control electrode (gate electrode) 13 becomes large, the connection portion of the drain electrode 12 is not provided so as to face the connection portion 13b. ) 13 and the drain electrode 12, and electric field concentration can be suppressed.

また、ソース電極11の主部11aから制御電極(ゲート電極)13の主部13aまでの距離は、制御電極(ゲート電極)13の主部13aからドレイン電極12の主部12aまでの距離よりも短くなっている。第1の接続部13bの曲率は第2の接続部13cの曲率よりも大きくなっていることが望ましい。これにより、第1の接続部13bで電界集中することを和らげることができる。もし第1の接続部13bの外側にドレイン電極12の接続部が設けられていると、その曲率に応じてドレイン電極12の接続部は外側へと移設又はパターン変更をしなければならなくなり、チップサイズがより大きくなってしまう。しかし、半導体装置1は半導体基板2上にドレイン電極12の接続部を設けていないので、電界集中を抑制しつつ、半導体基板2のチップサイズが大きくなることを抑制することができる。 The distance from the main portion 11a of the source electrode 11 to the main portion 13a of the control electrode (gate electrode) 13 is longer than the distance from the main portion 13a of the control electrode (gate electrode) 13 to the main portion 12a of the drain electrode 12. It's getting shorter. It is desirable that the curvature of the first connecting portion 13b is larger than the curvature of the second connecting portion 13c. As a result, electric field concentration at the first connecting portion 13b can be alleviated. If the connection portion of the drain electrode 12 is provided outside the first connection portion 13b, the connection portion of the drain electrode 12 must be moved to the outside or the pattern thereof changed according to the curvature thereof, and the chip size becomes larger. However, since the semiconductor device 1 does not have a connecting portion for the drain electrode 12 on the semiconductor substrate 2, it is possible to suppress the increase in the chip size of the semiconductor substrate 2 while suppressing electric field concentration.

また、ドレイン電極12の主部12aの一方の方向の寸法よりもソース電極11の主部11aの一方の方向の寸法は長く、ソース電極11の主部11aの他端はドレイン電極12の主部12aの端より突出(図2のzの寸法だけ突出)していることが望ましい。半導体基板2上にドレイン電極12の接続部を設けていないので、突出させることで、制御電極(ゲート電極)13の第1の接続部13bは外側へと移設され、制御電極(ゲート電極)13の第1の接続部13bとドレイン電極12の主部12aの端との距離をより確保することができる。 The dimension in one direction of the main portion 11a of the source electrode 11 is longer than the dimension in one direction of the main portion 12a of the drain electrode 12, and the other end of the main portion 11a of the source electrode 11 is It is desirable that it protrudes from the end of 12a (by the dimension z in FIG. 2). Since the connecting portion of the drain electrode 12 is not provided on the semiconductor substrate 2, the first connecting portion 13b of the control electrode (gate electrode) 13 is moved to the outside by protruding, so that the control electrode (gate electrode) 13 The distance between the first connection portion 13b of the drain electrode 12 and the end of the main portion 12a of the drain electrode 12 can be further ensured.

上述の1または複数の実施例は窒化物半導体に限らず、シリコンやシリコンカーバイドなど他の半導体材料の半導体基板を含む半導体装置に適用可能である。 One or more of the embodiments described above are applicable not only to nitride semiconductors, but also to semiconductor devices including semiconductor substrates of other semiconductor materials such as silicon and silicon carbide.

上記のように実施形態を記載したが、この開示の一部をなす論述及び図面は本発明を限定するものではなく、当業者は様々な代替実施形態、実施例及び運用技術が明らかとなろう。このように、本発明はここでは記載されていない様々な実施形態等を含む。したがって、本発明の技術的範囲は上記の説明から妥当な特許請求の範囲に係る発明特定事項によって定められるものである。 Although embodiments have been described as above, the discussion and drawings forming part of this disclosure are not intended to limit the invention, and various alternative embodiments, examples and operational techniques will become apparent to those skilled in the art. . Thus, the present invention includes various embodiments and the like not described here. Therefore, the technical scope of the present invention is defined by the matters specifying the invention according to the scope of claims that are valid from the above description.

本発明は、特にパワー半導体装置に適用可能である。 The invention is particularly applicable to power semiconductor devices.

1 半導体装置
10 半導体基板
11 ソース電極
12 ドレイン電極
13 制御電極
1 semiconductor device 10 semiconductor substrate 11 source electrode 12 drain electrode 13 control electrode

Claims (2)

半導体基板と、
前記半導体基板上に設けられ、第1の方向に延伸する第1の主電極と、
前記半導体基板上に設けられ、第1の方向と異なる第2の方向に延伸し、隣り合う第1の主電極の互いの一方の端を接続する第1の主電極の接続部と、
前記半導体基板上に設けられ、前記第1の主電極から離間して第1の方向に延伸する第2の主電極と、
前記半導体基板上に設けられ、前記第1の主電極と前記第2の主電極との間に形成された制御電極と、
前記半導体基板上に設けられ、第1の主電極の他方の端よりも外側であって、隣り合う制御電極の互いの一方の端を接続する制御電極の第1の接続部と、
半導体基板上に設けられ、前記第1の主電極の接続部と前記第2の主電極との間において、隣り合う制御電極の互いの他端を接続する制御電極の第2の接続部と、
前記第1の主電極上、前記第2の主電極上、並びに前記制御電極上に設けられた絶縁膜と、
前記第1の接続部の外側に隣り合う第2の主電極同志を接続する接続部を前記絶縁膜下に有さず、前記絶縁膜上に設けられた接続配線を介して隣り合う前記第2の主電極を電気的に接続することを特徴とする半導体装置。
a semiconductor substrate;
a first main electrode provided on the semiconductor substrate and extending in a first direction;
a first main electrode connection portion provided on the semiconductor substrate, extending in a second direction different from the first direction, and connecting one ends of adjacent first main electrodes to each other;
a second main electrode provided on the semiconductor substrate and spaced from the first main electrode and extending in a first direction;
a control electrode provided on the semiconductor substrate and formed between the first main electrode and the second main electrode;
a first connection portion of the control electrode provided on the semiconductor substrate, outside the other end of the first main electrode, and connecting one ends of adjacent control electrodes to each other;
a second connection portion of the control electrode provided on the semiconductor substrate and connecting the other ends of adjacent control electrodes between the connection portion of the first main electrode and the second main electrode;
an insulating film provided on the first main electrode, the second main electrode, and the control electrode;
The second main electrodes adjacent to each other through a connection wiring provided on the insulating film without a connecting portion for connecting the adjacent second main electrodes outside the first connecting portion under the insulating film. and electrically connecting the main electrodes of the semiconductor device.
前記第2の主電極の第1の方向の長さは、前記第1の主電極の第1の方向の長さよりも短いことを特徴とする請求項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the length of said second main electrode in the first direction is shorter than the length of said first main electrode in the first direction.
JP2021119587A 2021-07-20 2021-07-20 Semiconductor Device Active JP7656258B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2021119587A JP7656258B2 (en) 2021-07-20 2021-07-20 Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2021119587A JP7656258B2 (en) 2021-07-20 2021-07-20 Semiconductor Device

Publications (2)

Publication Number Publication Date
JP2023015669A true JP2023015669A (en) 2023-02-01
JP7656258B2 JP7656258B2 (en) 2025-04-03

Family

ID=85131209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021119587A Active JP7656258B2 (en) 2021-07-20 2021-07-20 Semiconductor Device

Country Status (1)

Country Link
JP (1) JP7656258B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012238809A (en) * 2011-05-13 2012-12-06 Sharp Corp Field-effect transistor
JP2012238808A (en) * 2011-05-13 2012-12-06 Sharp Corp Field-effect transistor
JP2013098222A (en) * 2011-10-28 2013-05-20 Sanken Electric Co Ltd Nitride semiconductor device
WO2016098391A1 (en) * 2014-12-18 2016-06-23 シャープ株式会社 Field effect transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012238809A (en) * 2011-05-13 2012-12-06 Sharp Corp Field-effect transistor
JP2012238808A (en) * 2011-05-13 2012-12-06 Sharp Corp Field-effect transistor
JP2013098222A (en) * 2011-10-28 2013-05-20 Sanken Electric Co Ltd Nitride semiconductor device
WO2016098391A1 (en) * 2014-12-18 2016-06-23 シャープ株式会社 Field effect transistor

Also Published As

Publication number Publication date
JP7656258B2 (en) 2025-04-03

Similar Documents

Publication Publication Date Title
JP4301462B2 (en) Field effect transistor
JP4689977B2 (en) Lateral power MOSFET for high switching speed
CN102893392B (en) Adopt the high-density gallium nitride device of island topology
CN103229284B (en) Nitride semiconductor device
JP6348703B2 (en) Semiconductor device and manufacturing method thereof
CN100524824C (en) High voltage semiconductor device and method for fabricating the same
JP2015032600A (en) Semiconductor device
US8399937B2 (en) Semiconductor body and method for the design of a semiconductor body with a connecting line
US9236438B2 (en) Semiconductor device
CN117529819A (en) Semiconductor device and power conversion device
CN104347719B (en) Semiconductor device
JP2008141055A (en) Semiconductor device
US20220352368A1 (en) Trench-gate field effect transistor with improved electrical performances and corresponding manufacturing process
JP7629262B2 (en) Semiconductor Device
JP2017220508A (en) Semiconductor device
JP2023015669A (en) semiconductor equipment
KR20070084339A (en) Passivation Scheme with Voltage Equalized Loops
US10937875B2 (en) Semiconductor device
JP7147510B2 (en) switching element
CN101192610A (en) High Voltage Semiconductor Device Structure
CN107180859A (en) Semiconductor structure element, especially power transistor
JP2024157636A (en) Semiconductor Device
US9893015B2 (en) Semiconductor device
CN103681825A (en) Semiconductor device
KR20130077477A (en) Power semiconductor device and method for manufacturing thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20240509

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20250131

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20250220

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20250305

R150 Certificate of patent or registration of utility model

Ref document number: 7656258

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150