JP2023176899A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of ensuring turn-off tolerance by suppressing carrier concentration in an active region near a gate common wiring region or a gate pad region.SOLUTION: In a semiconductor device including a plurality of switching elements, gate common wiring 1 commonly connected to gates of the plurality of switching elements, and a gate pad that supplies power to the gate common wiring 1, a carrier injection suppression region 18 is provided in a gate common wiring region 6 that overlaps with the gate common wiring 1 and in a gate pad region that overlaps with the gate pad.SELECTED DRAWING: Figure 5

Description

The present invention relates to a semiconductor device.

In power semiconductors such as IGBTs, it is necessary to ensure sufficient turn-off tolerance (RBSOA (Reverse Bias Safe Operating Area) tolerance).

For example, Patent Document 1 is known as a technique for improving the blocking ability of an IGBT at turn-off. The structure shown in paragraphs 0120 to 0123, FIGS. 32A, and 32B of Patent Document 1 is a structure that suppresses injection of carriers from the intermediate region (2) of the IGBT to the collector side of the edge termination region (5), In FIG. 32A, the collector layer (16) and metal (29) are in contact with each other in the active cell region (1), and the n-buffer layer (15) is in contact with the metal (29) in the intermediate region (2) and edge termination region (5). The contacting IGBTs are shown in FIG. 32B, with the p-collector layer (16) contacting the metal (29) in the active cell region (1), and the p-collector layer (16) contacting the metal (29) in the intermediate region (2) and edge termination region (5). (16) An IGBT is shown in which a low concentration p collector layer (16') with a lower impurity concentration is in contact with a metal (29), and as a result, the main junction p-n junction exists in the intermediate region (2) during turn-off operation. It is described that it has the effect of moderating the electric field strength of , suppressing a local increase in electric field strength, and suppressing thermal breakdown due to a local temperature rise caused by current concentration due to impact ionization.

International Publication No. 2017/115434

One of the reasons why IGBTs break down during turn-off is that a large amount of carriers such as holes are injected from the termination region during turn-off, resulting in carrier concentration in the periphery of the active region (particularly in the corner region), resulting in concentration of the electric field. This may lead to destruction.

According to the technique disclosed in Patent Document 1, since the injection of carriers from the termination region is suppressed, destruction at the time of turn-off in the peripheral portion of the active region can be suppressed.

However, studies conducted by the inventor of the present application have revealed that carrier injection also occurs from the lower part of the gate common wiring, also called gate finger, and the gate pad, and carrier concentration occurs in the active region near the gate common wiring area and gate pad area. It has been found that this can lead to destruction.

In Patent Document 1, a structure that suppresses carrier injection from the collector side is not adopted in the front gate wiring portion (3) in FIG. 1 of Patent Document 1, which corresponds to the gate common wiring, and this problem cannot be solved. Not yet.

In addition, the inventor of this application found that regardless of the presence or absence of a structure that suppresses carrier injection into the termination region, for example, when the switching speed is high, the gate common wiring region or gate pad is It was found that carrier concentration occurs in the active region near the active region, which can lead to destruction.

The reason for this will be explained using FIGS. 1, 2, and 10 to 12.

1 is a plan view of a semiconductor device, FIG. 2 is an enlarged view of part A of the semiconductor device in FIG. 1, FIG. 10 is a BB' cross-sectional view of a conventional semiconductor device, and FIG. 12 is a DD' cross-sectional view of a conventional semiconductor device, and FIG. 12 is a BB' cross-sectional view of a conventional semiconductor device.

As shown in FIG. 10, when the switching speed is slow, holes 20 in the gate common wiring region 6 overlapping the gate common wiring 1 and the termination region 4 are injected into the active region 3, and carriers are generated in the peripheral part of the active region 3. Concentration occurs. As shown in FIG. 11, holes 20 are also injected into the active region 3 in the gate common wiring region 6 sandwiched between the active regions 3, and carrier concentration occurs in the active region 3 near the gate common wiring region 6. However, as shown in FIG. 10, when the switching speed is slow, a larger amount of holes 20 are injected at the periphery of the active region 3, so destruction is more likely to occur at the periphery of the active region 3.

On the other hand, as shown in FIG. 12, when the switching speed is high, some of the holes 20 in the gate common wiring region 6 and the termination region 4 may be sandwiched between the active regions 3 as shown in FIG. The amount of holes 20 injected from the gate common wiring region 6 may become dominant, and there is a possibility that destruction may occur in the active region 3 near the gate common wiring region 6. Furthermore, since the structure of the gate pad region (not shown) is similar to that of the gate common wiring region 6, there is a possibility that the active region 3 near the gate pad region will be destroyed as well.

Therefore, it has been found that in order to ensure turn-off tolerance, a structure that suppresses carrier injection is required also in the gate common wiring region 6 and the gate pad region.

The problem to be solved by the present invention is to provide a semiconductor device that can suppress carrier concentration in an active region near a gate common wiring region or a gate pad region and ensure turn-off tolerance.

In order to solve the above problems, a semiconductor device of the present invention includes, for example, a plurality of switching elements, a gate common wiring commonly connected to the gates of the plurality of switching elements, and a gate that supplies power to the gate common wiring. The semiconductor device has a carrier injection suppressing region in a gate common wiring region overlapping the gate common wiring and in a gate pad region overlapping the gate pad.

According to the semiconductor device of the present invention, turn-off tolerance can be ensured by suppressing carrier concentration in the active region near the gate common wiring region and the gate pad region.

FIG. 2 is a plan view of a semiconductor device. 2 is an enlarged view of part A of the semiconductor device in FIG. 1. FIG. 3 is a sectional view taken along line B-B' of the semiconductor device of Example 1. FIG. FIG. 2 is a cross-sectional view taken along line CC' of the semiconductor device of Example 1. FIG. 3 is a cross-sectional view taken along line DD' of the semiconductor device of Example 1. FIG. 3 is a cross-sectional view taken along line B-B' of the semiconductor device of Example 2. FIG. 3 is a cross-sectional view taken along line DD' of the semiconductor device of Example 2. FIG. 3 is a cross-sectional view taken along line B-B' of the semiconductor device of Example 3. FIG. 4 is a cross-sectional view taken along line DD' of the semiconductor device of Example 3. B-B' cross-sectional view of a conventional semiconductor device. FIG. 3 is a cross-sectional view taken along line D-D' of a conventional semiconductor device. B-B' cross-sectional view of a conventional semiconductor device.

Embodiments of the present invention will be described below with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and overlapping explanations will be omitted.

1 is a plan view of the semiconductor device, FIG. 2 is an enlarged view of section A of the semiconductor device of FIG. 1, and FIG. 4 is a CC' cross-sectional view of the semiconductor device of Example 1, and FIG. 5 is a DD' cross-sectional view of the semiconductor device of Example 1.

As shown in FIGS. 1 and 2, the semiconductor device 100 includes an active region 3 in which a plurality of switching elements are formed, a gate common wiring 1 commonly connected to gates 5 of the plurality of switching elements, and a gate common wiring 1 and a gate pad 2 that supplies power to the gate pad 1 . The gate common wiring 1 has a portion that divides the active region 3 and a portion formed at the boundary between the active region 3 and the termination region 4.

Note that the gate 5 is not shown in FIG. 1, and the gate electrode 13, emitter electrode 14, and field plate 15 are not shown in FIGS. 1 and 2.

The semiconductor device of Example 1 has an IGBT as a switching element in the active region 3, as shown in FIG. Specifically, the semiconductor device of Example 1 includes a drift layer 7 of a first conductivity type (n type in FIG. 3) and a drift layer 7 of a second conductivity type (p type in FIG. 3) provided on the surface side of the drift layer 7. ), the gate 5 and gate insulating film 10 formed in the trench, the emitter layer 9 of the first conductivity type provided on the front side of the body layer 8, and the back side of the drift layer 7. A collector layer 17 of the second conductivity type is provided.

Although the description is given here assuming that the first conductivity type is n type and the second conductivity type is p type, the first conductivity type may be p type and the second conductivity type may be n type. In that case, the carriers are not holes 20 but electrons.

Further, the semiconductor device of Example 1 includes a first conductivity type buffer layer 16 provided between the drift layer 7 and the collector layer 17, a collector electrode 19 provided on the back side of the collector layer 17, and a body. It has an interlayer insulating film 12 provided on the surface side of the layer 8 and the emitter layer 9, and an emitter electrode 14 that contacts the emitter layer 9 and the body layer 8 through a contact hole provided in the interlayer insulating film 12.

In the semiconductor device of the first embodiment, in the termination region 4, the well layer 11 is connected to the well layer 11 of the second conductivity type provided on the surface side of the drift layer 7 through the contact hole provided in the interlayer insulating film 12. It has a field plate 15 in contact with the field plate 15.

In the semiconductor device of the first embodiment, in the gate common wiring region 6 overlapping the gate common wiring 1, the gate common wiring 1 is connected to the well layer 11, the gate common wiring 1, and the gate common wiring 1 through the contact hole provided in the interlayer insulating film 12. It has a gate electrode 13 in contact with it. Although not shown, the structure of the gate pad region overlapping the gate pad 2 is also substantially the same as that of the gate common wiring region 6.

As shown in FIG. 4, the gate common wiring 1 and the gate 5 are connected, and the gate common wiring 1, the gate 5, and the gate pad 2 are made of polysilicon, for example.

Here, as shown in FIGS. 3 to 5, the semiconductor device of Example 1 has carrier injection suppressing regions 18 in the gate common wiring region 6 and in the gate pad region (not shown). Thereby, carrier concentration in the active region 3 near the gate common wiring region 6 and the gate pad region can be suppressed, and turn-off tolerance can be ensured.

As shown in FIGS. 4 and 5, the carrier injection suppressing region 18 is preferably formed also in the gate common wiring region 6 sandwiched between the divided active regions 3. As a result, carrier concentration in the active region 3 near the gate common wiring region 6 sandwiched between the divided active regions 3 can be suppressed, and turn-off tolerance can be ensured.

Further, as shown in FIG. 3, the carrier injection suppressing region 18 is preferably formed also in the termination region 4. This makes it possible to suppress carrier concentration in the periphery of the active region 3 and ensure turn-off tolerance. Note that if hole injection from the termination region 4 is not dominant, such as when the switching speed is high, for example, the carrier injection suppression region 18 may not be provided in the termination region 4.

In Example 1, an example is shown in which a layer having the same conductivity type as the collector layer 17 and having a lower concentration than the collector layer 17 is used as the carrier injection suppressing region 18 .

Note that the impurity concentration of each semiconductor layer is, for example, a low concentration n-type in the drift layer, a high concentration n+ type in the emitter layer 9, and a low concentration p-type in the carrier injection suppressing region 18.

Example 2 is a modification of Example 1, and differs from Example 1 in the structure of the carrier injection suppression region 18. Other than this, the second embodiment is the same as the first embodiment, so redundant explanation will be omitted.

6 is a sectional view taken along line B-B' of the semiconductor device of Example 2, and FIG. 7 is a sectional view taken along line DD' of the semiconductor device of example 2.

In the carrier injection suppressing region 18 of Example 2, there is no collector layer 17, and a layer having a different conductivity type from the collector layer 17 (here, the buffer layer 16) is in direct contact with the collector electrode 19.

Compared with Example 1, there is an advantage that manufacturing is easy because there is no need to form a low concentration p-type layer on the back side. Other than that, the same effects as in Example 1 can be obtained.

Example 3 is a modification of Example 1, and differs from Example 1 in the structure of the carrier injection suppression region 18. Other than this, the second embodiment is the same as the first embodiment, so redundant explanation will be omitted.

8 is a sectional view taken along line B-B' of the semiconductor device of Example 3, and FIG. 9 is a sectional view taken along line DD' of the semiconductor device of Example 3.

The carrier injection suppression region 18 of Example 3 is a low lifetime region due to light ion irradiation. As light ions, protons, helium, etc. can be used, for example.

In the third embodiment as well, the same effects as in the first embodiment can be obtained.

Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various changes can be made within the scope of the technical idea of the present invention. Further, some or all of the configurations described in each embodiment may be combined and applied.

1 Gate common wiring 2 Gate pad 3 Active region 4 Termination region 5 Gate 6 Gate common wiring region 7 Drift layer 8 Body layer 9 Emitter layer 10 Gate insulating film 11 Well layer 12 Interlayer insulating film 13 Gate electrode 14 Emitter electrode 15 Field plate 16 Buffer layer 17 Collector layer 18 Carrier injection suppression region 19 Collector electrode 20 Hole 100 Semiconductor device

Claims (7)

In a semiconductor device having a plurality of switching elements, a gate common wiring commonly connected to the gates of the plurality of switching elements, and a gate pad supplying power to the gate common wiring,
A semiconductor device comprising a carrier injection suppression region in a gate common wiring region overlapping the gate common wiring and in a gate pad region overlapping the gate pad. In claim 1,
an active region having the plurality of switching elements;
The gate common wiring region has a portion that divides the active region,
The semiconductor device characterized in that the carrier injection suppression region is formed in the gate common wiring region sandwiched between the divided active regions. In claim 1,
has a termination area,
A semiconductor device characterized in that the termination region also has the carrier injection suppression region. In claim 1,
It has a collector layer provided on the back side,
A semiconductor device, wherein the carrier injection suppression region has a layer having the same conductivity type as the collector layer and having a lower concentration than the collector layer. In claim 1,
It has a collector layer provided on the back side and a collector electrode connected to the collector layer,
The semiconductor device is characterized in that the carrier injection suppressing region is a region where the collector layer is absent and a layer having a different conductivity type from the collector layer is in direct contact with the collector electrode. In claim 1,
A semiconductor device, wherein the carrier injection suppression region is a low lifetime region formed by light ion irradiation. In claim 1,
A semiconductor device characterized in that the carrier injection suppression region is a hole injection suppression region.

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