JP2023106098A - Semiconductor device inspection device, learning device, reasoning device, and manufacturing method - Google Patents

Abstract

Kind Code: A1 An object of the present invention is to improve the accuracy of detecting a semiconductor device having a defect that causes element breakdown, compared to electrical characteristic inspection. A model generating unit (7) generates data regarding the quality of a first semiconductor device from learning input data including data regarding at least one defect included in the first semiconductor device by machine learning using learning data. Generate a trained model for inference. The inference data processing unit 10 generates inference input data including data regarding at least one defect included in the second semiconductor device. The inference unit 11 infers data regarding the quality of the second semiconductor device from the inference input data using the trained model. [Selection drawing] Fig. 1

Description

The present disclosure relates to a semiconductor device inspection device, a learning device, an inference device, and a manufacturing method.

In a semiconductor device including an FET (Field Effect Transistor) or the like having a MOS (Metal Oxide Semiconductor) structure on a silicon carbide substrate, if a defect occurs on the silicon carbide substrate, current flows through the defect when the semiconductor device is energized. concentrate. Therefore, the defect can cause element breakdown. In order to prevent such element destruction, the manufacturing process of semiconductor devices requires an inspection process for removing semiconductor devices that may cause element destruction from products to be shipped.

For example, Japanese Patent No. 6471421 (Patent Document 1) discloses a semiconductor device inspection method for removing semiconductor devices that may cause switching failure. In the inspection method, the input/output characteristics (electrical characteristics) of a semiconductor device to which a voltage is input and a current is output are shown. It is specified whether or not the semiconductor device includes a defect from the characteristic curve for which is set. Specifically, a first slope of a straight line connecting two points in a first section set in the middle current section from the minute current of the characteristic curve is calculated, and the first slope of the straight line connecting two points in the first section from the middle current of the characteristic curve to the rated current section of the semiconductor device is calculated. A second slope of a straight line connecting two points in the set second section is calculated, and the first slope and the second slope are compared. When the first slope and the second slope do not match, it is specified that the semiconductor device includes a defect, and when the first slope and the second slope match, the semiconductor device includes a defect. is not specified. According to the inspection method, it is possible to suppress an increase in cost due to inspection and eliminate semiconductor devices that may cause switching failure.

Patent No. 6471421

In the inspection method disclosed in Japanese Patent Laid-Open No. 2002-200012, it is assumed that the presence or absence of a defect in the semiconductor device may not appear as the difference between the first slope and the second slope depending on the current measurement resolution of the inspection device. That is, even though the semiconductor device has a defect that causes element breakdown, the first tilt and the second tilt of the semiconductor device can match in the inspection result. Even in such a semiconductor device, the current during energization may concentrate on the defect and cause element breakdown. Therefore, it is necessary to remove the semiconductor device in the inspection process by increasing the measurement resolution of the inspection apparatus.

In order to increase the measurement resolution of the inspection device, it is necessary to provide a measurement time of 1 second or longer from the input of the input voltage to the measurement of the output current. However, lengthening the measurement time for each semiconductor device manufactured in large quantities results in a huge manufacturing cost. Therefore, in the inspection method disclosed in Patent Document 1 for inspecting the electrical characteristics of a semiconductor device, due to restrictions on manufacturing costs, the difference in the presence or absence of defects appears only in a region smaller than the current measurement resolution. The problem is that the device cannot be removed in the inspection process.

The present disclosure has been made to solve the problems described above, and the purpose thereof is to improve the accuracy of detecting a semiconductor device having a defect that causes element breakdown, compared to electrical property inspection. .

A semiconductor device inspection apparatus according to the present disclosure includes a learning data processing unit, a model generation unit, an inference data processing unit, and an inference unit. The learning data processing unit identifies at least one defect included in the first semiconductor device from defect data relating to defects occurring in the first silicon carbide substrate and positional information of the first semiconductor device formed on the first silicon carbide substrate. and generate learning data in which learning input data including data relating to at least one defect included in the first semiconductor device and teacher data including data relating to the quality of the first semiconductor device are associated. The model generation unit generates a trained model for inferring data regarding the quality of the first semiconductor device from learning input data by machine learning using learning data. The inference data processing unit identifies at least one defect included in the second semiconductor device from defect data relating to defects occurring in the second silicon carbide substrate and positional information of the second semiconductor device formed on the second silicon carbide substrate. and generating inference input data including data relating to at least one defect contained in the second semiconductor device. The inference unit uses the trained model to infer data regarding the quality of the second semiconductor device from the inference input data.

A learning device according to the present disclosure includes a learning data processing unit and a model generation unit. The learning data processing unit identifies at least one defect included in the semiconductor device from defect data relating to defects occurring in the silicon carbide substrate and positional information of the semiconductor device formed on the silicon carbide substrate, and identifies at least one defect included in the semiconductor device. learning data is generated in which input data including data regarding at least one defect included in and teacher data including data regarding the quality of the semiconductor device are associated with each other. The model generator generates a trained model for inferring data on the quality of the semiconductor device from the input data by machine learning using the learning data.

An inference device according to the present disclosure includes an inference data processing unit and an inference unit. The inference data processing unit specifies at least one defect included in the semiconductor device from the defect data regarding the defect occurring in the silicon carbide substrate and the positional information of the semiconductor device formed on the silicon carbide substrate, and identifies at least one defect included in the semiconductor device. generate inference input data including data about at least one defect that The inference unit uses the trained model to infer data regarding the quality of the semiconductor device from the inference input data.

According to a semiconductor device inspection device, a learning device, and an inference device according to the present disclosure, learned data relating to the quality of a semiconductor device is inferred from input data including data relating to at least one defect included in the semiconductor device. By using a model, it is possible to improve the accuracy of detecting a semiconductor device having a defect that causes element breakdown, compared to electrical characteristic inspection.

1 is a block diagram showing the configuration of a semiconductor device inspection apparatus according to a first embodiment; FIG. 2 is a block diagram of the configuration of the learning device in FIG. 1; FIG. 2 is a block diagram of the configuration of the inference device of FIG. 1; FIG. 3 is a diagram showing a neural network as an example of an inference model to be optimized by the model generator in FIG. 2; FIG. 3 is a flow chart showing the flow of learning processing performed in the learning device of FIG. 2; FIG. 4 is a diagram showing defect data including defects occurring in a silicon carbide substrate; 7 is a diagram in which manufacturing position information indicating a position where a semiconductor device is formed on the silicon carbide substrate of FIG. 6 is displayed superimposed in association with defect data; FIG. 8 is a diagram showing relative positions of defects in the semiconductor device of FIG. 7; FIG. FIG. 9 is a cross-sectional view taken along line A1-A2 of FIG. 8; 4 is a flow chart showing the flow of inference processing performed by the inference device and selection unit of FIG. 3; 2 is a block diagram showing the hardware configuration of the semiconductor device inspection apparatus of FIG. 1; FIG. FIG. 10 is a block diagram showing a configuration of a semiconductor device inspection apparatus according to Modification 1 of Embodiment 1; FIG. 9 is a block diagram showing the configuration of a semiconductor device inspection apparatus according to Modification 2 of Embodiment 1; FIG. 11 is a block diagram showing the configuration of a semiconductor device inspection apparatus according to Modification 3 of Embodiment 1; FIG. 12 is a block diagram showing an example of a configuration of a semiconductor device inspection apparatus according to Modification 4 of Embodiment 1; FIG. 12 is a block diagram showing another example of the configuration of the semiconductor device inspection apparatus according to Modification 4 of Embodiment 1; FIG. 11 is a block diagram showing the configuration of a semiconductor device inspection apparatus according to Modification 5 of Embodiment 1; FIG. 18 is a flow chart for explaining the processing flow of the unnecessary data calculation unit in FIG. 17; FIG. FIG. 11 is a block diagram showing the configuration of an inspection apparatus for a semiconductor device according to a second embodiment; 20 is a block diagram of the configuration of the learning device of FIG. 19; FIG. 20 is a block diagram of the configuration of the inference device of FIG. 19; FIG. 4 is a histogram of electrical characteristics previously measured before short-circuit withstand capability measurement of a semiconductor device; FIG. 22 is a histogram of short-circuit tolerance output from the inference unit of FIG. 21; FIG. 21 is a flow chart showing the flow of learning processing performed in the learning device of FIG. 20; FIG. 22 is a flow chart showing the flow of inference processing performed by the inference device and selection unit of FIG. 21; FIG. 10 is a flow chart showing the flow of a method for manufacturing a semiconductor device according to Embodiment 3;

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated in principle.

Embodiment 1.
In the first embodiment, a case where a semiconductor device to be inspected is a power semiconductor formed on a silicon carbide substrate will be described. FIG. 1 is a block diagram showing the configuration of a semiconductor device inspection apparatus 100 according to the first embodiment. As shown in FIG. 1 , semiconductor device inspection apparatus 100 includes teacher data storage unit 6 , learning device 13 , and reasoning device 14 . Each of learning device 13 and reasoning device 14 may be, for example, a device separate from semiconductor device inspection device 100 and connected to semiconductor device inspection device 100 via a network. Also, the learning device 13 and the reasoning device 14 may exist on a cloud server. The teaching data storage unit 6 stores data (data regarding quality) regarding the result of pass/fail determination, which is the result (acceptance or rejection) of the inspection of the semiconductor device to be manufactured.

FIG. 2 is a block diagram of the configuration of the learning device 13 of FIG. As shown in FIG. 2 , the learning device 13 includes a learning data acquisition unit 4 , a learning data processing unit 5 , a model generation unit 7 and a trained model storage unit 8 . The learning data acquisition unit 4 acquires defect data of the silicon carbide substrate (first silicon carbide substrate) from the defect inspection data storage unit 3, and also acquires the semiconductor device formed on the silicon carbide substrate from the dimension information storage unit 30. Acquire the manufacturing position information of (the first semiconductor device). The defect data includes, for example, types of known defects commonly occurring on silicon carbide substrates, such as micropipes, triangular defects, or stacking faults, and the size, angle, or location of the defects. The defect is measured by the silicon carbide substrate defect inspection apparatus 2 and stored in the defect inspection data storage unit 3 . The manufacturing position information of the semiconductor device includes information (position information) on the position on the silicon carbide substrate where the power semiconductor is formed. The learning data acquisition unit 4 outputs the manufacturing position information of the semiconductor device and the defect data to the learning data processing unit 5 .

The learning data processing unit 5 identifies at least one defect contained in the semiconductor device to be manufactured using the manufacturing position information of the semiconductor device and the defect data from the learning data acquisition unit 4, and identifies the at least one defect in the defect data. Manufacturing location information is associated with each of the defects. The learning data processing unit 5 converts feature amounts such as the relative position of each of at least one defect included in the semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into the type into the defect. Give to data. The learning data processing unit 5 acquires the pass/fail determination result (pass or fail) of the inspection of the semiconductor device from the teacher data storage unit 6, and associates the defect data of the semiconductor device with the pass/fail determination result. The learning data processing unit 5 creates learning data including combinations of defect data and pass/fail judgment results (teacher data). The learning data processing unit 5 outputs learning data to the model generation unit 7 .

The model generation unit 7 uses the learning data from the learning data processing unit 5 to learn the relationship between the defect data and the pass/fail judgment results. The model generation unit 7 generates a learned inference model (learned model) for inferring an optimum pass/fail judgment result from defect data and pass/fail judgment results (teacher data) of the semiconductor device. The inference model uses the defect data (learning input data) processed by the learning data processing unit 5 as an input (explanatory variable), and the quality judgment result as an output (objective variable). The model generation unit 7 saves the learned model in the learned model storage unit 8 . Note that the trained model may be a trained model of another semiconductor device or the like optimized by an external learning device different from the learning device 13 .

FIG. 3 is a block diagram of the configuration of the inference device 14 of FIG. As shown in FIG. 3 , the inference device 14 includes an inference data acquisition unit 9 , an inference data processing unit 10 , an inference unit 11 , and a determination unit 12 . The inference data acquisition unit 9 acquires the defect data of the silicon carbide substrate (second silicon carbide substrate) from the defect inspection data storage unit 3, and also acquires the semiconductor device formed on the silicon carbide substrate from the dimension information storage unit 30 ( second semiconductor device) is acquired. The inference data acquisition unit 9 outputs the manufacturing position information and the defect data of the semiconductor device to the inference data processing unit 10 .

The inference data processing unit 10 identifies at least one defect included in the semiconductor device to be manufactured using the semiconductor device manufacturing position information and the defect data from the inference data acquisition unit 9, and identifies the at least one defect. Associate manufacturing location information with each. The inference data processing unit 10 converts the feature amounts of the relative position of each of at least one defect included in the semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into the type into the defect. Give to data. The inference data processing unit 10 outputs the processed defect data to the inference unit 11 .

The inference unit 11 uses the learned model stored in the learned model storage unit 8 to infer the quality judgment result of the semiconductor device from the defect data. That is, the inference unit 11 inputs the defect data (inference input data) processed by the inference data processing unit 10 to the learned model, so that the quality determination probability (probability of good product and probability of defective product) inferred from the defect data. probability) to the determination unit 12 .

Judgment unit 12 specifies the highest probability among the probability of quality judgment output from inference unit 11, judges whether the semiconductor device is a non-defective product or a defective product according to the probability, and sorts the judgment result. Output to unit 23 . Note that the determination method of the determination unit 12 is not limited to the determination method of the first embodiment. For example, the determination method is a method of determining that the semiconductor device is defective unless the probability of the semiconductor device being non-defective exceeds a certain value, or vice versa, by comparing the semiconductor device with a predetermined threshold. A method for judging quality may also be used.

The sorting unit 23 sorts the semiconductor devices into non-defective products or defective products using the determination result from the determining unit 12 .

As a machine learning algorithm used by the model generation unit 7, a known algorithm such as supervised learning, semi-supervised learning, unsupervised learning, or reinforcement learning can be used. In addition, the model generation unit 7 uses deep learning for learning to extract the feature amount itself, genetic programming, functional logic programming, support vector machines, or other known methods such as GBDT (Gradient Boosting Decision Tree). Machine learning may be performed according to the method. A machine learning algorithm using a neural network will be described below as an example of the machine learning algorithm used by the model generation unit 7 .

The model generation unit 7 learns the relationship between the defect data and the pass/fail determination result of the semiconductor device by so-called supervised learning according to, for example, a neural network model. Here, supervised learning means a method of inferring a result from an input by using a set of input and result data (label or correct data) as learning data, learning the features of the learning data, and inferring the result from the input. do. A neural network consists of an input layer made up of multiple neurons, an intermediate layer (hidden layer) made up of multiple neurons, and an output layer made up of multiple neurons. The intermediate layer may comprise one layer, or two or more layers.

FIG. 4 is a diagram showing a neural network Nw1, which is an example of an inference model to be optimized by the model generator 7 of FIG. As shown in FIG. 4, neural network Nw1 includes an input layer X10, an intermediate layer Y10, and an output layer Z10. The input layer X10 includes neurons X11, X12, X13. The intermediate layer Y10 includes neurons Y11 and Y12. The output layer Z10 includes neurons Z11, Z12, Z13. The input layer X10 and the intermediate layer Y10 are fully coupled to each other. The intermediate layer Y10 and the output layer Z10 are fully coupled to each other.

When a plurality of inputs are input to neurons X11 to X13 of input layer X10, the values are multiplied by weights w11, w12, w13, w14, w15, and w16 and input to neurons Y11 and Y12 of intermediate layer Y10. . Outputs from neurons Y11 and Y12 are multiplied by weights w21, w22, w23, w24, w25 and w26 and output from neurons Z11, Z12 and Z13 of output layer Z10. The output result from the output layer Z10 varies depending on the values of weights w11-w16 and w21-w26.

The neural network Nw1 learns the relationship between defect data and pass/fail judgment results by so-called supervised learning according to learning data created using a combination of defect data and pass/fail judgment results (teacher data). In other words, the weights and biases of the neural network Nw1 are set so that the results obtained by inputting defect data to the input layer and outputting from the output layer are closer to the quality judgment results of the correct data. Updated by propagation.

FIG. 5 is a flow chart showing the flow of learning processing performed in the learning device 13 of FIG. FIG. 6 shows defect data including defects 15a, 15b and 15c occurring in silicon carbide substrate 16. In FIG. FIG. 7 is a diagram in which manufacturing position information 18 indicating the position where semiconductor device 17 is formed on silicon carbide substrate 16 in FIG. 6 is displayed superimposed in association with defect data in FIG. FIG. 8 is a diagram showing relative positions of defects 15a and 15c in the semiconductor device 17. As shown in FIG. 9 is a cross-sectional view taken along the line A1-A2 of FIG. 8. FIG. 8 and 9, the X-axis, Y-axis and Z-axis are orthogonal to each other. A step is simply denoted as S below.

Mainly referring to FIG. 5 and also referring to FIG. 6, the learning data acquisition unit 4 acquires defect data of the silicon carbide substrate 16 shown in FIG. 6 from the defect inspection data storage unit 3 in S101. At the same time, the manufacturing position information 18 of the semiconductor device 17 on the grid is acquired from the dimension information storage unit 30 .

Also referring to FIG. 7, in S102, the learning data processing unit 5 converts the defects 15a to 15c acquired by the learning data acquisition unit 4 into the manufacturing position information 18 on the silicon carbide substrate 16 of the semiconductor device 17. , the defect data is processed so as to be associated with the pass/fail judgment result (teaching data) of the semiconductor device 17 . Also referring to FIG. 8, in S102, the learning data processing unit 5 determines the relative position of each of the defects 15a to 15c, the size of the defect, the type of the defect, and the number of defects classified into the type. Information about the number is added to the defect data. That is, the learning data processing unit 5 determines whether each of the defects 15a to 15c is located in the ineffective region 19 or the gate pad 24 where little current flows when the semiconductor device 17 is energized, or in the effective region 20 where current flows when energized. Information as to whether the defect is located is added to the defect data. Furthermore, the learning data processing unit 5 also assigns the number of each defect type in the same semiconductor device 17 to the defect data. Also referring to FIG. 9, a region corresponding to the outer periphery of the semiconductor device 17 is defined as an invalid region 19 in which no current flows when current is applied. A flowing effective area 20 is defined. In addition, in S102, the case where the defect data and the pass/fail judgment results (teaching data) are individually acquired has been described, but the defect data and the pass/fail judgment results (teaching data) may be associated and input, and both may be acquired at the same time.

In S103, the model generating unit 7 generates defect data by so-called supervised learning according to the learning data created using a combination of the defect data output from the learning data processing unit 5 and the pass/fail judgment results (teacher data). and the pass/fail judgment result, a learned model is generated, and the process proceeds to S104. The model generation unit 7 stores the learned model in the learned model storage unit 8 in S104. Note that the model generation unit 7 may learn the relationship between defect data and pass/fail judgment results (teacher data) according to learning data created for a plurality of semiconductor devices. For example, learning data may be created from data of semiconductor devices manufactured from the same manufacturing lot, during the same period, or from the same ingot, etc., or from semiconductor devices manufactured from different manufacturing lots, during different periods, or from different ingots, etc. data for learning may be created from the data of

FIG. 10 is a flow chart showing the flow of inference processing performed by the inference device 14 and selection unit 23 of FIG. As shown in FIG. 10, in S111, the inference data acquisition unit 9 acquires the defect data of the silicon carbide substrate from the defect inspection data storage unit 3, and also acquires the manufacturing position of the semiconductor device from the dimension information storage unit 30. Get information.

In S112, the inference data processing unit 10 identifies at least one defect contained in the semiconductor device to be manufactured using the semiconductor device manufacturing position information and the defect data output from the inference data acquisition unit 9, and identifies the defect. Manufacturing location information is associated with each of the at least one defect in the data. In addition, the inference data processing unit 10 obtains feature quantities such as the relative position of each of at least one defect included in the semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into the type. to the defect data.

In S113, the inference unit 11 inputs the defect data (inference data) processed in S112 to the learned model stored in the learned model storage unit 8, and calculates the pass/fail judgment probability of the semiconductor device from the learned model. obtain.

The judging unit 12 selects the highest probabilities of the pass/fail judging probabilities output from the inferring unit 11, and outputs a judgment result as to whether the semiconductor device is non-defective or defective.

In S115, the sorting unit 23 sorts out semiconductor devices using the determination result output in S114. As a result, it is possible to more accurately remove the semiconductor device that causes element breakdown from the finished product.

Note that it is possible to add or remove the semiconductor device from which the learning data is to be collected from the inspection target on the way. Furthermore, an inference model obtained by learning the relationship between defect data and pass/fail determination results (teaching data) for a certain semiconductor device is applied to a semiconductor device other than the semiconductor device, and defect data and pass/fail for the other semiconductor device are applied. The inference model may be updated by re-learning (or additionally learning) the relationship with the determination result.

FIG. 11 is a block diagram showing the hardware configuration of the semiconductor device inspection apparatus 100 of FIG. As shown in FIG. 11 , inspection apparatus 100 includes processing circuitry 71 , memory 72 , and input/output section 73 . The processing circuit 71 includes a CPU (Central Processing Unit) that executes programs stored in the memory 72 . The processing circuit 71 may include a GPU (Graphics Processing Unit). The functions of the inspection apparatus 100 are implemented by software, firmware, or a combination of software and firmware. Software or firmware is written as a program and stored in memory 72 . The processing circuit 71 reads and executes a program stored in the memory 72 . Note that the CPU is also called a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, a processor, or a DSP (Digital Signal Processor).

The memory 72 includes nonvolatile or volatile semiconductor memory (eg, RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), or EEPROM (Electrically Erasable Programmable Read Only Memory)). )), and magnetic discs, flexible discs, optical discs, compact discs, mini discs, or DVDs (Digital Versatile Discs).

The memory 72 stores teacher data Ds, a machine learning program Pg1, an inspection program Pg2, and an inference model M1. A processing circuit 71 that executes the machine learning program Pg1 corresponds to the learning device 13 in FIG. A processing circuit 71 that executes the inspection program Pg2 corresponds to the inference device 14 in FIG. A memory 72 corresponds to the teacher data storage unit 6 and the learned model storage unit 8 in FIG.

The input/output unit 73 receives an operation from a user and outputs a processing result to the user. Input/output unit 73 includes, for example, a mouse, keyboard, touch panel, display, and speaker.

Modification 1 of the first embodiment.
In Modification 1 of Embodiment 1, a case will be described in which defect data input to an inspection apparatus for a semiconductor device is image data. By using image data as defect data, it is possible to make the inference model learn complex feature amounts that cannot be understood from low-dimensional data, so that the inference accuracy of the inference model can be improved. In addition, when a semiconductor device is determined to be defective, the grounds for the determination can be visually confirmed as image data. Therefore, it is possible to easily investigate the cause of the determination as a defective product and to plan countermeasures.

FIG. 12 is a block diagram showing a configuration of a semiconductor device inspection apparatus 100 according to Modification 1 of Embodiment 1. As shown in FIG. The configuration shown in FIG. 12 is a configuration in which the defect inspection data storage unit 3 in FIG. 1 is replaced with a defect image data storage unit 33. FIG. As shown in FIG. 12 , the learning data acquisition unit 4 and the inference data acquisition unit 9 acquire defect image data from the defect image data storage unit 33 . Since the configuration other than these is the same as that of the first embodiment, description thereof will not be repeated.

Modified example 2 of the first embodiment.
The data acquired by the learning data acquisition unit 4 and the inference data acquisition unit 9 are not limited to those of the first embodiment and the first modification. For example, as in the learning data acquisition unit 4 and the inference data acquisition unit 9 of the semiconductor device inspection apparatus 100 according to the second modification of the first embodiment shown in FIG. In addition to the information, product specification data for the semiconductor device to be manufactured may be obtained from the product specification storage unit 25 and used in learning and reasoning. The product specifications include, for example, information necessary for designing the semiconductor device such as the thickness and concentration of the epitaxial layer of the semiconductor device, the thickness of the semiconductor device, the channel concentration, the channel length, and the thickness of the gate oxide film. Includes manufacturing variability.

Modification of Embodiment 1 3.
The dimension information storage unit 30 and the product specification storage unit 25 need not be provided outside the semiconductor device inspection apparatus 100 . It may be provided inside the semiconductor device inspection apparatus 100 like the semiconductor device inspection apparatus 100 according to the third modification of the first embodiment shown in FIG.

Modified example 4 of the first embodiment.
FIG. 15 is a block diagram showing an example of a configuration of a semiconductor device inspection apparatus 100 according to Modification 4 of Embodiment 1. As shown in FIG. In FIG. 15, in order to emphasize the features of the fourth modification of the first embodiment, the configuration of the semiconductor device inspection apparatus 100 other than the model generation unit 7, the learned model storage unit 8, and the determination unit 12 is illustrated. do not have. As shown in FIG. 15, display device 28 includes display 281 . Operation input device 27 includes a keyboard 271 and a mouse 272 . In the semiconductor device inspection apparatus 100 , the judgment result of the judging section 12 is displayed on the display device 28 . The user can change the determination result displayed on the display device 28 using the operation input device 27 . The user can update the trained model by feeding back changes made to the determination result to the model generation unit 7 . Note that the display device 28 and the operation input device 27 in FIG. 15 may be integrally formed like the display/operation input device 29 including the touch display 291 shown in FIG.

Modified example 5 of the first embodiment.
FIG. 17 is a block diagram showing the configuration of a semiconductor device inspection apparatus 100 according to Modification 5 of Embodiment 1. As shown in FIG. In FIG. 17, in order to emphasize the features of the fifth modification of the first embodiment, the configuration of the semiconductor device inspection apparatus 100 other than the learning device 13, the teacher data storage unit 6, and the unnecessary data calculation unit 31 is illustrated. do not have. As shown in FIG. 17 , the semiconductor device inspection apparatus 100 further includes an unnecessary data calculation unit 31 . The unnecessary data calculation unit 31 extracts unnecessary defect inspection data that does not contribute to the determination by the determination unit of the inference device from the learned model generated by the model generation unit 7, and extracts unnecessary defect inspection data from the defect inspection data storage unit 3. Delete data.

FIG. 18 is a flow chart for explaining the processing flow of the unnecessary data calculation unit 31 of FIG. As shown in FIG. 18, the unnecessary data calculation unit 31 acquires the degree of importance of the defect data used by the model generation unit 7 in S131, and advances the process to S132. The unnecessary data calculation unit 31 determines in S132 whether or not the degree of importance obtained in S131 is higher than a predetermined threshold value. If the degree of importance is higher than the threshold (YES in S132), unnecessary data calculation unit 31 advances the process to S134. If the degree of importance is equal to or less than the threshold (NO in S132), unnecessary data calculation unit 31 advances the process to S133. The unnecessary data calculation unit 31 deletes the defect inspection data corresponding to the degree of importance from the defect inspection data storage unit 3 in S133, and advances the process to S134. The unnecessary data calculation unit 31 determines whether or not there is an undetermined degree of importance among the degrees of importance of the defect data used by the model generation unit 7 in S134. If there is an undetermined degree of importance (YES in S134), the unnecessary data calculation unit 31 returns the process to S131. If there is no undetermined importance (NO in S134), the unnecessary data calculation unit 31 ends the process.

According to the semiconductor device inspection apparatus 100 according to the fifth modification of the first embodiment, the amount of data held by the defect inspection data storage unit 3 can be reduced. can be reduced.

As described above, according to the semiconductor device inspection apparatus according to the first embodiment and modifications 1 to 5, it is possible to improve the accuracy of detecting a semiconductor device having a defect that causes element breakdown, compared to the electrical characteristic inspection.

Embodiment 2.
In the second embodiment, the semiconductor device to be inspected is a so-called SBD (Metal-Oxide-Semiconductor Field-Effect Transistor) having an SBD (Schottky Barrier Diode) structure, and the short-circuit resistance of the semiconductor device is inspected. A semiconductor device inspection apparatus for testing will be described. It should be noted that the short-circuit tolerance is the time from when the semiconductor device to be inspected is short-circuited to when the semiconductor device is destroyed.

FIG. 19 is a block diagram showing the configuration of a semiconductor device inspection apparatus 200 according to the second embodiment. The semiconductor device inspection apparatus 200 has a configuration in which the teacher data storage unit 6 and the inference unit 11 in FIG. 1 are replaced with the teacher data storage unit 26 and the inference unit 21, respectively. The teacher data storage unit 26 stores data on the short-circuit tolerance (data on quality) of the semiconductor device to be manufactured.

FIG. 20 is a block diagram of the configuration of the learning device 13 of FIG. As shown in FIG. 20 , the learning device 13 includes a learning data acquisition unit 4 , a learning data processing unit 5 , a model generation unit 7 and a trained model storage unit 8 . The learning data acquisition unit 4 performs the same processing as in the first embodiment, and outputs the manufacturing position information and the defect data of the semiconductor device to the learning data processing unit 5 .

The learning data processing unit 5 performs the same processing as in the first embodiment, acquires the short-circuit tolerance of the semiconductor device to be manufactured from the teacher data storage unit 26, and associates the defect data of the semiconductor device with the short-circuit tolerance. . The learning data processing unit 5 creates learning data including a combination of defect data and short-circuit tolerance (teaching data). The learning data processing unit 5 outputs learning data to the model generation unit 7 .

The model generation unit 7 uses the learning data from the learning data processing unit 5 to learn the relationship between the defect data and the short-circuit tolerance. The model generator 7 generates a learned model for inferring the optimum short-circuit tolerance from the defect data and the short-circuit tolerance (teacher data) of the semiconductor device. The inference model uses the defect data (learning input data) processed by the learning data processing unit 5 as an input (explanatory variable) and the short-circuit tolerance as an output (objective variable). The model generation unit 7 saves the learned model in the learned model storage unit 8 .

FIG. 21 is a block diagram of the configuration of the inference device 14 of FIG. As shown in FIG. 21 , the inference device 14 includes an inference data acquisition unit 9 , an inference data processing unit 10 , an inference unit 21 , and a determination unit 12 . The inference data acquisition unit 9 performs the same processing as in the first embodiment, and outputs the manufacturing position information and the defect data of the semiconductor device to the inference data processing unit 10 . The inference data processing unit 10 outputs the processed defect data to the inference unit 21 by performing the same processing as in the first embodiment.

The inference unit 21 infers the short-circuit tolerance of the semiconductor device from the defect data using the learned model stored in the learned model storage unit 8 . The inference unit 21 inputs the defect data (inference input data) processed by the inference data processing unit 10 to the trained model, and outputs the short-circuit tolerance inferred from the defect data to the determination unit 12 .

The determination unit 12 determines whether the semiconductor device to be inspected is a non-defective product or a defective product based on a predetermined threshold for the short-circuit resistance output from the inference unit 11 . That is, the determining unit 12 determines that the semiconductor device is non-defective when the short-circuit tolerance is equal to or greater than the threshold, and determines the semiconductor device as defective when the short-circuit tolerance is less than the threshold. do.

The sorting unit 23 sorts the semiconductor device to be inspected into either a non-defective product or a defective product using the determination result from the determination unit 12 .

FIG. 22 is a histogram of electrical characteristics measured in advance before measuring the short-circuit withstand capability of the semiconductor device. FIG. 23 is a histogram of short-circuit tolerance output from the inference unit 21 of FIG. In FIGS. 22 and 23, as a result of the actual measurement of the short-circuit withstand voltage, the class in which element breakdown occurred and the class of normal products in which element breakdown did not occur are shown separately. As shown in FIG. 22, in the histogram of electrical characteristics, the class of normal products and the class in which element breakdown occurs are mixed. I can't. On the other hand, as shown in FIG. 23, in the histogram of the short-circuit tolerance, the class of normal products and the class in which element breakdown occurs are separated by the threshold value Wth. Thus, it is possible to highly accurately classify semiconductor devices in which element destruction occurs and semiconductor devices in which element destruction does not occur.

FIG. 24 is a flow chart showing the flow of learning processing performed in the learning device 13 of FIG. As shown in FIG. 24, in S201, the learning data acquisition unit 4 acquires defect data of the silicon carbide substrate from the defect inspection data storage unit 3, and also acquires the semiconductor device on the grid from the semiconductor device dimension information storage unit. Get the manufacturing location information of

In S202, the learning data processing unit 5 converts the defect data acquired by the learning data acquisition unit 4 into the short-circuit tolerance (teacher data) of the semiconductor device via the manufacturing position information of the semiconductor device on the silicon carbide substrate. Process the defect data so as to be associated. In S202, the learning data processing unit 5 determines the relative position of each of at least one defect included in the semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into the type. is added to the defect data. In S202, the case where the defect data and the short-circuit tolerance (teaching data) are acquired separately has been described, but the defect data and the short-circuit tolerance (teaching data) of the semiconductor device may be associated and input. may be obtained at the same time.

In S203, the model generation unit 7 performs so-called supervised learning according to the learning data created based on the combination of the defect data output from the learning data processing unit 5 and the short-circuit tolerance (teacher data). The relationship with the short-circuit tolerance is learned, a learned model is generated, and the process proceeds to S204. The model generation unit 7 stores the learned model in the learned model storage unit 8 in S204. The model generation unit 7 may learn the relationship between the defect data and the short-circuit tolerance (teaching data) according to learning data created for a plurality of semiconductor devices. For example, learning data may be created from data of semiconductor devices manufactured from the same manufacturing lot, during the same period, or from the same ingot, etc., or from semiconductor devices manufactured from different manufacturing lots, during different periods, or from different ingots, etc. data for learning may be created from the data of

FIG. 25 is a flowchart showing the flow of inference processing performed by the inference device 14 and selection unit 23 of FIG. As shown in FIG. 25, in S211, the inference data acquisition unit 9 acquires the defect data of the silicon carbide substrate from the defect inspection data storage unit 3, and also acquires the semiconductor device manufacturing data from the semiconductor device dimension information storage unit 30. Get location information.

In S212, the inference data processing unit 10 identifies at least one defect contained in the semiconductor device to be manufactured using the semiconductor device manufacturing position information and the defect data output from the inference data acquisition unit 9, and identifies at least one defect included in the semiconductor device to be manufactured. The defect data is processed to associate manufacturing location information with each of the at least one defect. In addition, the inference data processing unit 10 obtains feature quantities such as the relative position of each of at least one defect included in the semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into the type. to the defect data.

In S213, the inference unit 11 inputs the inference data generated in S212 to the learned model stored in the learned model storage unit 8, and obtains the short-circuit tolerance of the semiconductor device from the learned model.

The determination unit 12 determines whether the semiconductor device to be inspected is a non-defective product or a defective product by using a predetermined threshold for the short-circuit resistance output from the inference unit 11 .

In S215, the sorting unit 23 sorts out semiconductor devices using the determination result output in S214. As a result, it is possible to more accurately remove the semiconductor device that causes element breakdown from the finished product.

Note that it is possible to add or remove the semiconductor device from which the learning data is to be collected from the inspection target on the way. Furthermore, an inference model obtained by learning the relationship between defect data and short-circuit tolerance (teaching data) for a certain semiconductor device is applied to a semiconductor device other than the semiconductor device, and defect data and short-circuit tolerance are applied to the other semiconductor device. The inference model may be updated by re-learning (or additionally learning) the relationship between .

As described above, according to the semiconductor device inspection apparatus according to the second embodiment, it is possible to improve the accuracy of detecting a semiconductor device having a defect that causes element breakdown, compared to the electrical characteristic inspection.

Embodiment 3.
In the third embodiment, a manufacturing method for manufacturing a semiconductor device using the semiconductor device inspection apparatus described in the first and second embodiments will be described. FIG. 26 is a flow chart showing the flow of the method for manufacturing a semiconductor device according to the third embodiment. As shown in FIG. 26, in S301, a silicon carbide substrate made of silicon carbide is procured. In S302 following S301, defect data of the silicon carbide substrate (semiconductor wafer) is acquired. In S303 following S302, the product specifications of the candidate semiconductor device to be manufactured on the silicon carbide substrate are acquired. In S304 following S303, the semiconductor device inspection apparatus infers the determination result of the semiconductor device when it is assumed that the semiconductor device of the product specification is manufactured on the semiconductor wafer, and determines the semiconductor wafer from the inferred determination result. Infer the number of non-defective products and the yield of semiconductor devices obtained from

In S305 following S304, it is determined from the inferred yield whether or not to start manufacturing semiconductor devices having the product specifications on the silicon carbide substrate. Whether to start manufacturing the semiconductor device is determined to start manufacturing, for example, when the inferred yield is equal to or higher than a predetermined threshold, and when the yield is less than the threshold, It is decided not to start manufacturing. If it is determined to start manufacturing the semiconductor device (YES at S305), manufacturing of the semiconductor device is started at S306. If it is determined not to start manufacturing the semiconductor device (NO in S305), it is determined in S307 whether or not there are other product specification candidates. If there are other product specification candidates (YES in S307), the process returns to S303. If there is no other product specification candidate (NO in S307), it is determined in S308 that the silicon carbide substrate is not used.

According to the method of manufacturing a semiconductor device according to the third embodiment described above, as a result of manufacturing the silicon carbide substrate, the number of non-defective products that do not cause failures is small, which causes a difference from the production plan, or reduces the manufacturing cost. can be prevented from increasing.

It is also planned that each embodiment disclosed this time will be appropriately combined and carried out within a non-contradictory range. It should be considered that the embodiments disclosed this time are illustrative in all respects and not restrictive. The scope of the present disclosure is indicated by the scope of the claims rather than the above description, and is intended to include all modifications within the scope and meaning of equivalents of the scope of the claims.

2 defect inspection device, 3 defect inspection data storage unit, 4 learning data acquisition unit, 5 learning data processing unit, 6, 26 teacher data storage unit, 7 model generation unit, 8 learned model storage unit, 9 inference data Acquisition unit 10 inference data processing unit 11, 21 inference unit 12 determination unit 13 learning device 14 inference device 15a to 15c defect 16 silicon carbide substrate 17 semiconductor device 18 manufacturing position information 19 invalid area , 20 effective area, 23 selection unit, 24 gate pad, 25 product specification storage unit, 27 operation input device, 29 display/operation input device, 28 display device, 30 dimension information storage unit, 31 unnecessary data calculation unit, 33 defect image Data storage unit, 71 processing circuit, 72 memory, 73 input/output unit, 100, 200 inspection device, 271 keyboard, 272 mouse, 281 display, 291 touch display, Ds teacher data, M1 inference model, Nw1 neural network, Pg1 machine learning program, Pg2 check program, Wth threshold, X10 input layer, X11-X13, Y11, Y12, Z11-Z13 neurons, Y10 hidden layer, Z10 output layer, w11-w16, w21-w26 weights.

Claims (10)

at least one defect included in the first semiconductor device is specified from defect data relating to defects included in the first silicon carbide substrate and positional information of the first semiconductor device formed on the first silicon carbide substrate; Data processing for learning to generate learning data in which learning input data including data relating to at least one defect included in a first semiconductor device and teacher data including data relating to quality of the first semiconductor device are associated with each other. Department and
a model generation unit that generates a trained model for inferring data regarding the quality of the first semiconductor device from the learning input data by machine learning using the learning data;
identifying at least one defect contained in the second semiconductor device from defect data relating to defects occurring in the second silicon carbide substrate and positional information of the second semiconductor device formed on the second silicon carbide substrate; an inference data processing unit that generates inference input data including data on at least one defect included in the second semiconductor device;
an inference unit that infers data regarding the quality of the second semiconductor device from the inference input data using the trained model. 2. The semiconductor device inspection apparatus according to claim 1, further comprising a determination unit that determines whether said second semiconductor device is a non-defective product or a defective product using the inference result of said inference unit. the training data includes information as to whether the first semiconductor device is a non-defective product or a defective product;
3. The inspection of the semiconductor device according to claim 1, wherein said data on the quality of said second semiconductor device includes a probability that said second semiconductor device is a non-defective product and a probability that said second semiconductor device is a defective product. Device. the training data includes a short-circuit tolerance of the first semiconductor device;
3. The semiconductor device inspection apparatus according to claim 1, wherein said data relating to the quality of said second semiconductor device includes a short-circuit tolerance of said second semiconductor device. the learning input data includes the relative position of each of at least one defect included in the first semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into the type;
3. The inference input data includes the relative position of each of at least one defect included in the second semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into the type. 5. The semiconductor device inspection apparatus according to any one of 1 to 4. the learning input data includes data on product specifications of the first semiconductor device;
6. The semiconductor device inspection apparatus according to claim 1, wherein said inference input data includes data relating to product specifications of said second semiconductor device. 7. The method according to any one of claims 1 to 6, wherein the defect data relating to defects occurring in each of said first silicon carbide substrate and said second silicon carbide substrate includes image data of defects occurring in said silicon carbide substrate. semiconductor device inspection equipment. At least one defect included in the semiconductor device is specified from defect data relating to defects occurring in the silicon carbide substrate and positional information on which the semiconductor device is formed on the silicon carbide substrate, and included in the semiconductor device. a learning data processing unit that generates learning data in which input data including data relating to at least one defect and teacher data including data relating to the quality of the semiconductor device are associated;
and a model generating unit that generates a trained model for inferring data on the quality of the semiconductor device from the input data by machine learning using the learning data. At least one defect included in the semiconductor device is specified from defect data relating to defects occurring in the silicon carbide substrate and positional information on which the semiconductor device is formed on the silicon carbide substrate, and at least one defect included in the semiconductor device is identified. an inference data processing unit that generates inference input data including defect-related data;
an inference unit that infers data regarding the quality of the semiconductor device from the inference input data using a trained model. acquiring defect data of a silicon carbide substrate and product specifications of a specific semiconductor device formed on the silicon carbide substrate;
a step of inferring a yield when the specific semiconductor device is manufactured according to the product specification from the defect data, using the semiconductor device inspection apparatus according to any one of claims 1 to 7;
From the inference result of the step of inferring the yield, any one of starting manufacturing of the specific semiconductor device, predicting the yield of the semiconductor device having the product specification different from the product specification, and not using the silicon carbide substrate is selected. A method of manufacturing a semiconductor device, comprising steps.

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