JP2023116851A - Electric power converter - Google Patents

Abstract

[Problem] To minimize thermal interference between components by separating the heat dissipation paths of a pulse transformer and a gate driver, and to reduce size and cost by mounting components close together. A gate driver 5 is in thermal contact with a cooler 300 via a first pattern 10 of a multilayer substrate 200 and a first screw 20 that fixes the multilayer substrate 200 to the cooler 300, The first pattern 10 is wired so as not to overlap the terminals of the pulse transformer 8 and the wires connected to the terminals of the pulse transformer 8 in plan view. [Selection diagram] Figure 2

Description

The present application relates to a power converter.

Power converters installed in hybrid electric vehicles (HEV), electric vehicles (EV), etc. are required to be downsized and low in cost.
Low-cost pulse transformers are often used in place of expensive isolation ICs in on-vehicle power converters that control output power based on input power.
However, when a pulse transformer is used to drive a plurality of switching elements, there is a concern that the mounting area will increase, leading to an increase in size. Therefore, for example, there has been a technique for miniaturization by combining a multi-output pulse transformer and a multi-output gate driver. (See Patent Document 1 below, for example).

JP 2021-168534 A

The pulse transformer and the gate driver that drives it are connected in series, and the wiring that connects the two components must be placed close to each other in consideration of noise superimposition. Since these are placed close to each other, if one of them generates heat, it will cause thermal interference with the other via the resin of the multilayer board or the pattern of the multilayer board, and the part that receives the heat will exceed the rated temperature of the part. tended to exceed. Since multi-output components tend to generate heat, this problem becomes even more pronounced with the method described above. When the wiring is thickened in order to reduce the DC resistance for the purpose of suppressing heat generation, the size of the parts is increased, and thus the power converter as a whole is increased in size. If a distance is provided between components so as not to cause thermal interference, the substrate may become large in terms of mounting area, and noise may be superimposed.

The present application is intended to solve the above problems, and by forming a heat dissipation path for each mounted component, heat generation due to thermal interference generated between components is suppressed, and the components, and thus the power converter, are made smaller and less expensive. It is intended to be

A power conversion device disclosed in the present application includes a gate driver that receives a drive signal output from a control unit that generates a drive signal for a semiconductor switching element and outputs a gate signal, and a gate signal that is transmitted from the gate driver to the semiconductor switching element. In a power conversion device in which a pulse transformer is mounted on a multilayer substrate, the gate driver is in thermal contact with the cooler through the first pattern provided on the multilayer substrate and the first screw that fixes the multilayer substrate to the cooler. The first pattern does not overlap the terminals of the pulse transformer and the wiring connected to the terminals of the pulse transformer in plan view.

According to the power conversion device of the present application, it is possible to implement a small pulse transformer and a gate driver, and to arrange them in close proximity, so that a small and low-cost power conversion device can be realized.

1 is a circuit diagram showing a circuit configuration example of a power converter according to Embodiment 1; FIG. FIG. 4 is a plan view showing an example of division of a heat dissipation path in the power conversion device according to Embodiment 1; FIG. 4 is a side view showing an example of dividing a heat dissipation path in the power conversion device according to Embodiment 1; 4 is a plan view showing an example in which the pulse transformer in the power converter according to Embodiment 1 has a heat radiation pattern; FIG. FIG. 4 is a side view showing an example in which the pulse transformer in the power converter according to Embodiment 1 has a heat dissipation pattern; FIG. 4 is a plan view showing an example of dividing a heat dissipation path using slits in the power conversion device according to the first embodiment; FIG. 4 is a side view showing an example of dividing a heat dissipation path using a slit in the power converter according to the first embodiment; FIG. 4 is a plan view showing an example in which a heat dissipation path is provided directly under the terminals of the pulse transformer in the power converter according to Embodiment 1; FIG. 4 is a side view showing an example in which a heat dissipation path is provided directly under the terminals of the pulse transformer in the power converter according to the first embodiment; FIG. 3 is an exploded perspective view showing an example of division of a heat radiation path when windings of a pulse transformer are mounted on a multilayer substrate in the power conversion device according to Embodiment 1; FIG. 4 is a plan view showing an example of division of a heat dissipation path when windings of a pulse transformer are mounted on a multilayer substrate in the power conversion device according to Embodiment 1; FIG. 4 is a side view showing an example of division of a heat dissipation path in the case where windings of a pulse transformer are mounted on a multilayer substrate in the power converter according to Embodiment 1; FIG. 4 is a plan view showing an example of division of a heat dissipation path when windings and a cooling pattern of a pulse transformer are brought into contact with a cooler in the power conversion device according to Embodiment 1; FIG. 4 is a side view showing an example of division of a heat radiation path when windings and a cooling pattern of a pulse transformer are brought into contact with a cooler in the power conversion device according to Embodiment 1; FIG. 2 is a plan view showing a wiring example related to a heat radiation pattern of a gate driver in the power conversion device according to the first embodiment;

Embodiment 1.
Embodiment 1 will be described below.
FIG. 1 is an example of a power converter according to Embodiment 1. FIG. As shown in FIG. 1, the power converter 1000 includes semiconductor switching elements 1a to 1d, a transformer 2, diodes 3a to 3d, and a smoothing reactor 4 to form a main circuit. A gate signal generated by the control unit 100 is applied to the gates of the semiconductor switching elements 1a to 1d through the gate driver 5, the gate resistor 6, the DC cut capacitor 7, the pulse transformer 8, and the gate resistors 9a to 9d. to drive. The semiconductor switching elements 1a to 1d may be self arc-extinguishing semiconductors such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors), or wide bandgap semiconductors.

The control unit 100 drives the semiconductor switching elements 1a to 1d in a desired topology based on the sensed input/output voltage and input/output current of the power converter 1000. FIG. A gate signal output from the control unit 100 is transmitted to the gate driver 5 .

A gate driver 5 drives each of the semiconductor switching elements 1a to 1d through a pulse transformer 8. FIG. In this embodiment, one gate driver IC having two outputs is used. However, two gate drivers having one output and having one output are used, or they are composed of discrete semiconductor components. You may The pulse transformer 8 is connected to two or more semiconductor switching elements 1a-1d, and the gate driver 5 drives the two or more semiconductor switching elements 1a-1d.

A gate signal transmitted from the gate driver 5 is passed through the pulse transformer 8 to drive the combination of the semiconductor switching elements 1a, 1d and 1b, 1c for each arm. By applying a pulse transformer, the high voltage side and the low voltage side can be insulated, and the number of power supply circuits can be minimized without adding a new power supply circuit for driving the switching element.
In this embodiment, when the semiconductor switching element 1a is turned on, the polarities of the output sides are reversed so that the semiconductor switching element 1b is turned off. Arm short-circuit can be prevented by doing in this way.

Gate resistors 6 and 9a to 9d are provided before and after the pulse transformer 8, and by adjusting the waveform when applied to each semiconductor switching element 1a to 1d, the rise and fall of the voltage and current during the main circuit switching operation are controlled. You can adjust the descent. This adjustment can suppress the surge voltage during the switching operation of the main circuit, thereby suppressing the noise caused by the switching of the main circuit. Although only one element of each of the gate resistors 6 and 9a-9d is shown, they may be implemented in parallel, in series, or in combination.

The DC cut capacitor 7 is for cutting the DC component to the pulse transformer input, thereby reducing the loss of the pulse transformer, suppressing the magnetic saturation of the pulse transformer, and contributing to the size reduction of the pulse transformer.

In order to avoid noise superimposition in the wiring between the pulse transformer 8 and the gate driver 5, these two components must be arranged in close proximity. When a gate signal is transmitted, a current is generated inside the pulse transformer 8 and the gate driver 5, and heat is generated due to the loss caused by this current. Thermal interference occurs in which the heat of one is transferred to the other. This thermal interference occurs through the cooling pattern, the air around the pulse transformer 8 and the gate driver 5, the resin of the substrate on which the pulse transformer 8 and the gate driver 5 are mounted, and the like.

In the following, a configuration will be described in which the pulse transformer 8 and the gate driver 5 are placed close to each other by dividing the thermal interference path, and the size can be reduced without thickening the winding wire of the pulse transformer.

As shown in FIGS. 2 and 3, the gate driver 5 receives a gate signal input from the control unit 100 via the input line 18 of the gate driver 5, and converts it to the gate resistor 6 mounted on the multi-layer substrate 200 and the DC blocking circuit. The signal is transmitted to the pulse transformer 8 via a circuit component group 23 including the capacitor 7 and the like and a pattern 15 between the circuit component group and the pulse transformer 8 . Note that the side view in the subsequent figures is a perspective view of the side seen from the front side of the substrate in plan view.

A gate signal input to the pulse transformer 8 is output to the pattern 17 between the pulse transformer 8 and the semiconductor switching elements 1a to 1d, and is input to the gate portions of the semiconductor switching elements 1a to 1d via the gate resistors 9a to 9d. be. The gate driver 5 includes a first pattern 10 for wiring in the multilayer substrate 200, a land provided in the first pattern 10 around a first screw 20 to be described later, and a first screw for fixing the multilayer substrate 200. 20 is thermally contacted via the protrusion 300a of the cooler 300. As shown in FIG. Hereafter, the screws described in the figures are shown on the front surface for clarity of their existence. At this time, the first pattern 10 is brought into contact with the thermal pad 19 of the gate driver 5 . Also, wiring is performed so that the terminal of the pulse transformer 8 and the first pattern 10 and the pattern 15 between the pulse transformer 8 and the circuit component group 23 and the first pattern 10 do not overlap in plan view.

Note that the first pattern 10 is generally a GND pattern, and extends to the periphery of the circuit component group 23 for noise suppression, for example. When the first pattern 10 is wired in the lower layer of the terminal of the pulse transformer 8 and the pattern 15 between the pulse transformer 8 and the circuit component group 23, the heat generated in the gate driver 5 is It is transmitted to the inside of the pulse transformer 8 via the upper terminal of the pulse transformer 8 and the pattern 15 between the pulse transformer 8 and the circuit component group 23 .

In order to prevent such thermal interference, wiring is performed so that the terminals of the pulse transformer 8, the pattern 15 between the pulse transformer 8 and the circuit component group 23, and the first pattern 10 do not overlap, as described above. As a result of suppressing the thermal interference, it is possible to keep the temperature within the rated temperature range of the parts, so that the size of the mounted parts can be reduced, and the size of the power converter can be reduced.

A case in which a cooling pattern is also provided for the pulse transformer 8 will be described below. As in the previous embodiment, as shown in FIGS. 4 and 5, the pulse transformer 8 and the gate driver 5 are connected via a circuit component group 23 mounted on a multilayer substrate 200 and a pattern 15 between the circuit component group and the pulse transformer 8. to transmit the gate signal. The gate driver 5 is connected to the cooler via the first pattern 10 in the multilayer substrate 200, the land provided around the first screw 20 in the first pattern 10, and the first screw 20 for fixing the multilayer substrate 200. 300 is thermally abutted.

On the other hand, the pulse transformer 8 includes an insulating heat radiating member 29, a second pattern 11 for wiring of the multilayer substrate 200 in contact with the heat radiating member 29, and a second screw provided in the second pattern 11. 21 and the second screws 21 for fixing the multilayer substrate 200 are thermally contacted via the projections 300 a of the cooler 300 . A heat-dissipating sheet or silicon-based grease may be used for the heat-dissipating member 29 .

In the above configuration, the first pattern 10 and the second pattern 11 are separated, and the first pattern 10 overlaps the second pattern 11, the pulse transformer 8 and the pattern 15 between the circuit component groups 23 in plan view. The first pattern 10 and the second pattern 11 are brought into contact with the cooler 300 through the protrusions 300b, respectively, while wiring so as not to cause the wiring to become uneven.

When the first pattern 10 and the second pattern 11 are not separated or overlap each other in a plan view, in an environment where the temperature of the gate driver 5 is higher than that of the pulse transformer 8, the heat is dissipated from the gate driver 5. While the heat is radiated to the cooler 300 via the first pattern 10 and the first screw 20, the heat is transmitted to the pulse transformer 8 via the first pattern 10 and the second pattern 11, and the pulse transformer The temperature of 8 rises. Therefore, the first pattern 10 and the second pattern 11 are separated to eliminate the heat transfer path and suppress heat generation due to thermal interference. As a result of suppressing the thermal interference, it is possible to keep the temperature within the rated temperature range of the parts, so that the size of the mounted parts can be reduced, and the size of the power converter can be reduced.

A method for suppressing not only the thermal interference due to the pattern of the multilayer substrate but also the thermal interference path through the base material of the multilayer substrate will be described below. As described above, the heat transfer path in the pulse transformer 8 and the gate driver 5 can be not only the pattern in the multilayer substrate but also the base material filled in the multilayer substrate. Therefore, as shown in FIGS. 6 and 7, spaces (slits 28) not filled with the base material are provided between the first pattern and the second pattern and between the pulse transformer 8 and the gate driver 5. establish.

This slit 28 can also suppress thermal interference between the pulse transformer 8 and the gate driver 5 through the resin of the multilayer substrate, so that the influence of thermal interference can be minimized. Between the slit 28 and the pattern 15 between the pulse transformer 8 and the circuit component group 23, for example, a minimum distance necessary for manufacturing the substrate is provided. If the distance can be eliminated as a manufacturing constraint, since the pattern 15 between the pulse transformer 8 and the circuit component group 23 is exposed in the slit 28, there is no gap between the pattern 15 between the pulse transformer 8 and the circuit component group 23 and the cooler 300. Provide insulation distance.

As shown in FIGS. 8 and 9, the second pattern 11 in the pulse transformer 8 may be an inner-layer substrate pattern that overlaps the terminals of the pulse transformer 8 in plan view. With such a configuration, heat generated in the pulse transformer 8 is transmitted through the terminals of the pulse transformer 8 to the pattern 17 between the pulse transformer 8 and the semiconductor switching elements 1a to 1d, the pulse transformer 8 and the semiconductor switching elements 1a to 1d. It is transmitted to the second pattern 11 which overlaps the pattern 17 in between. Furthermore, heat is radiated by being transmitted to the cooler 300 via the land of the second pattern 11 provided on the surface layer through the through hole 30 and the second screw 21 . The gate driver 5 is connected to the cooler via the first pattern 10 in the multilayer substrate 200, the land provided around the first screw 20 in the first pattern 10, and the first screw 20 for fixing the multilayer substrate 200. 300 is thermally abutted. In such a configuration, since it is not necessary to use the heat radiation member 29 described above, cost reduction can be realized.

The windings of the pulse transformer 8 described above may be mounted on a multilayer substrate. In this case, a hole is made in the substrate, the core is inserted, and the winding is formed by the substrate pattern around the core. For example, as shown in FIG. 10, in the second layer L2 of the multilayer substrate 200, the primary winding 14 that has wound around the cores 24 and 25 of the pulse transformer passes through the through-holes of the multilayer substrate 200 and reaches the third layer L3. , and contacts the pattern 15 between the pulse transformer 8 and the circuit component group 23 . Similarly, the secondary winding 16 that has wound around the core in the first layer L1 of the multilayer substrate 200 passes through the through holes in the multilayer substrate 200 and returns to the input side of the secondary via the fourth layer L4. It abuts on the pattern 17 between the pulse transformer 8 and the semiconductor switching elements 1a to 1d. By adopting such a configuration, the component height of the pulse transformer 8 can be suppressed, so that the size of the power converter can be reduced.

When the winding wire is mounted on the multilayer substrate 200, the heat generated in the pattern accumulates in the space surrounded by the core, making it difficult to dissipate the heat. Therefore, as shown in FIGS. 11 and 12, the wiring in the outermost layer of the secondary winding 16 of the pulse transformer 8 is partially thickened so that it does not overlap with the primary winding 14 of the pulse transformer 8 in plan view. After wiring the fourth pattern 13 so as to overlap the secondary winding wiring enlarged region 27 in a plan view, the through hole 30 is used to form the third wiring of the first layer L1. abuts on the pattern 12 of

As with the secondary winding 16, the primary winding 14 of the pulse transformer 8 has a part of the wiring in the outermost layer thickened so that it does not overlap the secondary winding 16 of the pulse transformer 8 in plan view. A primary side winding wire enlarged region 26 is formed, and the third pattern 12 is wired so as to overlap the primary side winding wire enlarged region 26 in plan view.

The third pattern 12 thermally abuts the cooler 300 via the second screw 21 that secures the multilayer substrate 200 to the cooler 300 . Also, the gate driver 5 is connected to the cooler via the first screw 20 for fixing the first pattern 10 in the multilayer substrate 200 , the land provided in the first pattern 10 and the first pattern 10 in the multilayer substrate 200 . 300 is thermally abutted through the protrusion 300a.

In the configuration as described above, the first pattern 10 and the third pattern 12 on the surface layer, and the first pattern 10 and the fourth pattern 13 on the inner layer do not contact each other. By adopting such a configuration, it is possible to suppress thermal interference occurring between the pulse transformer 8 and the gate driver 5 and also suppress heat transfer caused by mounting the windings of the pulse transformer 8 on the multilayer substrate. The heat generated in the primary winding 14 of the pulse transformer 8 passes through the third pattern 12 on the adjacent surface layer, the land around the second screw 21 provided in the third pattern 12, and the second screw 21. , the heat is radiated to the cooler 300 .

Further, the heat generated in the secondary winding of the pulse transformer 8 is transferred to the third pattern 12 of the surface layer through the fourth pattern 13 of the adjacent inner layer and through holes 30 provided in the fourth pattern 13. The heat is transmitted and radiated through the projection 300b of the cooler 300 through the land around the second screw provided in the third pattern 12 and the second screw 21, similar to the primary winding. At this time, the heat generated in the pulse transformer 8 and the heat generated in the gate driver 5 are dissipated through different paths, so that heat interference does not occur and the size of each can be reduced. In this embodiment, the cooling pattern for the primary winding of the pulse transformer 8 and the cooling pattern for the secondary winding are the same. Threads may be provided to abut the cooler. The pulse transformer 8 can be cooled more efficiently by dividing the heat radiation pattern between the primary winding and the secondary winding.

In the above description, the primary winding and the secondary winding of the pulse transformer 8 are cooled. A similar effect can be expected when the pattern 17 between the elements 1a to 1d is cooled. In addition, in this embodiment, a four-layer substrate is used, and a third pattern 12 is provided as a cooling pattern on the upper and lower layers of the primary winding 14 of the pulse transformer 8, and a cooling pattern 12 is provided on the upper and lower layers of the secondary winding 16 of the pulse transformer 8. A fourth pattern 13 is provided as a pattern. As a six-layer substrate, the fourth pattern 13 is provided as a cooling pattern for the secondary winding 16 of the pulse transformer 8 on the first layer, and the pulse transformer 8 is provided on the second layer. primary winding 14 of the pulse transformer 8 on the third layer, the third pattern 12 as a cooling pattern for the primary winding 14 of the pulse transformer 8 on the fourth layer, and the fifth A similar effect can be expected by wiring the primary winding 14 of the pulse transformer 8 on the layer and the secondary winding 16 of the pulse transformer 8 on the sixth layer to cool each winding.

A method for separating the heat dissipation path from the gate driver 5 without providing a screw for the cooling pattern of the pulse transformer 8 will be described below. In the above description, the primary winding of the pulse transformer 8 is the inner layer (second layer L2, third layer L3), and the secondary winding is the surface layer (first layer L1, fourth layer L4). A case where the secondary winding is on the inner layer (second layer L2, third layer L3) and the primary winding is on the surface layer (first layer L1, fourth layer L4) will be described. The primary winding 14 that has wound around the core in the first layer L1 of the multilayer substrate 200 passes through the through holes in the multilayer substrate 200 and returns to the input side of the primary via the fourth layer L4. Similarly, the secondary winding 16 wound around the core in the second layer L2 of the multilayer substrate 200 passes through the through holes in the multilayer substrate 200 and returns to the input side of the secondary via the third layer L3. As shown in FIGS. 13 and 14, the primary winding 14 of the pulse transformer 8 is wired on the surface layers (first layer L1, fourth layer L4) of the multilayer substrate 200. FIG.

On the other hand, the secondary winding 16 of the pulse transformer 8 is wired in the inner layers (second layer L2, third layer L3), and part of the outermost layer wiring of the secondary winding 16 of the pulse transformer 8 is thickened. Then, a secondary winding wiring enlarged area 27 is formed so as not to overlap with the primary winding 14 of the pulse transformer 8 in plan view, and a third winding wiring area is formed so as to overlap with the secondary winding wiring enlarged area 27 in plan view. The pattern 12 of is wired. In this case, a resist is not provided on a part of the third pattern 12 and a part of the primary winding of the pulse transformer 8 , the wiring is exposed, and the cooler 300 is thermally connected to the cooler 300 through the insulating heat dissipation member 29 . abut. The gate driver 5 is in thermal contact with the cooler 300 via the first pattern 10 on the multilayer substrate 200, the land provided on the first pattern 10, and the first screw 20 for fixing the multilayer substrate 200. be done. Heat generated in the gate driver 5 is radiated to the cooler 300 via the first pattern 10 , the land around the first screw 20 provided on the first pattern 10 , and the first screw 20 . On the other hand, the heat generated in the primary winding of the pulse transformer 8 is radiated to the cooler 300 via the heat radiating member 29, and the heat generated in the secondary winding 16 is transferred from the secondary winding wiring expanded region 27. Heat is radiated to the cooler 300 via the adjacent third pattern 12 and the heat radiating member 29 . By adopting such a configuration, it is possible to separate the heat radiation path of the gate driver 5 while directly cooling the windings of the pulse transformer 8 without using parts such as screws.

Since the secondary side of the pulse transformer 8 is in contact with the semiconductor switching elements 1a to 1d via the gate resistors 9a to 9d, the secondary side of the pulse transformer 8 inevitably forms a high voltage system. On the other hand, the primary side of the pulse transformer 8 is in contact with the control section 100 through the DC cut capacitor 7, the gate resistor 6, and the gate driver 5, and these are a low voltage system. When the windings of the pulse transformer 8 are wired on the surface layer of the multilayer substrate 200 , it is necessary to secure an insulating distance between the windings wired on the surface layer of the cooler 300 and the pulse transformer 8 . Therefore, as described with reference to FIGS. 13 and 14, by wiring the primary winding 14 of the pulse transformer 8 on the surface, the height between the cooler and the substrate can be increased more than when the secondary winding 16 is wired on the surface. A short insulation distance is sufficient, and the height of the power converter can be suppressed, which contributes to miniaturization of the power converter.

An optimum wiring method for the first pattern 10, which is a heat radiation pattern of the gate driver 5, will be described below. When the first pattern 10, which is a heat radiation pattern of the gate driver 5, is wired in the immediate vicinity of the pulse transformer 8, the heat generated in the gate driver 5 is transmitted through the air around the pulse transformer 8 or the gate driver 5, or through the base material. It is transmitted to the pulse transformer 8 . Therefore, as shown in FIG. 15, a line extending in the direction of the pulse transformer 8 with the gate driver 5 at the center is defined as a first line La. Assuming that a line passing through the pulse transformer 8 side end of 23 is a second line Lb, the first pattern 10 is laid out from the second line Lb in a direction opposite to that of the pulse transformer 8 . With such a structure, thermal interference from the first pattern 10, which is a heat dissipation pattern of the gate driver 5, to the pulse transformer 8 can be minimized.

The pulse transformer 8 or gate driver 5 may be multi-input/output. In multi-input/output components, the amount of current increases when driving a plurality of switching elements, which increases loss and tends to generate heat. Since the amount of heat generated is greater than that of a single input/output, the effect of thermal interference is also greater. Therefore, the effect of minimizing thermal interference by dividing the heat dissipation paths of the pulse transformer 8 and the gate driver 5 is great. Also, by using multi-input/output devices, the mounting area can be reduced and the size can be reduced.

Although the present application has described exemplary embodiments, the various features, aspects, and functions described in the embodiments are not limited to application of particular embodiments, alone or Various combinations are applicable to the embodiments.
Accordingly, numerous variations not illustrated are envisioned within the scope of the technology disclosed herein. For example, the modification, addition, or omission of at least one component shall be included.

1a to 1d semiconductor switching element 5 gate driver 8 pulse transformer 10 first pattern 11 second pattern 12 third pattern 13 fourth pattern 14 primary winding 16 secondary winding Line 20 First screw 21 Second screw 23 Circuit component group 28 Slit 29 Heat dissipation member 100 Control unit 200 Multilayer substrate 300 Cooler 1000 Power converter

A power conversion device disclosed in the present application includes a gate driver that receives a drive signal output from a control unit that generates a drive signal for a semiconductor switching element and outputs a gate signal, and a gate signal that is transmitted from the gate driver to the semiconductor switching element. In a power conversion device in which a pulse transformer is mounted on a multilayer substrate, the gate driver is in thermal contact with the cooler through the first pattern provided on the multilayer substrate and the first screw that fixes the multilayer substrate to the cooler. The first pattern does not overlap the terminals of the pulse transformer and the wiring connected to the terminals of the pulse transformer in plan view, and the pulse transformer serves as the first pattern for the wiring provided on the multilayer substrate. The first pattern and the second pattern on the multilayer substrate are in thermal contact with the cooler via a second screw that secures the two patterns and the multilayer substrate to the cooler. do not overlap in plan view .

Claims (11)

A gate driver that receives a drive signal output from a control unit that generates a drive signal for a semiconductor switching element and outputs a gate signal, and a pulse transformer that transmits the gate signal from the gate driver to the semiconductor switching element are mounted on a multi-layer substrate. The gate driver is in thermal contact with the cooler via a first pattern for wiring provided on the multilayer substrate and a first screw for fixing the multilayer substrate to the cooler. and the first pattern does not overlap terminals of the pulse transformer and wiring connected to the terminals of the pulse transformer in a plan view. The pulse transformer is in thermal contact with the cooler via a second pattern for wiring provided on the multilayer substrate and a second screw for fixing the multilayer substrate to the cooler, 2. The power conversion device according to claim 1, wherein said first pattern and said second pattern do not overlap in said multilayer substrate in plan view. 3. The power converter according to claim 2, wherein a slit is provided in at least a portion between said first pattern and said second pattern in said multilayer substrate. 3. The power converter according to claim 2, wherein the second pattern overlaps the terminals of the pulse transformer in plan view. The windings of the pulse transformer are mounted in the pattern of the multilayer substrate,
3. The power converter according to claim 2, wherein the core of said pulse transformer is formed in a space not filled with the base material of said multilayer substrate. The second pattern overlaps a part of the winding of the pulse transformer in plan view, is wired in a layer adjacent to the winding of the pulse transformer, and is part of the winding of the pulse transformer. is thermally abutted against the cooler via the second screws securing the second pattern and the multilayer substrate to the cooler. conversion device. A part of windings of either the primary winding of the pulse transformer or the secondary winding of the pulse transformer wired on the surface layer of the multilayer substrate includes a first heat radiation member having insulation. is in thermal contact with the cooler via
A part of the other winding of the primary winding of the pulse transformer or the secondary winding of the pulse transformer wired on the surface layer is wired on an inner layer of the multilayer substrate,
The second pattern is wired in a layer adjacent to the primary winding of the pulse transformer or a part of the secondary winding of the pulse transformer, which is wired in the inner layer, in plan view, and has insulating properties. is in thermal contact with the cooler via a second heat radiating member,
A portion of the primary winding of the pulse transformer or the secondary winding of the pulse transformer wired in the inner layer is thermally cooled via the second pattern and the second heat radiation member. 6. The power conversion device according to claim 5, wherein the power conversion device is in contact with a device. The primary winding of the pulse transformer is wired on the surface layer of the multilayer substrate,
8. A power converter according to claim 7, wherein said secondary winding of said pulse transformer is wired in an inner layer of said multilayer substrate. A line centered on the gate driver and extending in the direction of the pulse transformer was defined as a first line, and a line orthogonal to the first line and passing through the wiring end in contact with the pulse transformer was defined as a second line. 9. The power converter according to claim 1, wherein said first pattern extends from said second line in a direction opposite to said pulse transformer. 9. The power converter according to claim 1, wherein said pulse transformer is connected to two or more of said semiconductor switching elements. 9. The power converter according to claim 1, wherein said gate driver drives two or more of said semiconductor switching elements.

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