JP2023137179A - on-chip antenna - Google Patents

Abstract

[Problem] To increase the amount of signal radiation of an on-chip antenna. [Solution] The on-chip antenna includes a handle layer 1, a first insulating layer 2 provided on the handle layer 1, a device layer 3 provided on the first insulating layer 2, and a device layer 3 provided on the device layer 3. and an antenna 5 provided on the second insulating layer 4. The handle layer 1, the first insulating layer 2, and the device layer 3 are constructed using an SOI substrate. Of the handle layer 1 and the device layer 3, the device layer 3 is connected to ground, and the handle layer 1 is floating. [Selection diagram] Figure 1

Description

The present invention relates to an on-chip antenna in which a semiconductor integrated circuit chip and an antenna are integrated.

On-chip antennas are known in which an antenna is provided and integrated on a semiconductor integrated circuit chip in order to reduce size and cost.

Non-Patent Document 1 describes an on-chip antenna in which a meander dipole antenna is formed on a Si substrate.

Patent Document 1 describes that an insulating layer is formed in a lattice shape directly under an on-chip coil. It is described that this suppresses the generation of eddy currents and improves the amount of magnetic field radiation.

Patent Document 2 describes that a depletion layer is formed directly under an on-chip coil. It is described that this suppresses the generation of eddy currents similarly to Patent Document 1.

Japanese Patent Application Publication No. 10-321802 JP2009-252965A

H.Kikkawa, et al., “Gaussian Monocycle Pulse Transmitter Using 0.18um CMOS Technology With On-Chip integrated Antennas for Inter-Chip UWB Communication”, JSSC, 2008

As in Non-Patent Document 1, in a general Si substrate, the Si substrate is connected to the ground for the operation of a circuit mounted together with an on-chip antenna. Therefore, there was a problem in that the lower surface of the on-chip antenna became a ground plane, and the amount of signal radiation from the on-chip antenna decreased.

Furthermore, although the methods of Patent Documents 1 and 2 are effective for magnetic field emission type antennas, they are difficult to obtain effects for electric field emission type antennas.

Therefore, an object of the present invention is to increase the amount of signal radiation of an on-chip antenna.

The present invention includes a handle layer made of Si, a first insulating layer made of an insulator provided on the handle layer, a device layer made of Si provided on the first insulating layer, and a device layer made of Si provided on the device layer. a second insulating layer made of an insulator, and an antenna made of a conductor with a predetermined planar pattern and provided on the second insulating layer, and at least one of the handle layer and the device layer. is an on-chip antenna characterized by being floating.

In the present invention, it is preferable that the thinner one of the handle layer and the device layer is connected to ground.

In the present invention, the handle layer may be connected to ground.

In the present invention, the resistivity of the handle layer and the device layer is preferably 10 Ω·cm or less.

In the present invention, the antenna may be of an electric field emission type.

In the present invention, the antenna may be a meander antenna, and the device layer may include a Si oscillation circuit.

According to the present invention, the amount of signal radiation of the on-chip antenna can be increased.

FIG. 1 is a diagram showing the configuration of an on-chip antenna according to a first embodiment. The figure which showed the modification of the on-chip antenna of 1st Embodiment. The figure which showed the plane pattern of the meander antenna. A graph showing frequency characteristics of signal propagation amount. A graph showing frequency characteristics of signal propagation amount. A graph showing frequency characteristics of signal propagation amount.

Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing the configuration of an on-chip antenna according to the first embodiment. As shown in FIG. 1, the on-chip antenna of the first embodiment includes a handle layer 1, a first insulating layer 2 provided on the handle layer 1, and a device layer 3 provided on the first insulating layer 2. , a second insulating layer 4 provided on the device layer 3, and an antenna 5 provided on the second insulating layer 4. The handle layer 1, the first insulating layer 2, and the device layer 3 are constructed using an SOI substrate.

The handle layer 1 is a layer made of Si. The thickness of the handle layer 1 is, for example, 100 to 1000 μm. The handle layer 1 may be doped with impurities to control conduction type, and may be n-type, intrinsic, or p-type.

The first insulating layer 2 is a layer made of an insulator provided on the handle layer 1. The first insulating layer 2 may be made of any material as long as it can sufficiently insulate the handle layer 1 and the device layer 3, such as SiO ₂ . The thickness of the first insulating layer 2 may also be within a range that can sufficiently insulate the handle layer 1 and the device layer 3. For example, it is 0.1 to 10 μm.

The device layer 3 is a layer made of Si provided on the first insulating layer 2. The device layer 3 includes an integrated circuit (not shown) constituted by a semiconductor element made of Si. The integrated circuit includes, for example, a Si oscillation circuit. The thickness of the device layer 3 is, for example, 1 to 100 μm. In SOI substrates, the device layer 3 is typically thinner than the handle layer 1. The device layer 3 may be doped with impurities to control the conductivity type, and may be n-type, intrinsic, or p-type.

The resistivity of the handle layer 1 and the device layer 3 is preferably 10 Ω·cm or less. When the resistivity of the handle layer 1 and the device layer 3 is 10 Ω·cm or less, the signal radiation amount of the antenna 5 is significantly reduced due to the presence of the Si layer directly under the antenna 5. Accordingly, a decrease in signal radiation amount can be effectively suppressed. More preferably, it is 5 Ω·cm or less, and still more preferably 1 Ω·cm or less.

Of the handle layer 1 and the device layer 3, the device layer 3 is connected to ground, and the handle layer 1 is floating. Conversely, the handle layer 1 may be connected to ground and the device layer 3 may be floating (FIG. 2). Further, both the handle layer 1 and the device layer 3 may be floating.

For example, connect to ground as follows. A ground pattern is formed on a mounting board on which the on-chip antenna of the first embodiment is mounted, and wiring connected to the ground pattern is formed. When the handle layer 1 is connected to the ground, the on-chip antenna of the first embodiment is mounted on the mounting board so that the wiring of the mounting board and the handle layer 1 are in contact with each other. When connecting the device layer 3 to the ground, a part of the second insulating layer 4 is removed to expose the device layer 3, and after mounting the on-chip antenna of the first embodiment on the mounting board, the exposed device The layer 3 and the wiring of the mounting board are connected to the ground by wire bonding.

The second insulating layer 4 is a layer made of an insulator provided on the device layer 3. The second insulating layer 4 may be made of any material as long as it can sufficiently insulate the device layer 3 and antenna 5, such as SiO ₂ . The first insulating layer 2 and the second insulating layer 4 may be made of the same material. Further, the thickness of the second insulating layer 4 may be within a range that can sufficiently insulate the device layer 3 and the antenna 5. For example, it is 1 to 500 μm.

The antenna 5 is a conductive film provided on the second insulating layer 4 and formed in a predetermined planar pattern. The conductor is Al, Cu, Au, or the like. The antenna 5 is connected to the integrated circuit of the device layer 3. The position of the antenna 5 may be above the integrated circuit.

The planar pattern of the antenna 5 may be any pattern capable of transmitting and receiving electromagnetic waves. For example, there is a meander antenna with a meandering line (see Fig. 3). By using a meander antenna, the antenna bandwidth can be widened. The meander antenna is suitable when the device layer 3 includes a Si oscillation circuit. Although Si oscillation circuits have variations in frequency due to variations in transistor characteristics and temperature characteristics, they can be operated even with variations in frequency by using a wideband meander antenna. The line width and number of turns of the meander antenna are set according to the co-progressive frequency and bandwidth. In addition to the meander antenna, a square, rectangular, or circular patch antenna may also be used.

Moreover, it is preferable that the antenna 5 is of an electric field emission type. With conventional on-chip antennas, it was difficult to increase the signal radiation amount of electric field emission type antennas, but with the on-chip antenna of the first embodiment, even with electric field emission type antennas, it was difficult to increase the signal radiation amount. can be done.

Although the resonant frequency of the antenna 5 is not particularly limited, a frequency higher than the operating frequency of the circuit of the device layer 3 is preferable. For example, if the operating frequency of the circuit is 1 to 2 GHz, the resonant frequency of the antenna 5 is preferably 2 to 3 GHz.

Note that, in addition to the antenna 5, wiring for connecting each element of the integrated circuit of the device layer 3 is provided on the second insulating layer 4 (not shown). The elements of the device layer 3 and the wiring on the second insulating layer 4 are connected through the holes made in the second insulating layer 4 . It may also be a multilayer wiring in which the second insulating layer 4 and the wiring are alternately arranged in multiple layers.

The on-chip antenna of the first embodiment can increase the amount of signal radiation compared to the conventional on-chip antenna. The reason is as follows.

Since Si has conductivity, the Si layer connected to the ground located below the antenna 5 functions as a ground plane of the antenna 5. Generally, if a ground plane exists on the lower surface of the antenna 5, the amount of signal radiation will decrease. Therefore, in the on-chip antenna of the first embodiment, only one of the handle layer 1 and the device layer 3 is connected to the ground, and the other is made floating. As a result, the total thickness of the Si layer connected to the ground is reduced, and the function of the Si layer as a ground plane of the antenna 5 is weakened. As a result, in the on-chip antenna of the first embodiment, the amount of signal radiation of the antenna 5 can be increased.

As can be seen from the above reasons, it is preferable to connect the thinner one of the handle layer 1 and the device layer 3 to the ground. Generally, in an SOI substrate, the device layer 3 is thinner than the handle layer 1, so it is preferable to connect the device layer 3 to ground.

As described above, in the on-chip antenna of the first embodiment, the amount of signal radiation of the antenna 5 can be improved.

Next, simulation results regarding the first embodiment will be explained.

Regarding the on-chip antennas of the first embodiment, two antennas in which the antennas 5 were meander antennas with a resonance frequency of 3 GHz were prepared, and the two on-chip antennas were arranged so that the antennas 5 were separated by 5 mm. The handle layer 1 and the device layer 3 were changed into a total of four states: a grounded state and a floating state. The handle layer 1 and the device layer 3 had three resistivities: 40 Ω·cm, 10 Ω·cm, and 1 Ω·cm. Below, Example 1 is a case where the handle layer 1 is connected to the ground and the device layer 3 is made floating, Example 2 is a case where the device layer 3 is connected to the ground and the handle layer 1 is made floating, and both are made floating. Example 3 is the example in which the two are connected to ground, and Comparative Example 1 is the example in which both are connected to ground. Note that the antenna 5 was evaluated by itself without being connected to the circuit of the device layer 3.

4 to 6 are graphs showing the frequency characteristics of the amount of signal propagation between the antennas 5. FIG. 4 shows the case where the resistivity of the handle layer 1 and the device layer 3 is 40 Ω·cm, FIG. 5 shows the case when it is 10 Ω·cm, and FIG. 6 shows the case when the resistivity is 1 Ω·cm. Looking at the graphs in FIGS. 5 and 6, it was found that the amount of signal propagation was larger in the order of Example 3, Example 1, Example 2, and Comparative Example 1. As a result, it was found that the smaller the number of layers connected to the ground, the greater the amount of signal propagation. In addition, the amount of signal propagation was greater when device layer 3 was connected to ground than when handle layer 1 was connected to ground. ) It was found that the thinner the total thickness, the greater the amount of signal propagation. It was also found that the lower the resistivity of the Si layer, the more the connection state with the ground affects the amount of signal propagation, and it was found that this becomes noticeable when the resistivity is 10 Ω·cm or less.

The present invention can be used for various communications.

1: Handle layer 2: First insulating layer 3: Device layer 4: Second insulating layer 5: Antenna

Claims (6)

A handle layer made of Si,
a first insulating layer provided on the handle layer and made of an insulator;
a device layer provided on the first insulating layer and made of Si;
a second insulating layer provided on the device layer and made of an insulator;
an antenna provided on the second insulating layer and made of a conductor with a predetermined planar pattern;
has
at least one of the handle layer and the device layer is floating;
An on-chip antenna characterized by: The on-chip antenna according to claim 1, wherein the thinner one of the handle layer and the device layer is connected to ground. The on-chip antenna according to claim 1 or 2, wherein the handle layer is connected to ground. The on-chip antenna according to any one of claims 1 to 3, wherein the handle layer and the device layer have resistivities of 10 Ω·cm or less. The on-chip antenna according to any one of claims 1 to 4, wherein the antenna is of an electric field emission type. The on-chip antenna according to any one of claims 1 to 5, wherein the antenna is a meander antenna, and the device layer includes a Si oscillation circuit.