JP2024058238A - Signal processing circuit, DA converter circuit, AD converter circuit, and audio device - Google Patents

Abstract

To provide a signal processing circuit which can improve SNR.SOLUTION: A signal processing circuit (500) includes: a ΔΣ modulator (100) which is configured to convert an input signal into an n-value output signal (n is an integer of 2 or more) and output the converted signal; a PWM conversion part (200) which is configured to convert the n-value output signal into a PWM output signal having a duty corresponding to a level of the n-value output signal; and a pulse selection part (400) which is configured to select the pulse to be used among the pulses constituting the PWM signal with respect to the level of the n-value output signal in a non-stationary state.SELECTED DRAWING: Figure 11

Description

This disclosure relates to a signal processing circuit.

Conventionally, ΔΣ modulators are used in DA converters that convert digital signals to analog signals, or AD converters that convert analog signals to digital signals (an example of a ΔΣ modulator is disclosed in, for example, Patent Document 1).

JP 2019-87876 A

In DA converters or AD converters that use ΔΣ modulators, there is a demand for improved SNR (Signal-to-Noise Ratio).

For example, a signal processing circuit according to an embodiment of the present disclosure includes:
a ΔΣ modulator configured to convert an input signal into an n-ary output signal (n is an integer equal to or greater than 2) and output the signal;
a PWM conversion unit configured to convert the n-value output signal into a PWM output signal having a duty corresponding to a level of the n-value output signal;
a pulse selection unit configured to select the pulse to be used from among the pulses constituting the PWM signal in a non-fixed manner with respect to the level of the n-value output signal;
Equipped with.

The exemplary signal processing circuit of the present disclosure can improve the SNR.

FIG. 1 is a diagram showing the configuration of a DA converter circuit. FIG. 2 is a diagram showing the internal configuration of the ΔΣ modulator provided in the DA converter circuit shown in FIG. FIG. 3 is a diagram showing a binary ΔΣ modulator. FIG. 4 is a diagram showing a five-level ΔΣ modulator. FIG. 5 is a diagram showing an example of improvement in quantization noise. FIG. 6 is a diagram showing an example of improvement in quantization noise. FIG. 7 is a diagram showing a configuration of an AD converter circuit. FIG. 8 is a diagram showing the internal configuration of the ΔΣ modulator provided in the AD converter circuit shown in FIG. FIG. 9 is a diagram showing a configuration of a signal processing circuit according to a comparative example. FIG. 10 is a diagram showing the correspondence relationship between the output level (output amplitude) of the ΔΣ modulator and the waveform of the PWM output signal. FIG. 11 is a diagram showing a configuration of a signal processing circuit according to the first embodiment of the present disclosure. FIG. 12 is a diagram comparing the waveforms of the PWM output signal between the comparative example and the embodiment of the present disclosure. FIG. 13 is a diagram showing the configurations of a DA converter circuit and an AD converter circuit according to the first embodiment of the present disclosure. FIG. 14 is a diagram showing a configuration of a signal processing circuit according to the second embodiment of the present disclosure. FIG. 15 is a diagram showing a configuration of an audio device according to an embodiment of the present disclosure.

Below, an exemplary embodiment of the present disclosure will be described with reference to the drawings.

<Digital-to-analog converter>
1 is a diagram showing the configuration of a DA converter circuit 5. The DA converter circuit 5 includes a ΔΣ modulator 1, a DAC (DA converter) 2, and an analog LPF (low pass filter) 3.

The ΔΣ modulator 1 oversamples the input digital input signal Din at a sampling frequency f and converts it into a low-bit digital output signal Dout using ΔΣ modulation. The digital output signal Dout is input to the DAC 2, which converts it from a digital signal to an analog signal. The converted analog signal is input to an analog LPF and converted into an analog output signal Aout. By oversampling, the quantization noise can be dispersed over a wide frequency band, so by processing the output of the DAC 2 with the analog LPF 3, the quantization noise is removed and an analog output signal Aout with good SNR can be obtained.

FIG. 2 is a diagram showing the internal configuration of the ΔΣ modulator 1 provided in the DA converter circuit 5.
The ΔΣ modulator 1 includes an integrator 1 A and a quantizer 1 B. The difference between a digital input signal Din and an output fed back from the quantizer 1 B is accumulated by the integrator 1 A, and is converted into a low-bit digital output signal Dout by the quantizer 1 B.

Figure 3 is a diagram showing a binary ΔΣ modulator 1 as an example of a ΔΣ modulator 1. The binary ΔΣ modulator 1 outputs a digital output signal Dout of 1 bit (0 or 1). As shown in Figure 3, the digital output signal Dout is composed of pulses indicating 0 or 1, and the pulse width is 1/f. The binary ΔΣ modulator 1 uses a binary quantizer 1B (Figure 2) internally.

Figure 4 shows a five-level ΔΣ modulator 1 as an example of a ΔΣ modulator 1. The five-level ΔΣ modulator 1 outputs a digital output signal Dout with five values (output = 0 to 4). The digital output signal Dout is output every 1/f.

There are two ways to improve the accuracy of a ΔΣ modulator: increasing the sampling frequency f, or increasing the quantization level of the quantizer.

When the sampling frequency f is increased, for example, from A1 to A2 in Figure 5, the quantization noise of the ΔΣ modulator is distributed over a wider frequency band, so the quantization noise in the signal band S is reduced. However, using a high sampling frequency f increases the effect of clock jitter, and an expensive phase locked loop (PLL) circuit is required to generate high frequencies with high precision.

The quantization level of quantizer 1B refers to the number of possible values (levels) that the output of quantizer 1B can have (e.g., five values). Increasing the quantization level reduces quantization noise across the entire frequency band, as shown by A3→A4 in Figure 6. However, this increases the number of output pins of quantizer 1B, resulting in increased area and cost. For example, a binary quantizer 1B has one output pin, while a five-level quantizer 1B has four output pins.

<A/D converter>
7 is a diagram showing a configuration of the AD converter circuit 50. The AD converter circuit 50 includes a ΔΣ modulator 10, a digital LPF 20, and a decimation filter 30.

The ΔΣ modulator 10 oversamples the input analog input signal Ain at a sampling frequency f and converts it into a low-bit digital output signal Dout using ΔΣ modulation. The digital output signal Dout is input to the digital LPF 20. The digital LPF 20 removes quantization noise from the digital output signal Dout, and the downstream decimation filter 30 thins out the sampling frequency.

Figure 8 is a diagram showing the internal configuration of the ΔΣ modulator 10 provided in the AD converter circuit 50. The ΔΣ modulator 10 has an integrator 10A, a quantizer 10B, and a DAC 10C. The difference between the analog input signal Ain and the output of the DAC 10C is accumulated by the integrator 10A, and converted into a low-bit digital output signal Dout by the quantizer 10B. The digital output signal Dout is converted into an analog signal by the DAC 10C and fed back to the input side.

The method for improving the accuracy of the ΔΣ modulator 10 used in such an AD converter circuit 50 and the problems associated with it are similar to those described above.

<PWM output configuration>
As a means for solving the above problem, for example, a signal processing circuit 300 as shown in Fig. 9 can be considered. The signal processing circuit 300 includes a ΔΣ modulator 100 and a PWM (Pulse Width Modulation) conversion unit 200. Here, the ΔΣ modulator 100 is assumed to be a 5-value output ΔΣ modulator as an example of a multi-value output.

The PWM conversion unit 200 converts the quinary output (output levels = 0 to 4) output from the ΔΣ modulator 100 into a PWM output signal Spwm. Here, FIG. 10 shows the correspondence between the output level (output amplitude) of the ΔΣ modulator 100 and the waveform of the PWM output signal Spwm. The PWM output signal Spwm is composed of four pulses arranged in a row, each with a width of 1/4f, where f is the sampling frequency of the ΔΣ modulator 100.

When the output level of the ΔΣ modulator 100 is 0, all four pulses in the PWM output signal are 0. When the output level of the ΔΣ modulator 100 is 1, the first pulse in the PWM output signal is 1, and the remaining pulses are 0. When the output level of the ΔΣ modulator 100 is 2, the first and second pulses in the PWM output signal are 1, and the remaining pulses are 0. When the output level of the ΔΣ modulator 100 is 3, the first to third pulses in the PWM output signal are 1, and the remaining pulses are 0. When the output level of the ΔΣ modulator 100 is 4, all four pulses in the PWM output signal are 1.

In this way, the pulse width (duty) of the PWM output signal is changed according to the multi-value output of the ΔΣ modulator 100. This allows the PWM conversion unit 200 to have only one output pin, and the quantization level of the ΔΣ modulator 100 can be increased.

When configuring a DA converter circuit using a signal processing circuit 300 configured as in FIG. 9, a DAC and an analog LPF are provided downstream of the signal processing circuit 300 as in FIG. 1 (in this case, the input to the ΔΣ modulator 100 is a digital input signal). Also, when configuring an AD converter circuit using a signal processing circuit 300 configured as in FIG. 9, a digital LPF and a decimation filter are provided downstream of the signal processing circuit 300 as in FIG. 7 (in this case, the input to the ΔΣ modulator 100 is an analog input signal). However, in such a DA converter circuit or AD converter circuit, there is a risk of an increase in the noise level.

<Embodiments of the present disclosure>
In consideration of the problems in a configuration using a PWM conversion unit as described above, an embodiment of the present disclosure is implemented as follows: Fig. 11 is a diagram showing a configuration of a signal processing circuit 500 according to a first embodiment of the present disclosure.

The signal processing circuit 500 includes a ΔΣ modulator 100 and a PWM conversion unit 200, similar to the configuration shown in FIG. 9 described above, and also includes a pulse selection unit 400. In the configuration shown in FIG. 9 described above, the pulses selected to generate the PWM output signal were fixed according to the output level of the ΔΣ modulator 100, as shown in FIG. 10. In contrast, in this embodiment, the pulses that make up the PWM output signal Spwm are non-fixedly selected by the pulse selection unit 400 according to the output level of the ΔΣ modulator 100. In other words, even at the same output level of the ΔΣ modulator 100, the selected pulses change.

Specifically, the pulse selection unit 400 performs pulse selection using an algorithm called DWA (Data Weighted Averaging). Figure 12 shows an example of a change in the output level (output amplitude) of the ΔΣ modulator 100 and the corresponding transition in the waveform of the PWM output signal Spwm, comparing the configuration shown in Figure 9 (comparative example) with the configuration according to this embodiment. The output level of the ΔΣ modulator 100 can range from 0 to 4.

In the configuration according to this embodiment, when the first and last pulses among the pulses constituting the PWM output signal Spwm are connected to form a circular ring shape by the pulse selection unit 400 using a DWA, the pulses to be used in the circular ring shape are selected in order from the first pulse according to the output level of the ΔΣ modulator 100. Note that the number of pulses constituting the PWM output signal Spwm is n-1, where the output of the ΔΣ modulator 100 is n-valued (n is an integer of 2 or more). In the example of FIG. 11, since the ΔΣ modulator 100 has a 5-value output configuration, the number of pulses constituting the PWM output signal Spwm is 5-1=4.

Specifically, as shown in FIG. 12, in a portion where output level = 1 occurs twice in succession (samples 2 and 3), the first pulse is selected both times in the comparative example, but in this embodiment, the first pulse is selected the first time, and then the second pulse is selected the second time. In this embodiment, in a portion where output level = 2 occurs twice in succession (samples 4 and 5), the third and fourth pulses are selected the first time, and then the first and second pulses are selected the second time. In this embodiment, in a portion where output level = 3 occurs twice in succession (samples 6 and 7), the third, fourth and first pulses are selected the first time, and then the second, third and fourth pulses are selected the second time. Thereafter, four pulses are selected in a circular pattern in the same manner.

In this way, in this embodiment, the frequency of pulse use can be made uniform by performing pulse selection using the DWA. When a DA converter circuit is configured using the signal processing circuit 500 according to this embodiment, a DAC 2 and an analog LPF 3 are provided in the rear stage of the signal processing circuit 500 as in the DA converter circuit 600 shown in FIG. 13 (in this case, the input of the ΔΣ modulator 100 is a digital input signal Din). When an AD converter circuit is configured using the signal processing circuit 500 according to this embodiment, a digital LPF 20 and a decimation filter 30 are provided in the rear stage of the signal processing circuit 500 as in the AD converter circuit 700 shown in FIG. 12 (in this case, the input of the ΔΣ modulator 100 is an analog input signal Ain). The SNR can be improved in the DA converter circuit 600 or AD converter circuit 700 using the signal processing circuit 500 according to this embodiment. The effect of such characteristic improvement has been verified by the inventor of the present application.

In the embodiment described above, the PWM conversion unit 200 has one output pin, but the PWM conversion unit may have multiple output pins. Here, such a modification is described. FIG. 14 is a diagram showing the configuration of a signal processing circuit 510 according to the second embodiment of the present disclosure. The signal processing circuit 510 shown in FIG. 14 includes a ΔΣ modulator 110, a pulse selection unit 400, and a PWM conversion unit 210.

In the example of FIG. 14, the ΔΣ modulator 110 is configured to output 17 values, and the number of output pins of the PWM conversion unit 210 is four. That is, the PWM output signal Spwm is output from the four output pins of the PWM conversion unit 210. In this embodiment, the output of the ΔΣ modulator 110 is n values (n is an integer equal to or greater than 2), and (number of output pins of the PWM conversion unit 210) × (number of pulses per output pin) + 1 = n. In the example of FIG. 14, the number of pulses per output pin = 4, so 4 × 4 + 1 = 17 values. Therefore, in this embodiment, the quantization level of the ΔΣ modulator 110 can be further increased.

In this embodiment, the pulse selection unit 400 performs pulse selection using a DWA. More specifically, when the first and last pulses of the pulses at all pins of the PWM conversion unit 210, that is, the number of pulses represented by (the number of output pins of the PWM conversion unit 210) x (the number of pulses per output pin) are connected to form a circular ring, pulses are selected in order in the circular ring according to the output level of the ΔΣ modulator 110. This averages the frequency of use of the output pins, so that when, for example, a current segment type DAC is provided downstream of the PWM conversion unit 210, the frequency of use of the constant current source in the current segment type DAC is averaged. This makes it possible to suppress a decrease in SNR caused by a mismatch of the constant current source.

The pulse selection unit may use a method of pulse selection other than the above-mentioned DWA, such as dynamic element matching, or may select pulses randomly.

<Application to audio equipment>
The signal processing circuit according to the embodiment of the present disclosure can be applied to various devices, but is preferably applied to an audio device, for example, as shown in Fig. 15. An audio device 800 shown in Fig. 15 includes a DA converter 600 (Fig. 13) using a signal processing circuit 500. In this case, a digital audio input signal is used as a digital input signal Din in the signal processing circuit 500. Also, an audio device 900 shown in Fig. 15 includes an AD converter 700 (Fig. 13) using the signal processing circuit 500. In this case, an analog audio input signal is used as an analog input signal Ain in the signal processing circuit 500.

＜Other＞
In addition to the above-mentioned embodiment, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-mentioned embodiment, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

<Additional Notes>
As described above, the signal processing circuit (500) according to one embodiment of the present disclosure includes:
A ΔΣ modulator (100) configured to convert an input signal into an n-value output signal (n is an integer equal to or greater than 2) and output the signal;
a PWM conversion unit (200) configured to convert the n-value output signal into a PWM output signal having a duty corresponding to a level of the n-value output signal;
and a pulse selection unit (400) configured to select the pulses to be used from among the pulses constituting the PWM signal in a non-fixed manner with respect to the level of the n-value output signal (first configuration).

In the first configuration, the number of output pins of the PWM conversion unit is one,
The number of pulses may be n-1 (second configuration).

In the first configuration, the PWM conversion unit has a plurality of output pins,
A configuration where (the number of the output pins)×(the number of the pulses per one of the output pins)+1=n may be used (third configuration).

In addition, in any of the first to third configurations, the pulse selection unit may be configured to sequentially select the pulses to be used in a circular ring shape when the first and last pulses among the pulses to be used are connected to form the circular ring shape (fourth configuration).

In addition, in any of the first to third configurations, the pulse selection unit may be configured to randomly select the pulse to be used (fifth configuration).

A DA converter circuit (600) according to one aspect of the present disclosure includes a signal processing circuit (500) having any one of the first to fifth configurations described above, a DA converter (2) arranged downstream of the signal processing circuit, and an analog low-pass filter (3) arranged downstream of the DA converter (sixth configuration).

An AD converter circuit (700) according to one aspect of the present disclosure includes a signal processing circuit (500) having any one of the first to fifth configurations described above, a digital low-pass filter (20) arranged downstream of the signal processing circuit, and a decimation filter (30) arranged downstream of the digital low-pass filter (seventh configuration).

An audio device (800) according to one aspect of the present disclosure includes a DA converter circuit (600) having the sixth configuration described above (eighth configuration).

An audio device (900) according to one aspect of the present disclosure includes an AD converter circuit (700) having the seventh configuration described above (ninth configuration).

This disclosure can be used in a variety of devices, such as audio equipment.

1 ΔΣ modulator 1A integrator 1B quantizer 2 DA converter 3 analog low-pass filter 5 DA converter circuit 10 ΔΣ modulator 10A integrator 10B quantizer 10C DA converter 20 digital low-pass filter 30 decimation filter 50 AD converter circuit 100 ΔΣ modulator 110 ΔΣ modulator 200 PWM conversion section 210 PWM conversion section 300 signal processing circuit 400 pulse selection section 500 signal processing circuit 510 signal processing circuit 600 DA converter circuit 700 AD converter circuit 800 audio device 900 audio device

Claims (9)

a ΔΣ modulator configured to convert an input signal into an n-ary output signal (n is an integer equal to or greater than 2) and output the signal;
a PWM conversion unit configured to convert the n-value output signal into a PWM output signal having a duty corresponding to a level of the n-value output signal;
a pulse selection unit configured to select the pulse to be used from among the pulses constituting the PWM signal in a non-fixed manner with respect to the level of the n-value output signal;
A signal processing circuit comprising: The number of output pins of the PWM conversion unit is one,
2. The signal processing circuit according to claim 1, wherein the number of pulses=n-1. The PWM conversion unit has a plurality of output pins,
2. The signal processing circuit of claim 1, wherein (the number of said output pins) x (the number of said pulses per said output pin) + 1 = n. The signal processing circuit according to claim 1, wherein the pulse selection unit is configured to sequentially select the pulses to be used in a circular ring shape when the first and last pulses among the pulses to be used are connected to form the circular ring shape. The signal processing circuit of claim 1, wherein the pulse selection unit is configured to randomly select the pulse to be used. A DA converter circuit comprising the signal processing circuit according to any one of claims 1 to 5, a DA converter arranged downstream of the signal processing circuit, and an analog low-pass filter arranged downstream of the DA converter. An AD converter circuit comprising the signal processing circuit according to any one of claims 1 to 5, a digital low-pass filter arranged downstream of the signal processing circuit, and a decimation filter arranged downstream of the digital low-pass filter. An audio device equipped with the DA converter circuit according to claim 6. An audio device comprising the AD converter circuit according to claim 7.

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