JP2025079969A - Non-volatile memory device - Google Patents

Abstract

To provide a nonvolatile memory device capable of shortening time required for shipping tests.SOLUTION: A nonvolatile memory device (1) including a first memory element (M1) and a second memory element (M2) that are complementary and can execute program operations is configured to use either the first memory element or the second memory element as a test target to determine a threshold value with a reference current supplied from the outside, and determine the magnitude relation between the current flowing in the test target and the threshold value.SELECTED DRAWING: Figure 2

Description

The invention disclosed herein relates to a non-volatile memory device.

The semiconductor non-volatile memory circuit proposed in Patent Document 1 is configured by integrating a transistor pair, which is a memory cell for storing one bit of data, and is made up of a first transistor and a second transistor having a higher on-state current than the first transistor.

JP 2011-103158 A

[overview]
If analog characteristics of memory cells are directly measured in the shipping test of a semiconductor nonvolatile memory circuit as proposed in Patent Document 1, the shipping test takes a very long time.

The non-volatile memory device disclosed in this specification includes a first memory element and a second memory element that are complementary to each other and capable of executing a program operation, and is configured to test either the first memory element or the second memory element, determine a threshold value based on an externally supplied reference current, and determine whether the current flowing through the test object is greater than or less than the threshold value.

FIG. 1 is a block diagram showing an example of the overall configuration of a nonvolatile memory device. FIG. 2 is a circuit diagram showing an example of the configuration of a memory array. FIG. 3 is a diagram showing the gate-source voltage dependence of the drain current of a memory element before and after hot carrier injection. FIG. 4 is a timing chart showing example waveforms of the signal XRST, the voltage V1 on the line Ln1, and the voltage V2 on the line Ln2.

Detailed Description
In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure is composed of at least three layers: a "layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," an "insulating layer," and a "P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. Hereinafter, an N-channel MOS field effect transistor is referred to as an NMOS transistor, and a P-channel MOS field effect transistor is referred to as a PMOS transistor.

<Non-volatile memory device>
1 is a block diagram showing an example of the overall configuration of a nonvolatile memory device 1. The nonvolatile memory device 1 shown in FIG.

The memory array 10 includes m gate lines G1 to Gm (=word lines) laid in the X-axis direction, 2n bit lines BL1 to BL2n laid in the Y-axis direction, and a plurality of (=m×n) memory cells CELL arranged in a matrix along the gate lines G1 to Gm and the bit lines BL1 to BL2n. The configuration and operation of the memory array 10 will be described in detail later.

The X-decoder (row decoder) 20 drives the gate lines G1 to Gm in response to instructions from the controller 50.

The Y decoder (column decoder) 30 drives the bit lines BL1 to BL2n in response to instructions from the controller 50.

The controller 40 controls each part of the device in response to commands input from outside the device.

<Memory Array>
2 is a circuit diagram showing a configuration example of the memory array 10. The memory array 10 shown in FIG. 2 includes a first memory element M1, a second memory element M2, a sense amplifier SA, NMOS transistors Q1 and Q2, and PMOS transistors Q3 and Q4. A pair of the first memory element M1 and the second memory element M2 constitutes one memory cell CELL (see FIG. 1). In FIG. 2, the first memory element M1 arranged in the first row and first column of the matrix is represented as the first memory element M1(1,1), the first memory element M1 arranged in the second row and first column of the matrix is represented as the first memory element M1(2,1), the second memory element M2 arranged in the first row and first column of the matrix is represented as the second memory element M2(1,1), and the second memory element M2 arranged in the second row and first column of the matrix is represented as the second memory element M1(2,1).

The combination of the first memory element M1 and the second memory element M2 stores data "0" or "1".

The first memory element M1 and the second memory element M2 are each composed of an NMOS transistor. The first memory element M1 and the second memory element M2 are each an element capable of executing a program operation by changing the transistor characteristics through hot carrier injection, and are also referred to as an OTP (One Time Programmable) element. Note that the first memory element M1 and the second memory element M2 may be elements other than NMOS transistors as long as they are elements capable of executing a program operation.

The gates of the first memory element M1 and the second memory element M2 arranged in the i-th row are connected to the gate line Gk. i is any natural number between 1 and m. The drain of the first memory element M1 is connected to the first input terminal of the sense amplifier SA via the NMOS transistor Q1. The drain of the second memory element M2 is connected to the second input terminal of the sense amplifier SA via the NMOS transistor Q2.

The source of the first memory element M1 is connected to the source of the PMOS transistor Q3. The source of the second memory element M2 is connected to the source of the PMOS transistor Q4. The drain of the PMOS transistor Q4 arranged in the jth column is connected to the bit line BL2j-1. The drain of the PMOS transistor Q3 arranged in the jth column is connected to the bit line BL2j. j is any natural number between 1 and n.

Before the program operation is performed in the first memory element M1 and the second memory element M2, the drain current Id1 flowing through the first memory element M1 is equal to the drain current Id2 flowing through the second memory element M2. In this case, since there is no difference between the drain current Id1 flowing through the first memory element M1 and the drain current Id2 flowing through the second memory element M2, the data becomes indefinite. In other words, in the non-volatile memory device 1, the initial value of the data is not set in the state where the program operation is not performed in the first memory element M1 and the second memory element M2.

Here, with regard to transistors, the structure is a concept that includes the size of the transistor, and therefore, for any number of transistors, the structure being the same means that the size of the multiple transistors is also the same. When certain transistors have the same structure, if hot carrier injection has not been performed on the multiple transistors by a program operation, the electrical characteristics (including gate threshold voltage, etc.) of the multiple transistors will also be the same. However, the structure and electrical characteristics of any number of transistors being the same means that they are the same by design, and may actually include errors (i.e., same is understood to be a concept that includes errors).

The non-volatile memory device 1 can perform a read operation to read data stored in the first memory element M1 and the second memory element M2, and a program operation (write operation) to store data (logical values) in the first memory element M1 and the second memory element M2.

In the program operation, hot carriers are injected into one of the first memory element M1 and the second memory element M2 to change the electrical characteristics of one of the first memory element M1 and the second memory element M2. This change causes the gate threshold voltage of one of the first memory element M1 and the second memory element M2 to rise. Here, in FIG. 3, the solid line waveform INI represents the gate-source voltage dependency of the drain current of one of the first memory element M1 and the second memory element M2 before the program operation is executed. Also, in FIG. 3, the dotted line waveform PRG represents the gate-source voltage dependency of the drain current of one of the first memory element M1 and the second memory element M2 after the program operation is executed. In this way, the program operation causes the gate threshold voltage Vth of one of the first memory element M1 and the second memory element M2 to rise.

For example, when the controller 40 executes a program operation on the first memory element M1 (1,1) and the second memory element M2 (1,1), the controller 40 applies a high voltage (power supply voltage VDD) to the gate line G1 connected to the gates of the first memory element M1 (1,1) and the second memory element M2 (1,1) that execute the program operation, and turns on the switch S12 described later. Then, when the transistor that injects hot carriers is the first memory element M1 (1,1), the controller 40 turns on the switch S7 described later to ground the drain of the first memory element M1 (1,1) that injects hot carriers, and turns off the switch S8 described later. On the other hand, when the transistor that injects hot carriers is the second memory element M2 (1,1), the controller 40 turns on the switch S8 described later to ground the drain of the second memory element M2 (1,1) that injects hot carriers, and turns off the switch S7 described later.

When the drain current Id1 of the first memory element M1 and the drain current Id2 of the second memory element M2 are supplied, the sense amplifier SA outputs an output signal DOUT corresponding to the value (logical value) of the data stored in the memory cell CELL based on the magnitude relationship between the drain current Id1 of the first memory element M1 and the drain current Id2 of the second memory element M2 during a read operation.

Before the program operation is performed, hot carriers are injected into the first memory element M1 and the second memory element M2, causing the gate threshold voltage of the first memory element M1 to rise. As a result, after the program operation is performed, the gate threshold voltage of the first memory element M1 becomes higher than the gate threshold voltage of the second memory element M2. Therefore, the drain current Id1 of the first memory element M1 becomes smaller than the drain current Id2 of the second memory element M2. The state in which the drain current Id1 of the first memory element M1 is smaller than the drain current Id2 of the second memory element M2 corresponds to a state in which data "0" is stored. Therefore, in a read operation, when the drain current Id1 of the first memory element M1 is smaller than the drain current Id2 of the second memory element M2, the sense amplifier SA outputs an output signal DOUT (low level DOUT) corresponding to data "0".

On the other hand, before the program operation is performed, hot carriers are injected into the second memory element M2 of the first memory element M1 and the second memory element M2, and the gate threshold voltage of the second memory element M2 rises. As a result, after the program operation is performed, the gate threshold voltage of the second memory element M2 becomes higher than the gate threshold voltage of the first memory element M1. Therefore, the drain current Id1 of the first memory element M1 becomes higher than the drain current Id2 of the second memory element M2. The state in which the drain current Id1 of the first memory element M1 is higher than the drain current Id2 of the second memory element M2 corresponds to a state in which data "1" is stored. Therefore, in a read operation, when the drain current Id1 of the first memory element M1 is higher than the drain current Id2 of the second memory element M2, the sense amplifier SA outputs an output signal DOUT (high level DOUT) corresponding to data "1".

As shown in FIG. 2, the sense amplifier SA includes PMOS transistors Q5 and Q6, switches S1 to S4, and inverters IV1 to IV4. The memory array 10 also includes switches S5 to S12.

The source of the PMOS transistor Q6 is connected to the application terminal of the power supply voltage VDD. The drain of the PMOS transistor Q6 is connected to the line Ln1. The gate of the PMOS transistor Q6 is connected to the line Ln2. The line Ln1 is connected to the drain of the first memory element M1 via the NMOS transistor Q1. The line Ln2 is connected to the drain of the second memory element M2 via the NMOS transistor Q2.

The source of the PMOS transistor Q5 is connected to the application terminal of the power supply voltage VDD. The drain of the PMOS transistor Q5 is connected to the line Ln2. The gate of the PMOS transistor Q5 is connected to the line Ln1.

A switch S1 is connected between the application terminal of the power supply voltage VDD and the line Ln1. A switch S2 is connected between the application terminal of the power supply voltage VDD and the line Ln2.

The input terminal of inverter IV1 is connected to line Ln1. The output terminal of inverter IV1 is connected to the input terminal of inverter IV2. The output terminal of inverter IV2 is connected to the input terminal of inverter IV3. An output signal DOUT is output from inverter IV3.

Switches S3 and S5 are connected between the line Ln1 and the ground terminal. The on/off of the switch S3 is controlled according to the output of the inverter IV1. Switches S4 and S6 are connected between the line Ln2 and the ground terminal. The input terminal of the inverter IV4 is connected to the line Ln2. The on/off of the switch S4 is controlled according to the output of the inverter IV4. A switch S7 is connected between the source of the NMOS transistor Q1 and the ground terminal. A switch S8 is connected between the source of the NMOS transistor Q2 and the ground terminal. A switch S9 is connected between the drain of the PMOS transistor Q3 and the application terminal of the power supply voltage VDD. A switch S10 is connected between the drain and source of the PMOS transistor Q4 and the application terminal of the power supply voltage VDD. A switch S11 is connected between the sources of the first memory element M1 and the second memory element M2 and the ground terminal. A switch S12 is connected between the sources of the first memory element M1 and the second memory element M2 and the application terminal of the power supply voltage VDD.

The controller 40 can output a signal XRST and controls the on/off of switches S1 and S2.

Here, FIG. 4 is a timing chart showing example waveforms of the signal XRST, the voltage V1 on line Ln1, and the voltage V2 on line Ln2. The operation of the sense amplifier SA will be described with reference to FIG. 4 as well. In a read operation, the period during which the signal XRST is at a low level is called a precharge period, and the period during which it is at a high level is called a read period. In addition, in a read operation, the controller 40 turns on the switches S5 and S6.

During the precharge period, during which the signal XRST is at a low level, the controller 40 sets the gate voltages of the first memory element M1 and the second memory element M2 to a low level and turns on the switches S1 and S2. This shorts the gates and sources of the PMOS transistors Q5 and Q6, turning them off. A positive charge is supplied to the line Ln1 via the switch S1 in the on state, and the voltage V1 reaches the level of the power supply voltage VDD. A positive charge is supplied to the line Ln2 via the switch S2 in the on state, and the voltage V2 also reaches the level of the power supply voltage VDD. At this time, the outputs of the inverters IV1 and IV4 are at a low level, so the switches S3 and S4 are turned off.

When the signal XRST is switched from low to high to transition from the precharge period to the read period, the controller 40 sets the gate voltages of the first memory element M1 and the second memory element M2 to high level and turns off the switches S1 and S2. When the drain current Id2 of the second memory element M2 flows, the voltage V2 drops, and when the drain current Id1 of the first memory element M1 flows, the voltage V1 drops.

In a read operation after performing a program operation and injecting hot carriers into the first memory element M1, the drain current Id1 of the first memory element M1 is approximately zero, and the drain current Id2 of the second memory element M2 is greater than the drain current Id1 of the first memory element M1, so the voltage V2 drops (V2 (Id2>Id1) in FIG. 4). When the voltage V2 reaches the threshold value Th, the output of the inverter IV4 switches from low to high, and the switch S4 is switched on. As a result, the voltage V2=0V, the PMOS transistor Q6 turns on, and the voltage V1=VDD. At this time, the PMOS transistor Q5 turns off. Therefore, the output signal DOUT output from the inverter IV3 becomes low. That is, the output signal DOUT is output as a signal indicating that "0" is stored.

On the other hand, in a read operation after the program operation is performed and hot carriers are injected into the second memory element M2, the drain current Id2 of the second memory element M2 is approximately zero. Since the drain current Id2 of the second memory element M2 is smaller than the drain current Id1 of the first memory element M1, the voltage V1 drops. When the voltage V1 reaches the threshold value Th, the output of the inverter IV1 switches from low to high, and the switch S3 is switched on. As a result, the voltage V1=0V, the PMOS transistor Q5 is turned on, and the voltage V2=VDD. At this time, the PMOS transistor Q6 is turned off. Therefore, the output signal DOUT output from the inverter IV3 becomes high. In other words, the output signal DOUT is output as a signal indicating that "1" is stored.

<Shipping test>
Before the non-volatile memory device 1 is shipped, a shipping test is performed on the non-volatile memory device 1 .

In the case of a shipping test based on the difference between the drain current Id1 of the first memory element M1 and the drain current Id2 of the second memory element M2, even if the difference between the drain current Id1 of the first memory element M1 and the drain current Id2 of the second memory element M2 is small due to insufficient hot carrier injection, it will not be determined to be defective as long as the difference between current Id1 and current Id2 can be detected by the sense amplifier SA. However, if the difference between current Id1 and current Id2 is small, there is a risk that data will be rewritten due to the escape of hot carriers after shipping. Therefore, if the difference between current Id1 and current Id2 is small after a program operation is executed, it should be identified as defective.

By directly measuring the currents Id1 and Id2, it is possible to detect that the difference between the currents Id1 and Id2 is small, but if the currents Id1 and Id2 are directly measured in a shipping test, a problem occurs in that the shipping test takes a long time.

The non-volatile memory device 1 solves the above problem by providing a shipping test circuit 11 in the memory array 10. In other words, the non-volatile memory device 1 can reduce the time required for shipping tests.

The shipping test circuit 11 includes a terminal T1, NMOS transistors Q7 and Q8, n NMOS transistors Q9, and n NMOS transistors Q10.

Terminal T1 is configured to receive a reference current IREF supplied from outside the non-volatile memory device 1.

The terminal T1 is connected to the drains and gates of the NMOS transistors Q7 and Q9, and to the gates of the NMOS transistors Q8 and Q10. The source of the NMOS transistor Q7 is connected to the drain of the NMOS transistor Q8. The sources of the NMOS transistors Q8 and Q10 are connected to the ground terminal. The drain of the NMOS transistor Q9 arranged in the jth column is connected to the first terminals of the switches S13 and S14 arranged in the jth column. The second terminal of the switch S13 is connected to the line Ln2. The second terminal of the switch S14 is connected to the line Ln1. The NMOS transistors Q7 to Q10 form a cascode-connected current mirror circuit. The threshold voltage of the NMOS transistor Q8 is higher than the threshold voltage of the NMOS transistor Q7 that is cascode-connected to the NMOS transistor Q8. The threshold voltage of the NMOS transistor Q10 is higher than the threshold voltage of the NMOS transistor Q9 that is cascode-connected to the NMOS transistor Q10. The drain current of NMOS transistor Q9 is a mirrored current of the drain current of NMOS transistor Q7. Therefore, the value (threshold) of the drain current of NMOS transistor Q9 is a value that corresponds to the value of the reference current IREF.

The non-volatile memory device 1 performs a first test. In the first test, the first memory element M1 is the test target before a program operation is executed.

The controller 40 sets the gate voltage of the first memory element M1 to be tested to a high level, turns on the NMOS transistor Q1 in the same column as the first memory element M1 to be tested, and turns off the switch S14 in the same column as the first memory element M1 to be tested. Furthermore, the controller 40 turns off the NMOS transistor Q2 in the same column as the first memory element M1 to be tested, and turns on the switch S13 in the same column as the first memory element M1 to be tested.

As a result, the sense amplifier SA in the same column as the first memory element M1 to be tested determines whether the drain current of the first memory element M1 to be tested is greater than the threshold value. In the first test, the value of the reference current IREF is adjusted so that the threshold value is 80α, for example. If the drain current of the first memory element M1 before the program operation to be tested is executed is greater than the threshold value, it is determined that there is no abnormality in the first memory element M1 before the program operation to be tested is executed. On the other hand, if the drain current of the first memory element M1 before the program operation to be tested is executed is less than the threshold value, it is determined that there is an abnormality in the first memory element M1 before the program operation to be tested is executed.

The non-volatile memory device 1 performs a second test. In the second test, the second memory element M2 is the test target before the program operation is executed.

The controller 40 sets the gate voltage of the second memory element M2 to be tested to a high level, turns on the NMOS transistor Q2 in the same column as the second memory element M2 to be tested, and turns off the switch S13 in the same column as the second memory element M2 to be tested. Furthermore, the controller 40 turns off the NMOS transistor Q1 in the same column as the second memory element M2 to be tested, and turns on the switch S14 in the same column as the second memory element M2 to be tested.

As a result, the sense amplifier SA in the same column as the second memory element M2 to be tested determines whether the drain current of the second memory element M2 to be tested is greater than the threshold value. In the second test, the value of the reference current IREF is adjusted so that the threshold value is 80α, for example. If the drain current of the second memory element M2 before the program operation to be tested is executed is greater than the threshold value, it is determined that there is no abnormality in the second memory element M2 before the program operation to be tested is executed. On the other hand, if the drain current of the second memory element M2 before the program operation to be tested is executed is less than the threshold value, it is determined that there is an abnormality in the second memory element M2 before the program operation to be tested is executed.

The non-volatile memory device 1 performs a third test. In the third test, the memory element into which hot carriers are injected of the first memory element M1 and the second memory element M2 after the program operation is executed is the test target. The memory element into which hot carriers are injected by executing the program operation is a memory element whose characteristics are expected to change so that it becomes difficult for current to flow due to the execution of the program operation.

The following describes the case where the first memory element M1 after the program operation is a memory element into which hot carriers have been injected. The controller 40 sets the gate voltage of the first memory element M1 under test to a high level, turns on the NMOS transistor Q1 in the same column as the first memory element M1 under test, and turns off the switch S14 in the same column as the first memory element M1 under test. Furthermore, the controller 40 turns off the NMOS transistor Q2 in the same column as the first memory element M1 under test, and turns on the switch S13 in the same column as the first memory element M1 under test.

As a result, the sense amplifier SA in the same column as the first memory element M1 to be tested determines whether the drain current of the first memory element M1 to be tested is greater than the threshold value. In the third test, the value of the reference current IREF is adjusted so that the threshold value is 5α, for example. If the drain current of the first memory element M1 after the program operation to be tested is executed is smaller than the threshold value, it is determined that there is no abnormality in the first memory element M1 after the program operation to be tested is executed. On the other hand, if the drain current of the first memory element M1 after the program operation to be tested is executed is larger than the threshold value, it is determined that there is an abnormality in the first memory element M1 after the program operation to be tested is executed.

The non-volatile memory device 1 performs a fourth test. In the fourth test, the memory element into which hot carriers are not injected of the first memory element M1 and the second memory element M2 after the program operation is executed is the test object. The memory element into which hot carriers are not injected by the execution of the program operation is a memory element whose characteristics are expected not to change by the execution of the program operation.

Below, we will explain the case where the second memory element M2 after the program operation is executed is a memory element into which hot carriers are not injected. The controller 40 sets the gate voltage of the second memory element M2 to be tested to a high level, turns on the NMOS transistor Q2 in the same column as the second memory element M2 to be tested, and turns off the switch S13 in the same column as the second memory element M2 to be tested. Furthermore, the controller 40 turns off the NMOS transistor Q1 in the same column as the second memory element M2 to be tested, and turns on the switch S14 in the same column as the second memory element M2 to be tested.

As a result, the sense amplifier SA in the same column as the second memory element M2 to be tested determines whether the drain current of the second memory element M2 to be tested is greater than the threshold value. In the fourth test, the value of the reference current IREF is adjusted so that the threshold value is 80α, for example. If the drain current of the second memory element M2 after the program operation to be tested is executed is greater than the threshold value, it is determined that there is no abnormality in the second memory element M2 after the program operation to be tested is executed. On the other hand, if the drain current of the second memory element M2 after the program operation to be tested is executed is less than the threshold value, it is determined that there is an abnormality in the second memory element M2 after the program operation to be tested is executed.

The non-volatile memory device 1 performs the fifth test. In the fifth test, the first memory element M1 is the test target after the erase operation is performed.

The controller 40 sets the gate voltage of the first memory element M1 to be tested to a high level, turns on the NMOS transistor Q1 in the same column as the first memory element M1 to be tested, and turns off the switch S14 in the same column as the first memory element M1 to be tested. Furthermore, the controller 40 turns off the NMOS transistor Q2 in the same column as the first memory element M1 to be tested, and turns on the switch S13 in the same column as the first memory element M1 to be tested.

As a result, the sense amplifier SA in the same column as the first memory element M1 to be tested determines whether the drain current of the first memory element M1 to be tested is greater than the threshold value. In the first test, the value of the reference current IREF is adjusted so that the threshold value is 80α, for example. If the drain current of the first memory element M1 to be tested after the erase operation to be performed is greater than the threshold value, it is determined that there is no abnormality in the first memory element M1 to be tested after the erase operation to be performed. On the other hand, if the drain current of the first memory element M1 to be tested after the erase operation to be performed is less than the threshold value, it is determined that there is an abnormality in the first memory element M1 to be tested after the erase operation to be performed.

The non-volatile memory device 1 performs the sixth test. In the sixth test, the second memory element M2 after the erase operation is performed is the test target.

The controller 40 sets the gate voltage of the second memory element M2 to be tested to a high level, turns on the NMOS transistor Q2 in the same column as the second memory element M2 to be tested, and turns off the switch S13 in the same column as the second memory element M2 to be tested. Furthermore, the controller 40 turns off the NMOS transistor Q1 in the same column as the second memory element M2 to be tested, and turns on the switch S14 in the same column as the second memory element M2 to be tested.

As a result, the sense amplifier SA in the same column as the second memory element M2 to be tested determines whether the drain current of the second memory element M2 to be tested is greater than the threshold value. In the second test, the value of the reference current IREF is adjusted so that the threshold value is 80α, for example. If the drain current of the second memory element M2 to be tested after the erase operation to be performed is greater than the threshold value, it is determined that there is no abnormality in the second memory element M2 to be tested after the erase operation to be performed. On the other hand, if the drain current of the second memory element M2 to be tested after the erase operation to be performed is less than the threshold value, it is determined that there is an abnormality in the second memory element M2 to be tested after the erase operation to be performed.

As described above, the threshold in the third test is different from the threshold in the first test, the threshold in the second test, the threshold in the fourth test, the threshold in the fifth test, and the threshold in the sixth test. Specifically, the threshold in the third test is smaller than the threshold in the first test, the threshold in the second test, the threshold in the fourth test, the threshold in the fifth test, and the threshold in the sixth test. In the above example, the threshold in the first test, the threshold in the second test, the threshold in the fourth test, the threshold in the fifth test, and the threshold in the sixth test are the same value, but some or all of the threshold in the first test, the threshold in the second test, the threshold in the fourth test, the threshold in the fifth test, and the threshold in the sixth test may be different values.

The memory array 10 shown in FIG. 2 further includes an inverter IV5, NAND gates N1 to N3, and buffers B1 and B2.

The circuit composed of inverter IV5, NAND gates N1 and N2, and buffers B1 and B2 controls the on/off of NMOS transistors Q1 and Q2 based on signals SG1 and SG2 output from controller 40. Signal SG1 is supplied to the first input terminals of NAND gates N1 and N2. Signal SG2 is supplied to the second input terminal of NAND gate N1. Signal SG2 is supplied to the input terminal of inverter IV5. The output terminal of inverter IV5 is connected to the second input terminal of NAND gate N2. The output terminal of NAND gate N1 is connected to the gate of NMOS transistor Q1 via buffer B1. The output terminal of NAND gate N2 is connected to the gate of NMOS transistor Q2 via buffer B2.

Signal SG1 goes high when a shipping test is being performed and goes low when a shipping test is not being performed. Signal SG2 is the same signal that goes low when hot carriers are injected into the first memory element M1 and goes high when hot carriers are injected into the second memory element M2.

The NAND gate N3 controls the on/off of the PMOS transistors Q3 and Q4 based on the signals SG2 and SG3 output from the controller 40. The signal SG2 is supplied to the first input terminal of the NAND gate N3. The signal SG3 is supplied to the second input terminal of the NAND gate N3. The output terminal of the NAND gate N3 is connected to the gates of the PMOS transistors Q3 and Q4.

＜Other＞
The embodiments of the present disclosure may be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The various embodiments described above may be combined as appropriate within a range that does not cause inconsistency. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments.

In the above-mentioned shipping test, the controller 40 controls the gate voltage of the NMOS transistor under test at two values (high level or low level), but in, for example, debugging and evaluation tests, the controller 40 may be able to control the gate voltage of the NMOS transistor under test at three or more values. This makes it possible to inspect a wide range of characteristics of the NMOS transistor under test.

<Additional Notes>
Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

The non-volatile memory device (1) disclosed herein is a configuration (first configuration) that includes a complementary first memory element (M1) and a second memory element (M2) capable of executing program operations, and is configured to test either the first memory element or the second memory element, determine a threshold value based on a reference current supplied from the outside, and determine the magnitude relationship between the current flowing through the test object and the threshold value.

The non-volatile memory device of the first configuration described above eliminates the need to directly measure the analog characteristics of the memory cells, thereby reducing the time required for shipping tests.

The non-volatile memory device of the first configuration may be configured (second configuration) to perform a first test in which the first memory element is the test subject before the program operation is executed, and a second test in which the second memory element is the test subject before the program operation is executed.

The non-volatile memory device of the first configuration may be configured to perform a third test (third configuration) on the first memory element and the second memory element after the program operation is executed, the memory element being the test subject whose characteristics are expected to change due to the program operation so that it becomes difficult for a current to flow.

The non-volatile memory device of the third configuration may be configured to perform a fourth test (fourth configuration) on the first memory element and the second memory element after the program operation is executed, the memory element being the test subject whose characteristics are expected not to change due to the execution of the program operation.

In the non-volatile memory device of the fourth configuration, the threshold value in the third test and the threshold value in the fourth test may be configured to be different from each other (fifth configuration).

The non-volatile memory device of the third configuration may be configured to perform a first test in which the first memory element is the test subject before the program operation is executed, and a second test in which the second memory element is the test subject before the program operation is executed, and may be configured to set the threshold value in the third test and the threshold value in the first test to different values, and may be configured to set the threshold value in the third test and the threshold value in the second test to different values (sixth configuration).

The non-volatile memory device of the first configuration may be configured to perform a fifth test in which the first memory element is the test subject after an erase operation has been performed, and a sixth test in which the second memory element is the test subject after the erase operation has been performed (seventh configuration).

In the non-volatile memory device having the third configuration, a fifth test is performed on the first memory element after an erase operation is performed, and a sixth test is performed on the second memory element after the erase operation is performed,
The threshold value in the third test and the threshold value in the fifth test may be set to different values, and the threshold value in the third test and the threshold value in the sixth test may be set to different values (eighth configuration).

In the non-volatile memory device of any of the first to eighth configurations, the first memory element and the second memory element may each be an NMOS transistor, and the gate voltage of the NMOS transistor to be tested may be controlled between three or more values (ninth configuration).

1 Non-volatile memory device 10 Memory array 11 Shipping test circuit 20 X-decoder 30 Y-decoder 40 Controller B1, B1 Buffer BL1 to BL2n Bit line CELL Memory cell G1 to Gm Gate line IV1 to IV5 Inverter Ln1, Ln2 Line M1, M2 Memory element N1, N2 NAND gate Q1, Q2 NMOS transistor Q3 to Q6 PMOS transistor S1 to S14 Switch

Claims (9)

a first memory element and a second memory element, each of which is complementary to each other and capable of performing a program operation;
A non-volatile memory device configured to test either the first memory element or the second memory element, determine a threshold value using a reference current supplied from the outside, and determine the relationship between the current flowing through the test object and the threshold value. The non-volatile memory device according to claim 1, configured to perform a first test in which the first memory element is the test subject before the program operation is performed, and a second test in which the second memory element is the test subject before the program operation is performed. The non-volatile memory device according to claim 1, configured to perform a third test in which the test subject is a memory element, of the first memory element and the second memory element after the program operation is executed, whose characteristics are expected to change so that current does not easily flow due to the execution of the program operation. The non-volatile memory device according to claim 3, configured to perform a fourth test in which the test target is a memory element of the first memory element and the second memory element after the program operation is executed, the memory element being assumed to have characteristics that are not changed by the execution of the program operation. The non-volatile memory device of claim 4, configured to set the threshold value in the third test and the threshold value in the fourth test to different values. a first test for testing the first memory device before the program operation is performed, and a second test for testing the second memory device before the program operation is performed,
the threshold value in the third test and the threshold value in the first test are configured to be set to different values from each other,
The non-volatile memory device of claim 3 , configured to set the threshold in the third test and the threshold in the second test to different values from each other. The non-volatile memory device according to claim 1, configured to perform a fifth test in which the first memory element is the test target after the erase operation has been performed, and a sixth test in which the second memory element is the test target after the erase operation has been performed. a fifth test in which the first memory element after an erase operation is performed is the test object, and a sixth test in which the second memory element after the erase operation is the test object is the test object,
the threshold value in the third test and the threshold value in the fifth test are configured to be set to different values from each other,
The non-volatile memory device of claim 3 , configured to set the threshold in the third test and the threshold in the sixth test to different values from each other. the first memory element and the second memory element are each an NMOS transistor;
9. The non-volatile memory device according to claim 1, wherein the gate voltage of the NMOS transistor to be tested is controllable among three or more values.