JP2025117237A - Test method for insulated gate SiC semiconductor device, insulated gate SiC semiconductor device - Google Patents

Abstract

【assignment】
A method for testing insulated gate SiC semiconductor elements is provided that enables highly accurate sorting of non-standard products that are difficult to distinguish using conventional testing methods.
[Solution]
A method for testing an insulated gate SiC semiconductor device, comprising: (a) incorporating a device under test into an H-bridge circuit having an inductance load; and (b) repeatedly performing on/off switching using a gate voltage signal of the H-bridge circuit to pass a bidirectional current through the device under test, wherein the device under test satisfies the relational expression dv/dt>0.06×t×Vav, where Vav [kV] is a rated interrupting voltage rating, t [nm] is a gate insulating film thickness, and dv/dt [kV/us] is a voltage change rate during on/off switching.
[Selected figure] Figure 6

Description

The present invention relates to a semiconductor device testing method and the semiconductor device to be tested, and in particular to technology that is effective when applied to screening tests of insulated gate SiC semiconductor devices.

Silicon carbide (SiC) is attracting attention as a semiconductor material that can be used to manufacture power semiconductor elements with low resistance, high voltage resistance, heat resistance, and excellent high-speed characteristics. Power semiconductor elements using SiC include SBDs (Schottky Barrier Diodes), PNDs (PN Diodes), MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), and IGBTs (Insulated Gate Bipolar Transistors).

Because SiC has a dielectric breakdown field strength approximately 10 times higher than that of Si (silicon), high-voltage power semiconductor elements of several hundred to several thousand volts can be fabricated with a higher impurity concentration and thinner drift layer than Si semiconductor elements, enabling the realization of high-voltage elements with extremely low on-resistance per unit area.

In addition, with Si, minority carrier devices such as IGBTs are mainly used to alleviate the increase in on-resistance that accompanies higher voltages, but they have the problem of large switching losses, and the resulting heat generation places limits on high-frequency operation. On the other hand, with SiC, high voltages can be achieved using majority carrier devices such as SBDs and MOSFETs, which have high-speed device structures, making it possible to simultaneously achieve the three performance characteristics of high voltage, low on-resistance, and high speed.

Furthermore, since its bandgap is approximately three times wider than that of Si, it is possible to realize power semiconductor elements that can operate even at high temperatures.

As background technology in this technical field, there is, for example, technology such as that disclosed in Patent Document 1. Patent Document 1 discloses "a method for screening silicon carbide semiconductor devices that can screen for silicon carbide semiconductor devices that do not lose reliability even when used at high temperatures for long periods of time in an inverter circuit in which a diode is connected in anti-parallel to the silicon carbide semiconductor device."

Japanese Patent Application Laid-Open No. 2018-205251

In a power semiconductor device (for example, a power MOSFET), a voltage is repeatedly and intermittently applied between the drain and source as the device switches. When the MOSFET switches from a conductive state (on) to a cut-off state (off), the voltage applied to the drain electrode of the MOSFET increases rapidly. This change in drain voltage generates a displacement current via the depletion layer capacitance between the source and drain. This displacement current flows through the P-well and into the source electrode, and at that time, a voltage proportional to the magnitude of the current is generated in the P-well (see Figure 1, described later).
In the area where the gate oxide is sandwiched between the P-well and the gate electrode, the high voltage causes a high electric field to be applied to the gate oxide, which can damage the gate oxide. In particular, in the case of high-voltage elements that handle large power supply voltages, the displacement current generated during switching is large, and the electric field applied to the gate oxide is also large, so there is a concern that damage will accumulate over long-term use and lead to element destruction.

Although there are ways to prevent damage from internal electric fields through element structural design, it is inevitable that elements that are easily damaged will be included due to variations in the manufacturing process and the influence of foreign matter that cannot be completely removed. Therefore, such vulnerable elements must be selected and removed through stress testing.

In addition, the breakdown resistance of high-voltage elements is closely related to the interrupting voltage rating and gate insulating film thickness of the element in question, and is also affected by the switching speed during stress testing, so stress testing must take these factors into consideration.

Patent Document 1 above does not take these parameters into consideration, and there is room for improvement in achieving highly accurate sorting.

The object of the present invention is to provide a testing method for insulated gate SiC semiconductor devices that enables highly accurate sorting of non-standard products that are difficult to identify using conventional testing methods, and an insulated gate SiC semiconductor device that uses the same.

In order to solve the above problems, the present invention provides a method for testing an insulated gate SiC semiconductor device, comprising the steps of: (a) incorporating a device under test into an H-bridge circuit having an inductance load; and (b) repeatedly switching the H-bridge circuit on and off using a gate voltage signal to pass a bidirectional current through the device under test, wherein the device under test satisfies the relationship dv/dt > 0.06 × t × Vav, where Vav is the rated interrupting voltage rating, t is the gate insulating film thickness, and dv/dt is the voltage change rate during on/off switching.

The present invention also provides an insulated gate SiC semiconductor device comprising a gate terminal, a source terminal, and a drain terminal, which controls the current flowing between the source terminal and the drain terminal by applying a voltage to the gate terminal. The device is incorporated into an H-bridge circuit having an inductance load, and has a history of repeatedly switching on and off using a gate voltage signal from the H-bridge circuit, causing a bidirectional current to flow through the device under test. When the interrupting rated withstand voltage is Vav [kV], the gate insulating film thickness is t [nm], and the voltage change rate during on/off switching is dv/dt [kV/us], the device satisfies the relationship dv/dt > 0.06 × t × Vav.

The present invention provides a testing method for insulated gate SiC semiconductor devices that enables highly accurate sorting of non-standard products that are difficult to identify using conventional testing methods, as well as an insulated gate SiC semiconductor device that uses the same.

This will contribute to improving the reliability and extending the lifespan of insulated gate SiC semiconductor devices.

Other issues, configurations, and advantages will become clear from the description of the following embodiments.

1 is a diagram schematically illustrating a cross-sectional structure of a SiC-MOSFET according to a first embodiment of the present invention. FIG. 10 is a diagram showing the relationship between the rated withstand voltage of an element and the voltage change rate dv/dt required for defect screening. FIG. 10 is a diagram showing the relationship between the gate insulating film thickness and the voltage change rate dv/dt required for defect screening. 1 is a diagram showing an H-bridge type test circuit according to a first embodiment of the present invention; 4 is a diagram showing an example of a test waveform obtained by the H-bridge type test circuit of FIG. 3; FIG. 4 is a diagram showing the temperature of an element during a test using the H-bridge type test circuit of FIG. 3 . 3 is a flowchart showing a method for testing a SiC semiconductor device according to Example 1 of the present invention.

Embodiments of the present invention will be described below using the drawings. Note that identical components in each drawing will be assigned the same reference numerals, and detailed descriptions of overlapping parts will be omitted.

With reference to Figures 1 to 6, a method for testing a SiC semiconductor device according to Example 1 of the present invention and the SiC semiconductor device to be tested will be described.

Figure 1 is a diagram showing a schematic cross-sectional structure of the SiC-MOSFET of this embodiment, using a planar MOSFET as an example.

As shown in Figure 1, the SiC-MOSFET 1 of this embodiment has an n-type drift layer 3, also made of SiC, provided on the main surface of an n+ type SiC substrate 2.

Near the surface of the drift layer 3, a p-type body region 4, an n+ type source region 5 containing n-type dopants at a higher concentration than the n-type drift layer 3, and a p+ type contact region 6 containing p-type dopants at a higher concentration than the p-type body region 4 are formed.

A source electrode 7 is formed in contact with at least a portion of the n+ type source region 5 and p+ type contact region 6 near the surface of the drift layer 3.

In addition, a gate insulating film 8 and a gate electrode 9 are formed in contact with the p-type body region 4 near the surface of the drift layer 3.

A drain electrode 10 is provided on the back surface of the SiC substrate 2.

When the gate electrode 9 is biased to a certain voltage or higher (threshold voltage VGSth) relative to the source electrode 7, the portion of the p-type body region 4 that is in contact with the gate insulating film 8 on the surface side is inverted to n-type, forming a conductive channel. In this state, when the drain electrode 10 is biased positively relative to the source electrode 7, electrons flow from the n+ type source region 5 toward the drain electrode 10 through the conductive channel.

When the gate voltage is below the threshold voltage VGSth, no conductive channel is formed, and when a high drain voltage is applied, a depletion region is formed in the drift layer 3, causing only a small leakage current to flow through the drain electrode 10.

In this way, by controlling the voltage applied to the gate electrode 9, it is possible to control the on/off state of the current (switching operation).

The testing method for SiC semiconductor devices in this embodiment will be explained using the flowchart in Figure 6.

First, in step S1, a target SiC semiconductor device is incorporated into an H-bridge circuit having an inductance load (see FIG. 3, which will be described later).
Next, in step S2, a gate voltage signal is input to repeatedly perform on/off switching to pass a bidirectional current through the SiC semiconductor element, thereby applying stress to the SiC semiconductor element.

When switching, the operating conditions are set so that the relationship in equation (1) is satisfied.

dv/dt>0.06×t×Vav...(1)
Here, Vav [kV] is the rated interruption voltage of the SiC semiconductor element, t [nm] is the thickness of the gate insulating film, and dv/dt [kV/us] is the rate of voltage change during switching.

Next, in step S3, the SiC semiconductor device is removed from the H-bridge circuit.

Next, in step S4, the gate leakage current of the SiC semiconductor element removed from the H-bridge circuit is measured.

Next, in step S5, it is determined whether the gate leakage current value is within a predetermined specified value. If the gate leakage current value is within the predetermined specified value (Yes), the process proceeds to step S6, where the product is classified as a non-defective product. On the other hand, if the gate leakage current value is outside the predetermined specified value (No), the process proceeds to step S7, where the product is classified as a defective product.

According to the test method of this embodiment, by setting the operating conditions in the H-bridge circuit so that the above relational expression (1) is satisfied, weak elements will malfunction or break down, and will be screened out as defective.

Incidentally, since devices with a higher interrupting voltage rating place greater stress on the gate oxide film, efficient screening is possible if the voltage rating is 2 kV or higher.

As will be explained later using Figure 5, since higher stress can be applied by raising the temperature inside the element due to self-heating caused by current flow, the maximum current flowing during testing should be at least 1/5 (preferably at least 1/2) of the rated current of the element, and the element junction temperature should desirably be heated to 100°C or higher.

Using Figures 2A and 2B, we will explain the voltage change rate dv/dt required for defective product screening.

Figure 2A shows the relationship between the rated breakdown voltage of an element and the voltage change speed (voltage change rate) dv/dt required for defect screening, and Figure 2B shows the relationship between the gate insulating film thickness and the voltage change speed (voltage change rate) dv/dt required for defect screening.

The voltage change rate dv/dt at which a weak element can be classified as defective was calculated, and the relationship shown in Figures 2A and 2B was obtained.

As shown in Figure 2A, the voltage change rate dv/dt required for selection increases in proportion to the device's rated breakdown voltage (rated interrupting voltage). This is because the higher the rated voltage, the smaller the capacitance of the depletion layer, and the smaller the amount of displacement current associated with capacitance change.

Furthermore, as shown in Figure 2B, the thinner the gate insulating film, the lower the withstand voltage, and therefore the voltage change rate dv/dt required for sorting becomes smaller.

The voltage change rate dv/dt shown in these two figures gives the relationship shown in equation (1) above.

Figure 3 shows the device under test (SiC semiconductor device) incorporated into an H-bridge test circuit.

In addition to SW1, which is the device under test (DUT), four other switch elements, SW2, SW3, and SW4, form an H-bridge circuit, along with a DC power supply 11 and an inductance load 12. A gate driver GD is connected to each of switch elements SW1 to SW4, which inputs a gate signal to each switch element.

If the switching element has a rated interruption voltage of 3.3 kV and a rated current capacity of 1000 A, for example, the voltage of the DC power supply 11 is 1.8 kV and the inductance load 12 is 2 mH.

In this example, switch element SW1 is the device under test (DUT), and switch elements SW2 to SW4 are auxiliary elements that form an H-bridge circuit. However, to apply sufficient stress to switch element SW1, which is the device under test (DUT), it is desirable that the interrupting rated voltage and rated current capacity of switch elements SW2 to SW4 be greater than those of switch element SW1. Alternatively, switch elements SW2 to SW4 can also be incorporated with the same elements as switch element SW1, and all four can be tested as devices under test (DUT).

Also, if the product under test (DUT) is a type in which two switch elements are implemented in one package (2-in-1 type), switch elements SW1 and SW2 in Figure 3 may be incorporated into a circuit as a single package product and tested.

To control the switching speed (speed of voltage change) dv/dt, the gate voltage during on/off and the resistance value connected between the gate driver output and the gate terminal of the device under test are adjusted. To apply high stress more efficiently, the gate-on voltage needs to be high, the gate-off voltage low, and the gate resistance small.

The signal input to the gate of each switch element in an H-bridge circuit can be output by comparing the magnitude of a sine-wave modulating wave and a sawtooth-wave carrier wave, a technique known as pulse width modulation (PWM).

Figure 4 shows an example of a test waveform generated by the H-bridge test circuit shown in Figure 3.

Figure 4 shows the gate voltage signal input to the device under test (DUT) when PWM controlled with a 50 Hz modulating wave and a 1 kHz carrier wave, as well as the waveforms of the drain voltage and current flowing through the device under test (DUT) at that time.

The drain voltage applied to the device under test changes repeatedly in accordance with the on/off signal input to the gate. If the switching speed (speed of voltage change) dv/dt at this time falls within the range shown in equation (1) above, stress can be applied to the device under test efficiently. In the H-bridge test circuit shown in Figure 3, the current reverses positive and negative within one cycle, indicating that it flows in both directions. With such an H-bridge circuit, it is possible to test all operating modes, including on and off of the switching element, as well as forward and reverse recovery.

Figure 5 shows the temperature of the element during testing using the H-bridge test circuit in Figure 3.

Figure 5 shows the change in the junction temperature of the device under test during testing. The temperature of the switching element gradually rises due to Joule heat generated by the current flowing through it during the test. This temperature rise depends on the thermal characteristics determined by the switching element's structure and the method of cooling the switching element, but it generally reaches a nearly constant steady-state temperature within a few seconds to a few tens of seconds.

The test should be conducted by repeatedly passing current for a sufficient period of time to reach this steady state, and it is desirable that the temperature at that time reach 100°C or higher. Furthermore, to reach that temperature, the current applied to the device under test must be at least 1/5 (preferably 1/2 or more) of its maximum rated current. If the current is low and the maximum temperature reached is low, the stress may be insufficient.

As described above, the method for testing SiC semiconductor devices in this embodiment includes the steps of (a) incorporating the device under test into an H-bridge circuit having an inductance load, and (b) repeatedly switching the H-bridge circuit on and off using a gate voltage signal to pass a bidirectional current through the device under test. The device under test satisfies the relational expression dv/dt > 0.06 × t × Vav, where Vav [kV] is the rated interrupting voltage, t [nm] is the gate insulating film thickness, and dv/dt [kV/us] is the voltage change rate during on/off switching.

The SiC semiconductor element of this embodiment is an insulated gate SiC semiconductor element that has a gate terminal, a source terminal, and a drain terminal, and controls the current flowing between the source terminal and the drain terminal by applying a voltage to the gate terminal. It is incorporated into an H-bridge circuit having an inductance load, and has a history of repeatedly switching on and off using the gate voltage signal of the H-bridge circuit, causing a bidirectional current to flow through the insulated gate SiC semiconductor element. When the interrupting rated withstand voltage is Vav [kV], the gate insulating film thickness is t [nm], and the voltage change rate during on/off switching is dv/dt [kV/us], the relationship dv/dt > 0.06 × t × Vav is satisfied.

This enables highly accurate sorting of non-standard products that are difficult to identify using conventional testing methods, contributing to improved reliability and longer lifespans of insulated gate SiC semiconductor devices.

The present invention is not limited to the above-described embodiments, and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

1...SiC-MOSFET
2...SiC substrate (n+ type)
3...Drift layer (n-type)
4...Body region (p-type)
5...Source region (n+ type)
6...contact region (p+ type)
7...Source electrode 8...Gate insulating film 9...Gate electrode 10...Drain electrode 11...DC power supply 12...Inductance load GD...Gate driver SW1 to SW4...Switch elements.

Claims (10)

A test method for an insulated gate SiC semiconductor device, comprising:
(a) incorporating a device under test into an H-bridge type circuit having an inductance load;
(b) repeatedly switching on and off the H-bridge circuit using a gate voltage signal to pass a bidirectional current through the device under test;
and
When the device under test has an interruption rated withstand voltage of Vav [kV], a gate insulating film thickness of t [nm], and a voltage change rate during on/off switching of dv/dt [kV/us],
dv/dt>0.06×t×Vav
A method for testing an insulated gate SiC semiconductor device, characterized in that the following relational expression is satisfied: 2. A method for testing an insulated gate SiC semiconductor device according to claim 1, comprising:
A method for testing an insulated gate SiC semiconductor device, wherein the device under test has an interruption rated withstand voltage of 2 kV or more. 2. A method for testing an insulated gate SiC semiconductor device according to claim 1, comprising:
A method for testing an insulated gate SiC semiconductor device, wherein in the step (b), the junction temperature of the device under test is heated to 100°C or higher due to self-heating caused by current flow. 2. A method for testing an insulated gate SiC semiconductor device according to claim 1, comprising:
A method for testing an insulated gate SiC semiconductor device, wherein in the step (b), the maximum value of the bidirectional current flowing through the device under test is 1/5 or more of the maximum rated current of the device under test. 2. A method for testing an insulated gate SiC semiconductor device according to claim 1, comprising:
A method for testing an insulated gate SiC semiconductor device, wherein in the step (b), the maximum value of the bidirectional current flowing through the device under test is equal to or greater than half of the maximum rated current of the device under test. a gate terminal, a source terminal, and a drain terminal;
An insulated gate SiC semiconductor element that controls a current flowing between the source terminal and the drain terminal by applying a voltage to the gate terminal,
It is incorporated into an H-bridge circuit with an inductive load,
The H-bridge circuit has a history of repeatedly switching on and off using a gate voltage signal to pass a bidirectional current through the insulated gate SiC semiconductor element;
When the rated breakdown voltage is Vav [kV], the gate insulating film thickness is t [nm], and the voltage change rate during on/off switching is dv/dt [kV/us],
dv/dt>0.06×t×Vav
An insulated gate SiC semiconductor element characterized by satisfying the following relational expression. 7. The insulated gate SiC semiconductor device according to claim 6,
An insulated gate SiC semiconductor element having a rated breakdown voltage of 2 kV or more. 7. The insulated gate SiC semiconductor device according to claim 6,
An insulated gate SiC semiconductor element, characterized in that the junction temperature is heated to 100°C or higher due to self-heating caused by current flow during the repeated on/off switching. 7. The insulated gate SiC semiconductor device according to claim 6,
an insulated gate SiC semiconductor element, wherein a maximum value of a bidirectional current flowing through the insulated gate SiC semiconductor element during the repeated on/off switching is 1/5 or more of a maximum rated current of the insulated gate SiC semiconductor element. 7. The insulated gate SiC semiconductor device according to claim 6,
an insulated gate SiC semiconductor element, wherein a maximum value of a bidirectional current flowing through the insulated gate SiC semiconductor element during the repeated on/off switching is equal to or greater than half of a maximum rated current of the insulated gate SiC semiconductor element.